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172 lines
7.4 KiB
172 lines
7.4 KiB
/*
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*******************************************************************************
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* Copyright(C) NEC Electronics Corporation 2010
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* All rights reserved by NEC Electronics Corporation.
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* This program should be used on your own responsibility.
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* NEC Electronics Corporation assumes no responsibility for any losses
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* incurred by customers or third parties arising from the use of this file.
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*
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* This device driver was created by Applilet3 for V850ES/Jx3
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* 32-Bit Single-Chip Microcontrollers
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* Filename: CG_system.h
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* Abstract: This file implements device driver for System module.
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* APIlib: Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010]
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* Device: uPD70F3746
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* Compiler: IAR Systems ICCV850
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* Creation date: 6/26/2010
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*******************************************************************************
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*/
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#ifndef _MDSYSTEM_
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#define _MDSYSTEM_
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/*
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*******************************************************************************
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** Register bit define
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*******************************************************************************
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*/
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/*
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Processor clock control register (PCC)
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*/
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#define _03_CG_PCC_INITIALVALUE 0x03U
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/* Use of subclock on-chip feedback resistor (FRC) */
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#define _00_CG_SUBCLK_FEEDBACK_USE 0x00U /* subclock on-chip feedback resistor connected */
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#define _08_CG_SUBCLK_FEEDBACK_UNUSE 0x80U /* subclock on-chip feedback resistor not connected */
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/* Main clock osillator control (MCK) */
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#define _00_CG_MAINCLK_ENABLE 0x00U /* main clock oscillation enabled */
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#define _04_CG_MAINCLK_STOP 0x40U /* main clock oscillation stopped */
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/* Use of main clock on-chip feedback resistor (MFRC) */
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#define _00_CG_MAINCLK_FEEDBACK_USE 0x00U /* main clock feedback resistor connected */
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#define _20_CG_MAINCLK_FEEDBACK_UNUSE 0x20U /* main clock feedback resistor not connected */
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/* Status of CPU clock fCPU (CLS) */
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#define _00_CG_CPUCLK_MAINCLK 0x00U /* main clock operation */
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#define _10_CG_CPUCLK_SUBCLK 0x10U /* subclock operation */
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/* Clock(fCLK/fCPU) selection (CK3 - CK0) */
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#define _0F_CG_CPUCLK 0x0FU
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#define _00_CG_CPUCLK_MAIN0 0x00U /* fCPU = fXX */
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#define _01_CG_CPUCLK_MAIN1 0x01U /* fCPU = fXX/2 */
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#define _02_CG_CPUCLK_MAIN2 0x02U /* fCPU = fXX/2^2 */
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#define _03_CG_CPUCLK_MAIN3 0x03U /* fCPU = fXX/2^3 */
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#define _04_CG_CPUCLK_MAIN4 0x04U /* fCPU = fXX/2^4 */
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#define _05_CG_CPUCLK_MAIN5 0x05U /* fCPU = fXX/2^5 */
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#define _0B_CG_CPUCLK_SUB 0x0BU /* fXT */
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/*
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Internal oscillator mode register (RCM)
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*/
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/* Oscillation/stop of internal oscillator (RSTOP) */
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#define _00_CG_INTER_OSC_ON 0x00U /* internal oscillator oscillation */
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#define _01_CG_INTER_OSC_OFF 0x01U /* internal oscillator stopped */
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/*
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CPU operation clock status register (CCLS)
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*/
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/* CPU operation clock status (CCLSF) */
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#define _00_CG_CPUCLK_STATUS_MAINORSUB 0x00U /* operating on main clock(fX) or subclock(fXT) */
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#define _01_CG_CPUCLK_STATUS_INTEROSC 0x01U /* operating on internal oscillation clock(fR) */
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/*
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Lock register (LOCKR)
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*/
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/* PLL lock status check (LOCK) */
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#define _00_CG_PLLSTATUS_LOCK 0x00U /* locked status */
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#define _01_CG_PLLSTATUS_UNLOCK 0x01U /* unlocked status */
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/*
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PLL control register (PLLCTL)
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*/
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#define _01_CG_PLLCTL_INITIALVALUE 0x01U
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/* CPU operation clock selection register (SELPLL) */
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#define _00_CG_CPUCLK_CLKTHROUGH 0x00U /* clock-through mode */
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#define _02_CG_CPUCLK_PLL 0x02U /* PLL mode */
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/* PLL operation stop register (PLLON) */
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#define _00_CG_CPUCLK_PLLOFF 0x00U /* PLL stopped */
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#define _01_CG_CPUCLK_PLLON 0x01U /* PLL operating */
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/*
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Clock control register (CKC)
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*/
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#define _0A_CG_CKC_INITIALVALUE 0x0AU
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/* Internal system clock(fXX) in PLL mode */
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#define _00_CG_CPUCLK_4PLL 0x00U /* fXX = 4* fX (fX = 2.5 to 5.0 MHz) */
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#define _01_CG_CPUCLK_8PLL 0x01U /* fXX = 8* fX (fX = 2.5 to 4.0 MHz) */
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/*
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PLL lockup time specification register (PLLS)
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*/
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#define _03_CG_PLLS_INITIALVALUE 0x03U
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/* PLL lockup time selection (PLLS2 - PLLS0) */
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#define _00_CG_PLLLOCKUP_SEL0 0x00U /* 2^10/fX */
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#define _01_CG_PLLLOCKUP_SEL1 0x01U /* 2^11/fX*/
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#define _02_CG_PLLLOCKUP_SEL2 0x02U /* 2^12/fX */
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#define _03_CG_PLLLOCKUP_SEL3 0x03U /* 2^13/fX (default value) */
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/*
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Power save control register (PSC)
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*/
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/* Stand-by mode release control by occurrence of INTWDT2 signal (NMI1M) */
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#define _00_CG_STANDBY_INTWDT2EN 0x00U /* enable releasing stand-by mode by INTWDT2 signal */
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#define _40_CG_STANDBY_INTWDT2DIS 0x40U /* disable releasing stand-by mode by INTWDT2 signal */
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/* Stand-by mode release control by NMI pin input (NMI0M) */
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#define _00_CG_STANDBY_NMIEN 0x00U /* enable releasing stand-by mode by NMI pin input */
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#define _20_CG_STANDBY_NMIDIS 0x20U /* disable releasing stand-by mode by NMI pin input */
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/* Stand-by mode release control by maskable interrupt request signal (NMI0M) */
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#define _00_CG_STANDBY_MASKIEN 0x00U /* enable releasing stand-by mode by maskable interrupt request signal */
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#define _10_CG_STANDBY_MASKIDIS 0x10U /* disable releasing stand-by mode by maskable interrupt request signal */
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/* Setting of stand-by mode (STP) */
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#define _00_CG_STANDBY_UNUSE 0x00U /* normal mode */
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#define _02_CG_STANDBY_USE 0x02U /* stand-by mode */
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/*
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Power save mode control register (PSMR)
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*/
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/* Specification of operation in software stand-by mode (PSM1,PSM0) */
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#define _00_CG_POWERSAVE_IDLE1 0x00U /* IDLE1, sub-IDLE modes */
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#define _01_CG_POWERSAVE_STOP1 0x01U /* STOP, sub-IDLE modes */
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#define _02_CG_POWERSAVE_IDLE2 0x02U /* IDLE2, sub-IDLE modes */
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#define _03_CG_POWERSAVE_STOP2 0x03U /* STOP mode */
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/*
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Clock monitor mode register (CLM)
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*/
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/* Clock monitor operation enable or disable (CLME) */
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#define _01_CG_MONITOR_ENABLE 0x01U /* enable clock monitor operation */
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#define _00_CG_MONITOR_DISABLE 0x00U /* disable clock monitor operation */
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/*
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Watchdog Timer 2 mode register (WDTM2)
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*/
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/* Selection of operation mode (WDM21, WDM20) */
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#define _00_WDT2_OPERMODE_STOP 0x00U /* stops operation */
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#define _20_WDT2_OPERMODE_NONMASK 0x20U /* non-maskable interrupt request mode (generation of INTWDT2) */
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#define _40_WDT2_OPERMODE_RESET 0x40U /* reset mode (generation of RESWDT2) */
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/* Selection of clock mode (WDCS24,WDCS23) */
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#define _00_WDT2_CLKMODE_INTEROSC 0x00U /* use internal oscillator */
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#define _08_WDT2_CLKMODE_MAINCLK 0x08U /* use Main clock */
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#define _10_WDT2_CLKMODE_SUBCLK 0x10U /* use subclock */
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/* Watchdog Timer 2 clock Selection (WDCS22 - WDCS20) */
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#define _00_WDT2_CLOCK_SEL0 0x00U /* 2^12/fR or 2^18/fXX or 2^9/fXT */
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#define _01_WDT2_CLOCK_SEL1 0x01U /* 2^13/fR or 2^19/fXX or 2^10/fXT */
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#define _02_WDT2_CLOCK_SEL2 0x02U /* 2^14/fR or 2^20/fXX or 2^11/fXT */
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#define _03_WDT2_CLOCK_SEL3 0x03U /* 2^15/fR or 2^21/fXX or 2^12/fXT */
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#define _04_WDT2_CLOCK_SEL4 0x04U /* 2^16/fR or 2^22/fXX or 2^13/fXT */
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#define _05_WDT2_CLOCK_SEL5 0x05U /* 2^17/fR or 2^23/fXX or 2^14/fXT */
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#define _06_WDT2_CLOCK_SEL6 0x06U /* 2^18/fR or 2^24/fXX or 2^15/fXT */
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#define _07_WDT2_CLOCK_SEL7 0x07U /* 2^19/fR or 2^25/fXX or 2^16/fXT */
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/*
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*******************************************************************************
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** Macro define
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*******************************************************************************
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*/
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#define _00_CG_VSWC_VALUE 0x00U
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/*
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*******************************************************************************
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** Function define
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*******************************************************************************
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*/
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void CLOCK_Init(void);
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void WDT2_Restart(void);
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void CG_ReadResetSource(void);
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/* Start user code for function. Do not edit comment generated here */
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/* End user code. Do not edit comment generated here */
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#endif
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