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61 lines
1.5 KiB
61 lines
1.5 KiB
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2024-03-11 Wangyuqiang first version
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*/
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#ifndef __BOARD_H__
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#define __BOARD_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <rtdef.h>
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#include <cp15.h>
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#include <hal_data.h>
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#define RZ_SRAM_SIZE 1536 /* The SRAM size of the chip needs to be modified */
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#define RZ_SRAM_END (0x10000000 + RZ_SRAM_SIZE * 1024)
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#ifdef __ARMCC_VERSION
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extern int Image$$RAM_END$$ZI$$Base;
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#define HEAP_BEGIN ((void *)&Image$$RAM_END$$ZI$$Base)
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#else
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#define HEAP_BEGIN (0x10000000)
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#endif
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#define HEAP_END RZ_SRAM_END
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/***********************************************************************************************************************
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* Macro definitions
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**********************************************************************************************************************/
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#define MAX_HANDLERS (512)
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#define GIC_IRQ_START 0
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#define GIC_ACK_INTID_MASK (0x000003FFU)
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/* number of interrupts on board */
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#define ARM_GIC_NR_IRQS (448)
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/* only one GIC available */
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#define ARM_GIC_MAX_NR 1
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/* end defined */
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#define GICV3_DISTRIBUTOR_BASE_ADDR (0x100000)
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/* the basic constants and interfaces needed by gic */
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rt_inline rt_uint32_t platform_get_gic_dist_base(void)
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{
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rt_uint32_t gic_base;
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__get_cp(15, 1, gic_base, 15, 3, 0);
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return gic_base + GICV3_DISTRIBUTOR_BASE_ADDR;
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}
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#ifdef __cplusplus
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}
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#endif
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#endif
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