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231 lines
3.0 KiB
231 lines
3.0 KiB
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Email: opensource_embedded@phytium.com.cn
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*
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* Change Logs:
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* Date Author Notes
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* 2023-07-26 huanghe first commit
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*
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*/
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#include "fparameters.h"
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#include "rtconfig.h"
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#ifndef __aarch64__
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.globl cpu_id_mapping
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cpu_id_mapping:
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#if defined(TARGET_E2000Q) || defined(TARGET_PHYTIUMPI)
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cmp r0, #0 // compare cpu_id with 0
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beq map_cpu_id_0
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cmp r0, #1 // compare cpu_id with 1
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beq map_cpu_id_1
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cmp r0, #2 // compare cpu_id with 2
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beq map_cpu_id_2
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cmp r0, #3 // compare cpu_id with 3
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beq map_cpu_id_3
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mov pc, lr // no mapping needed
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#endif
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mov pc, lr // no mapping needed
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// Mapping for E2000Q
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map_cpu_id_0:
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mov r0, #2
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mov pc, lr
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map_cpu_id_1:
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mov r0, #3
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mov pc, lr
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map_cpu_id_2:
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mov r0, #0
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mov pc, lr
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map_cpu_id_3:
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mov r0, #1
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mov pc, lr
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.globl rt_hw_cpu_id_early
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rt_hw_cpu_id_early:
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// read MPIDR
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mov r9, lr
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mrc p15, 0, r0, c0, c0, 5
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ubfx r0, r0, #0, #12
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ldr r1,= CORE0_AFF
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cmp r0, r1
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beq core0
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#if defined(CORE1_AFF)
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ldr r1,= CORE1_AFF
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cmp r0, r1
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beq core1
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#endif
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#if defined(CORE2_AFF)
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ldr r1,= CORE2_AFF
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cmp r0, r1
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beq core2
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#endif
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#if defined(CORE3_AFF)
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ldr r1,= CORE3_AFF
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cmp r0, r1
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beq core3
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#endif
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b default
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core0:
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mov r0, #0
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b return
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core1:
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mov r0, #1
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b return
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core2:
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mov r0, #2
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b return
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core3:
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mov r0, #3
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b return
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core4:
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mov r0, #4
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b return
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core5:
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mov r0, #5
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b return
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core6:
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mov r0, #6
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b return
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core8:
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mov r0, #8
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b return
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default:
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and r0, r0, #15
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return:
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bl cpu_id_mapping
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mov pc, r9
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#else
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.globl cpu_id_mapping
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cpu_id_mapping:
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#if defined(TARGET_E2000Q) || defined(TARGET_PHYTIUMPI)
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cmp x0, #0 // compare cpu_id with 0
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beq map_cpu_id_0
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cmp x0, #1 // compare cpu_id with 1
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beq map_cpu_id_1
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cmp x0, #2 // compare cpu_id with 2
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beq map_cpu_id_2
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cmp x0, #3 // compare cpu_id with 3
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beq map_cpu_id_3
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RET // no mapping needed
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#endif
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RET // no mapping needed
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// Mapping for E2000Q
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map_cpu_id_0:
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mov x0, #2
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RET
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map_cpu_id_1:
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mov x0, #3
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RET
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map_cpu_id_2:
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mov x0, #0
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RET
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map_cpu_id_3:
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mov x0, #1
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RET
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.globl rt_hw_cpu_id_set
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rt_hw_cpu_id_set:
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mov x9, lr
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mrs x0,MPIDR_EL1
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and x1, x0, #15
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msr tpidr_el1, x1
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ubfx x0, x0, #0, #12
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ldr x1,= CORE0_AFF
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cmp x0, x1
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beq core0
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#if defined(CORE1_AFF)
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ldr x1,= CORE1_AFF
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cmp x0, x1
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beq core1
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#endif
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#if defined(CORE2_AFF)
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ldr x1,= CORE2_AFF
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cmp x0, x1
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beq core2
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#endif
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#if defined(CORE3_AFF)
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ldr x1,= CORE3_AFF
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cmp x0, x1
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beq core3
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#endif
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b default
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core0:
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mov x0, #0
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b return
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core1:
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mov x0, #1
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b return
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core2:
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mov x0, #2
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b return
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core3:
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mov x0, #3
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b return
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core4:
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mov x0, #4
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b return
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core5:
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mov x0, #5
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b return
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core6:
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mov x0, #6
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b return
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core8:
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mov x0, #8
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b return
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default:
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and x0, x0, #15
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return:
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//bl cpu_id_mapping
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mov lr, x9
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RET
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#endif
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