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658 lines
23 KiB
658 lines
23 KiB
/**************************************************************************//**
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*
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* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-6-1 Wayne First version
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*
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******************************************************************************/
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#include <rtthread.h>
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#include <rtdevice.h>
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#include "drv_gpio.h"
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#include "drv_sys.h"
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#include "drv_sspcc.h"
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#include "board.h"
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#if defined(BOARD_USING_STORAGE_SPIFLASH)
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#if defined(RT_USING_SFUD)
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#include "spi_flash.h"
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#include "spi_flash_sfud.h"
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#endif
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#include "drv_qspi.h"
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#define W25X_REG_READSTATUS (0x05)
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#define W25X_REG_READSTATUS2 (0x35)
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#define W25X_REG_WRITEENABLE (0x06)
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#define W25X_REG_WRITESTATUS (0x01)
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#define W25X_REG_QUADENABLE (0x02)
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static rt_uint8_t SpiFlash_ReadStatusReg(struct rt_qspi_device *qspi_device)
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{
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rt_uint8_t u8Val;
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rt_err_t result = RT_EOK;
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rt_uint8_t w25x_txCMD1 = W25X_REG_READSTATUS;
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result = rt_qspi_send_then_recv(qspi_device, &w25x_txCMD1, 1, &u8Val, 1);
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RT_ASSERT(result > 0);
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return u8Val;
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}
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static rt_uint8_t SpiFlash_ReadStatusReg2(struct rt_qspi_device *qspi_device)
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{
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rt_uint8_t u8Val;
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rt_err_t result = RT_EOK;
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rt_uint8_t w25x_txCMD1 = W25X_REG_READSTATUS2;
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result = rt_qspi_send_then_recv(qspi_device, &w25x_txCMD1, 1, &u8Val, 1);
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RT_ASSERT(result > 0);
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return u8Val;
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}
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static rt_err_t SpiFlash_WriteStatusReg(struct rt_qspi_device *qspi_device, uint8_t u8Value1, uint8_t u8Value2)
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{
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rt_uint8_t w25x_txCMD1;
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rt_uint8_t au8Val[2];
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rt_err_t result;
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struct rt_qspi_message qspi_message = {0};
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/* Enable WE */
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w25x_txCMD1 = W25X_REG_WRITEENABLE;
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result = rt_qspi_send(qspi_device, &w25x_txCMD1, sizeof(w25x_txCMD1));
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if (result != sizeof(w25x_txCMD1))
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goto exit_SpiFlash_WriteStatusReg;
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/* Prepare status-1, 2 data */
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au8Val[0] = u8Value1;
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au8Val[1] = u8Value2;
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/* 1-bit mode: Instruction+payload */
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qspi_message.instruction.content = W25X_REG_WRITESTATUS;
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qspi_message.instruction.qspi_lines = 1;
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qspi_message.qspi_data_lines = 1;
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qspi_message.parent.cs_take = 1;
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qspi_message.parent.cs_release = 1;
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qspi_message.parent.send_buf = &au8Val[0];
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qspi_message.parent.length = sizeof(au8Val);
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qspi_message.parent.next = RT_NULL;
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if (rt_qspi_transfer_message(qspi_device, &qspi_message) != sizeof(au8Val))
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{
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result = -RT_ERROR;
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}
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result = RT_EOK;
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exit_SpiFlash_WriteStatusReg:
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return result;
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}
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static void SpiFlash_WaitReady(struct rt_qspi_device *qspi_device)
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{
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volatile uint8_t u8ReturnValue;
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do
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{
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u8ReturnValue = SpiFlash_ReadStatusReg(qspi_device);
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u8ReturnValue = u8ReturnValue & 1;
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}
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while (u8ReturnValue != 0); // check the BUSY bit
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}
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static void SpiFlash_EnterQspiMode(struct rt_qspi_device *qspi_device)
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{
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rt_err_t result = RT_EOK;
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uint8_t u8Status1 = SpiFlash_ReadStatusReg(qspi_device);
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uint8_t u8Status2 = SpiFlash_ReadStatusReg2(qspi_device);
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u8Status2 |= W25X_REG_QUADENABLE;
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result = SpiFlash_WriteStatusReg(qspi_device, u8Status1, u8Status2);
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RT_ASSERT(result == RT_EOK);
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SpiFlash_WaitReady(qspi_device);
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}
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static void SpiFlash_ExitQspiMode(struct rt_qspi_device *qspi_device)
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{
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rt_err_t result = RT_EOK;
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uint8_t u8Status1 = SpiFlash_ReadStatusReg(qspi_device);
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uint8_t u8Status2 = SpiFlash_ReadStatusReg2(qspi_device);
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u8Status2 &= ~W25X_REG_QUADENABLE;
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result = SpiFlash_WriteStatusReg(qspi_device, u8Status1, u8Status2);
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RT_ASSERT(result == RT_EOK);
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SpiFlash_WaitReady(qspi_device);
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}
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static int rt_hw_spiflash_init(void)
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{
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if (nu_qspi_bus_attach_device("qspi0", "qspi01", 4, SpiFlash_EnterQspiMode, SpiFlash_ExitQspiMode) != RT_EOK)
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return -1;
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#if defined(RT_USING_SFUD)
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if (rt_sfud_flash_probe(FAL_USING_NOR_FLASH_DEV_NAME, "qspi01") == RT_NULL)
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{
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return -(RT_ERROR);
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}
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#endif
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return 0;
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}
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INIT_DEVICE_EXPORT(rt_hw_spiflash_init);
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#endif /* BOARD_USING_STORAGE_SPIFLASH */
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#if defined(BOARD_USING_STORAGE_SPINAND) && defined(NU_PKG_USING_SPINAND)
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#include "drv_qspi.h"
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#include "spinand.h"
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struct rt_mtd_nand_device mtd_partitions[MTD_SPINAND_PARTITION_NUM] =
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{
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[0] =
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{
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/*nand0: U-boot, env, rtthread*/
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.block_start = 0,
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.block_end = 63,
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.block_total = 64,
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},
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[1] =
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{
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/*nand1: for filesystem mounting*/
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.block_start = 64,
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.block_end = 4095,
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.block_total = 4032,
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},
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[2] =
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{
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/*nand2: Whole blocks size, overlay*/
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.block_start = 0,
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.block_end = 4095,
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.block_total = 4096,
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}
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};
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static int rt_hw_spinand_init(void)
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{
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if (nu_qspi_bus_attach_device("qspi0", "qspi01", 4, RT_NULL, RT_NULL) != RT_EOK)
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return -1;
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if (rt_hw_mtd_spinand_register("qspi01") != RT_EOK)
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return -1;
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return 0;
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}
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INIT_DEVICE_EXPORT(rt_hw_spinand_init);
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#endif
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#if defined(BOARD_USING_MPU6500) && defined(PKG_USING_MPU6XXX)
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#include "sensor_inven_mpu6xxx.h"
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int rt_hw_mpu6xxx_port(void)
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{
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struct rt_sensor_config cfg;
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rt_base_t mpu_int = NU_GET_PININDEX(NU_PL, 8);
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cfg.intf.dev_name = "i2c1";
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cfg.intf.arg = (void *)MPU6XXX_ADDR_DEFAULT;
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cfg.irq_pin.pin = mpu_int;
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return rt_hw_mpu6xxx_init("mpu", &cfg);
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}
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INIT_APP_EXPORT(rt_hw_mpu6xxx_port);
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#endif /* BOARD_USING_MPU6500 */
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#if defined(BOARD_USING_STORAGE_RAWNAND) && defined(BSP_USING_NFI)
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struct rt_mtd_nand_device mtd_partitions_nfi[MTD_NFI_PARTITION_NUM] =
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{
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[0] =
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{
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/*nand0: rtthread*/
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.block_start = 0,
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.block_end = 63,
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.block_total = 64,
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},
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[1] =
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{
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/*nand1: for filesystem mounting*/
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.block_start = 64,
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.block_end = 8191,
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.block_total = 8128,
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},
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[2] =
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{
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/*nand2: Whole blocks size, overlay*/
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.block_start = 0,
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.block_end = 8191,
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.block_total = 8192,
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}
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};
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#endif
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#if defined(BOARD_USING_NAU8822) && defined(NU_PKG_USING_NAU8822)
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#include <acodec_nau8822.h>
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S_NU_NAU8822_CONFIG sCodecConfig =
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{
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.i2c_bus_name = "i2c2",
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.i2s_bus_name = "sound0",
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.pin_phonejack_en = NU_GET_PININDEX(NU_PD, 13),
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.pin_phonejack_det = NU_GET_PININDEX(NU_PI, 0),
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};
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int rt_hw_nau8822_port(void)
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{
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if (nu_hw_nau8822_init(&sCodecConfig) != RT_EOK)
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return -1;
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return 0;
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}
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INIT_COMPONENT_EXPORT(rt_hw_nau8822_port);
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#endif /* BOARD_USING_NAU8822 */
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#if defined(NU_PKG_USING_ADC_TOUCH)
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#include "adc_touch.h"
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S_CALIBRATION_MATRIX g_sCalMat = { -17558, 1, 69298832, -10, 11142, -2549195, 65536 };
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#endif
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#if defined(NU_PKG_USING_TPC_GT911) && defined(BOARD_USING_GT911)
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#include "drv_gpio.h"
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#include "gt911.h"
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#define TPC_RST_PIN NU_GET_PININDEX(NU_PM, 12)
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#define TPC_IRQ_PIN NU_GET_PININDEX(NU_PD, 12)
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extern int tpc_sample(const char *name);
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int rt_hw_gt911_port(void)
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{
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struct rt_touch_config cfg;
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rt_uint8_t rst_pin;
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rst_pin = TPC_RST_PIN;
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cfg.dev_name = "i2c5";
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cfg.irq_pin.pin = TPC_IRQ_PIN;
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cfg.irq_pin.mode = PIN_MODE_INPUT_PULLDOWN;
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cfg.user_data = &rst_pin;
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rt_hw_gt911_init("gt911", &cfg);
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return tpc_sample("gt911");
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}
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INIT_ENV_EXPORT(rt_hw_gt911_port);
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#endif /* if defined(BOARD_USING_GT911) && defined(PKG_USING_GT911) */
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#if defined(BOARD_USING_BUZZER)
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#define EPWM_DEV_NAME "epwm1"
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#define EPWM_DEV_CHANNEL (5)
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static void PlayRingTone(void)
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{
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struct rt_device_pwm *epwm_dev;
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rt_uint32_t period;
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int i, j;
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period = 1000;
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if ((epwm_dev = (struct rt_device_pwm *)rt_device_find(EPWM_DEV_NAME)) != RT_NULL)
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{
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rt_pwm_set(epwm_dev, EPWM_DEV_CHANNEL, period, period);
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rt_pwm_enable(epwm_dev, EPWM_DEV_CHANNEL);
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for (j = 0; j < 5; j++)
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{
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for (i = 0; i < 10; i++)
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{
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rt_pwm_set(epwm_dev, EPWM_DEV_CHANNEL, period, period);
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rt_thread_mdelay(50);
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rt_pwm_set(epwm_dev, EPWM_DEV_CHANNEL, period, period / 2);
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rt_thread_mdelay(50);
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}
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/* Mute 2 seconds */
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rt_pwm_set(epwm_dev, EPWM_DEV_CHANNEL, period, period);
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rt_thread_mdelay(2000);
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}
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rt_pwm_disable(epwm_dev, EPWM_DEV_CHANNEL);
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}
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else
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{
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rt_kprintf("Can't find %s\n", EPWM_DEV_NAME);
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}
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}
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#if defined(BOARD_USING_LCM)
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#if defined(PKG_USING_GUIENGINE)
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#include <rtgui/driver.h>
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#endif
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#if defined(RT_USING_PIN)
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#include <drv_gpio.h>
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/* defined the LCM_BLEN pin: PK7 */
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#define LCM_BACKLIGHT_CTRL NU_GET_PININDEX(NU_PK, 7)
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#endif
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#define EPWM_DEV_NAME "epwm1"
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#define LCM_PWM_CHANNEL (1)
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void nu_lcd_backlight_on(void)
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{
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struct rt_device_pwm *pwm_dev;
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if ((pwm_dev = (struct rt_device_pwm *)rt_device_find(EPWM_DEV_NAME)) != RT_NULL)
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{
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rt_pwm_enable(pwm_dev, LCM_PWM_CHANNEL);
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rt_pwm_set(pwm_dev, LCM_PWM_CHANNEL, 100000, 100);
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}
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else
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{
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rt_kprintf("Can't find %s\n", EPWM_DEV_NAME);
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}
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rt_pin_mode(LCM_BACKLIGHT_CTRL, PIN_MODE_OUTPUT);
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rt_pin_write(LCM_BACKLIGHT_CTRL, PIN_HIGH);
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}
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void nu_lcd_backlight_off(void)
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{
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struct rt_device_pwm *pwm_dev;
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if ((pwm_dev = (struct rt_device_pwm *)rt_device_find(EPWM_DEV_NAME)) != RT_NULL)
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{
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rt_pwm_disable(pwm_dev, LCM_PWM_CHANNEL);
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}
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else
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{
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rt_kprintf("Can't find %s\n", EPWM_DEV_NAME);
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}
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rt_pin_mode(LCM_BACKLIGHT_CTRL, PIN_MODE_OUTPUT);
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rt_pin_write(LCM_BACKLIGHT_CTRL, PIN_LOW);
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}
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int rt_hw_lcm_port(void)
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{
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#if defined(PKG_USING_GUIENGINE)
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rt_device_t lcm_vpost;
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lcm_vpost = rt_device_find("lcd");
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if (lcm_vpost)
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{
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rtgui_graphic_set_device(lcm_vpost);
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}
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#endif
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return 0;
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}
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INIT_COMPONENT_EXPORT(rt_hw_lcm_port);
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#endif /* BOARD_USING_LCM */
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int buzzer_test(void)
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{
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PlayRingTone();
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return 0;
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}
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#ifdef FINSH_USING_MSH
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MSH_CMD_EXPORT(buzzer_test, Buzzer - Play ring tone);
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#endif
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#endif /* BOARD_USING_BUZZER */
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#if defined(BOARD_USING_SENSOR0)
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#include "ccap_sensor.h"
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#define SENSOR0_RST_PIN NU_GET_PININDEX(NU_PM, 1)
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#define SENSOR0_PD_PIN NU_GET_PININDEX(NU_PK, 8)
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ccap_sensor_io sIo_sensor0 =
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{
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.RstPin = SENSOR0_RST_PIN,
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.PwrDwnPin = SENSOR0_PD_PIN,
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.I2cName = "i2c3"
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};
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#endif /* BOARD_USING_SENSOR0 */
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#if defined(BOARD_USING_SENSOR1)
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#include "ccap_sensor.h"
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#define SENSOR1_RST_PIN NU_GET_PININDEX(NU_PN, 14)
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#define SENSOR1_PD_PIN NU_GET_PININDEX(NU_PD, 15)
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ccap_sensor_io sIo_sensor1 =
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{
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.RstPin = SENSOR1_RST_PIN,
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.PwrDwnPin = SENSOR1_PD_PIN,
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.I2cName = "i2c4"
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};
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#endif /* BOARD_USING_SENSOR1 */
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int rt_hw_sensors_port(void)
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{
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#if defined(BOARD_USING_SENSOR0)
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nu_ccap_sensor_create(&sIo_sensor0, (ccap_sensor_id)BOARD_USING_SENSON0_ID, "sensor0");
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#endif
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#if defined(BOARD_USING_SENSOR1)
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nu_ccap_sensor_create(&sIo_sensor1, (ccap_sensor_id)BOARD_USING_SENSON1_ID, "sensor1");
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#endif
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return 0;
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}
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INIT_COMPONENT_EXPORT(rt_hw_sensors_port);
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void nu_rtp_sspcc_setup(void)
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{
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SSPCC_SET_REALM(SSPCC_UART16, SSPCC_SSET_SUBM);
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SSPCC_SET_REALM(SSPCC_TMR23, SSPCC_SSET_SUBM);
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/* PDMA2/3 */
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SSPCC_SET_REALM(SSPCC_PDMA2, SSPCC_SSET_SUBM);
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SSPCC_SET_REALM(SSPCC_PDMA3, SSPCC_SSET_SUBM);
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/* UART16 Pins */
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SSPCC_SET_GPIO_REALM(PK, 0, SSPCC_SSET_SUBM);
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SSPCC_SET_GPIO_REALM(PK, 1, SSPCC_SSET_SUBM);
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SSPCC_SET_GPIO_REALM(PK, 2, SSPCC_SSET_SUBM);
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SSPCC_SET_GPIO_REALM(PK, 3, SSPCC_SSET_SUBM);
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/* LED_1 Pin */
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SSPCC_SET_GPIO_REALM(PJ, 15, SSPCC_SSET_SUBM);
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}
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#define CLK_CLKDIV0_DCUPDIV_2 CLK_CLKDIV0_DCUP(1)
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#define DISP_FRAMEBUFFERCONFIG0 (DISP_BASE + 0x1518U)
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#define DISP_OVERLAYCONFIG0 (DISP_BASE + 0x1540U)
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static S_NU_REG s_NuReg_arr[] =
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{
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/* DISP PIN */
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NUREG_EXPORT(SYS_GPH_MFPH, SYS_GPH_MFPH_PH15MFP_Msk, SYS_GPH_MFPH_PH15MFP_LCM_DATA23),
|
|
NUREG_EXPORT(SYS_GPH_MFPH, SYS_GPH_MFPH_PH14MFP_Msk, SYS_GPH_MFPH_PH14MFP_LCM_DATA22),
|
|
NUREG_EXPORT(SYS_GPH_MFPH, SYS_GPH_MFPH_PH13MFP_Msk, SYS_GPH_MFPH_PH13MFP_LCM_DATA21),
|
|
NUREG_EXPORT(SYS_GPH_MFPH, SYS_GPH_MFPH_PH12MFP_Msk, SYS_GPH_MFPH_PH12MFP_LCM_DATA20),
|
|
|
|
NUREG_EXPORT(SYS_GPC_MFPH, SYS_GPC_MFPH_PC15MFP_Msk, SYS_GPC_MFPH_PC15MFP_LCM_DATA19),
|
|
NUREG_EXPORT(SYS_GPC_MFPH, SYS_GPC_MFPH_PC14MFP_Msk, SYS_GPC_MFPH_PC14MFP_LCM_DATA18),
|
|
NUREG_EXPORT(SYS_GPC_MFPH, SYS_GPC_MFPH_PC13MFP_Msk, SYS_GPC_MFPH_PC13MFP_LCM_DATA17),
|
|
NUREG_EXPORT(SYS_GPC_MFPH, SYS_GPC_MFPH_PC12MFP_Msk, SYS_GPC_MFPH_PC12MFP_LCM_DATA16),
|
|
|
|
NUREG_EXPORT(SYS_GPH_MFPL, SYS_GPH_MFPL_PH7MFP_Msk, SYS_GPH_MFPL_PH7MFP_LCM_DATA15),
|
|
NUREG_EXPORT(SYS_GPH_MFPL, SYS_GPH_MFPL_PH6MFP_Msk, SYS_GPH_MFPL_PH6MFP_LCM_DATA14),
|
|
NUREG_EXPORT(SYS_GPH_MFPL, SYS_GPH_MFPL_PH5MFP_Msk, SYS_GPH_MFPL_PH5MFP_LCM_DATA13),
|
|
NUREG_EXPORT(SYS_GPH_MFPL, SYS_GPH_MFPL_PH4MFP_Msk, SYS_GPH_MFPL_PH4MFP_LCM_DATA12),
|
|
NUREG_EXPORT(SYS_GPH_MFPL, SYS_GPH_MFPL_PH3MFP_Msk, SYS_GPH_MFPL_PH3MFP_LCM_DATA11),
|
|
NUREG_EXPORT(SYS_GPH_MFPL, SYS_GPH_MFPL_PH2MFP_Msk, SYS_GPH_MFPL_PH2MFP_LCM_DATA10),
|
|
NUREG_EXPORT(SYS_GPH_MFPL, SYS_GPH_MFPL_PH1MFP_Msk, SYS_GPH_MFPL_PH1MFP_LCM_DATA9),
|
|
NUREG_EXPORT(SYS_GPH_MFPL, SYS_GPH_MFPL_PH0MFP_Msk, SYS_GPH_MFPL_PH0MFP_LCM_DATA8),
|
|
|
|
NUREG_EXPORT(SYS_GPI_MFPH, SYS_GPI_MFPH_PI15MFP_Msk, SYS_GPI_MFPH_PI15MFP_LCM_DATA7),
|
|
NUREG_EXPORT(SYS_GPI_MFPH, SYS_GPI_MFPH_PI14MFP_Msk, SYS_GPI_MFPH_PI14MFP_LCM_DATA6),
|
|
NUREG_EXPORT(SYS_GPI_MFPH, SYS_GPI_MFPH_PI13MFP_Msk, SYS_GPI_MFPH_PI13MFP_LCM_DATA5),
|
|
NUREG_EXPORT(SYS_GPI_MFPH, SYS_GPI_MFPH_PI12MFP_Msk, SYS_GPI_MFPH_PI12MFP_LCM_DATA4),
|
|
NUREG_EXPORT(SYS_GPI_MFPH, SYS_GPI_MFPH_PI11MFP_Msk, SYS_GPI_MFPH_PI11MFP_LCM_DATA3),
|
|
NUREG_EXPORT(SYS_GPI_MFPH, SYS_GPI_MFPH_PI10MFP_Msk, SYS_GPI_MFPH_PI10MFP_LCM_DATA2),
|
|
NUREG_EXPORT(SYS_GPI_MFPH, SYS_GPI_MFPH_PI9MFP_Msk, SYS_GPI_MFPH_PI9MFP_LCM_DATA1),
|
|
NUREG_EXPORT(SYS_GPI_MFPH, SYS_GPI_MFPH_PI8MFP_Msk, SYS_GPI_MFPH_PI8MFP_LCM_DATA0),
|
|
|
|
NUREG_EXPORT(SYS_GPK_MFPL, SYS_GPK_MFPL_PK4MFP_Msk, SYS_GPK_MFPL_PK4MFP_LCM_DEN),
|
|
|
|
NUREG_EXPORT(SYS_GPG_MFPH, SYS_GPG_MFPH_PG10MFP_Msk, SYS_GPG_MFPH_PG10MFP_LCM_CLK),
|
|
NUREG_EXPORT(SYS_GPG_MFPH, SYS_GPG_MFPH_PG9MFP_Msk, SYS_GPG_MFPH_PG9MFP_LCM_HSYNC),
|
|
NUREG_EXPORT(SYS_GPG_MFPH, SYS_GPG_MFPH_PG8MFP_Msk, SYS_GPG_MFPH_PG8MFP_LCM_VSYNC),
|
|
|
|
/* DISP CLK */
|
|
NUREG_EXPORT(CLK_SYSCLK0, CLK_SYSCLK0_DCUEN_Msk, CLK_SYSCLK0_DCUEN_Msk),
|
|
|
|
/* DISP Engine */
|
|
NUREG_EXPORT(DISP_FRAMEBUFFERCONFIG0, DISP_FrameBufferConfig0_UNDERFLOW_Msk, DISP_FrameBufferConfig0_UNDERFLOW_Msk),
|
|
NUREG_EXPORT(DISP_OVERLAYCONFIG0, DISP_OverlayConfig0_UNDERFLOW_Msk, DISP_OverlayConfig0_UNDERFLOW_Msk),
|
|
|
|
/* I2C5 */
|
|
NUREG_EXPORT(SYS_GPJ_MFPH, SYS_GPJ_MFPH_PJ12MFP_Msk, SYS_GPJ_MFPH_PJ12MFP_I2C5_SDA),
|
|
NUREG_EXPORT(SYS_GPJ_MFPH, SYS_GPJ_MFPH_PJ13MFP_Msk, SYS_GPJ_MFPH_PJ13MFP_I2C5_SCL),
|
|
|
|
/* GPD12, PM12 */
|
|
NUREG_EXPORT(SYS_GPD_MFPH, SYS_GPD_MFPH_PD12MFP_Msk, (0 << SYS_GPD_MFPH_PD12MFP_Pos)),
|
|
NUREG_EXPORT(SYS_GPM_MFPH, SYS_GPM_MFPH_PM12MFP_Msk, (0 << SYS_GPM_MFPH_PM12MFP_Pos)),
|
|
|
|
/* QSPI0 */
|
|
NUREG_EXPORT(CLK_CLKSEL4, CLK_CLKSEL4_QSPI0SEL_Msk, CLK_CLKSEL4_QSPI0SEL_PCLK0),
|
|
NUREG_EXPORT(CLK_APBCLK1, CLK_APBCLK1_QSPI0CKEN_Msk, CLK_APBCLK1_QSPI0CKEN_Msk),
|
|
NUREG_EXPORT(SYS_GPD_MFPL, SYS_GPD_MFPL_PD5MFP_Msk, SYS_GPD_MFPL_PD5MFP_QSPI0_MISO1),
|
|
NUREG_EXPORT(SYS_GPD_MFPL, SYS_GPD_MFPL_PD4MFP_Msk, SYS_GPD_MFPL_PD4MFP_QSPI0_MOSI1),
|
|
NUREG_EXPORT(SYS_GPD_MFPL, SYS_GPD_MFPL_PD3MFP_Msk, SYS_GPD_MFPL_PD3MFP_QSPI0_MISO0),
|
|
NUREG_EXPORT(SYS_GPD_MFPL, SYS_GPD_MFPL_PD2MFP_Msk, SYS_GPD_MFPL_PD2MFP_QSPI0_MOSI0),
|
|
NUREG_EXPORT(SYS_GPD_MFPL, SYS_GPD_MFPL_PD1MFP_Msk, SYS_GPD_MFPL_PD1MFP_QSPI0_CLK),
|
|
NUREG_EXPORT(SYS_GPD_MFPL, SYS_GPD_MFPL_PD0MFP_Msk, SYS_GPD_MFPL_PD0MFP_QSPI0_SS0),
|
|
|
|
/* TIMERn */
|
|
NUREG_EXPORT(CLK_APBCLK0, CLK_APBCLK0_TMR0CKEN_Msk, CLK_APBCLK0_TMR0CKEN_Msk),
|
|
NUREG_EXPORT(CLK_APBCLK0, CLK_APBCLK0_TMR1CKEN_Msk, CLK_APBCLK0_TMR1CKEN_Msk),
|
|
NUREG_EXPORT(CLK_APBCLK0, CLK_APBCLK0_TMR2CKEN_Msk, CLK_APBCLK0_TMR2CKEN_Msk),
|
|
NUREG_EXPORT(CLK_APBCLK0, CLK_APBCLK0_TMR3CKEN_Msk, CLK_APBCLK0_TMR3CKEN_Msk),
|
|
NUREG_EXPORT(CLK_APBCLK0, CLK_APBCLK0_TMR4CKEN_Msk, CLK_APBCLK0_TMR4CKEN_Msk),
|
|
NUREG_EXPORT(CLK_APBCLK0, CLK_APBCLK0_TMR5CKEN_Msk, CLK_APBCLK0_TMR5CKEN_Msk),
|
|
NUREG_EXPORT(CLK_APBCLK0, CLK_APBCLK0_TMR6CKEN_Msk, CLK_APBCLK0_TMR6CKEN_Msk),
|
|
NUREG_EXPORT(CLK_APBCLK0, CLK_APBCLK0_TMR7CKEN_Msk, CLK_APBCLK0_TMR7CKEN_Msk),
|
|
NUREG_EXPORT(CLK_APBCLK0, CLK_APBCLK0_TMR8CKEN_Msk, CLK_APBCLK0_TMR8CKEN_Msk),
|
|
NUREG_EXPORT(CLK_APBCLK0, CLK_APBCLK0_TMR9CKEN_Msk, CLK_APBCLK0_TMR9CKEN_Msk),
|
|
NUREG_EXPORT(CLK_APBCLK0, CLK_APBCLK0_TMR10CKEN_Msk, CLK_APBCLK0_TMR10CKEN_Msk),
|
|
NUREG_EXPORT(CLK_APBCLK0, CLK_APBCLK0_TMR11CKEN_Msk, CLK_APBCLK0_TMR11CKEN_Msk),
|
|
|
|
/* USB Host */
|
|
NUREG_EXPORT(CLK_SYSCLK0, CLK_SYSCLK0_USBHEN_Msk, CLK_SYSCLK0_USBHEN_Msk),
|
|
NUREG_EXPORT(CLK_SYSCLK0, CLK_SYSCLK0_HUSBH0EN_Msk, CLK_SYSCLK0_HUSBH0EN_Msk),
|
|
NUREG_EXPORT(CLK_SYSCLK0, CLK_SYSCLK0_HUSBH1EN_Msk, CLK_SYSCLK0_HUSBH1EN_Msk),
|
|
NUREG_EXPORT(SYS_USBPMISCR, SYS_USBPMISCR_PHY0SUSPEND_Msk, SYS_USBPMISCR_PHY0SUSPEND_Msk),
|
|
NUREG_EXPORT(SYS_USBPMISCR, SYS_USBPMISCR_PHY1SUSPEND_Msk, SYS_USBPMISCR_PHY1SUSPEND_Msk),
|
|
NUREG_EXPORT(SYS_GPL_MFPH, SYS_GPL_MFPH_PL12MFP_Msk, SYS_GPL_MFPH_PL12MFP_HSUSBH_PWREN),
|
|
NUREG_EXPORT(SYS_GPL_MFPH, SYS_GPL_MFPH_PL13MFP_Msk, SYS_GPL_MFPH_PL13MFP_HSUSBH_OVC),
|
|
|
|
/* SDH0 */
|
|
NUREG_EXPORT(CLK_SYSCLK0, CLK_SYSCLK0_SDH0EN_Msk, CLK_SYSCLK0_SDH0EN_Msk),
|
|
NUREG_EXPORT(CLK_CLKSEL0, CLK_CLKSEL0_SD0SEL_Msk, CLK_CLKSEL0_SD0SEL_APLL),
|
|
NUREG_EXPORT(CLK_CLKSEL0, CLK_CLKSEL0_SD0SEL_Msk, CLK_CLKSEL0_SD0SEL_SYSPLL),
|
|
|
|
NUREG_EXPORT(SYS_GPC_MFPL, SYS_GPC_MFPL_PC7MFP_Msk, SYS_GPC_MFPL_PC7MFP_SD0_WP),
|
|
NUREG_EXPORT(SYS_GPC_MFPL, SYS_GPC_MFPL_PC6MFP_Msk, SYS_GPC_MFPL_PC6MFP_SD0_nCD),
|
|
NUREG_EXPORT(SYS_GPC_MFPL, SYS_GPC_MFPL_PC5MFP_Msk, SYS_GPC_MFPL_PC5MFP_SD0_DAT3),
|
|
NUREG_EXPORT(SYS_GPC_MFPL, SYS_GPC_MFPL_PC4MFP_Msk, SYS_GPC_MFPL_PC4MFP_SD0_DAT2),
|
|
NUREG_EXPORT(SYS_GPC_MFPL, SYS_GPC_MFPL_PC3MFP_Msk, SYS_GPC_MFPL_PC3MFP_SD0_DAT1),
|
|
NUREG_EXPORT(SYS_GPC_MFPL, SYS_GPC_MFPL_PC2MFP_Msk, SYS_GPC_MFPL_PC2MFP_SD0_DAT0),
|
|
NUREG_EXPORT(SYS_GPC_MFPL, SYS_GPC_MFPL_PC1MFP_Msk, SYS_GPC_MFPL_PC1MFP_SD0_CLK),
|
|
NUREG_EXPORT(SYS_GPC_MFPL, SYS_GPC_MFPL_PC0MFP_Msk, SYS_GPC_MFPL_PC0MFP_SD0_CMD),
|
|
|
|
/* SDH1 */
|
|
NUREG_EXPORT(CLK_SYSCLK0, CLK_SYSCLK0_SDH1EN_Msk, CLK_SYSCLK0_SDH1EN_Msk),
|
|
NUREG_EXPORT(CLK_CLKSEL0, CLK_CLKSEL0_SD1SEL_Msk, CLK_CLKSEL0_SD1SEL_APLL),
|
|
NUREG_EXPORT(CLK_CLKSEL0, CLK_CLKSEL0_SD1SEL_Msk, CLK_CLKSEL0_SD1SEL_SYSPLL),
|
|
|
|
NUREG_EXPORT(SYS_GPJ_MFPH, SYS_GPJ_MFPH_PJ11MFP_Msk, SYS_GPJ_MFPH_PJ11MFP_SD1_DAT3),
|
|
NUREG_EXPORT(SYS_GPJ_MFPH, SYS_GPJ_MFPH_PJ10MFP_Msk, SYS_GPJ_MFPH_PJ10MFP_SD1_DAT2),
|
|
NUREG_EXPORT(SYS_GPJ_MFPH, SYS_GPJ_MFPH_PJ9MFP_Msk, SYS_GPJ_MFPH_PJ9MFP_SD1_DAT1),
|
|
NUREG_EXPORT(SYS_GPJ_MFPH, SYS_GPJ_MFPH_PJ8MFP_Msk, SYS_GPJ_MFPH_PJ8MFP_SD1_DAT0),
|
|
NUREG_EXPORT(SYS_GPJ_MFPL, SYS_GPJ_MFPL_PJ7MFP_Msk, SYS_GPJ_MFPL_PJ7MFP_SD1_CLK),
|
|
NUREG_EXPORT(SYS_GPJ_MFPL, SYS_GPJ_MFPL_PJ6MFP_Msk, SYS_GPJ_MFPL_PJ6MFP_SD1_CMD),
|
|
NUREG_EXPORT(SYS_GPJ_MFPL, SYS_GPJ_MFPL_PJ5MFP_Msk, SYS_GPJ_MFPL_PJ5MFP_SD1_nCD),
|
|
NUREG_EXPORT(SYS_GPJ_MFPL, SYS_GPJ_MFPL_PJ4MFP_Msk, SYS_GPJ_MFPL_PJ4MFP_SD1_WP),
|
|
|
|
/* UART11 */
|
|
NUREG_EXPORT(SYS_GPL_MFPL, SYS_GPL_MFPL_PL0MFP_Msk, SYS_GPL_MFPL_PL0MFP_UART11_nCTS),
|
|
NUREG_EXPORT(SYS_GPL_MFPL, SYS_GPL_MFPL_PL1MFP_Msk, SYS_GPL_MFPL_PL1MFP_UART11_nRTS),
|
|
NUREG_EXPORT(SYS_GPL_MFPL, SYS_GPL_MFPL_PL2MFP_Msk, SYS_GPL_MFPL_PL2MFP_UART11_RXD),
|
|
NUREG_EXPORT(SYS_GPL_MFPL, SYS_GPL_MFPL_PL3MFP_Msk, SYS_GPL_MFPL_PL3MFP_UART11_TXD),
|
|
|
|
NUREG_EXPORT(CLK_CLKSEL3, CLK_CLKSEL3_UART11SEL_Msk, CLK_CLKSEL3_UART11SEL_HXT),
|
|
NUREG_EXPORT(CLK_APBCLK0, CLK_APBCLK0_UART11CKEN_Msk, CLK_APBCLK0_UART11CKEN_Msk),
|
|
|
|
/* WDT */
|
|
NUREG_EXPORT(CLK_CLKSEL3, CLK_CLKSEL3_WDT0SEL_Msk, CLK_CLKSEL3_WDT0SEL_PCLK3_DIV4096),
|
|
|
|
/* GMAC0 */
|
|
NUREG_EXPORT(SYS_GPE_MFPL, SYS_GPE_MFPL_PE0MFP_Msk, SYS_GPE_MFPL_PE0MFP_RGMII0_MDC),
|
|
NUREG_EXPORT(SYS_GPE_MFPL, SYS_GPE_MFPL_PE1MFP_Msk, SYS_GPE_MFPL_PE1MFP_RGMII0_MDIO),
|
|
NUREG_EXPORT(SYS_GPE_MFPL, SYS_GPE_MFPL_PE2MFP_Msk, SYS_GPE_MFPL_PE2MFP_RGMII0_TXCTL),
|
|
NUREG_EXPORT(SYS_GPE_MFPL, SYS_GPE_MFPL_PE3MFP_Msk, SYS_GPE_MFPL_PE3MFP_RGMII0_TXD0),
|
|
NUREG_EXPORT(SYS_GPE_MFPL, SYS_GPE_MFPL_PE4MFP_Msk, SYS_GPE_MFPL_PE4MFP_RGMII0_TXD1),
|
|
NUREG_EXPORT(SYS_GPE_MFPL, SYS_GPE_MFPL_PE5MFP_Msk, SYS_GPE_MFPL_PE5MFP_RGMII0_RXCLK),
|
|
NUREG_EXPORT(SYS_GPE_MFPL, SYS_GPE_MFPL_PE6MFP_Msk, SYS_GPE_MFPL_PE6MFP_RGMII0_RXCTL),
|
|
NUREG_EXPORT(SYS_GPE_MFPL, SYS_GPE_MFPL_PE7MFP_Msk, SYS_GPE_MFPL_PE7MFP_RGMII0_RXD0),
|
|
NUREG_EXPORT(SYS_GPE_MFPH, SYS_GPE_MFPH_PE8MFP_Msk, SYS_GPE_MFPH_PE8MFP_RGMII0_RXD1),
|
|
NUREG_EXPORT(SYS_GPE_MFPH, SYS_GPE_MFPH_PE9MFP_Msk, SYS_GPE_MFPH_PE9MFP_RGMII0_RXD2),
|
|
NUREG_EXPORT(SYS_GPE_MFPH, SYS_GPE_MFPH_PE10MFP_Msk, SYS_GPE_MFPH_PE10MFP_RGMII0_RXD3),
|
|
NUREG_EXPORT(SYS_GPE_MFPH, SYS_GPE_MFPH_PE11MFP_Msk, SYS_GPE_MFPH_PE11MFP_RGMII0_TXCLK),
|
|
NUREG_EXPORT(SYS_GPE_MFPH, SYS_GPE_MFPH_PE12MFP_Msk, SYS_GPE_MFPH_PE12MFP_RGMII0_TXD2),
|
|
NUREG_EXPORT(SYS_GPE_MFPH, SYS_GPE_MFPH_PE13MFP_Msk, SYS_GPE_MFPH_PE13MFP_RGMII0_TXD3),
|
|
NUREG_EXPORT(SYS_GPE_MFPH, SYS_GPE_MFPH_PE13MFP_Msk, SYS_GPE_MFPH_PE13MFP_RGMII0_TXD3),
|
|
NUREG_EXPORT(CLK_SYSCLK0, CLK_SYSCLK0_GMAC0EN_Msk, CLK_SYSCLK0_GMAC0EN_Msk),
|
|
NUREG_EXPORT(CLK_SYSCLK1, CLK_SYSCLK1_GPECKEN_Msk, CLK_SYSCLK1_GPECKEN_Msk),
|
|
NUREG_EXPORT(CLK_CLKDIV0, CLK_CLKDIV0_EMAC0DIV_Msk, 0 << CLK_CLKDIV0_EMAC0DIV_Pos), //RGMII
|
|
|
|
/* GMAC1 */
|
|
NUREG_EXPORT(SYS_GPF_MFPL, SYS_GPF_MFPL_PF0MFP_Msk, SYS_GPF_MFPL_PF0MFP_RGMII1_MDC),
|
|
NUREG_EXPORT(SYS_GPF_MFPL, SYS_GPF_MFPL_PF1MFP_Msk, SYS_GPF_MFPL_PF1MFP_RGMII1_MDIO),
|
|
NUREG_EXPORT(SYS_GPF_MFPL, SYS_GPF_MFPL_PF2MFP_Msk, SYS_GPF_MFPL_PF2MFP_RGMII1_TXCTL),
|
|
NUREG_EXPORT(SYS_GPF_MFPL, SYS_GPF_MFPL_PF3MFP_Msk, SYS_GPF_MFPL_PF3MFP_RGMII1_TXD0),
|
|
NUREG_EXPORT(SYS_GPF_MFPL, SYS_GPF_MFPL_PF4MFP_Msk, SYS_GPF_MFPL_PF4MFP_RGMII1_TXD1),
|
|
NUREG_EXPORT(SYS_GPF_MFPL, SYS_GPF_MFPL_PF5MFP_Msk, SYS_GPF_MFPL_PF5MFP_RGMII1_RXCLK),
|
|
NUREG_EXPORT(SYS_GPF_MFPL, SYS_GPF_MFPL_PF6MFP_Msk, SYS_GPF_MFPL_PF6MFP_RGMII1_RXCTL),
|
|
NUREG_EXPORT(SYS_GPF_MFPL, SYS_GPF_MFPL_PF7MFP_Msk, SYS_GPF_MFPL_PF7MFP_RGMII1_RXD0),
|
|
NUREG_EXPORT(SYS_GPF_MFPH, SYS_GPF_MFPH_PF8MFP_Msk, SYS_GPF_MFPH_PF8MFP_RGMII1_RXD1),
|
|
NUREG_EXPORT(SYS_GPF_MFPH, SYS_GPF_MFPH_PF9MFP_Msk, SYS_GPF_MFPH_PF9MFP_RGMII1_RXD2),
|
|
NUREG_EXPORT(SYS_GPF_MFPH, SYS_GPF_MFPH_PF10MFP_Msk, SYS_GPF_MFPH_PF10MFP_RGMII1_RXD3),
|
|
NUREG_EXPORT(SYS_GPF_MFPH, SYS_GPF_MFPH_PF11MFP_Msk, SYS_GPF_MFPH_PF11MFP_RGMII1_TXCLK),
|
|
NUREG_EXPORT(SYS_GPF_MFPH, SYS_GPF_MFPH_PF12MFP_Msk, SYS_GPF_MFPH_PF12MFP_RGMII1_TXD2),
|
|
NUREG_EXPORT(SYS_GPF_MFPH, SYS_GPF_MFPH_PF13MFP_Msk, SYS_GPF_MFPH_PF13MFP_RGMII1_TXD3),
|
|
NUREG_EXPORT(CLK_SYSCLK0, CLK_SYSCLK0_GMAC1EN_Msk, CLK_SYSCLK0_GMAC1EN_Msk),
|
|
NUREG_EXPORT(CLK_SYSCLK1, CLK_SYSCLK1_GPFCKEN_Msk, CLK_SYSCLK1_GPFCKEN_Msk),
|
|
NUREG_EXPORT(CLK_CLKDIV0, CLK_CLKDIV0_EMAC1DIV_Msk, 0 << CLK_CLKDIV0_EMAC1DIV_Pos), //RGMII
|
|
|
|
/* CANFD0 CLK */
|
|
NUREG_EXPORT(CLK_SYSCLK0, CLK_SYSCLK0_CANFD0CKEN_Msk, CLK_SYSCLK0_CANFD0CKEN_Msk),
|
|
NUREG_EXPORT(CLK_CLKSEL4, CLK_CLKSEL4_CANFD0SEL_Msk, CLK_CLKSEL4_CANFD0SEL_APLL),
|
|
NUREG_EXPORT(CLK_CLKDIV0, CLK_CLKDIV0_CANFD0DIV_Msk, CLK_CLKDIV0_CANFD0(1)),
|
|
|
|
{0}
|
|
};
|
|
|
|
void nu_check_register(void)
|
|
{
|
|
nu_sys_check_register(&s_NuReg_arr[0]);
|
|
}
|
|
MSH_CMD_EXPORT(nu_check_register, Check registers);
|
|
|