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74 lines
2.0 KiB
74 lines
2.0 KiB
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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*/
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#ifndef __DM9000_H__
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#define __DM9000_H__
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/*MACRO DEFINATIONS*/
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#define SEP4020_ID_EMAC ((unsigned int) 28) // Ethernet Mac
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/* Davicom 9161 PHY */
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#define MII_DM9161_ID 0x0181b880
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#define MII_DM9161A_ID 0x0181b8a0
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/* Davicom specific registers */
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#define MII_DSCR_REG 16
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#define MII_DSCSR_REG 17
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#define MII_DSINTR_REG 21
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/* Intel LXT971A PHY */
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#define MII_LXT971A_ID 0x001378E0
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/* Intel specific registers */
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#define MII_ISINTE_REG 18
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#define MII_ISINTS_REG 19
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#define MII_LEDCTRL_REG 20
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/* Realtek RTL8201 PHY */
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#define MII_RTL8201_ID 0x00008200
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/* Broadcom BCM5221 PHY */
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#define MII_BCM5221_ID 0x004061e0
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/* Broadcom specific registers */
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#define MII_BCMINTR_REG 26
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/* National Semiconductor DP83847 */
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#define MII_DP83847_ID 0x20005c30
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/* Altima AC101L PHY */
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#define MII_AC101L_ID 0x00225520
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/* Micrel KS8721 PHY */
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#define MII_KS8721_ID 0x00221610
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/* ........................................................................ */
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#define MAX_RBUFF_SZ 0x600 /* 1518 rounded up */
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#define MAX_RX_DESCR 20 /* max number of receive buffers */
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#define MAX_TBUFF_SZ 0x600 /* 1518 rounded up */
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#define MAX_TX_DESCR 20 /* max number of receive buffers */
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#define EMAC_DESC_DONE 0x00000001 /* bit for if DMA is done */
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#define EMAC_DESC_WRAP 0x00000002 /* bit for wrap */
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#define EMAC_BROADCAST 0x80000000 /* broadcast address */
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#define EMAC_MULTICAST 0x40000000 /* multicast address */
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#define EMAC_UNICAST 0x20000000 /* unicast address */
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#define DM9161_inb(r) (*(volatile rt_uint8_t *)r)
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#define DM9161_outb(r, d) (*(volatile rt_uint8_t *)r = d)
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#define DM9161_inw(r) (*(volatile rt_uint16_t *)r)
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#define DM9161_outw(r, d) (*(volatile rt_uint16_t *)r = d)
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void rt_hw_dm9616_init(void);
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#endif
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