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718 lines
20 KiB
718 lines
20 KiB
/* ****************************************************************************
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* Copyright (C) 2014-2018 Maxim Integrated Products, Inc., All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
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* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Except as contained in this notice, the name of Maxim Integrated
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* Products, Inc. shall not be used except as stated in the Maxim Integrated
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* Products, Inc. Branding Policy.
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*
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* The mere transfer of this software does not imply any licenses
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* of trade secrets, proprietary technology, copyrights, patents,
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* trademarks, maskwork rights, or any other form of intellectual
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* property whatsoever. Maxim Integrated Products, Inc. retains all
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* ownership rights.
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*
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* $Date: 2020-09-08 13:28:39 -0500 (Tue, 08 Sep 2020) $
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* $Revision: 55611 $
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*
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*************************************************************************** */
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/* **** Includes **** */
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#include <stdint.h>
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#include <string.h>
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#include "mxc_config.h"
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#include "mxc_assert.h"
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#include "uart_regs.h"
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#include "uart.h"
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#include "mxc_lock.h"
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#include "mxc_sys.h"
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/* **** Definitions **** */
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#define UART_ER_IF (MXC_F_UART_INT_FL_RX_FRAME_ERROR | \
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MXC_F_UART_INT_FL_RX_PARITY_ERROR | \
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MXC_F_UART_INT_FL_RX_OVERRUN)
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#define UART_ER_IE (MXC_F_UART_INT_EN_RX_FRAME_ERROR | \
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MXC_F_UART_INT_EN_RX_PARITY_ERROR | \
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MXC_F_UART_INT_EN_RX_OVERRUN )
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#define UART_RX_IF (MXC_F_UART_INT_FL_RX_FIFO_THRESH)
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#define UART_RX_IE (MXC_F_UART_INT_EN_RX_FIFO_THRESH)
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#define UART_TX_IF (MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY | \
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MXC_F_UART_INT_FL_TX_FIFO_THRESH)
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#define UART_TX_IE (MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY | \
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MXC_F_UART_INT_EN_TX_FIFO_THRESH)
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#if (TARGET == 32660) || (TARGET == 32665)
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#define MAX_FACTOR 3
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#else
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#define MAX_FACTOR 7
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#endif
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/* **** File Scope Data **** */
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// Saves the state of the non-blocking read requests.
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static uart_req_t *rx_states[MXC_UART_INSTANCES];
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// Saves the state of the non-blocking write requests.
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static uart_req_t *tx_states[MXC_UART_INSTANCES];
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/* **** Functions **** */
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static void UART_WriteHandler(mxc_uart_regs_t *uart, uart_req_t *req, int uart_num);
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static void UART_ReadHandler(mxc_uart_regs_t *uart, uart_req_t *req, int uart_num,
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uint32_t flags);
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static uint32_t uart_error_check(mxc_uart_regs_t *uart);
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static void uart_error_clear(mxc_uart_regs_t *uart);
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/* ************************************************************************* */
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uint32_t uart_error_check(mxc_uart_regs_t *uart)
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{
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return (uart->int_fl & UART_ER_IF);
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}
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/* ************************************************************************* */
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void uart_error_clear(mxc_uart_regs_t *uart)
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{
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UART_ClearFlags(uart,UART_ER_IF);
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}
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/* ************************************************************************* */
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int UART_Init(mxc_uart_regs_t *uart, const uart_cfg_t *cfg, const sys_cfg_uart_t* sys_cfg)
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{
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int err;
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int uart_num;
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uint32_t baud0 = 0, baud1 = 0,div;
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int32_t factor = -1;
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// Get the state array index
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uart_num = MXC_UART_GET_IDX(uart);
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if (uart_num == -1) {
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return E_BAD_PARAM;
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}
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if ((err = SYS_UART_Init(uart, sys_cfg)) != E_NO_ERROR) {
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return err;
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}
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// Initialize state pointers
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rx_states[uart_num] = NULL;
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tx_states[uart_num] = NULL;
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// Drain FIFOs, enable UART, and set configuration
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uart->ctrl = (MXC_F_UART_CTRL_ENABLE | cfg->parity | cfg->size | cfg->stop | cfg->flow | cfg->pol);
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// Set the baud rate
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// Calculate divisor
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#if (TARGET != 32660)
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uart->ctrl |= cfg->clksel;
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if (cfg->clksel == UART_CLKSEL_ALTERNATE) {
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div = UART_ALTERNATE_CLOCK_HZ / ((cfg->baud));
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} else {
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div = PeripheralClock / ((cfg->baud));
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}
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#else
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div = PeripheralClock / ((cfg->baud));
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#endif
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// Search for integer and fractional baud rate registers based on divisor
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do {
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factor += 1;
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baud0 = div >> (7-factor); // divide by 128,64,32,16 to extract integer part
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baud1 = ((div << factor) - (baud0 << 7)); //subtract factor corrected div - integer parts
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} while ((baud0 == 0) && (factor < MAX_FACTOR));
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uart->baud0 = ((factor << MXC_F_UART_BAUD0_FACTOR_POS) | baud0);
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#if (TARGET == 32660) || (TARGET == 32665) || (TARGET == 32650)
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/* Erratum:
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* Hardware bug causes exact baud rates to generate framing error. Slightly mis-adjust timing
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* to help avoid this bug.
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*/
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if (baud1 > 3) {
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uart->baud1 = baud1 - 3;
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} else {
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uart->baud1 = baud1 + 3;
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}
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#else
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uart->baud1 = baud1;
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#endif
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// Clear pending requests
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rx_states[uart_num] = NULL;
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tx_states[uart_num] = NULL;
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return E_NO_ERROR;
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}
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/* ************************************************************************* */
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int UART_Shutdown(mxc_uart_regs_t *uart)
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{
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int uart_num;
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uart_req_t *temp_req;
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// Get the state array index
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uart_num = MXC_UART_GET_IDX(uart);
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if (uart_num < 0) {
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return E_BAD_PARAM;
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}
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// Disable interrupts
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uart->int_en = 0;
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// Flush RX and TX FIFOS
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uart->ctrl |= (MXC_F_UART_CTRL_TX_FLUSH | MXC_F_UART_CTRL_RX_FLUSH);
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// Call all of the pending callbacks for this UART
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if(rx_states[uart_num] != NULL) {
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// Save the request
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temp_req = rx_states[uart_num];
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// Unlock this UART to read
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mxc_free_lock((uint32_t*)&rx_states[uart_num]);
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// Callback if not NULL
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if (temp_req->callback != NULL) {
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temp_req->callback(temp_req, E_SHUTDOWN);
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}
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}
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if (tx_states[uart_num] != NULL) {
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// Save the request
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temp_req = tx_states[uart_num];
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// Unlock this UART to write
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mxc_free_lock((uint32_t*)&tx_states[uart_num]);
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// Callback if not NULL
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if (temp_req->callback != NULL) {
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temp_req->callback(temp_req, E_SHUTDOWN);
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}
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}
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// Wait for not busy
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while (uart->status & (MXC_F_UART_STATUS_TX_BUSY | MXC_F_UART_STATUS_RX_BUSY)) {
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}
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// Shutdown the UART
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uart->ctrl = 0;
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// Shutdown any system level setup
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SYS_UART_Shutdown(uart);
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// Clear pending requests
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rx_states[uart_num] = NULL;
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tx_states[uart_num] = NULL;
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return E_NO_ERROR;
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}
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/* ************************************************************************* */
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void UART_Handler(mxc_uart_regs_t *uart)
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{
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int uart_num; // Holds the current index of rx_states or tx_states
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uint32_t intst;
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// Get the state array index
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uart_num = MXC_UART_GET_IDX(uart);
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if (uart_num == -1) {
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return;
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}
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// Read and clear interrupts
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intst = uart->int_fl;
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uart->int_fl = intst;
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// Read interrupt
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if (intst & (UART_RX_IF | UART_ER_IF)) {
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UART_ReadHandler(uart, rx_states[uart_num], uart_num, intst);
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}
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// Write Interrupt
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if (intst & (UART_TX_IF | UART_ER_IF)) {
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UART_WriteHandler(uart, tx_states[uart_num], uart_num);
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}
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}
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/* ************************************************************************* */
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static void UART_WriteHandler(mxc_uart_regs_t *uart, uart_req_t *req, int uart_num)
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{
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int remain, avail;
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req = tx_states[uart_num];
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if (req == NULL) {
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// Nothing to do
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uart->int_en &= ~MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY; // disable interrupt
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return;
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}
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// Refill the TX FIFO
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avail = UART_NumWriteAvail(uart);
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remain = req->len - req->num;
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while (avail && remain) {
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uart->fifo = req->data[req->num++];
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remain--;
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avail--;
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}
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// See if we've sent all of the characters
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if (req->len == req->num) {
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// Disable interrupts
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uart->int_en &= ~MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY;
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// Deinit state before callback in case another is requested
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tx_states[uart_num] = NULL;
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mxc_free_lock((uint32_t*)&tx_states[uart_num]);
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// Callback when we've written all the characters
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if (req->callback != NULL) {
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req->callback(req, E_NO_ERROR);
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}
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}
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// Enable the interrupts
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uart->int_en |= UART_TX_IE | UART_ER_IE;
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}
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/* ************************************************************************* */
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static void UART_ReadHandler(mxc_uart_regs_t *uart, uart_req_t *req, int uart_num,
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uint32_t flags)
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{
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int remain, avail;
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if (req == NULL) {
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// Nothing to do
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uart->int_en &= ~(UART_RX_IE | UART_ER_IE); // disable interrupts
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return;
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}
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// Save the data in the FIFO while we still need data
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avail = UART_NumReadAvail(uart);
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remain = req->len - req->num;
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while (avail && remain) {
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req->data[req->num++] = uart->fifo;
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remain--;
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avail--;
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}
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// Check for errors
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if (flags & MXC_F_UART_INT_FL_RX_OVERRUN) {
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// Unlock this UART to read
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mxc_free_lock((uint32_t*)&rx_states[uart_num]);
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if (req->callback != NULL) {
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req->callback(req, E_OVERFLOW);
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}
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return;
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}
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if (flags & (MXC_F_UART_INT_FL_RX_FRAME_ERROR |
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MXC_F_UART_INT_FL_RX_PARITY_ERROR)) {
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// Unlock this UART to read
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mxc_free_lock((uint32_t*)&rx_states[uart_num]);
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if (req->callback != NULL) {
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req->callback(req, E_COMM_ERR);
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}
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return;
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}
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// Check to see if we've received all of the characters.
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if (req->num == req->len) {
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// Disable interrupts
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uart->int_en &= ~(UART_RX_IE | UART_ER_IE);
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// Deinit state before callback in case another is requested
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rx_states[uart_num] = NULL;
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// Call the callback function
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if (req->callback != NULL) {
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req->callback(req, E_NO_ERROR);
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}
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return;
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} else if (req->num > (req->len - MXC_UART_FIFO_DEPTH)) {
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// Set RX threshold less than FIFO_DEPTH characters if needed
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uart->thresh_ctrl = ((req->len - req->num)<<
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MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS);
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} else {
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uart->thresh_ctrl = MXC_UART_FIFO_DEPTH<<
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MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS;
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}
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}
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/* ************************************************************************* */
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int UART_Read(mxc_uart_regs_t *uart, uint8_t *data, int len, int *num)
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{
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int uart_num; // Holds the current index of rx_states
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int char_read = 0; // Holds the number of characters successfully read
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int error_code =0; // Holds the error to return while reading
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// Get the state array index
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uart_num = MXC_UART_GET_IDX(uart);
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if (uart_num < 0) {
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return E_BAD_PARAM;
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}
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// Check to make sure baud rate has been set
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if (uart->baud0 == 0) {
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return E_UNINITIALIZED;
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}
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// Check data pointer
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if (data == NULL) {
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return E_BAD_PARAM;
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}
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// Check if there is already a request in progress
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if (rx_states[uart_num] != NULL) {
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return E_BUSY;
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}
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// Lock this UART from reading
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while (mxc_get_lock((uint32_t*)&rx_states[uart_num], 1) != E_NO_ERROR) {
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}
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// Get bytes FIFO
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while (char_read < len) {
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// Wait for RXFIFO to not be empty
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while (uart->status & MXC_F_UART_STATUS_RX_EMPTY) {
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// Check for error
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if (uart_error_check(uart) != E_NO_ERROR) {
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if (uart->int_fl & MXC_F_UART_INT_FL_RX_OVERRUN) {
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error_code = E_OVERFLOW;
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} else {
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error_code = E_COMM_ERR;
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}
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uart_error_clear(uart);
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mxc_free_lock((uint32_t*)&rx_states[uart_num]);
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return error_code;
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}
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}
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data[char_read] = uart->fifo;
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char_read++;
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}
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if (num != NULL) {
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*num = char_read;
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}
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// Unlock this UART to read
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mxc_free_lock((uint32_t*)&rx_states[uart_num]);
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return char_read;
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}
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/* ************************************************************************* */
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uint8_t UART_ReadByte(mxc_uart_regs_t *uart)
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{
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while (uart->status & MXC_F_UART_STATUS_RX_EMPTY) {}
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return uart->fifo;
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}
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/* ************************************************************************* */
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int UART_Write(mxc_uart_regs_t *uart, const uint8_t *data, int len)
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{
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int uart_num; // Holds the current index of tx_states
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int char_written = 0; // Holds the number of characters successfully written
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// Get the state array index
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uart_num = MXC_UART_GET_IDX(uart);
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if (uart_num < 0) {
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return E_BAD_PARAM;
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}
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// Check to make sure baud rate has been set
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if (uart->baud0 == 0) {
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return E_UNINITIALIZED;
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}
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// Check data pointer
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if (data == NULL) {
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return E_BAD_PARAM;
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}
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// Check if there is already a request in progress
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if (tx_states[uart_num] != NULL) {
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return E_BUSY;
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}
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// Lock this UART from writing
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while (mxc_get_lock((uint32_t*)&tx_states[uart_num], 1) != E_NO_ERROR) {
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}
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// Clear errors
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uart_error_clear(uart);
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// Put bytes into FIFO
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while (char_written < len) {
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UART_WriteByte(uart,data[char_written]);
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char_written++;
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}
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// Unlock this UART to write
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mxc_free_lock((uint32_t*)&tx_states[uart_num]);
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return char_written;
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}
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/* ************************************************************************* */
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void UART_WriteByte(mxc_uart_regs_t *uart, uint8_t data)
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{
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// Wait for TXFIFO if full
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while (uart->status & MXC_F_UART_STATUS_TX_FULL) {
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}
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// Put data into fifo
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uart->fifo = data;
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}
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/* ************************************************************************* */
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int UART_ReadAsync(mxc_uart_regs_t *uart, uart_req_t *req)
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{
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int uart_num; // Holds the current index of tx_states
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uint32_t flags; // Holds the Interrupt flags
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// Check data pointer
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if (req == NULL) {
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return E_BAD_PARAM;
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}
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// Get the state array index
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uart_num = MXC_UART_GET_IDX(uart);
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if (uart_num < 0) {
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return E_BAD_PARAM;
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}
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if (req->data == NULL) {
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return E_NULL_PTR;
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}
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|
// Check to make sure baud rate has been set
|
|
if (uart->baud0 == 0) {
|
|
return E_UNINITIALIZED;
|
|
}
|
|
|
|
// Check if there is already a request in progress
|
|
if (rx_states[uart_num] != NULL) {
|
|
return E_BUSY;
|
|
}
|
|
|
|
if (!(req->len > 0)) {
|
|
return E_NO_ERROR;
|
|
}
|
|
|
|
// Attempt to register this write request
|
|
if (mxc_get_lock((uint32_t*)&rx_states[uart_num], (uint32_t)req) != E_NO_ERROR) {
|
|
return E_BUSY;
|
|
}
|
|
|
|
// Clear the data counter
|
|
req->num = 0;
|
|
|
|
// Clear Interrupt Flags
|
|
flags = uart->int_fl;
|
|
uart->int_fl = flags;
|
|
UART_ReadHandler(uart,req,uart_num,flags);
|
|
|
|
// Enable the interrupts
|
|
uart->int_en |= UART_RX_IE | UART_ER_IE;
|
|
|
|
return E_NO_ERROR;
|
|
}
|
|
|
|
/* ************************************************************************* */
|
|
int UART_WriteAsync(mxc_uart_regs_t *uart, uart_req_t *req)
|
|
{
|
|
int uart_num; // Holds the current index of tx_states
|
|
|
|
// Check data pointer
|
|
if (req == NULL) {
|
|
return E_BAD_PARAM;
|
|
}
|
|
|
|
// Get the state array index
|
|
uart_num = MXC_UART_GET_IDX(uart);
|
|
if (uart_num < 0) {
|
|
return E_BAD_PARAM;
|
|
}
|
|
|
|
if (req->data == NULL) {
|
|
return E_NULL_PTR;
|
|
}
|
|
// Check to make sure baud rate has been set
|
|
if (uart->baud0 == 0) {
|
|
return E_UNINITIALIZED;
|
|
}
|
|
|
|
// Check if there is already a request in progress
|
|
if (tx_states[uart_num] != NULL) {
|
|
return E_BUSY;
|
|
}
|
|
if (!(req->len > 0)) {
|
|
return E_NO_ERROR;
|
|
}
|
|
// Attempt to register this write request
|
|
if (mxc_get_lock((uint32_t*)&tx_states[uart_num], (uint32_t)req) != E_NO_ERROR) {
|
|
return E_BUSY;
|
|
}
|
|
|
|
// Clear the data counter
|
|
req->num = 0;
|
|
UART_WriteHandler(uart, req, uart_num);
|
|
|
|
return E_NO_ERROR;
|
|
}
|
|
|
|
/* ************************************************************************* */
|
|
int UART_Busy(mxc_uart_regs_t *uart)
|
|
{
|
|
int uart_num = MXC_UART_GET_IDX(uart); // Holds the current index of tx_states
|
|
MXC_ASSERT(uart_num >= 0);
|
|
if ((uart->status & MXC_F_UART_STATUS_TX_BUSY) || (uart->status & MXC_F_UART_STATUS_RX_BUSY)) {
|
|
return E_BUSY;
|
|
}
|
|
// Check to see if there are any ongoing transactions and the UART has room in its FIFO
|
|
if ((tx_states[uart_num] == NULL) &&
|
|
!(uart->status & MXC_F_UART_STATUS_TX_FULL)) {
|
|
|
|
return E_NO_ERROR;
|
|
}
|
|
|
|
return E_BUSY;
|
|
}
|
|
|
|
/* ************************************************************************* */
|
|
int UART_PrepForSleep(mxc_uart_regs_t *uart)
|
|
{
|
|
if (UART_Busy(uart) != E_NO_ERROR) {
|
|
return E_BUSY;
|
|
}
|
|
|
|
// Leave read interrupts enabled, if already enabled
|
|
uart->int_en &= (UART_RX_IE | UART_ER_IE);
|
|
|
|
return E_NO_ERROR;
|
|
}
|
|
|
|
/* ************************************************************************* */
|
|
int UART_AbortAsync(uart_req_t *req)
|
|
{
|
|
int uart_num;
|
|
|
|
// Figure out if this was a read or write request, find the request, set to NULL
|
|
for (uart_num = 0; uart_num < MXC_UART_INSTANCES; uart_num++) {
|
|
if (req == rx_states[uart_num]) {
|
|
|
|
// Disable read interrupts, clear flags.
|
|
MXC_UART_GET_UART(uart_num)->int_en &= ~(UART_RX_IE | UART_ER_IE);
|
|
MXC_UART_GET_UART(uart_num)->int_fl = (UART_RX_IF | UART_ER_IF);
|
|
|
|
// Unlock this UART to read
|
|
mxc_free_lock((uint32_t*)&rx_states[uart_num]);
|
|
|
|
// Callback if not NULL
|
|
if (req->callback != NULL) {
|
|
req->callback(req, E_ABORT);
|
|
}
|
|
|
|
return E_NO_ERROR;
|
|
}
|
|
|
|
if (req == tx_states[uart_num]) {
|
|
|
|
// Disable write interrupts, clear flags.
|
|
MXC_UART_GET_UART(uart_num)->int_en &= ~(UART_TX_IE | UART_ER_IE);
|
|
MXC_UART_GET_UART(uart_num)->int_fl = (UART_TX_IF | UART_ER_IF);
|
|
|
|
// Unlock this UART to write
|
|
mxc_free_lock((uint32_t*)&tx_states[uart_num]);
|
|
|
|
// Callback if not NULL
|
|
if (req->callback != NULL) {
|
|
req->callback(req, E_ABORT);
|
|
}
|
|
|
|
return E_NO_ERROR;
|
|
}
|
|
}
|
|
|
|
return E_BAD_PARAM;
|
|
}
|
|
|
|
/* ************************************************************************* */
|
|
unsigned UART_NumWriteAvail(mxc_uart_regs_t *uart)
|
|
{
|
|
return MXC_UART_FIFO_DEPTH - ((uart->status & MXC_F_UART_STATUS_TX_FIFO_CNT) >>
|
|
MXC_F_UART_STATUS_TX_FIFO_CNT_POS);
|
|
}
|
|
|
|
/* ************************************************************************* */
|
|
unsigned UART_NumReadAvail(mxc_uart_regs_t *uart)
|
|
{
|
|
return ((uart->status & MXC_F_UART_STATUS_RX_FIFO_CNT) >>
|
|
MXC_F_UART_STATUS_RX_FIFO_CNT_POS);
|
|
}
|
|
|
|
/* ************************************************************************* */
|
|
unsigned UART_GetFlags(mxc_uart_regs_t *uart)
|
|
{
|
|
return (uart->int_fl);
|
|
}
|
|
|
|
/* ************************************************************************* */
|
|
void UART_ClearFlags(mxc_uart_regs_t *uart, uint32_t mask)
|
|
{
|
|
uart->int_fl = mask;
|
|
}
|
|
|
|
/* ************************************************************************* */
|
|
void UART_Enable(mxc_uart_regs_t *uart)
|
|
{
|
|
uart->ctrl |= MXC_F_UART_CTRL_ENABLE;
|
|
}
|
|
|
|
/* ************************************************************************* */
|
|
void UART_Disable(mxc_uart_regs_t *uart)
|
|
{
|
|
uart->ctrl &= ~MXC_F_UART_CTRL_ENABLE;
|
|
}
|
|
|
|
/* ************************************************************************* */
|
|
void UART_DrainRX(mxc_uart_regs_t *uart)
|
|
{
|
|
uart->ctrl |= MXC_F_UART_CTRL_RX_FLUSH;
|
|
}
|
|
|
|
/* ************************************************************************* */
|
|
void UART_DrainTX(mxc_uart_regs_t *uart)
|
|
{
|
|
uart->ctrl |= MXC_F_UART_CTRL_TX_FLUSH;
|
|
}
|
|
|