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1060 lines
32 KiB
1060 lines
32 KiB
/* ****************************************************************************
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* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
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* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Except as contained in this notice, the name of Maxim Integrated
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* Products, Inc. shall not be used except as stated in the Maxim Integrated
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* Products, Inc. Branding Policy.
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*
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* The mere transfer of this software does not imply any licenses
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* of trade secrets, proprietary technology, copyrights, patents,
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* trademarks, maskwork rights, or any other form of intellectual
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* property whatsoever. Maxim Integrated Products, Inc. retains all
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* ownership rights.
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*
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* $Date: 2020-02-03 10:33:50 -0600 (Mon, 03 Feb 2020) $
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* $Revision: 51326 $
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*
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*************************************************************************** */
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#include <stddef.h>
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#include <stdint.h>
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#include "mxc_config.h"
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#include "mxc_assert.h"
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#include "mxc_lock.h"
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#include "mxc_sys.h"
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#include "i2c.h"
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#include <stdio.h>
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#include "mxc_delay.h"
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/* **** Definitions **** */
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#define I2C_ERROR (MXC_F_I2C_INT_FL0_ARB_ER | MXC_F_I2C_INT_FL0_TO_ER | MXC_F_I2C_INT_FL0_ADDR_NACK_ER | \
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MXC_F_I2C_INT_FL0_DATA_ER | MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER | MXC_F_I2C_INT_FL0_START_ER | \
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MXC_F_I2C_INT_FL0_STOP_ER)
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#define MASTER 1
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#define SLAVE 0
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/* For high speed mode, if the I2C bus capacitance is greater than 100pF, set this value to ((capacitance - 100) / 3).
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Otherwise leave it at 0. */
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#define HS_SCALE_FACTOR (0)
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#define T_LOW_MIN (160 + (160 * HS_SCALE_FACTOR / 100)) /* tLOW minimum in nanoseconds */
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#define T_HIGH_MIN (60 + (60 * HS_SCALE_FACTOR / 100)) /* tHIGH minimum in nanoseconds */
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#define T_R_MAX_HS (40 + (40 * HS_SCALE_FACTOR / 100)) /* tR maximum for high speed mode in nanoseconds */
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#define T_F_MAX_HS (40 + (40 * HS_SCALE_FACTOR / 100)) /* tF maximum for high speed mode in nanoseconds */
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#define T_AF_MIN (10 + (10 * HS_SCALE_FACTOR / 100)) /* tAF minimun in nanoseconds */
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/* **** Variable Declaration **** */
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// Saves the state of the non-blocking requests
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typedef struct {
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i2c_req_t *req;
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i2c_state_t state;
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uint8_t num_wr; // keep track of number of bytes loaded in the fifo during slave transmit
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} i2c_req_state_t;
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static i2c_req_state_t states[MXC_I2C_INSTANCES];
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/* **** Function Prototypes **** */
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static void I2C_MasterHandler(mxc_i2c_regs_t *i2c);
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static void I2C_SlaveHandler(mxc_i2c_regs_t *i2c);
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static void I2C_FreeCallback(int i2c_num, int error);
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static void I2C_Recover(mxc_i2c_regs_t *i2c);
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/* ************************************************************************** */
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static int I2C_Setspeed(mxc_i2c_regs_t * i2c, i2c_speed_t i2cspeed)
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{
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uint32_t ticks, ticks_lo, ticks_hi;
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if (i2cspeed == I2C_HS_MODE) {
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uint32_t sys_freq, tPCLK, targBusFreq, tSCLmin, cklMin, ckhMin, ckh_cklMin;
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/* Compute dividers for high speed mode. */
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sys_freq = SYS_I2C_GetFreq(i2c);
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MXC_ASSERT(sys_freq >= 1000);
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tPCLK = 1000000 / (sys_freq / 1000);
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MXC_ASSERT(tPCLK > 0)
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targBusFreq = i2cspeed - ((i2cspeed/2) * HS_SCALE_FACTOR / 100);
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if(targBusFreq < 1000) {
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return E_BAD_PARAM;
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}
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tSCLmin = 1000000 / (targBusFreq / 1000);
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cklMin = ((T_LOW_MIN + T_F_MAX_HS + (tPCLK - 1) - T_AF_MIN) / tPCLK) - 1;
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ckhMin = ((T_HIGH_MIN + T_R_MAX_HS + (tPCLK - 1) - T_AF_MIN) / tPCLK) - 1;
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ckh_cklMin = ((tSCLmin + (tPCLK - 1)) / tPCLK) - 2;
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ticks_lo = (cklMin > (ckh_cklMin - ckhMin)) ? (cklMin) : (ckh_cklMin - ckhMin);
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ticks_hi = ckhMin;
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if((ticks_lo > (MXC_F_I2C_HS_CLK_HS_CLK_LO >> MXC_F_I2C_HS_CLK_HS_CLK_LO_POS)) ||
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(ticks_hi > (MXC_F_I2C_HS_CLK_HS_CLK_HI >> MXC_F_I2C_HS_CLK_HS_CLK_HI_POS))) {
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return E_BAD_PARAM;
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}
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/* Write results to destination registers. */
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i2c->hs_clk = (ticks_lo << MXC_F_I2C_HS_CLK_HS_CLK_LO_POS) | (ticks_hi <<
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MXC_F_I2C_HS_CLK_HS_CLK_HI_POS);
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/* Still need to load dividers for the preamble that each high-speed transaction starts with.
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Switch setting to fast mode and fall out of if statement. */
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i2cspeed = I2C_FAST_MODE;
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}
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/* Get the number of periph clocks needed to achieve selected speed. */
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ticks = SYS_I2C_GetFreq(i2c) / i2cspeed;
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/* For a 50% duty cycle, half the ticks will be spent high and half will be low. */
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ticks_hi = (ticks >> 1) - 1;
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ticks_lo = (ticks >> 1) - 1;
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/* Account for rounding error in odd tick counts. */
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if (ticks & 1) {
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ticks_hi++;
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}
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/* Will results fit into 9 bit registers? (ticks_hi will always be >= ticks_lo. No need to check ticks_lo.) */
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if (ticks_hi > 0x1FF) {
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return E_BAD_PARAM;
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}
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/* 0 is an invalid value for the destination registers. (ticks_hi will always be >= ticks_lo. No need to check ticks_hi.) */
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if (ticks_lo == 0) {
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return E_BAD_PARAM;
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}
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/* Write results to destination registers. */
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i2c->clk_lo = ticks_lo;
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i2c->clk_hi = ticks_hi;
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return E_NO_ERROR;
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}
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/* ************************************************************************** */
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int I2C_Init(mxc_i2c_regs_t *i2c, i2c_speed_t i2cspeed, const sys_cfg_i2c_t* sys_cfg)
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{
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int err;
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int idx = MXC_I2C_GET_IDX(i2c);
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// Check the base pointer
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MXC_ASSERT(idx >= 0);
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// Set system level configurations
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if ((err = SYS_I2C_Init(i2c, sys_cfg)) != E_NO_ERROR) {
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return err;
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}
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// Always disable the HW autoflush on data NACK and let the SW handle the flushing.
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i2c->tx_ctrl0 |= 0x20;
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states[idx].num_wr = 0;
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i2c->ctrl = 0; // clear configuration bits
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i2c->ctrl = MXC_F_I2C_CTRL_I2C_EN; // Enable I2C
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i2c->master_ctrl = 0; // clear master configuration bits
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i2c->status = 0; // clear status bits
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/* If either SDA or SCL is already low, there is a problem.
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* Try reclaiming the bus by sending clocks until we have control of the SDA line.
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* Follow procedure defined in i2c spec.
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*/
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if ((i2c->ctrl & (MXC_F_I2C_CTRL_SCL | MXC_F_I2C_CTRL_SDA)) !=
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(MXC_F_I2C_CTRL_SCL | MXC_F_I2C_CTRL_SDA)) {
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int i, have_control;
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// Set SCL/SDA as software controlled.
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i2c->ctrl |= MXC_F_I2C_CTRL_SW_OUT_EN;
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// Try to get control of SDA.
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for (i = 0; i < 16; i++) {
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have_control = 1;
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// Drive SCL low and check its state.
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i2c->ctrl &= ~(MXC_F_I2C_CTRL_SCL_OUT);
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mxc_delay(MXC_DELAY_USEC(5));
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if ((i2c->ctrl & MXC_F_I2C_CTRL_SCL) == MXC_F_I2C_CTRL_SCL) {
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have_control = 0;
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}
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// Drive SDA low and check its state.
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i2c->ctrl &= ~(MXC_F_I2C_CTRL_SDA_OUT);
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mxc_delay(MXC_DELAY_USEC(5));
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if ((i2c->ctrl & MXC_F_I2C_CTRL_SDA) == MXC_F_I2C_CTRL_SDA) {
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have_control = 0;
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}
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// Release SDA and check its state.
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i2c->ctrl |= (MXC_F_I2C_CTRL_SDA_OUT);
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mxc_delay(MXC_DELAY_USEC(5));
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if ((i2c->ctrl & MXC_F_I2C_CTRL_SDA) != MXC_F_I2C_CTRL_SDA) {
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have_control = 0;
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}
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// Release SCL and check its state.
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i2c->ctrl |= (MXC_F_I2C_CTRL_SCL_OUT);
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mxc_delay(MXC_DELAY_USEC(5));
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if ((i2c->ctrl & MXC_F_I2C_CTRL_SCL) != MXC_F_I2C_CTRL_SCL) {
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have_control = 0;
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}
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if (have_control) {
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// Issue stop
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// Drive SDA low.
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i2c->ctrl &= ~(MXC_F_I2C_CTRL_SDA_OUT);
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mxc_delay(MXC_DELAY_USEC(5));
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// Release SDA.
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i2c->ctrl |= (MXC_F_I2C_CTRL_SDA_OUT);
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mxc_delay(MXC_DELAY_USEC(5));
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break;
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}
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}
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if (!have_control) {
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return E_COMM_ERR;
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}
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}
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i2c->ctrl = 0; // clear configuration bits
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i2c->ctrl = MXC_F_I2C_CTRL_I2C_EN; // Enable I2C
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i2c->master_ctrl = 0; // clear master configuration bits
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i2c->status= 0; // clear status bits
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// Check for HS mode
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if (i2cspeed == I2C_HS_MODE) {
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i2c->ctrl |= MXC_F_I2C_CTRL_HS_MODE; // Enable HS mode
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}
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// Disable and clear interrupts
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i2c->int_en0 = 0;
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i2c->int_en1 = 0;
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i2c->int_fl0 = i2c->int_fl0;
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i2c->int_fl1 = i2c->int_fl1;
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i2c->timeout = 0x0; // set timeout
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i2c->rx_ctrl0 |= MXC_F_I2C_RX_CTRL0_RX_FLUSH; // clear the RX FIFO
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i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH; // clear the TX FIFO
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return I2C_Setspeed(i2c, i2cspeed);
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}
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/* ************************************************************************** */
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int I2C_Shutdown(mxc_i2c_regs_t *i2c)
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{
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int i2c_num, err;
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// Check the base pointer
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i2c_num = MXC_I2C_GET_IDX(i2c);
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MXC_ASSERT(i2c_num >= 0);
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// Disable and clear interrupts
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i2c->int_en0 = 0;
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i2c->int_en1 = 0;
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i2c->int_fl0 = i2c->int_fl0;
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i2c->int_fl1 = i2c->int_fl1;
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i2c->rx_ctrl0 |= MXC_F_I2C_RX_CTRL0_RX_FLUSH; // clear the RX FIFO
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i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH; // clear the TX FIFO
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// Call all of the pending callbacks for this I2C
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if (states[i2c_num].req != NULL) {
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I2C_Recover(i2c);
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I2C_FreeCallback(i2c_num, E_SHUTDOWN);
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}
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i2c->ctrl = 0;
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// Clears system level configurations
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if ((err = SYS_I2C_Shutdown(i2c)) != E_NO_ERROR) {
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return err;
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}
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return E_NO_ERROR;
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}
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/* ************************************************************************** */
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int I2C_MasterWrite(mxc_i2c_regs_t *i2c, uint8_t addr, const uint8_t* data, int len, int restart)
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{
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int save_len = len;
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if (len == 0) {
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return E_NO_ERROR;
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}
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// Clear the lock out bit (W1C) in case it is set.
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i2c->int_fl0 = MXC_F_I2C_INT_FL0_TX_LOCK_OUT;
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i2c->int_fl0 = i2c->int_fl0;
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// Enable master mode
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i2c->ctrl |= MXC_F_I2C_CTRL_MST;
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// Load FIFO with slave address for WRITE and as much data as we can
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while (i2c->status & MXC_F_I2C_STATUS_TX_FULL) {}
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i2c->fifo = addr & ~(0x1);
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while ((len > 0) && !(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) {
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i2c->fifo = *data++;
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len--;
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}
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i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_START;
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// Write remaining data to FIFO
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while (len > 0) {
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// Check for errors
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if (i2c->int_fl0 & I2C_ERROR) {
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// Set the stop bit
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i2c->master_ctrl &= ~(MXC_F_I2C_MASTER_CTRL_RESTART);
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i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
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while (!(i2c->int_fl0 & (MXC_F_I2C_INT_FL0_STOP))) {}
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return E_COMM_ERR;
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}
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if (!(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) {
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i2c->fifo = *data++;
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len--;
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}
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}
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if (restart) {
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i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_RESTART;
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} else {
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i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
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}
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// Wait for Done or time out if enabled
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while (!(i2c->int_fl0 & (MXC_F_I2C_INT_FL0_DONE | I2C_ERROR ))) {}
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i2c->int_fl0 = MXC_F_I2C_INT_FL0_DONE;
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// Wait for Stop
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if (!restart) {
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while (!(i2c->int_fl0 & (MXC_F_I2C_INT_FL0_STOP ))) {}
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i2c->int_fl0 = MXC_F_I2C_INT_FL0_STOP;
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}
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// Check for errors
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if (i2c->int_fl0 & I2C_ERROR) {
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return E_COMM_ERR;
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}
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return save_len;
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}
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/* ************************************************************************** */
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int I2C_MasterRead(mxc_i2c_regs_t *i2c, uint8_t addr, uint8_t* data, int len, int restart)
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{
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int save_len = len;
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if (len == 0) {
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return E_NO_ERROR;
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}
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if (len > 256) {
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return E_BAD_PARAM;
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}
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i2c->int_fl0 = MXC_F_I2C_INT_FL0_TX_LOCK_OUT;
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i2c->int_fl0 = i2c->int_fl0;
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// Make sure the I2C has been initialized
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if (!(i2c->ctrl & MXC_F_I2C_CTRL_I2C_EN)) {
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return E_UNINITIALIZED;
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}
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// Enable master mode
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i2c->ctrl |= MXC_F_I2C_CTRL_MST;
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// Set receive count
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i2c->rx_ctrl1= len;
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i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_START;
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// Load FIFO with slave address
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while (i2c->status & MXC_F_I2C_STATUS_TX_FULL) {}
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i2c->fifo = (addr | 1);
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// Wait for all data to be received or error
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while (len > 0) {
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// Check for errors
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if (i2c->int_fl0 & I2C_ERROR) {
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// Set the stop bit
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i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
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return E_COMM_ERR;
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}
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if (!(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) {
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*data++ = i2c->fifo;
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len--;
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}
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}
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if (i2c->int_fl0 & I2C_ERROR) {
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// Set the stop bit
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i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
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return E_COMM_ERR;
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}
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if (restart) {
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i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_RESTART;
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} else {
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i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
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}
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// Wait for Done or time out if enabled
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while (!(i2c->int_fl0 & (MXC_F_I2C_INT_FL0_DONE | I2C_ERROR ))) {}
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i2c->int_fl0 = MXC_F_I2C_INT_FL0_DONE;
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// Wait for Stop
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if (!restart) {
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while (!(i2c->int_fl0 & (MXC_F_I2C_INT_FL0_STOP | I2C_ERROR))) {
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}
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i2c->int_fl0 = MXC_F_I2C_INT_FL0_STOP;
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}
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|
// Check for errors
|
|
if (i2c->int_fl0 & I2C_ERROR) {
|
|
return E_COMM_ERR;
|
|
}
|
|
|
|
return save_len;
|
|
}
|
|
|
|
/* ************************************************************************** */
|
|
int I2C_Slave(mxc_i2c_regs_t *i2c, uint8_t addr, const uint8_t* read_data, int read_len,
|
|
uint8_t* write_data, int write_len, int* tx_num, int* rx_num,
|
|
i2c_autoflush_disable_t sw_autoflush_disable)
|
|
{
|
|
int i2c_num;
|
|
|
|
i2c_num = MXC_I2C_GET_IDX(i2c);
|
|
if ((read_data == NULL) && (write_data == NULL)) {
|
|
return E_NULL_PTR;
|
|
}
|
|
|
|
// Make sure the I2C has been initialized
|
|
if (!(i2c->ctrl & MXC_F_I2C_CTRL_I2C_EN)) {
|
|
return E_UNINITIALIZED;
|
|
}
|
|
|
|
if ((read_len == 0) && (write_len == 0)) {
|
|
return E_NO_ERROR;
|
|
}
|
|
|
|
if (mxc_get_lock((uint32_t*)&states[i2c_num].req, 1) != E_NO_ERROR) {
|
|
return E_BUSY;
|
|
}
|
|
// Disable master mode
|
|
i2c->ctrl &= ~MXC_F_I2C_CTRL_MST;
|
|
|
|
// Clear any previous errors
|
|
i2c->int_fl0 = i2c->int_fl0;
|
|
i2c->int_fl1 = i2c->int_fl1;
|
|
|
|
// Set the slave address
|
|
i2c->slave_addr = (addr >> 1);
|
|
|
|
// Wait for address match
|
|
while (!(i2c->int_fl0 & MXC_F_I2C_INT_FL0_ADDR_MATCH) && !(i2c->int_fl0 & I2C_ERROR)) {
|
|
|
|
}
|
|
|
|
i2c->int_fl0 = MXC_F_I2C_INT_FL0_ADDR_MATCH;
|
|
i2c->int_fl0 = MXC_F_I2C_INT_FL0_TX_LOCK_OUT;
|
|
|
|
if (i2c->int_fl0 & I2C_ERROR) {
|
|
if (!sw_autoflush_disable) {
|
|
i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH;
|
|
i2c->rx_ctrl0 |= MXC_F_I2C_RX_CTRL0_RX_FLUSH;
|
|
}
|
|
mxc_free_lock((uint32_t*)&states[i2c_num]);
|
|
return E_COMM_ERR;
|
|
}
|
|
|
|
// See if we're reading or writing
|
|
if (i2c->ctrl & MXC_F_I2C_CTRL_READ) {
|
|
// This is the master read/slave write case
|
|
if (read_data == NULL || read_len == 0) {
|
|
mxc_free_lock((uint32_t*)&states[i2c_num]);
|
|
return E_NULL_PTR;
|
|
}
|
|
|
|
// Wait for all data to be received or error
|
|
while (read_len > 0) {
|
|
|
|
// Check for errors
|
|
if (i2c->int_fl0 & I2C_ERROR) {
|
|
*tx_num = states[i2c_num].num_wr - ((i2c->tx_ctrl1 & MXC_F_I2C_TX_CTRL1_TX_FIFO) >> MXC_F_I2C_TX_CTRL1_TX_FIFO_POS);
|
|
states[i2c_num].num_wr = 0;
|
|
if (!sw_autoflush_disable) {
|
|
i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH;
|
|
}
|
|
mxc_free_lock((uint32_t*)&states[i2c_num]);
|
|
return E_COMM_ERR;
|
|
}
|
|
|
|
// Check for nack from master
|
|
if (i2c->int_fl0 & MXC_F_I2C_INT_FL0_TX_LOCK_OUT) {
|
|
break;
|
|
}
|
|
|
|
// Check for done bit
|
|
if (i2c->int_fl0 & MXC_F_I2C_INT_FL0_DONE) {
|
|
break;
|
|
}
|
|
|
|
if (!(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) {
|
|
i2c->fifo = *read_data++;
|
|
states[i2c_num].num_wr++;
|
|
read_len--;
|
|
}
|
|
}
|
|
|
|
// Wait for Done
|
|
while (!(i2c->int_fl0 & MXC_F_I2C_INT_FL0_DONE)) {}
|
|
|
|
// Calculate number of bytes sent by the slave
|
|
*tx_num = states[i2c_num].num_wr - ((i2c->tx_ctrl1 & MXC_F_I2C_TX_CTRL1_TX_FIFO) >> MXC_F_I2C_TX_CTRL1_TX_FIFO_POS);
|
|
states[i2c_num].num_wr = 0;
|
|
if (!sw_autoflush_disable) {
|
|
// Flush the TX FIFO
|
|
i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH;
|
|
}
|
|
|
|
} else {
|
|
// This is the master write/slave read case
|
|
if (write_data == NULL || write_len == 0) {
|
|
mxc_free_lock((uint32_t*)&states[i2c_num]);
|
|
return E_NULL_PTR;
|
|
}
|
|
|
|
// Wait for all data to be written or error
|
|
while (write_len > 0) {
|
|
|
|
// Check for errors
|
|
if (i2c->int_fl0 & I2C_ERROR) {
|
|
if (!sw_autoflush_disable) {
|
|
i2c->rx_ctrl0 |= MXC_F_I2C_RX_CTRL0_RX_FLUSH;
|
|
}
|
|
mxc_free_lock((uint32_t*)&states[i2c_num]);
|
|
return E_COMM_ERR;
|
|
}
|
|
|
|
// Check for done bit
|
|
if (i2c->int_fl0 & MXC_F_I2C_INT_FL0_DONE) {
|
|
break;
|
|
}
|
|
|
|
if (!(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) {
|
|
*write_data++ = i2c->fifo;
|
|
(*rx_num)++;
|
|
write_len--;
|
|
}
|
|
}
|
|
|
|
// Wait for Done
|
|
while (!(i2c->int_fl0 & MXC_F_I2C_INT_FL0_DONE)) {
|
|
|
|
}
|
|
// Flush the FIFO
|
|
if (!sw_autoflush_disable) {
|
|
i2c->rx_ctrl0 |= MXC_F_I2C_RX_CTRL0_RX_FLUSH;
|
|
}
|
|
}
|
|
|
|
// Check for errors
|
|
if (i2c->int_fl0 & I2C_ERROR) {
|
|
// Flush the FIFO
|
|
if (!sw_autoflush_disable) {
|
|
i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH;
|
|
i2c->rx_ctrl0 |= MXC_F_I2C_RX_CTRL0_RX_FLUSH;
|
|
}
|
|
mxc_free_lock((uint32_t*)&states[i2c_num]);
|
|
return E_COMM_ERR;
|
|
}
|
|
mxc_free_lock((uint32_t*)&states[i2c_num]);
|
|
return E_NO_ERROR;
|
|
}
|
|
|
|
/* ************************************************************************** */
|
|
int I2C_MasterAsync(mxc_i2c_regs_t *i2c, i2c_req_t *req)
|
|
{
|
|
int i2c_num;
|
|
|
|
i2c_num = MXC_I2C_GET_IDX(i2c);
|
|
if (req->state == I2C_STATE_READING) {
|
|
// Check the parameters
|
|
if (req->rx_len == 0) {
|
|
return E_NO_ERROR;
|
|
}
|
|
if (req->rx_data == NULL) {
|
|
return E_NULL_PTR;
|
|
}
|
|
|
|
} else {
|
|
// Check the parameters
|
|
if (req->tx_len == 0) {
|
|
return E_NO_ERROR;
|
|
}
|
|
if (req->tx_data == NULL) {
|
|
return E_NULL_PTR;
|
|
}
|
|
}
|
|
|
|
// Make sure the I2C has been initialized
|
|
if (!(i2c->ctrl & MXC_F_I2C_CTRL_I2C_EN)) {
|
|
return E_UNINITIALIZED;
|
|
}
|
|
|
|
// Attempt to register this request
|
|
if (mxc_get_lock((uint32_t*)&states[i2c_num].req, (uint32_t)req) != E_NO_ERROR) {
|
|
return E_BUSY;
|
|
}
|
|
states[i2c_num].state = req->state;
|
|
states[i2c_num].req = req;
|
|
|
|
// Enable master mode
|
|
i2c->ctrl |= MXC_F_I2C_CTRL_MST;
|
|
|
|
// Clear the byte counters
|
|
req->tx_num = 0;
|
|
req->rx_num = 0;
|
|
|
|
// Disable and clear the interrupts
|
|
i2c->int_en0 = 0;
|
|
i2c->int_en1 = 0;
|
|
i2c->int_fl0 = i2c->int_fl0;
|
|
i2c->int_fl1 = i2c->int_fl1;
|
|
|
|
// Start the transaction
|
|
I2C_MasterHandler(i2c);
|
|
return E_NO_ERROR;
|
|
}
|
|
|
|
|
|
/* ************************************************************************** */
|
|
static void I2C_MasterHandler(mxc_i2c_regs_t *i2c)
|
|
{
|
|
|
|
uint32_t int0, inten0 = 0;
|
|
int rx_remain, tx_remain, i2c_num;
|
|
i2c_req_t *req;
|
|
|
|
i2c_num = MXC_I2C_GET_IDX(i2c);
|
|
req = states[i2c_num].req;
|
|
|
|
// Check for errors
|
|
int0 = i2c->int_fl0;
|
|
if (int0 & I2C_ERROR) {
|
|
|
|
// Set the done bit
|
|
i2c->master_ctrl &= ~(MXC_F_I2C_MASTER_CTRL_RESTART);
|
|
i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
|
|
|
|
i2c->int_en0 = 0;
|
|
if (req->callback != NULL) {
|
|
I2C_Recover(i2c);
|
|
I2C_FreeCallback(i2c_num, E_COMM_ERR);
|
|
}
|
|
return;
|
|
}
|
|
|
|
rx_remain = req->rx_len - req->rx_num;
|
|
tx_remain = req->tx_len - req->tx_num;
|
|
if (req->restart) {
|
|
// Check for DONE interrupt
|
|
if ((int0 & MXC_F_I2C_INT_FL0_DONE)) {
|
|
// Read out any data in the RX FIFO
|
|
while (rx_remain && !(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) {
|
|
*(req->rx_data)++ = i2c->fifo;
|
|
req->rx_num++;
|
|
rx_remain--;
|
|
}
|
|
i2c->int_en0 = 0;
|
|
if (req->callback != NULL) {
|
|
I2C_Recover(i2c);
|
|
I2C_FreeCallback(i2c_num, E_NO_ERROR);
|
|
}
|
|
return;
|
|
}
|
|
} else {
|
|
// Check for STOP interrupt
|
|
if ((int0 & MXC_F_I2C_INT_FL0_STOP)) {
|
|
i2c->int_en0 = 0;
|
|
if (req->callback != NULL) {
|
|
I2C_Recover(i2c);
|
|
I2C_FreeCallback(i2c_num, E_NO_ERROR);
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
// Check for DONE interrupt
|
|
if ((int0 & MXC_F_I2C_INT_FL0_DONE)) {
|
|
// Read out any data in the RX FIFO
|
|
while (rx_remain && !(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) {
|
|
*(req->rx_data)++ = i2c->fifo;
|
|
req->rx_num++;
|
|
rx_remain--;
|
|
}
|
|
|
|
return;
|
|
}
|
|
}
|
|
|
|
// Clear the interrupts
|
|
i2c->int_fl0 = int0;
|
|
|
|
if (states[i2c_num].state == I2C_STATE_READING) {
|
|
|
|
|
|
// Read out any data in the RX FIFO
|
|
while (rx_remain && !(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) {
|
|
*(req->rx_data)++ = i2c->fifo;
|
|
req->rx_num++;
|
|
rx_remain--;
|
|
}
|
|
|
|
// Load the slave address if we haven't already started reading the data
|
|
if (rx_remain == req->rx_len) {
|
|
i2c->fifo = (req->addr | 1);
|
|
|
|
// Set the RX Count
|
|
i2c->rx_ctrl1 = req->rx_len;
|
|
|
|
// Start transmission if idle
|
|
if (!(i2c->status & MXC_F_I2C_STATUS_BUS)) {
|
|
i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_START;
|
|
}
|
|
|
|
// Set restart or stop
|
|
if (req->restart) {
|
|
i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_RESTART;
|
|
} else {
|
|
i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
|
|
inten0 |= MXC_F_I2C_INT_EN0_STOP;
|
|
}
|
|
}
|
|
|
|
// Set the RX threshold interrupt level
|
|
if (rx_remain >= (MXC_I2C_FIFO_DEPTH - 1)) {
|
|
i2c->rx_ctrl1 = ((i2c->rx_ctrl1 & ~(MXC_F_I2C_RX_CTRL0_RX_THRESH)) |
|
|
(MXC_I2C_FIFO_DEPTH - 1) << MXC_F_I2C_RX_CTRL0_RX_THRESH_POS);
|
|
|
|
inten0 |= MXC_F_I2C_INT_EN0_RX_THRESH;
|
|
}else{
|
|
i2c->rx_ctrl1 = ((i2c->rx_ctrl1 & ~(MXC_F_I2C_RX_CTRL0_RX_THRESH)) |
|
|
(rx_remain) << MXC_F_I2C_RX_CTRL0_RX_THRESH_POS);
|
|
|
|
inten0 |= MXC_F_I2C_INT_EN0_RX_THRESH;
|
|
}
|
|
|
|
} else {
|
|
|
|
// Load the slave address if we haven't already started writing the data
|
|
if (tx_remain == req->tx_len) {
|
|
i2c->fifo = req->addr;
|
|
// Start transmission if idle
|
|
if (!(i2c->status & MXC_F_I2C_STATUS_BUS)) {
|
|
i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_START;
|
|
}
|
|
}
|
|
|
|
// Fill the FIFO
|
|
while ((tx_remain > 0) && !(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) {
|
|
i2c->fifo = *(req->tx_data)++;
|
|
req->tx_num++;
|
|
tx_remain--;
|
|
}
|
|
|
|
// Set the TX threshold interrupt level, or restart/stop
|
|
if (tx_remain) {
|
|
i2c->tx_ctrl1 = ((i2c->tx_ctrl1 & ~(MXC_F_I2C_TX_CTRL0_TX_THRESH)) | (1 << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS));
|
|
inten0 |= MXC_F_I2C_INT_EN0_TX_THRESH;
|
|
}
|
|
// Set restart or stop if at the end of the transaction since these actions happen at the moment the bit is set.
|
|
else if (req->restart) {
|
|
i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_RESTART;
|
|
} else {
|
|
i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
|
|
inten0 |= MXC_F_I2C_INT_EN0_STOP;
|
|
}
|
|
}
|
|
|
|
inten0 |= (MXC_F_I2C_INT_EN0_DONE | I2C_ERROR);
|
|
i2c->int_en0 = inten0;
|
|
}
|
|
|
|
/* ************************************************************************** */
|
|
int I2C_SlaveAsync(mxc_i2c_regs_t *i2c, i2c_req_t *req)
|
|
{
|
|
int i2c_num;
|
|
|
|
i2c_num = MXC_I2C_GET_IDX(i2c);
|
|
|
|
// Make sure the I2C has been initialized
|
|
if (!(i2c->ctrl & MXC_F_I2C_CTRL_I2C_EN)) {
|
|
return E_UNINITIALIZED;
|
|
}
|
|
|
|
// Attempt to register this request
|
|
if (mxc_get_lock((uint32_t*)&states[i2c_num].req, (uint32_t)req) != E_NO_ERROR) {
|
|
return E_BUSY;
|
|
}
|
|
|
|
states[i2c_num].req = req;
|
|
|
|
// Set Slave Address
|
|
i2c->slave_addr = (req->addr >> 1);
|
|
|
|
// Clear the byte counters
|
|
req->tx_num = 0;
|
|
req->rx_num = 0;
|
|
|
|
// Disable and clear the interrupts
|
|
i2c->int_en0 = 0;
|
|
i2c->int_en1 = 0;
|
|
i2c->int_fl0 = i2c->int_fl0;
|
|
i2c->int_fl1 = i2c->int_fl1;
|
|
i2c->int_en0 |= MXC_F_I2C_INT_EN0_ADDR_MATCH;
|
|
|
|
return E_NO_ERROR;
|
|
}
|
|
/* ************************************************************************** */
|
|
static void I2C_SlaveHandler(mxc_i2c_regs_t *i2c)
|
|
{
|
|
uint32_t int0, inten0 = 0;
|
|
int rx_remain, tx_remain, i2c_num;
|
|
i2c_req_t *req;
|
|
|
|
i2c_num = MXC_I2C_GET_IDX(i2c);
|
|
req = states[i2c_num].req;
|
|
|
|
if ( i2c->int_fl0 & MXC_F_I2C_INT_FL0_ADDR_MATCH ) {
|
|
i2c->int_fl0 |=MXC_F_I2C_INT_EN0_STOP;
|
|
}
|
|
|
|
// Check for errors
|
|
int0 = i2c->int_fl0;
|
|
if (int0 & I2C_ERROR) {
|
|
i2c->int_en0 = 0;
|
|
// Calculate the number of bytes sent by the slave
|
|
req->tx_num = states[i2c_num].num_wr - ((i2c->tx_ctrl1 & MXC_F_I2C_TX_CTRL1_TX_FIFO) >> MXC_F_I2C_TX_CTRL1_TX_FIFO_POS);
|
|
|
|
if (!req->sw_autoflush_disable) {
|
|
// Manually clear the TXFIFO
|
|
i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH;
|
|
}
|
|
states[i2c_num].num_wr = 0;
|
|
if (req->callback != NULL) {
|
|
I2C_Recover(i2c);
|
|
I2C_FreeCallback(i2c_num, E_COMM_ERR);
|
|
}
|
|
return;
|
|
}
|
|
|
|
rx_remain = req->rx_len - req->rx_num;
|
|
tx_remain = req->tx_len - states[i2c_num].num_wr;
|
|
|
|
//Check if Master Write has been called and if there is a rx_data buffer
|
|
if ((i2c->int_fl0 & MXC_F_I2C_INT_FL0_TX_LOCK_OUT) && !(i2c->ctrl & MXC_F_I2C_CTRL_READ)) {
|
|
|
|
i2c->int_en0 = 0;
|
|
if (req->rx_data == NULL) {
|
|
I2C_Recover(i2c);
|
|
I2C_FreeCallback(i2c_num, E_NULL_PTR);
|
|
return;
|
|
}
|
|
}
|
|
|
|
// Check for DONE interrupt
|
|
if (int0 & MXC_F_I2C_INT_EN0_DONE) {
|
|
// Read out any data in the RX FIFO
|
|
while (rx_remain && !(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) {
|
|
*(req->rx_data)++ = i2c->fifo;
|
|
req->rx_num++;
|
|
rx_remain--;
|
|
}
|
|
|
|
// Calculate the number of bytes sent by the slave
|
|
req->tx_num = states[i2c_num].num_wr - ((i2c->tx_ctrl1 & MXC_F_I2C_TX_CTRL1_TX_FIFO) >> MXC_F_I2C_TX_CTRL1_TX_FIFO_POS);
|
|
|
|
if (!req->sw_autoflush_disable) {
|
|
// Manually clear the TXFIFO
|
|
i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH;
|
|
}
|
|
states[i2c_num].num_wr = 0;
|
|
i2c->int_en0 = 0;
|
|
if (req->callback != NULL) {
|
|
if (i2c->int_fl0 & MXC_F_I2C_INT_FL0_STOP) {
|
|
I2C_Recover(i2c);
|
|
} else {
|
|
i2c->int_fl0 = i2c->int_fl0;
|
|
i2c->int_fl1 = i2c->int_fl1;
|
|
}
|
|
I2C_FreeCallback(i2c_num, E_NO_ERROR);
|
|
}
|
|
return;
|
|
}
|
|
|
|
// Clear the interrupts
|
|
i2c->int_fl0 = int0;
|
|
if (i2c->ctrl & MXC_F_I2C_CTRL_READ) {
|
|
|
|
i2c->int_en0 = 0;
|
|
if (req->tx_data == NULL) {
|
|
I2C_Recover(i2c);
|
|
I2C_FreeCallback(i2c_num, E_NULL_PTR);
|
|
return;
|
|
}
|
|
// Fill the FIFO
|
|
while ((tx_remain > 0) && !(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) {
|
|
i2c->fifo = *(req->tx_data)++;
|
|
states[i2c_num].num_wr++;
|
|
tx_remain--;
|
|
}
|
|
|
|
// Set the TX threshold interrupt level
|
|
if (tx_remain) {
|
|
i2c->tx_ctrl0 = ((i2c->tx_ctrl0 & ~(MXC_F_I2C_TX_CTRL0_TX_THRESH)) | (1 << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS));
|
|
inten0 |= MXC_F_I2C_INT_EN0_TX_THRESH;
|
|
}
|
|
|
|
} else {
|
|
// Read out any data in the RX FIFO
|
|
while (rx_remain && !(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) {
|
|
*(req->rx_data)++ = i2c->fifo;
|
|
req->rx_num++;
|
|
rx_remain--;
|
|
}
|
|
|
|
// Set the RX threshold interrupt level
|
|
if (rx_remain >= (MXC_I2C_FIFO_DEPTH - 1)) {
|
|
i2c->rx_ctrl0 = ((i2c->rx_ctrl0 & ~(MXC_F_I2C_RX_CTRL0_RX_THRESH)) |
|
|
(MXC_I2C_FIFO_DEPTH - 1) << MXC_F_I2C_RX_CTRL0_RX_THRESH_POS);
|
|
|
|
inten0 |= MXC_F_I2C_INT_EN0_RX_THRESH;
|
|
}else{
|
|
i2c->rx_ctrl0 = ((i2c->rx_ctrl0 & ~(MXC_F_I2C_RX_CTRL0_RX_THRESH)) |
|
|
(rx_remain) << MXC_F_I2C_RX_CTRL0_RX_THRESH_POS);
|
|
|
|
inten0 |= MXC_F_I2C_INT_EN0_RX_THRESH;
|
|
}
|
|
|
|
}
|
|
inten0 |= (MXC_F_I2C_INT_EN0_DONE | I2C_ERROR | MXC_F_I2C_INT_EN0_TX_LOCK_OUT);
|
|
i2c->int_en0 = inten0;
|
|
}
|
|
|
|
/* ************************************************************************** */
|
|
void I2C_Handler(mxc_i2c_regs_t *i2c)
|
|
{
|
|
if (i2c->ctrl & MXC_F_I2C_CTRL_MST && i2c->int_fl0) {
|
|
// Service master interrupts if we're in master mode
|
|
I2C_MasterHandler(i2c);
|
|
} else if (i2c->int_fl0 || i2c->int_fl1) {
|
|
// Service the slave interrupts
|
|
I2C_SlaveHandler(i2c);
|
|
}
|
|
}
|
|
|
|
/* ************************************************************************** */
|
|
void I2C_DrainRX(mxc_i2c_regs_t *i2c)
|
|
{
|
|
i2c->rx_ctrl0 |= MXC_F_I2C_RX_CTRL0_RX_FLUSH;
|
|
}
|
|
|
|
/* ************************************************************************** */
|
|
void I2C_DrainTX(mxc_i2c_regs_t *i2c)
|
|
{
|
|
i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH;
|
|
}
|
|
/* ************************************************************************* */
|
|
static void I2C_FreeCallback(int i2c_num, int error)
|
|
{
|
|
// Save the request
|
|
i2c_req_t *temp_req = states[i2c_num].req;
|
|
|
|
mxc_free_lock((uint32_t*)&states[i2c_num].req);
|
|
|
|
// Callback if not NULL
|
|
if (temp_req->callback != NULL) {
|
|
temp_req->callback(temp_req, error);
|
|
}
|
|
}
|
|
|
|
/* ************************************************************************* */
|
|
static void I2C_Recover(mxc_i2c_regs_t *i2c)
|
|
{
|
|
// Disable and clear interrupts
|
|
i2c->int_en0 = 0;
|
|
i2c->int_en1 = 0;
|
|
i2c->int_fl0 = i2c->int_fl0;
|
|
i2c->int_fl1 = i2c->int_fl1;
|
|
i2c->ctrl = 0;
|
|
i2c->ctrl = MXC_F_I2C_CTRL_I2C_EN;
|
|
}
|
|
|
|
/* ************************************************************************* */
|
|
int I2C_AbortAsync(i2c_req_t *req)
|
|
{
|
|
int i2c_num;
|
|
mxc_i2c_regs_t *i2c;
|
|
|
|
// Find the request, set to NULL
|
|
for (i2c_num = 0; i2c_num < MXC_I2C_INSTANCES; i2c_num++) {
|
|
if (req == states[i2c_num].req) {
|
|
|
|
i2c = MXC_I2C_GET_I2C(i2c_num);
|
|
I2C_Recover(i2c);
|
|
I2C_FreeCallback(i2c_num, E_ABORT);
|
|
|
|
return E_NO_ERROR;
|
|
}
|
|
}
|
|
|
|
return E_BAD_PARAM;
|
|
}
|
|
|
|
/* ************************************************************************* */
|
|
int I2C_SetTimeout(mxc_i2c_regs_t *i2c, int us){
|
|
uint32_t timeout;
|
|
timeout = (PeripheralClock/1000000) * us;
|
|
if(timeout > 0xFFFF){
|
|
return E_BAD_PARAM;
|
|
}
|
|
i2c->timeout = timeout;
|
|
return E_NO_ERROR;
|
|
}
|
|
|
|
/* ************************************************************************* */
|
|
void I2C_ClearTimeout (mxc_i2c_regs_t *i2c)
|
|
{
|
|
i2c->timeout = 0;
|
|
}
|
|
|