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1445 lines
47 KiB
1445 lines
47 KiB
/*
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* Copyright (c) 2021-2023 HPMicro
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#include "board.h"
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#include "hpm_uart_drv.h"
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#include "hpm_gptmr_drv.h"
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#include "hpm_lcdc_drv.h"
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#include "hpm_i2c_drv.h"
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#include "hpm_gpio_drv.h"
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#include "hpm_debug_console.h"
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#include "hpm_femc_drv.h"
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#include "pinmux.h"
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#include "hpm_pmp_drv.h"
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#include "assert.h"
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#include "hpm_clock_drv.h"
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#include "hpm_sysctl_drv.h"
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#include "hpm_sdxc_drv.h"
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#include "hpm_pwm_drv.h"
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#include "hpm_trgm_drv.h"
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#include "hpm_pllctl_drv.h"
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#include "hpm_enet_drv.h"
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#include "hpm_pcfg_drv.h"
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static board_timer_cb timer_cb;
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static bool invert_led_level;
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/**
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* @brief FLASH configuration option definitions:
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* option[0]:
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* [31:16] 0xfcf9 - FLASH configuration option tag
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* [15:4] 0 - Reserved
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* [3:0] option words (exclude option[0])
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* option[1]:
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* [31:28] Flash probe type
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* 0 - SFDP SDR / 1 - SFDP DDR
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* 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
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* 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
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* 6 - OctaBus DDR (SPI -> OPI DDR)
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* 8 - Xccela DDR (SPI -> OPI DDR)
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* 10 - EcoXiP DDR (SPI -> OPI DDR)
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* [27:24] Command Pads after Power-on Reset
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* 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
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* [23:20] Command Pads after Configuring FLASH
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* 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
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* [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
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* 0 - Not needed
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* 1 - QE bit is at bit 6 in Status Register 1
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* 2 - QE bit is at bit1 in Status Register 2
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* 3 - QE bit is at bit7 in Status Register 2
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* 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
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* [15:8] Dummy cycles
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* 0 - Auto-probed / detected / default value
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* Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
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* [7:4] Misc.
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* 0 - Not used
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* 1 - SPI mode
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* 2 - Internal loopback
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* 3 - External DQS
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* [3:0] Frequency option
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* 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
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*
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* option[2] (Effective only if the bit[3:0] in option[0] > 1)
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* [31:20] Reserved
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* [19:16] IO voltage
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* 0 - 3V / 1 - 1.8V
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* [15:12] Pin group
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* 0 - 1st group / 1 - 2nd group
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* [11:8] Connection selection
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* 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
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* [7:0] Drive Strength
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* 0 - Default value
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* option[3] (Effective only if the bit[3:0] in option[0] > 2, required only for the QSPI NOR FLASH that not supports
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* JESD216)
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* [31:16] reserved
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* [15:12] Sector Erase Command Option, not required here
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* [11:8] Sector Size Option, not required here
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* [7:0] Flash Size Option
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* 0 - 4MB / 1 - 8MB / 2 - 16MB
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*/
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#if defined(FLASH_XIP) && FLASH_XIP
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__attribute__ ((section(".nor_cfg_option"))) const uint32_t option[4] = {0xfcf90001, 0x00000007, 0x1000, 0x0};
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#endif
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#if defined(FLASH_UF2) && FLASH_UF2
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ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATURE;
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#endif
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void board_init_console(void)
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{
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#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE
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#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART
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console_config_t cfg;
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/* uart needs to configure pin function before enabling clock, otherwise the level change of
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uart rx pin when configuring pin function will cause a wrong data to be received.
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And a uart rx dma request will be generated by default uart fifo dma trigger level. */
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init_uart_pins((UART_Type *) BOARD_CONSOLE_UART_BASE);
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/* Configure the UART clock to 24MHz */
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clock_set_source_divider(BOARD_CONSOLE_UART_CLK_NAME, clk_src_osc24m, 1U);
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clock_add_to_group(BOARD_CONSOLE_UART_CLK_NAME, 0);
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cfg.type = BOARD_CONSOLE_TYPE;
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cfg.base = (uint32_t) BOARD_CONSOLE_UART_BASE;
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cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_UART_CLK_NAME);
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cfg.baudrate = BOARD_CONSOLE_UART_BAUDRATE;
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if (status_success != console_init(&cfg)) {
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/* failed to initialize debug console */
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while (1) {
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}
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}
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#else
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while (1) {
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}
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#endif
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#endif
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}
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void board_print_clock_freq(void)
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{
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printf("==============================\n");
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printf(" %s clock summary\n", BOARD_NAME);
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printf("==============================\n");
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printf("cpu0:\t\t %luHz\n", clock_get_frequency(clock_cpu0));
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printf("cpu1:\t\t %luHz\n", clock_get_frequency(clock_cpu1));
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printf("axi0:\t\t %luHz\n", clock_get_frequency(clock_axi0));
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printf("axi1:\t\t %luHz\n", clock_get_frequency(clock_axi1));
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printf("axi2:\t\t %luHz\n", clock_get_frequency(clock_axi2));
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printf("ahb:\t\t %luHz\n", clock_get_frequency(clock_ahb));
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printf("mchtmr0:\t %luHz\n", clock_get_frequency(clock_mchtmr0));
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printf("mchtmr1:\t %luHz\n", clock_get_frequency(clock_mchtmr1));
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printf("xpi0:\t\t %luHz\n", clock_get_frequency(clock_xpi0));
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printf("xpi1:\t\t %luHz\n", clock_get_frequency(clock_xpi1));
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printf("femc:\t\t %luHz\n", clock_get_frequency(clock_femc));
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printf("display:\t %luHz\n", clock_get_frequency(clock_display));
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printf("cam0:\t\t %luHz\n", clock_get_frequency(clock_camera0));
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printf("cam1:\t\t %luHz\n", clock_get_frequency(clock_camera1));
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printf("jpeg:\t\t %luHz\n", clock_get_frequency(clock_jpeg));
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printf("pdma:\t\t %luHz\n", clock_get_frequency(clock_pdma));
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printf("==============================\n");
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}
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void board_init_uart(UART_Type *ptr)
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{
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/* configure uart's pin before opening uart's clock */
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init_uart_pins(ptr);
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board_init_uart_clock(ptr);
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}
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void board_init_ahb(void)
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{
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clock_set_source_divider(clock_ahb,clk_src_pll1_clk1,2);/*200m hz*/
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}
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void board_print_banner(void)
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{
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const uint8_t banner[] = {"\n\
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----------------------------------------------------------------------\n\
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$$\\ $$\\ $$$$$$$\\ $$\\ $$\\ $$\\\n\
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$$ | $$ |$$ __$$\\ $$$\\ $$$ |\\__|\n\
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$$ | $$ |$$ | $$ |$$$$\\ $$$$ |$$\\ $$$$$$$\\ $$$$$$\\ $$$$$$\\\n\
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$$$$$$$$ |$$$$$$$ |$$\\$$\\$$ $$ |$$ |$$ _____|$$ __$$\\ $$ __$$\\\n\
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$$ __$$ |$$ ____/ $$ \\$$$ $$ |$$ |$$ / $$ | \\__|$$ / $$ |\n\
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$$ | $$ |$$ | $$ |\\$ /$$ |$$ |$$ | $$ | $$ | $$ |\n\
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$$ | $$ |$$ | $$ | \\_/ $$ |$$ |\\$$$$$$$\\ $$ | \\$$$$$$ |\n\
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\\__| \\__|\\__| \\__| \\__|\\__| \\_______|\\__| \\______/\n\
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----------------------------------------------------------------------\n"};
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#ifdef SDK_VERSION_STRING
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printf("hpm_sdk: %s\n", SDK_VERSION_STRING);
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#endif
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printf("%s", banner);
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}
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static void board_turnoff_rgb_led(void)
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{
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uint8_t p11_stat;
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uint8_t p12_stat;
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uint8_t p13_stat;
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uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
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HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_GPIO_B_11;
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HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_GPIO_B_12;
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HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_GPIO_B_13;
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HPM_IOC->PAD[IOC_PAD_PB11].PAD_CTL = pad_ctl;
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HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = pad_ctl;
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HPM_IOC->PAD[IOC_PAD_PB13].PAD_CTL = pad_ctl;
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p11_stat = gpio_read_pin(BOARD_G_GPIO_CTRL, GPIO_DI_GPIOB, 11);
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p12_stat = gpio_read_pin(BOARD_G_GPIO_CTRL, GPIO_DI_GPIOB, 12);
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p13_stat = gpio_read_pin(BOARD_G_GPIO_CTRL, GPIO_DI_GPIOB, 13);
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invert_led_level = false;
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/*
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* check led gpio level
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*/
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if ((p11_stat & p12_stat & p13_stat) == 0) {
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/* Rev B */
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invert_led_level = true;
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pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(0);
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HPM_IOC->PAD[IOC_PAD_PB11].PAD_CTL = pad_ctl;
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HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = pad_ctl;
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HPM_IOC->PAD[IOC_PAD_PB13].PAD_CTL = pad_ctl;
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}
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}
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void board_ungate_mchtmr_at_lp_mode(void)
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{
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/* Keep cpu clock on wfi, so that mchtmr irq can still work after wfi */
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sysctl_set_cpu_lp_mode(HPM_SYSCTL, BOARD_RUNNING_CORE, cpu_lp_mode_ungate_cpu_clock);
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}
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void board_init(void)
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{
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board_turnoff_rgb_led();
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board_init_clock();
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board_init_console();
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board_init_pmp();
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board_init_ahb();
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#if BOARD_SHOW_CLOCK
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board_print_clock_freq();
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#endif
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#if BOARD_SHOW_BANNER
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board_print_banner();
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#endif
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}
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void board_init_core1(void)
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{
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board_init_console();
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board_init_pmp();
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}
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void board_init_sdram_pins(void)
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{
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init_sdram_pins();
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}
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uint32_t board_init_femc_clock(void)
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{
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clock_set_source_divider(clock_femc, clk_src_pll2_clk0, 2U); /* 166Mhz */
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/* clock_set_source_divider(clock_femc, clk_src_pll1_clk1, 2U); [> 200Mhz <] */
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return clock_get_frequency(clock_femc);
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}
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uint32_t board_lcdc_clock_init(clock_name_t clock_name, uint32_t pixel_clk_khz);
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#if defined(CONFIG_PANEL_RGB_TM070RDH13) && CONFIG_PANEL_RGB_TM070RDH13
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static void set_reset_pin_level_tm070rdh13(uint8_t level)
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{
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gpio_write_pin(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN, level);
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}
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static void set_backlight_tm070rdh13(uint16_t percent)
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{
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gpio_write_pin(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN, percent > 0 ? 1 : 0);
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}
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void board_init_lcd_rgb_tm070rdh13(void)
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{
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init_lcd_pins(BOARD_LCD_BASE);
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gpio_set_pin_output(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN);
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gpio_set_pin_output(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN);
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hpm_panel_hw_interface_t hw_if = {0};
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hpm_panel_t *panel = hpm_panel_find_device_default();
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const hpm_panel_timing_t *timing = hpm_panel_get_timing(panel);
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uint32_t lcdc_pixel_clk_khz = board_lcdc_clock_init(clock_display, timing->pixel_clock_khz);
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hw_if.set_reset_pin_level = set_reset_pin_level_tm070rdh13;
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hw_if.set_backlight = set_backlight_tm070rdh13;
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hw_if.lcdc_pixel_clk_khz = lcdc_pixel_clk_khz;
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hpm_panel_register_interface(panel, &hw_if);
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printf("name: %s, lcdc_clk: %ukhz\n",
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hpm_panel_get_name(panel),
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lcdc_pixel_clk_khz);
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hpm_panel_reset(panel);
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hpm_panel_init(panel);
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hpm_panel_power_on(panel);
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}
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#endif
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#ifdef CONFIG_HPM_PANEL
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uint32_t board_lcdc_clock_init(clock_name_t clock_name, uint32_t pixel_clk_khz)
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{
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clock_add_to_group(clock_name, 0);
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uint32_t freq_khz = clock_get_frequency(clk_pll4clk0) / 1000;
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uint32_t div = (freq_khz + pixel_clk_khz / 2) / pixel_clk_khz;
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clock_set_source_divider(clock_name, clk_src_pll4_clk0, div);
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return clock_get_frequency(clock_name) / 1000;
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}
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void board_lcd_backlight(bool is_on)
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{
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hpm_panel_t *panel = hpm_panel_find_device_default();
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hpm_panel_set_backlight(panel, is_on == true ? 100 : 0);
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}
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void board_init_lcd(void)
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{
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#ifdef CONFIG_PANEL_RGB_TM070RDH13
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board_init_lcd_rgb_tm070rdh13();
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#endif
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}
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void board_panel_para_to_lcdc(lcdc_config_t *config)
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{
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const hpm_panel_timing_t *timing;
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hpm_panel_t *panel = hpm_panel_find_device_default();
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timing = hpm_panel_get_timing(panel);
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config->resolution_x = timing->hactive;
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config->resolution_y = timing->vactive;
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config->hsync.pulse_width = timing->hsync_len;
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config->hsync.back_porch_pulse = timing->hback_porch;
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config->hsync.front_porch_pulse = timing->hfront_porch;
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config->vsync.pulse_width = timing->vsync_len;
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config->vsync.back_porch_pulse = timing->vback_porch;
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config->vsync.front_porch_pulse = timing->vfront_porch;
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config->control.invert_hsync = timing->hsync_pol;
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config->control.invert_vsync = timing->vsync_pol;
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config->control.invert_href = timing->de_pol;
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config->control.invert_pixel_data = timing->pixel_data_pol;
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config->control.invert_pixel_clock = timing->pixel_clk_pol;
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}
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#endif
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void board_delay_ms(uint32_t ms)
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{
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clock_cpu_delay_ms(ms);
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}
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void board_delay_us(uint32_t us)
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{
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clock_cpu_delay_us(us);
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}
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void board_timer_isr(void)
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{
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if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) {
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gptmr_clear_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH));
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timer_cb();
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}
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}
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SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr);
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void board_timer_create(uint32_t ms, board_timer_cb cb)
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{
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uint32_t gptmr_freq;
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gptmr_channel_config_t config;
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timer_cb = cb;
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gptmr_channel_get_default_config(BOARD_CALLBACK_TIMER, &config);
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clock_add_to_group(BOARD_CALLBACK_TIMER_CLK_NAME, 0);
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gptmr_freq = clock_get_frequency(BOARD_CALLBACK_TIMER_CLK_NAME);
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config.reload = gptmr_freq / 1000 * ms;
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gptmr_channel_config(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH, &config, false);
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gptmr_enable_irq(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_IRQ_MASK(BOARD_CALLBACK_TIMER_CH));
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intc_m_enable_irq_with_priority(BOARD_CALLBACK_TIMER_IRQ, 1);
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gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH);
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}
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void board_i2c_bus_clear(I2C_Type *ptr)
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{
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init_i2c_pins_as_gpio(ptr);
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if (ptr == BOARD_CAP_I2C_BASE) {
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gpio_set_pin_input(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_SDA_GPIO_INDEX, BOARD_CAP_I2C_SDA_GPIO_PIN);
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gpio_set_pin_input(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN);
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if (!gpio_read_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN)) {
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printf("CLK is low, please power cycle the board\n");
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while (1) {
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}
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}
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if (!gpio_read_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_SDA_GPIO_INDEX, BOARD_CAP_I2C_SDA_GPIO_PIN)) {
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printf("SDA is low, try to issue I2C bus clear\n");
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} else {
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printf("I2C bus is ready\n");
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return;
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}
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gpio_set_pin_output(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN);
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while (1) {
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for (uint32_t i = 0; i < 9; i++) {
|
|
gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN, 1);
|
|
board_delay_ms(10);
|
|
gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN, 0);
|
|
board_delay_ms(10);
|
|
}
|
|
board_delay_ms(100);
|
|
}
|
|
printf("I2C bus is cleared\n");
|
|
}
|
|
}
|
|
|
|
void board_init_i2c(I2C_Type *ptr)
|
|
{
|
|
hpm_stat_t stat;
|
|
uint32_t freq;
|
|
i2c_config_t config;
|
|
|
|
board_i2c_bus_clear(ptr);
|
|
|
|
init_i2c_pins(ptr);
|
|
clock_add_to_group(clock_i2c0, 0);
|
|
clock_add_to_group(clock_i2c1, 0);
|
|
clock_add_to_group(clock_i2c2, 0);
|
|
clock_add_to_group(clock_i2c3, 0);
|
|
/* Configure the I2C clock to 24MHz */
|
|
clock_set_source_divider(BOARD_CAP_I2C_CLK_NAME, clk_src_osc24m, 1U);
|
|
|
|
config.i2c_mode = i2c_mode_normal;
|
|
config.is_10bit_addressing = false;
|
|
freq = clock_get_frequency(BOARD_CAP_I2C_CLK_NAME);
|
|
stat = i2c_init_master(BOARD_CAP_I2C_BASE, freq, &config);
|
|
if (stat != status_success) {
|
|
printf("failed to initialize i2c 0x%x\n", (uint32_t)BOARD_CAP_I2C_BASE);
|
|
while (1) {
|
|
}
|
|
}
|
|
}
|
|
|
|
uint32_t board_init_uart_clock(UART_Type *ptr)
|
|
{
|
|
uint32_t freq = 0U;
|
|
clock_name_t clock_name = clock_uart0;
|
|
bool need_init_clock = true;
|
|
if (ptr == HPM_UART0) {
|
|
clock_name = clock_uart0;
|
|
} else if (ptr == HPM_UART1) {
|
|
clock_name = clock_uart1;
|
|
} else if (ptr == HPM_UART2) {
|
|
clock_name = clock_uart2;
|
|
} else if (ptr == HPM_UART3) {
|
|
clock_name = clock_uart3;
|
|
} else if (ptr == HPM_UART4) {
|
|
clock_name = clock_uart4;
|
|
} else if (ptr == HPM_UART5) {
|
|
clock_name = clock_uart5;
|
|
} else if (ptr == HPM_UART6) {
|
|
clock_name = clock_uart6;
|
|
} else if (ptr == HPM_UART7) {
|
|
clock_name = clock_uart7;
|
|
} else if (ptr == HPM_UART8) {
|
|
clock_name = clock_uart8;
|
|
} else if (ptr == HPM_UART9) {
|
|
clock_name = clock_uart9;
|
|
} else if (ptr == HPM_UART10) {
|
|
clock_name = clock_uart10;
|
|
} else if (ptr == HPM_UART11) {
|
|
clock_name = clock_uart11;
|
|
} else if (ptr == HPM_UART12) {
|
|
clock_name = clock_uart12;
|
|
} else if (ptr == HPM_UART13) {
|
|
clock_name = clock_uart13;
|
|
} else if (ptr == HPM_UART14) {
|
|
clock_name = clock_uart14;
|
|
} else if (ptr == HPM_UART15) {
|
|
clock_name = clock_uart15;
|
|
} else {
|
|
/* Unsupported instance */
|
|
need_init_clock = false;
|
|
}
|
|
|
|
if (need_init_clock) {
|
|
clock_set_source_divider(clock_name, clk_src_osc24m, 1);
|
|
clock_add_to_group(clock_name, 0);
|
|
freq = clock_get_frequency(clock_name);
|
|
}
|
|
|
|
return freq;
|
|
}
|
|
|
|
uint32_t board_init_spi_clock(SPI_Type *ptr)
|
|
{
|
|
if (ptr == HPM_SPI2) {
|
|
/* SPI2 clock configure */
|
|
clock_add_to_group(clock_spi2, 0);
|
|
clock_set_source_divider(clock_spi2, clk_src_pll1_clk1, 5U); /* 80MHz */
|
|
|
|
return clock_get_frequency(clock_spi2);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
void board_init_cap_touch(void)
|
|
{
|
|
init_cap_pins();
|
|
gpio_set_pin_output_with_initial(BOARD_CAP_RST_GPIO, BOARD_CAP_RST_GPIO_INDEX, BOARD_CAP_RST_GPIO_PIN, 0);
|
|
gpio_set_pin_output_with_initial(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, 0);
|
|
|
|
board_delay_ms(1);
|
|
gpio_write_pin(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, 1);
|
|
board_delay_ms(10);
|
|
gpio_write_pin(BOARD_CAP_RST_GPIO, BOARD_CAP_RST_GPIO_INDEX, BOARD_CAP_RST_GPIO_PIN, 1);
|
|
|
|
gpio_set_pin_input(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN);
|
|
board_init_i2c(BOARD_CAP_I2C_BASE);
|
|
}
|
|
|
|
void board_init_gpio_pins(void)
|
|
{
|
|
uint8_t led_pin_pull_selsect;
|
|
HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_GPIO_B_12;
|
|
HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
|
|
|
|
led_pin_pull_selsect = gpio_read_pin(BOARD_G_GPIO_CTRL, GPIO_DI_GPIOB, 12);
|
|
init_gpio_pins(led_pin_pull_selsect);
|
|
}
|
|
|
|
void board_init_spi_pins(SPI_Type *ptr)
|
|
{
|
|
init_spi_pins(ptr);
|
|
}
|
|
|
|
void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr)
|
|
{
|
|
init_spi_pins_with_gpio_as_cs(ptr);
|
|
gpio_set_pin_output_with_initial(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(BOARD_SPI_CS_PIN),
|
|
GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL);
|
|
}
|
|
|
|
void board_write_spi_cs(uint32_t pin, uint8_t state)
|
|
{
|
|
gpio_write_pin(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(pin), GPIO_GET_PIN_INDEX(pin), state);
|
|
}
|
|
|
|
uint8_t board_get_led_pwm_off_level(void)
|
|
{
|
|
if (invert_led_level) {
|
|
return BOARD_LED_ON_LEVEL;
|
|
} else {
|
|
return BOARD_LED_OFF_LEVEL;
|
|
}
|
|
}
|
|
|
|
uint8_t board_get_led_gpio_off_level(void)
|
|
{
|
|
if (invert_led_level) {
|
|
return BOARD_LED_ON_LEVEL;
|
|
} else {
|
|
return BOARD_LED_OFF_LEVEL;
|
|
}
|
|
}
|
|
|
|
void board_init_led_pins(void)
|
|
{
|
|
board_turnoff_rgb_led();
|
|
init_led_pins_as_gpio();
|
|
gpio_set_pin_output_with_initial(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, board_get_led_gpio_off_level());
|
|
gpio_set_pin_output_with_initial(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, board_get_led_gpio_off_level());
|
|
gpio_set_pin_output_with_initial(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, board_get_led_gpio_off_level());
|
|
}
|
|
|
|
void board_led_toggle(void)
|
|
{
|
|
#ifdef BOARD_LED_TOGGLE_RGB
|
|
static uint8_t i;
|
|
gpio_write_port(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, invert_led_level ? ((1 << i) << BOARD_R_GPIO_PIN) : ((7 & ~(1 << i)) << BOARD_R_GPIO_PIN));
|
|
i++;
|
|
i = i % 3;
|
|
#else
|
|
gpio_toggle_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN);
|
|
#endif
|
|
}
|
|
|
|
void board_led_write(uint8_t state)
|
|
{
|
|
gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state);
|
|
}
|
|
|
|
void board_init_cam_pins(void)
|
|
{
|
|
init_cam_pins();
|
|
/* enable cam RST pin out with high level */
|
|
gpio_set_pin_output_with_initial(BOARD_CAM_RST_GPIO_CTRL, BOARD_CAM_RST_GPIO_INDEX, BOARD_CAM_RST_GPIO_PIN, 1);
|
|
}
|
|
|
|
void board_write_cam_rst(uint8_t state)
|
|
{
|
|
gpio_write_pin(BOARD_CAM_RST_GPIO_CTRL, BOARD_CAM_RST_GPIO_INDEX, BOARD_CAM_RST_GPIO_PIN, state);
|
|
|
|
}
|
|
|
|
void board_init_usb_pins(void)
|
|
{
|
|
/* set pull-up for USBx OC pins and ID pins */
|
|
init_usb_pins();
|
|
|
|
/* configure USBx ID pins as input function */
|
|
gpio_set_pin_input(BOARD_USB0_ID_PORT, BOARD_USB0_ID_GPIO_INDEX, BOARD_USB0_ID_GPIO_PIN);
|
|
gpio_set_pin_input(BOARD_USB1_ID_PORT, BOARD_USB1_ID_GPIO_INDEX, BOARD_USB1_ID_GPIO_PIN);
|
|
|
|
/* configure USBx OC Flag pins as input function */
|
|
gpio_set_pin_input(BOARD_USB0_OC_PORT, BOARD_USB0_OC_GPIO_INDEX, BOARD_USB0_OC_GPIO_PIN);
|
|
gpio_set_pin_input(BOARD_USB1_OC_PORT, BOARD_USB1_OC_GPIO_INDEX, BOARD_USB1_OC_GPIO_PIN);
|
|
}
|
|
|
|
void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level)
|
|
{
|
|
(void) usb_index;
|
|
(void) level;
|
|
}
|
|
|
|
void board_init_pmp(void)
|
|
{
|
|
uint32_t start_addr;
|
|
uint32_t end_addr;
|
|
uint32_t length;
|
|
pmp_entry_t pmp_entry[16];
|
|
uint8_t index = 0;
|
|
|
|
/* Init noncachable memory */
|
|
extern uint32_t __noncacheable_start__[];
|
|
extern uint32_t __noncacheable_end__[];
|
|
start_addr = (uint32_t) __noncacheable_start__;
|
|
end_addr = (uint32_t) __noncacheable_end__;
|
|
length = end_addr - start_addr;
|
|
if (length > 0) {
|
|
/* Ensure the address and the length are power of 2 aligned */
|
|
assert((length & (length - 1U)) == 0U);
|
|
assert((start_addr & (length - 1U)) == 0U);
|
|
pmp_entry[index].pmp_addr = PMP_NAPOT_ADDR(start_addr, length);
|
|
pmp_entry[index].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK);
|
|
pmp_entry[index].pma_addr = PMA_NAPOT_ADDR(start_addr, length);
|
|
pmp_entry[index].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN);
|
|
index++;
|
|
}
|
|
|
|
pmp_config(&pmp_entry[0], index);
|
|
}
|
|
|
|
void board_init_clock(void)
|
|
{
|
|
uint32_t cpu0_freq = clock_get_frequency(clock_cpu0);
|
|
if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) {
|
|
/* Configure the External OSC ramp-up time: ~9ms */
|
|
pllctl_xtal_set_rampup_time(HPM_PLLCTL, 32UL * 1000UL * 9U);
|
|
|
|
/* Select clock setting preset1 */
|
|
sysctl_clock_set_preset(HPM_SYSCTL, sysctl_preset_1);
|
|
}
|
|
|
|
/* Add most Clocks to group 0 */
|
|
/* not open uart clock in this API, uart should configure pin function before opening clock */
|
|
clock_add_to_group(clock_cpu0, 0);
|
|
clock_add_to_group(clock_mchtmr0, 0);
|
|
clock_add_to_group(clock_axi0, 0);
|
|
clock_add_to_group(clock_axi1, 0);
|
|
clock_add_to_group(clock_axi2, 0);
|
|
clock_add_to_group(clock_ahb, 0);
|
|
clock_add_to_group(clock_femc, 0);
|
|
clock_add_to_group(clock_xpi0, 0);
|
|
clock_add_to_group(clock_xpi1, 0);
|
|
clock_add_to_group(clock_gptmr0, 0);
|
|
clock_add_to_group(clock_gptmr1, 0);
|
|
clock_add_to_group(clock_gptmr2, 0);
|
|
clock_add_to_group(clock_gptmr3, 0);
|
|
clock_add_to_group(clock_gptmr4, 0);
|
|
clock_add_to_group(clock_gptmr5, 0);
|
|
clock_add_to_group(clock_gptmr6, 0);
|
|
clock_add_to_group(clock_gptmr7, 0);
|
|
clock_add_to_group(clock_i2c0, 0);
|
|
clock_add_to_group(clock_i2c1, 0);
|
|
clock_add_to_group(clock_i2c2, 0);
|
|
clock_add_to_group(clock_i2c3, 0);
|
|
clock_add_to_group(clock_spi0, 0);
|
|
clock_add_to_group(clock_spi1, 0);
|
|
clock_add_to_group(clock_spi2, 0);
|
|
clock_add_to_group(clock_spi3, 0);
|
|
clock_add_to_group(clock_can0, 0);
|
|
clock_add_to_group(clock_can1, 0);
|
|
clock_add_to_group(clock_can2, 0);
|
|
clock_add_to_group(clock_can3, 0);
|
|
clock_add_to_group(clock_display, 0);
|
|
clock_add_to_group(clock_sdxc0, 0);
|
|
clock_add_to_group(clock_sdxc1, 0);
|
|
clock_add_to_group(clock_camera0, 0);
|
|
clock_add_to_group(clock_camera1, 0);
|
|
clock_add_to_group(clock_ptpc, 0);
|
|
clock_add_to_group(clock_ref0, 0);
|
|
clock_add_to_group(clock_ref1, 0);
|
|
clock_add_to_group(clock_watchdog0, 0);
|
|
clock_add_to_group(clock_eth0, 0);
|
|
clock_add_to_group(clock_eth1, 0);
|
|
clock_add_to_group(clock_sdp, 0);
|
|
clock_add_to_group(clock_xdma, 0);
|
|
clock_add_to_group(clock_ram0, 0);
|
|
clock_add_to_group(clock_ram1, 0);
|
|
clock_add_to_group(clock_usb0, 0);
|
|
clock_add_to_group(clock_usb1, 0);
|
|
clock_add_to_group(clock_jpeg, 0);
|
|
clock_add_to_group(clock_pdma, 0);
|
|
clock_add_to_group(clock_kman, 0);
|
|
clock_add_to_group(clock_gpio, 0);
|
|
clock_add_to_group(clock_mbx0, 0);
|
|
clock_add_to_group(clock_hdma, 0);
|
|
clock_add_to_group(clock_rng, 0);
|
|
clock_add_to_group(clock_mot0, 0);
|
|
clock_add_to_group(clock_mot1, 0);
|
|
clock_add_to_group(clock_mot2, 0);
|
|
clock_add_to_group(clock_mot3, 0);
|
|
clock_add_to_group(clock_acmp, 0);
|
|
clock_add_to_group(clock_dao, 0);
|
|
clock_add_to_group(clock_msyn, 0);
|
|
clock_add_to_group(clock_lmm0, 0);
|
|
clock_add_to_group(clock_lmm1, 0);
|
|
clock_add_to_group(clock_pdm, 0);
|
|
|
|
clock_add_to_group(clock_adc0, 0);
|
|
clock_add_to_group(clock_adc1, 0);
|
|
clock_add_to_group(clock_adc2, 0);
|
|
clock_add_to_group(clock_adc3, 0);
|
|
|
|
clock_add_to_group(clock_i2s0, 0);
|
|
clock_add_to_group(clock_i2s1, 0);
|
|
clock_add_to_group(clock_i2s2, 0);
|
|
clock_add_to_group(clock_i2s3, 0);
|
|
/* Connect Group0 to CPU0 */
|
|
clock_connect_group_to_cpu(0, 0);
|
|
|
|
/* Add the CPU1 clock to Group1 */
|
|
clock_add_to_group(clock_mchtmr1, 1);
|
|
clock_add_to_group(clock_mbx1, 1);
|
|
/* Connect Group1 to CPU1 */
|
|
clock_connect_group_to_cpu(1, 1);
|
|
|
|
/* Bump up DCDC voltage to 1200mv */
|
|
pcfg_dcdc_set_voltage(HPM_PCFG, 1200);
|
|
pcfg_dcdc_switch_to_dcm_mode(HPM_PCFG);
|
|
|
|
if (status_success != pllctl_init_int_pll_with_freq(HPM_PLLCTL, 0, BOARD_CPU_FREQ)) {
|
|
printf("Failed to set pll0_clk0 to %luHz\n", BOARD_CPU_FREQ);
|
|
while (1) {
|
|
}
|
|
}
|
|
|
|
clock_set_source_divider(clock_cpu0, clk_src_pll0_clk0, 1);
|
|
clock_set_source_divider(clock_cpu1, clk_src_pll0_clk0, 1);
|
|
clock_update_core_clock();
|
|
|
|
clock_set_source_divider(clock_ahb, clk_src_pll1_clk1, 2); /*200m hz*/
|
|
clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1);
|
|
clock_set_source_divider(clock_mchtmr1, clk_src_osc24m, 1);
|
|
}
|
|
|
|
uint32_t board_init_cam_clock(CAM_Type *ptr)
|
|
{
|
|
uint32_t freq = 0;
|
|
if (ptr == HPM_CAM0) {
|
|
/* Configure camera clock to 24MHz */
|
|
clock_set_source_divider(clock_camera0, clk_src_osc24m, 1U);
|
|
freq = clock_get_frequency(clock_camera0);
|
|
} else if (ptr == HPM_CAM1) {
|
|
/* Configure camera clock to 24MHz */
|
|
clock_set_source_divider(clock_camera1, clk_src_osc24m, 1U);
|
|
freq = clock_get_frequency(clock_camera1);
|
|
} else {
|
|
/* Invalid camera instance */
|
|
}
|
|
return freq;
|
|
}
|
|
|
|
uint32_t board_init_lcd_clock(void)
|
|
{
|
|
uint32_t freq;
|
|
clock_add_to_group(clock_display, 0);
|
|
/* Configure LCDC clock to 59.4MHz */
|
|
clock_set_source_divider(clock_display, (clk_src_t) clock_source_pll4_clk0, 10U);
|
|
freq = clock_get_frequency(clock_display);
|
|
return freq;
|
|
}
|
|
|
|
uint32_t board_init_dao_clock(void)
|
|
{
|
|
clock_add_to_group(clock_dao, 0);
|
|
|
|
sysctl_config_clock(HPM_SYSCTL, clock_node_aud1, clock_source_pll3_clk0, 25);
|
|
sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s1, clock_source_i2s_aud1_clk);
|
|
|
|
return clock_get_frequency(clock_dao);
|
|
}
|
|
|
|
uint32_t board_init_pdm_clock(void)
|
|
{
|
|
clock_add_to_group(clock_pdm, 0);
|
|
|
|
sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25);
|
|
sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s0, clock_source_i2s_aud0_clk);
|
|
|
|
return clock_get_frequency(clock_pdm);
|
|
}
|
|
|
|
hpm_stat_t board_set_audio_pll_clock(uint32_t freq)
|
|
{
|
|
return pllctl_init_frac_pll_with_freq(HPM_PLLCTL, 3, freq); /* pll3clk */
|
|
}
|
|
|
|
void board_init_i2s_pins(I2S_Type *ptr)
|
|
{
|
|
init_i2s_pins(ptr);
|
|
}
|
|
|
|
uint32_t board_init_i2s_clock(I2S_Type *ptr)
|
|
{
|
|
uint32_t freq = 0;
|
|
|
|
if (ptr == HPM_I2S0) {
|
|
clock_add_to_group(clock_i2s0, 0);
|
|
|
|
sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25);
|
|
sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s0, clock_source_i2s_aud0_clk);
|
|
|
|
freq = clock_get_frequency(clock_i2s0);
|
|
} else if (ptr == HPM_I2S1) {
|
|
clock_add_to_group(clock_i2s1, 0);
|
|
|
|
sysctl_config_clock(HPM_SYSCTL, clock_node_aud1, clock_source_pll3_clk0, 25);
|
|
sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s1, clock_source_i2s_aud1_clk);
|
|
|
|
freq = clock_get_frequency(clock_i2s1);
|
|
} else {
|
|
;
|
|
}
|
|
|
|
return freq;
|
|
}
|
|
|
|
/* adjust I2S source clock base on sample rate */
|
|
uint32_t board_config_i2s_clock(I2S_Type *ptr, uint32_t sample_rate)
|
|
{
|
|
uint32_t freq = 0;
|
|
|
|
if (ptr == HPM_I2S0) {
|
|
clock_add_to_group(clock_i2s0, 0);
|
|
if ((sample_rate % 22050) == 0) {
|
|
clock_set_source_divider(clock_aud0, clk_src_pll3_clk0, 54); /* config clock_aud1 for 22050*n sample rate */
|
|
} else {
|
|
clock_set_source_divider(clock_aud0, clk_src_pll3_clk0, 25); /* config clock_aud0 for 8000*n sample rate */
|
|
}
|
|
clock_set_i2s_source(clock_i2s0, clk_i2s_src_aud0);
|
|
freq = clock_get_frequency(clock_i2s0);
|
|
} else if (ptr == HPM_I2S1) {
|
|
clock_add_to_group(clock_i2s1, 0);
|
|
if ((sample_rate % 22050) == 0) {
|
|
clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 54); /* config clock_aud1 for 22050*n sample rate */
|
|
} else {
|
|
clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 25); /* config clock_aud0 for 8000*n sample rate */
|
|
}
|
|
clock_set_i2s_source(clock_i2s1, clk_i2s_src_aud1);
|
|
freq = clock_get_frequency(clock_i2s1);
|
|
} else {
|
|
;
|
|
}
|
|
|
|
return freq;
|
|
}
|
|
|
|
void board_init_adc12_pins(void)
|
|
{
|
|
init_adc12_pins();
|
|
}
|
|
|
|
void board_init_adc16_pins(void)
|
|
{
|
|
init_adc16_pins();
|
|
}
|
|
|
|
uint32_t board_init_adc12_clock(ADC12_Type *ptr, bool clk_src_ahb)
|
|
{
|
|
uint32_t freq = 0;
|
|
|
|
if (ptr == HPM_ADC0) {
|
|
if (clk_src_ahb) {
|
|
/* Configure the ADC clock from AHB (@200MHz by default)*/
|
|
clock_set_adc_source(clock_adc0, clk_adc_src_ahb0);
|
|
} else {
|
|
/* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */
|
|
clock_set_adc_source(clock_adc0, clk_adc_src_ana0);
|
|
clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U);
|
|
}
|
|
freq = clock_get_frequency(clock_adc0);
|
|
} else if (ptr == HPM_ADC1) {
|
|
if (clk_src_ahb) {
|
|
/* Configure the ADC clock from AHB (@200MHz by default)*/
|
|
clock_set_adc_source(clock_adc1, clk_adc_src_ahb0);
|
|
} else {
|
|
/* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */
|
|
clock_set_adc_source(clock_adc1, clk_adc_src_ana1);
|
|
clock_set_source_divider(clock_ana1, clk_src_pll1_clk1, 2U);
|
|
}
|
|
freq = clock_get_frequency(clock_adc1);
|
|
} else if (ptr == HPM_ADC2) {
|
|
if (clk_src_ahb) {
|
|
/* Configure the ADC clock from AHB (@200MHz by default)*/
|
|
clock_set_adc_source(clock_adc2, clk_adc_src_ahb0);
|
|
} else {
|
|
/* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */
|
|
clock_set_adc_source(clock_adc2, clk_adc_src_ana2);
|
|
clock_set_source_divider(clock_ana2, clk_src_pll1_clk1, 2U);
|
|
}
|
|
freq = clock_get_frequency(clock_adc2);
|
|
}
|
|
|
|
return freq;
|
|
}
|
|
|
|
uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb)
|
|
{
|
|
uint32_t freq = 0;
|
|
|
|
if (ptr == HPM_ADC3) {
|
|
if (clk_src_ahb) {
|
|
/* Configure the ADC clock from AHB (@200MHz by default)*/
|
|
clock_set_adc_source(clock_adc3, clk_adc_src_ahb0);
|
|
} else {
|
|
/* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */
|
|
clock_set_adc_source(clock_adc3, clk_adc_src_ana2);
|
|
clock_set_source_divider(clock_ana2, clk_src_pll1_clk1, 2U);
|
|
}
|
|
|
|
freq = clock_get_frequency(clock_adc3);
|
|
}
|
|
|
|
return freq;
|
|
}
|
|
|
|
void board_init_can(CAN_Type *ptr)
|
|
{
|
|
init_can_pins(ptr);
|
|
}
|
|
|
|
uint32_t board_init_can_clock(CAN_Type *ptr)
|
|
{
|
|
uint32_t freq = 0;
|
|
if (ptr == HPM_CAN0) {
|
|
/* Set the CAN0 peripheral clock to 80MHz */
|
|
clock_set_source_divider(clock_can0, clk_src_pll1_clk1, 5);
|
|
freq = clock_get_frequency(clock_can0);
|
|
} else if (ptr == HPM_CAN1) {
|
|
/* Set the CAN1 peripheral clock to 80MHz */
|
|
clock_set_source_divider(clock_can1, clk_src_pll1_clk1, 5);
|
|
freq = clock_get_frequency(clock_can1);
|
|
} else if (ptr == HPM_CAN2) {
|
|
/* Set the CAN2 peripheral clock to 80MHz */
|
|
clock_set_source_divider(clock_can2, clk_src_pll1_clk1, 5);
|
|
freq = clock_get_frequency(clock_can2);
|
|
} else if (ptr == HPM_CAN3) {
|
|
/* Set the CAN3 peripheral clock to 80MHz */
|
|
clock_set_source_divider(clock_can3, clk_src_pll1_clk1, 5);
|
|
freq = clock_get_frequency(clock_can3);
|
|
} else {
|
|
/* Invalid CAN instance */
|
|
}
|
|
return freq;
|
|
}
|
|
|
|
uint32_t board_init_pwm_clock(PWM_Type *ptr)
|
|
{
|
|
uint32_t freq = 0;
|
|
if (ptr == HPM_PWM0) {
|
|
clock_add_to_group(clock_mot0, 0);
|
|
freq = clock_get_frequency(clock_mot0);
|
|
} else if (ptr == HPM_PWM1) {
|
|
clock_add_to_group(clock_mot1, 0);
|
|
freq = clock_get_frequency(clock_mot1);
|
|
} else if (ptr == HPM_PWM2) {
|
|
clock_add_to_group(clock_mot2, 0);
|
|
freq = clock_get_frequency(clock_mot2);
|
|
} else if (ptr == HPM_PWM3) {
|
|
clock_add_to_group(clock_mot3, 0);
|
|
freq = clock_get_frequency(clock_mot3);
|
|
} else {
|
|
|
|
}
|
|
return freq;
|
|
}
|
|
|
|
uint32_t board_init_gptmr_clock(GPTMR_Type *ptr)
|
|
{
|
|
uint32_t freq = 0;
|
|
|
|
if (ptr == HPM_GPTMR0) {
|
|
clock_add_to_group(clock_gptmr0, 0);
|
|
clock_set_source_divider(clock_gptmr0, clk_src_pll1_clk1, 4);
|
|
freq = clock_get_frequency(clock_gptmr0);
|
|
}
|
|
else if (ptr == HPM_GPTMR1) {
|
|
clock_add_to_group(clock_gptmr1, 0);
|
|
clock_set_source_divider(clock_gptmr1, clk_src_pll1_clk1, 4);
|
|
freq = clock_get_frequency(clock_gptmr1);
|
|
}
|
|
else if (ptr == HPM_GPTMR2) {
|
|
clock_add_to_group(clock_gptmr2, 0);
|
|
clock_set_source_divider(clock_gptmr2, clk_src_pll1_clk1, 4);
|
|
freq = clock_get_frequency(clock_gptmr2);
|
|
}
|
|
else if (ptr == HPM_GPTMR3) {
|
|
clock_add_to_group(clock_gptmr3, 0);
|
|
clock_set_source_divider(clock_gptmr3, clk_src_pll1_clk1, 4);
|
|
freq = clock_get_frequency(clock_gptmr3);
|
|
}
|
|
else if (ptr == HPM_GPTMR4) {
|
|
clock_add_to_group(clock_gptmr4, 0);
|
|
clock_set_source_divider(clock_gptmr4, clk_src_pll1_clk1, 4);
|
|
freq = clock_get_frequency(clock_gptmr4);
|
|
}
|
|
else if (ptr == HPM_GPTMR5) {
|
|
clock_add_to_group(clock_gptmr5, 0);
|
|
clock_set_source_divider(clock_gptmr5, clk_src_pll1_clk1, 4);
|
|
freq = clock_get_frequency(clock_gptmr5);
|
|
}
|
|
else if (ptr == HPM_GPTMR6) {
|
|
clock_add_to_group(clock_gptmr6, 0);
|
|
clock_set_source_divider(clock_gptmr6, clk_src_pll1_clk1, 4);
|
|
freq = clock_get_frequency(clock_gptmr6);
|
|
}
|
|
else if (ptr == HPM_GPTMR7) {
|
|
clock_add_to_group(clock_gptmr7, 0);
|
|
clock_set_source_divider(clock_gptmr7, clk_src_pll1_clk1, 4);
|
|
freq = clock_get_frequency(clock_gptmr7);
|
|
}
|
|
else {
|
|
/* Invalid instance */
|
|
}
|
|
return freq;
|
|
}
|
|
|
|
|
|
/*
|
|
* this function will be called during startup to initialize external memory for data use
|
|
*/
|
|
void _init_ext_ram(void)
|
|
{
|
|
uint32_t femc_clk_in_hz;
|
|
clock_add_to_group(clock_femc, 0);
|
|
board_init_sdram_pins();
|
|
femc_clk_in_hz = board_init_femc_clock();
|
|
|
|
femc_config_t config = {0};
|
|
femc_sdram_config_t sdram_config = {0};
|
|
|
|
femc_default_config(HPM_FEMC, &config);
|
|
femc_init(HPM_FEMC, &config);
|
|
|
|
sdram_config.bank_num = FEMC_SDRAM_BANK_NUM_4;
|
|
sdram_config.prescaler = 0x3;
|
|
sdram_config.burst_len_in_byte = 8;
|
|
sdram_config.auto_refresh_count_in_one_burst = 1;
|
|
sdram_config.col_addr_bits = FEMC_SDRAM_COLUMN_ADDR_9_BITS;
|
|
sdram_config.cas_latency = FEMC_SDRAM_CAS_LATENCY_3;
|
|
|
|
sdram_config.precharge_to_act_in_ns = 18; /* Trp */
|
|
sdram_config.act_to_rw_in_ns = 18; /* Trcd */
|
|
sdram_config.refresh_recover_in_ns = 70; /* Trfc/Trc */
|
|
sdram_config.write_recover_in_ns = 12; /* Twr/Tdpl */
|
|
sdram_config.cke_off_in_ns = 42; /* Trcd */
|
|
sdram_config.act_to_precharge_in_ns = 42; /* Tras */
|
|
|
|
sdram_config.self_refresh_recover_in_ns = 66; /* Txsr */
|
|
sdram_config.refresh_to_refresh_in_ns = 66; /* Trfc/Trc */
|
|
sdram_config.act_to_act_in_ns = 12; /* Trrd */
|
|
sdram_config.idle_timeout_in_ns = 6;
|
|
sdram_config.cs_mux_pin = FEMC_IO_MUX_NOT_USED;
|
|
|
|
sdram_config.cs = BOARD_SDRAM_CS;
|
|
sdram_config.base_address = BOARD_SDRAM_ADDRESS;
|
|
sdram_config.size_in_byte = BOARD_SDRAM_SIZE;
|
|
sdram_config.port_size = BOARD_SDRAM_PORT_SIZE;
|
|
sdram_config.refresh_count = BOARD_SDRAM_REFRESH_COUNT;
|
|
sdram_config.refresh_in_ms = BOARD_SDRAM_REFRESH_IN_MS;
|
|
sdram_config.data_width_in_byte = BOARD_SDRAM_DATA_WIDTH_IN_BYTE;
|
|
sdram_config.delay_cell_disable = true;
|
|
sdram_config.delay_cell_value = 0;
|
|
|
|
femc_config_sdram(HPM_FEMC, femc_clk_in_hz, &sdram_config);
|
|
}
|
|
|
|
|
|
void board_sd_power_switch(SDXC_Type *ptr, bool on_off)
|
|
{
|
|
/* This feature is not supported on current board */
|
|
}
|
|
|
|
|
|
uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq, bool need_inverse)
|
|
{
|
|
uint32_t actual_freq = 0;
|
|
do {
|
|
if (ptr != HPM_SDXC1) {
|
|
break;
|
|
}
|
|
clock_name_t sdxc_clk = (ptr == HPM_SDXC0) ? clock_sdxc0 : clock_sdxc1;
|
|
sdxc_enable_inverse_clock(ptr, false);
|
|
sdxc_enable_sd_clock(ptr, false);
|
|
/* Configure the clock below 400KHz for the identification state */
|
|
if (freq <= 400000UL) {
|
|
clock_set_source_divider(sdxc_clk, clk_src_osc24m, 63);
|
|
}
|
|
/* configure the clock to 24MHz for the SDR12/Default speed */
|
|
else if (freq <= 26000000UL) {
|
|
clock_set_source_divider(sdxc_clk, clk_src_osc24m, 1);
|
|
}
|
|
/* Configure the clock to 50MHz for the SDR25/High speed/50MHz DDR/50MHz SDR */
|
|
else if (freq <= 52000000UL) {
|
|
clock_set_source_divider(sdxc_clk, clk_src_pll1_clk1, 8);
|
|
}
|
|
/* Configure the clock to 100MHz for the SDR50 */
|
|
else if (freq <= 100000000UL) {
|
|
clock_set_source_divider(sdxc_clk, clk_src_pll1_clk1, 4);
|
|
}
|
|
/* Configure the clock to 166MHz for SDR104/HS200/HS400 */
|
|
else if (freq <= 208000000UL) {
|
|
clock_set_source_divider(sdxc_clk, clk_src_pll2_clk0, 2);
|
|
}
|
|
/* For other unsupported clock ranges, configure the clock to 24MHz */
|
|
else {
|
|
clock_set_source_divider(sdxc_clk, clk_src_osc24m, 1);
|
|
}
|
|
if (need_inverse) {
|
|
sdxc_enable_inverse_clock(ptr, true);
|
|
}
|
|
sdxc_enable_sd_clock(ptr, true);
|
|
actual_freq = clock_get_frequency(sdxc_clk);
|
|
} while (false);
|
|
|
|
return actual_freq;
|
|
}
|
|
|
|
static void set_rgb_output_off(PWM_Type *ptr, uint8_t pin, uint8_t cmp_index)
|
|
{
|
|
pwm_cmp_config_t cmp_config = {0};
|
|
pwm_output_channel_t ch_config = {0};
|
|
|
|
pwm_stop_counter(ptr);
|
|
pwm_get_default_cmp_config(ptr, &cmp_config);
|
|
pwm_get_default_output_channel_config(ptr, &ch_config);
|
|
|
|
pwm_set_reload(ptr, 0, 0xF);
|
|
pwm_set_start_count(ptr, 0, 0);
|
|
|
|
cmp_config.mode = pwm_cmp_mode_output_compare;
|
|
cmp_config.cmp = 0x10;
|
|
cmp_config.update_trigger = pwm_shadow_register_update_on_modify;
|
|
pwm_config_cmp(ptr, cmp_index, &cmp_config);
|
|
|
|
ch_config.cmp_start_index = cmp_index;
|
|
ch_config.cmp_end_index = cmp_index;
|
|
ch_config.invert_output = false;
|
|
|
|
pwm_config_output_channel(ptr, pin, &ch_config);
|
|
}
|
|
|
|
void board_init_rgb_pwm_pins(void)
|
|
{
|
|
trgm_output_t config = {0};
|
|
board_turnoff_rgb_led();
|
|
|
|
set_rgb_output_off(BOARD_RED_PWM, BOARD_RED_PWM_OUT, BOARD_RED_PWM_CMP);
|
|
set_rgb_output_off(BOARD_GREEN_PWM, BOARD_GREEN_PWM_OUT, BOARD_GREEN_PWM_CMP);
|
|
set_rgb_output_off(BOARD_BLUE_PWM, BOARD_BLUE_PWM_OUT, BOARD_BLUE_PWM_CMP);
|
|
|
|
init_rgb_pwm_pins();
|
|
|
|
config.type = 0;
|
|
config.invert = false;
|
|
|
|
/* Red: TRGM1 P1 */
|
|
config.input = HPM_TRGM1_INPUT_SRC_PWM1_CH8REF;
|
|
trgm_output_config(HPM_TRGM1, TRGM_TRGOCFG_TRGM_OUT1, &config);
|
|
|
|
/* Green: TRGM0 P6 */
|
|
config.input = HPM_TRGM0_INPUT_SRC_PWM0_CH8REF;
|
|
trgm_output_config(HPM_TRGM0, TRGM_TRGOCFG_TRGM_OUT6, &config);
|
|
|
|
/* Blue: TRGM1 P3 */
|
|
config.input = HPM_TRGM1_INPUT_SRC_PWM1_CH9REF;
|
|
trgm_output_config(HPM_TRGM1, TRGM_TRGOCFG_TRGM_OUT3, &config);
|
|
}
|
|
|
|
void board_disable_output_rgb_led(uint8_t color)
|
|
{
|
|
switch (color) {
|
|
case BOARD_RGB_RED:
|
|
trgm_disable_io_output(HPM_TRGM1, 1 << 1);
|
|
break;
|
|
case BOARD_RGB_GREEN:
|
|
trgm_disable_io_output(HPM_TRGM0, 1 << 6);
|
|
break;
|
|
case BOARD_RGB_BLUE:
|
|
trgm_disable_io_output(HPM_TRGM1, 1 << 3);
|
|
break;
|
|
default:
|
|
while (1) {
|
|
;
|
|
}
|
|
}
|
|
}
|
|
|
|
void board_enable_output_rgb_led(uint8_t color)
|
|
{
|
|
switch (color) {
|
|
case BOARD_RGB_RED:
|
|
trgm_enable_io_output(HPM_TRGM1, 1 << 1);
|
|
break;
|
|
case BOARD_RGB_GREEN:
|
|
trgm_enable_io_output(HPM_TRGM0, 1 << 6);
|
|
break;
|
|
case BOARD_RGB_BLUE:
|
|
trgm_enable_io_output(HPM_TRGM1, 1 << 3);
|
|
break;
|
|
default:
|
|
while (1) {
|
|
;
|
|
}
|
|
}
|
|
}
|
|
|
|
hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr)
|
|
{
|
|
/* set clock source */
|
|
if (ptr == HPM_ENET0) {
|
|
/* make sure pll0_clk0 output clock at 400MHz to get a clock at 100MHz for the enet0 ptp function */
|
|
clock_set_source_divider(clock_ptp0, clk_src_pll1_clk1, 4); /* 100MHz */
|
|
} else if (ptr == HPM_ENET1) {
|
|
/* make sure pll0_clk0 output clock at 400MHz to get a clock at 100MHz for the enet1 ptp function */
|
|
clock_set_source_divider(clock_ptp1, clk_src_pll1_clk1, 4); /* 100MHz */
|
|
} else {
|
|
return status_invalid_argument;
|
|
}
|
|
|
|
return status_success;
|
|
}
|
|
|
|
hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal)
|
|
{
|
|
/* Configure Enet clock to output reference clock */
|
|
if (ptr == HPM_ENET1) {
|
|
if (internal) {
|
|
/* set pll output frequency at 1GHz */
|
|
if (pllctl_init_int_pll_with_freq(HPM_PLLCTL, PLLCTL_PLL_PLL2, 1000000000UL) == status_success) {
|
|
/* set pll2_clk1 output frequence at 250MHz from PLL2 divided by 4 */
|
|
pllctl_set_div(HPM_PLLCTL, PLLCTL_PLL_PLL2, 1, 4);
|
|
/* set eth clock frequency at 50MHz for enet0 */
|
|
clock_set_source_divider(ptr == HPM_ENET0 ? clock_eth0 : clock_eth1, clk_src_pll2_clk1, 5);
|
|
} else {
|
|
return status_fail;
|
|
}
|
|
}
|
|
} else {
|
|
return status_invalid_argument;
|
|
}
|
|
|
|
enet_rmii_enable_clock(ptr, internal);
|
|
|
|
return status_success;
|
|
}
|
|
|
|
hpm_stat_t board_init_enet_rgmii_clock_delay(ENET_Type *ptr)
|
|
{
|
|
if (ptr == HPM_ENET0) {
|
|
return enet_rgmii_set_clock_delay(ptr, BOARD_ENET_RGMII_TX_DLY, BOARD_ENET_RGMII_RX_DLY);
|
|
}
|
|
|
|
return status_invalid_argument;
|
|
}
|
|
|
|
hpm_stat_t board_init_enet_pins(ENET_Type *ptr)
|
|
{
|
|
init_enet_pins(ptr);
|
|
|
|
if (ptr == HPM_ENET0) {
|
|
gpio_set_pin_output_with_initial(BOARD_ENET_RGMII_RST_GPIO, BOARD_ENET_RGMII_RST_GPIO_INDEX, BOARD_ENET_RGMII_RST_GPIO_PIN, 0);
|
|
} else if (ptr == HPM_ENET1) {
|
|
gpio_set_pin_output_with_initial(BOARD_ENET_RMII_RST_GPIO, BOARD_ENET_RMII_RST_GPIO_INDEX, BOARD_ENET_RMII_RST_GPIO_PIN, 0);
|
|
} else {
|
|
return status_invalid_argument;
|
|
}
|
|
|
|
return status_success;
|
|
}
|
|
|
|
hpm_stat_t board_reset_enet_phy(ENET_Type *ptr)
|
|
{
|
|
if (ptr == HPM_ENET0) {
|
|
gpio_write_pin(BOARD_ENET_RGMII_RST_GPIO, BOARD_ENET_RGMII_RST_GPIO_INDEX, BOARD_ENET_RGMII_RST_GPIO_PIN, 0);
|
|
board_delay_ms(1);
|
|
gpio_write_pin(BOARD_ENET_RGMII_RST_GPIO, BOARD_ENET_RGMII_RST_GPIO_INDEX, BOARD_ENET_RGMII_RST_GPIO_PIN, 1);
|
|
} else if (ptr == HPM_ENET1) {
|
|
gpio_write_pin(BOARD_ENET_RMII_RST_GPIO, BOARD_ENET_RMII_RST_GPIO_INDEX, BOARD_ENET_RMII_RST_GPIO_PIN, 0);
|
|
board_delay_ms(1);
|
|
gpio_write_pin(BOARD_ENET_RMII_RST_GPIO, BOARD_ENET_RMII_RST_GPIO_INDEX, BOARD_ENET_RMII_RST_GPIO_PIN, 1);
|
|
} else {
|
|
return status_invalid_argument;
|
|
}
|
|
|
|
return status_success;
|
|
}
|
|
|
|
uint8_t board_get_enet_dma_pbl(ENET_Type *ptr)
|
|
{
|
|
(void) ptr;
|
|
return enet_pbl_32;
|
|
}
|
|
|
|
hpm_stat_t board_enable_enet_irq(ENET_Type *ptr)
|
|
{
|
|
if (ptr == HPM_ENET0) {
|
|
intc_m_enable_irq(IRQn_ENET0);
|
|
} else if (ptr == HPM_ENET1) {
|
|
intc_m_enable_irq(IRQn_ENET1);
|
|
} else {
|
|
return status_invalid_argument;
|
|
}
|
|
|
|
return status_success;
|
|
}
|
|
|
|
hpm_stat_t board_disable_enet_irq(ENET_Type *ptr)
|
|
{
|
|
if (ptr == HPM_ENET0) {
|
|
intc_m_disable_irq(IRQn_ENET0);
|
|
} else if (ptr == HPM_ENET1) {
|
|
intc_m_disable_irq(IRQn_ENET1);
|
|
} else {
|
|
return status_invalid_argument;
|
|
}
|
|
|
|
return status_success;
|
|
}
|
|
|
|
void board_init_enet_pps_pins(ENET_Type *ptr)
|
|
{
|
|
(void) ptr;
|
|
init_enet_pps_pins();
|
|
}
|
|
|
|
#if defined(ENET_MULTIPLE_PORT) && ENET_MULTIPLE_PORT
|
|
|
|
hpm_stat_t board_init_multiple_enet_pins(void)
|
|
{
|
|
board_init_enet_pins(HPM_ENET0);
|
|
board_init_enet_pins(HPM_ENET1);
|
|
|
|
return status_success;
|
|
}
|
|
|
|
hpm_stat_t board_init_multiple_enet_clock(void)
|
|
{
|
|
/* Set RGMII clock delay */
|
|
board_init_enet_rgmii_clock_delay(HPM_ENET0);
|
|
|
|
/* Set RMII reference clock */
|
|
board_init_enet_rmii_reference_clock(HPM_ENET1, BOARD_ENET_RMII_INT_REF_CLK);
|
|
printf("Enet1 Reference Clock: %s\n", BOARD_ENET_RMII_INT_REF_CLK ? "Internal Clock" : "External Clock");
|
|
|
|
return status_success;
|
|
}
|
|
|
|
hpm_stat_t board_reset_multiple_enet_phy(void)
|
|
{
|
|
board_reset_enet_phy(HPM_ENET0);
|
|
board_reset_enet_phy(HPM_ENET1);
|
|
|
|
return status_success;
|
|
}
|
|
|
|
hpm_stat_t board_init_enet_phy(ENET_Type *ptr)
|
|
{
|
|
dp83867_config_t phy_config0;
|
|
dp83848_config_t phy_config1;
|
|
|
|
if (ptr == HPM_ENET0) {
|
|
dp83867_reset(HPM_ENET0);
|
|
#if defined(__DISABLE_AUTO_NEGO) && __DISABLE_AUTO_NEGO
|
|
dp83867_set_mdi_crossover_mode(HPM_ENET0, enet_phy_mdi_crossover_manual_mdix);
|
|
#endif
|
|
dp83867_basic_mode_default_config(HPM_ENET0, &phy_config0);
|
|
if (dp83867_basic_mode_init(HPM_ENET0, &phy_config0) == true) {
|
|
return status_success;
|
|
} else {
|
|
printf("Enet0 phy init failed!\n");
|
|
return status_fail;
|
|
}
|
|
} else if (ptr == HPM_ENET1) {
|
|
dp83848_reset(HPM_ENET1);
|
|
dp83848_basic_mode_default_config(HPM_ENET1, &phy_config1);
|
|
if (dp83848_basic_mode_init(HPM_ENET1, &phy_config1) == true) {
|
|
return status_success;
|
|
} else {
|
|
printf("Enet1 phy init failed!\n");
|
|
return status_fail;
|
|
}
|
|
} else {
|
|
return status_invalid_argument;
|
|
}
|
|
}
|
|
|
|
ENET_Type *board_get_enet_base(uint8_t idx)
|
|
{
|
|
if (idx == 0) {
|
|
return HPM_ENET0;
|
|
} else {
|
|
return HPM_ENET1;
|
|
}
|
|
}
|
|
|
|
uint8_t board_get_enet_phy_itf(uint8_t idx)
|
|
{
|
|
if (idx == 0) {
|
|
return BOARD_ENET_RGMII_PHY_ITF;
|
|
} else {
|
|
return BOARD_ENET_RMII_PHY_ITF;
|
|
}
|
|
}
|
|
|
|
void board_get_enet_phy_status(uint8_t idx, void *status)
|
|
{
|
|
if (idx == 0) {
|
|
dp83867_get_phy_status(HPM_ENET0, status);
|
|
} else {
|
|
dp83848_get_phy_status(HPM_ENET1, status);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
void board_init_dao_pins(void)
|
|
{
|
|
init_dao_pins();
|
|
}
|
|
|