guoxin
/
test-example-projects
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
用于EagleEye3.0 规则集漏报和误报测试的示例项目，项目收集于github和gitee
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
3 Commits
1 Branch
0 Tags
722 MiB
 
 
 
 
 
 
Tag: Branch: Tree: 574f9c1e1d
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from '574f9c1e1d'
${ noResults }
test-example-projects/c_projects/30wklite/examples/apollo3p/Sources/cmsis/apollo3.h

24424 lines
2.3 MiB
Raw Blame History

/*
* Copyright (c) 2020, Ambiq Micro, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* Third party software included in this distribution is subject to the
* additional license terms as defined in the /docs/licenses directory.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* @file apollo3.h
* @brief CMSIS HeaderFile
* @version 1.0
* @date 16. September 2020
* @note Generated by SVDConv V3.3.27 on Wednesday, 16.09.2020 08:45:27
* from File './apollo3.svd',
* last modified on Wednesday, 16.09.2020 13:45:26
*/
/** @addtogroup Ambiq Micro
* @{
*/
/** @addtogroup apollo3
* @{
*/
#ifndef APOLLO3_H
#define APOLLO3_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup Configuration_of_CMSIS
* @{
*/
/* =========================================================================================================================== */
/* ================ Interrupt Number Definition ================ */
/* =========================================================================================================================== */
typedef enum {
/* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation
and No Match */
BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
related Fault */
UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
SysTick_IRQn = -1, /*!< -1 System Tick Timer */
/* ========================================== apollo3 Specific Interrupt Numbers =========================================== */
BROWNOUT_IRQn = 0, /*!< 0 BROWNOUT IRQ */
WDT_IRQn = 1, /*!< 1 WDT IRQ */
RTC_IRQn = 2, /*!< 2 RTC IRQ */
VCOMP_IRQn = 3, /*!< 3 VCOMP IRQ */
IOSLAVE_IRQn = 4, /*!< 4 IOSLAVE IRQ */
IOSLAVEACC_IRQn = 5, /*!< 5 IOSLAVEACC IRQ */
IOMSTR0_IRQn = 6, /*!< 6 IOMSTR0 IRQ */
IOMSTR1_IRQn = 7, /*!< 7 IOMSTR1 IRQ */
IOMSTR2_IRQn = 8, /*!< 8 IOMSTR2 IRQ */
IOMSTR3_IRQn = 9, /*!< 9 IOMSTR3 IRQ */
IOMSTR4_IRQn = 10, /*!< 10 IOMSTR4 IRQ */
IOMSTR5_IRQn = 11, /*!< 11 IOMSTR5 IRQ */
BLE_IRQn = 12, /*!< 12 BLE IRQ */
GPIO_IRQn = 13, /*!< 13 GPIO IRQ */
CTIMER_IRQn = 14, /*!< 14 CTIMER IRQ */
UART0_IRQn = 15, /*!< 15 UART0 IRQ */
UART1_IRQn = 16, /*!< 16 UART1 IRQ */
SCARD_IRQn = 17, /*!< 17 SCARD IRQ */
ADC_IRQn = 18, /*!< 18 ADC IRQ */
PDM_IRQn = 19, /*!< 19 PDM IRQ */
MSPI0_IRQn = 20, /*!< 20 MSPI0 IRQ */
STIMER_IRQn = 22, /*!< 22 STIMER IRQ */
STIMER_CMPR0_IRQn = 23, /*!< 23 STIMER_CMPR0 IRQ */
STIMER_CMPR1_IRQn = 24, /*!< 24 STIMER_CMPR1 IRQ */
STIMER_CMPR2_IRQn = 25, /*!< 25 STIMER_CMPR2 IRQ */
STIMER_CMPR3_IRQn = 26, /*!< 26 STIMER_CMPR3 IRQ */
STIMER_CMPR4_IRQn = 27, /*!< 27 STIMER_CMPR4 IRQ */
STIMER_CMPR5_IRQn = 28, /*!< 28 STIMER_CMPR5 IRQ */
STIMER_CMPR6_IRQn = 29, /*!< 29 STIMER_CMPR6 IRQ */
STIMER_CMPR7_IRQn = 30, /*!< 30 STIMER_CMPR7 IRQ */
CLKGEN_IRQn = 31 /*!< 31 CLKGEN IRQ */
} IRQn_Type;
/* =========================================================================================================================== */
/* ================ Processor and Core Peripheral Section ================ */
/* =========================================================================================================================== */
/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */
#define __CM4_REV 0x0100U /*!< CM4 Core Revision */
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __MPU_PRESENT 1 /*!< MPU present */
#define __FPU_PRESENT 1 /*!< FPU present */
/** @} */ /* End of group Configuration_of_CMSIS */
#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */
#include "system_apollo3.h" /*!< apollo3 System */
#ifndef __IM /*!< Fallback for older CMSIS versions */
#define __IM __I
#endif
#ifndef __OM /*!< Fallback for older CMSIS versions */
#define __OM __O
#endif
#ifndef __IOM /*!< Fallback for older CMSIS versions */
#define __IOM __IO
#endif
/* ======================================== Start of section using anonymous unions ======================================== */
#if defined (__CC_ARM)
#pragma push
#pragma anon_unions
#elif defined (__ICCARM__)
#pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wc11-extensions"
#pragma clang diagnostic ignored "-Wreserved-id-macro"
#pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
#pragma clang diagnostic ignored "-Wnested-anon-types"
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
/* =========================================================================================================================== */
/* ================ Device Specific Peripheral Section ================ */
/* =========================================================================================================================== */
/** @addtogroup Device_Peripheral_peripherals
* @{
*/
/* =========================================================================================================================== */
/* ================ ADC ================ */
/* =========================================================================================================================== */
/**
* @brief Analog Digital Converter Control (ADC)
*/
typedef struct { /*!< (@ 0x50010000) ADC Structure */
union {
__IOM uint32_t CFG; /*!< (@ 0x00000000) The ADC Configuration Register contains the software
control for selecting the clock frequency
used for the SAR conversions, the trigger
polarity, the trigger select, the reference
voltage select, the low power mode, the
operating mode (single scan per trigger
vs. repeating mode) and ADC enable. */
struct {
__IOM uint32_t ADCEN : 1; /*!< [0..0] This bit enables the ADC module. While the ADC is enabled,
the ADCCFG and SLOT Configuration regsiter settings must
remain stable and unchanged. All configuration register
settings, slot configuration settings and window comparison
settings should be written prior to setting the ADCEN bit
to '1'. */
__IM uint32_t : 1;
__IOM uint32_t RPTEN : 1; /*!< [2..2] This bit enables Repeating Scan Mode. */
__IOM uint32_t LPMODE : 1; /*!< [3..3] Select power mode to enter between active scans. */
__IOM uint32_t CKMODE : 1; /*!< [4..4] Clock mode register */
__IM uint32_t : 3;
__IOM uint32_t REFSEL : 2; /*!< [9..8] Select the ADC reference voltage. */
__IM uint32_t : 2;
__IOM uint32_t DFIFORDEN : 1; /*!< [12..12] Destructive FIFO Read Enable. Setting this will enable
FIFO pop upon reading the FIFOPR register. */
__IM uint32_t : 3;
__IOM uint32_t TRIGSEL : 3; /*!< [18..16] Select the ADC trigger source. */
__IOM uint32_t TRIGPOL : 1; /*!< [19..19] This bit selects the ADC trigger polarity for external
off chip triggers. */
__IM uint32_t : 4;
__IOM uint32_t CLKSEL : 2; /*!< [25..24] Select the source and frequency for the ADC clock.
All values not enumerated below are undefined. */
} CFG_b;
} ;
union {
__IOM uint32_t STAT; /*!< (@ 0x00000004) This register indicates the basic power status
for the ADC. For detailed power status,
see the power control power status register.
ADC power mode 0 indicates the ADC is in
it's full power state and is ready to process
scans. ADC Power mode 1 indicates the ADC
enabled and in a low power state. */
struct {
__IOM uint32_t PWDSTAT : 1; /*!< [0..0] Indicates the power-status of the ADC. */
} STAT_b;
} ;
union {
__IOM uint32_t SWT; /*!< (@ 0x00000008) This register enables initiating an ADC scan
through software. */
struct {
__IOM uint32_t SWT : 8; /*!< [7..0] Writing 0x37 to this register generates a software trigger. */
} SWT_b;
} ;
union {
__IOM uint32_t SL0CFG; /*!< (@ 0x0000000C) Slot 0 Configuration Register */
struct {
__IOM uint32_t SLEN0 : 1; /*!< [0..0] This bit enables slot 0 for ADC conversions. */
__IOM uint32_t WCEN0 : 1; /*!< [1..1] This bit enables the window compare function for slot
0. */
__IM uint32_t : 6;
__IOM uint32_t CHSEL0 : 4; /*!< [11..8] Select one of the 14 channel inputs for this slot. */
__IM uint32_t : 4;
__IOM uint32_t PRMODE0 : 2; /*!< [17..16] Set the Precision Mode For Slot. */
__IM uint32_t : 6;
__IOM uint32_t ADSEL0 : 3; /*!< [26..24] Select the number of measurements to average in the
accumulate divide module for this slot. */
} SL0CFG_b;
} ;
union {
__IOM uint32_t SL1CFG; /*!< (@ 0x00000010) Slot 1 Configuration Register */
struct {
__IOM uint32_t SLEN1 : 1; /*!< [0..0] This bit enables slot 1 for ADC conversions. */
__IOM uint32_t WCEN1 : 1; /*!< [1..1] This bit enables the window compare function for slot
1. */
__IM uint32_t : 6;
__IOM uint32_t CHSEL1 : 4; /*!< [11..8] Select one of the 14 channel inputs for this slot. */
__IM uint32_t : 4;
__IOM uint32_t PRMODE1 : 2; /*!< [17..16] Set the Precision Mode For Slot. */
__IM uint32_t : 6;
__IOM uint32_t ADSEL1 : 3; /*!< [26..24] Select the number of measurements to average in the
accumulate divide module for this slot. */
} SL1CFG_b;
} ;
union {
__IOM uint32_t SL2CFG; /*!< (@ 0x00000014) Slot 2 Configuration Register */
struct {
__IOM uint32_t SLEN2 : 1; /*!< [0..0] This bit enables slot 2 for ADC conversions. */
__IOM uint32_t WCEN2 : 1; /*!< [1..1] This bit enables the window compare function for slot
2. */
__IM uint32_t : 6;
__IOM uint32_t CHSEL2 : 4; /*!< [11..8] Select one of the 14 channel inputs for this slot. */
__IM uint32_t : 4;
__IOM uint32_t PRMODE2 : 2; /*!< [17..16] Set the Precision Mode For Slot. */
__IM uint32_t : 6;
__IOM uint32_t ADSEL2 : 3; /*!< [26..24] Select the number of measurements to average in the
accumulate divide module for this slot. */
} SL2CFG_b;
} ;
union {
__IOM uint32_t SL3CFG; /*!< (@ 0x00000018) Slot 3 Configuration Register */
struct {
__IOM uint32_t SLEN3 : 1; /*!< [0..0] This bit enables slot 3 for ADC conversions. */
__IOM uint32_t WCEN3 : 1; /*!< [1..1] This bit enables the window compare function for slot
3. */
__IM uint32_t : 6;
__IOM uint32_t CHSEL3 : 4; /*!< [11..8] Select one of the 14 channel inputs for this slot. */
__IM uint32_t : 4;
__IOM uint32_t PRMODE3 : 2; /*!< [17..16] Set the Precision Mode For Slot. */
__IM uint32_t : 6;
__IOM uint32_t ADSEL3 : 3; /*!< [26..24] Select the number of measurements to average in the
accumulate divide module for this slot. */
} SL3CFG_b;
} ;
union {
__IOM uint32_t SL4CFG; /*!< (@ 0x0000001C) Slot 4 Configuration Register */
struct {
__IOM uint32_t SLEN4 : 1; /*!< [0..0] This bit enables slot 4 for ADC conversions. */
__IOM uint32_t WCEN4 : 1; /*!< [1..1] This bit enables the window compare function for slot
4. */
__IM uint32_t : 6;
__IOM uint32_t CHSEL4 : 4; /*!< [11..8] Select one of the 14 channel inputs for this slot. */
__IM uint32_t : 4;
__IOM uint32_t PRMODE4 : 2; /*!< [17..16] Set the Precision Mode For Slot. */
__IM uint32_t : 6;
__IOM uint32_t ADSEL4 : 3; /*!< [26..24] Select the number of measurements to average in the
accumulate divide module for this slot. */
} SL4CFG_b;
} ;
union {
__IOM uint32_t SL5CFG; /*!< (@ 0x00000020) Slot 5 Configuration Register */
struct {
__IOM uint32_t SLEN5 : 1; /*!< [0..0] This bit enables slot 5 for ADC conversions. */
__IOM uint32_t WCEN5 : 1; /*!< [1..1] This bit enables the window compare function for slot
5. */
__IM uint32_t : 6;
__IOM uint32_t CHSEL5 : 4; /*!< [11..8] Select one of the 14 channel inputs for this slot. */
__IM uint32_t : 4;
__IOM uint32_t PRMODE5 : 2; /*!< [17..16] Set the Precision Mode For Slot. */
__IM uint32_t : 6;
__IOM uint32_t ADSEL5 : 3; /*!< [26..24] Select number of measurements to average in the accumulate
divide module for this slot. */
} SL5CFG_b;
} ;
union {
__IOM uint32_t SL6CFG; /*!< (@ 0x00000024) Slot 6 Configuration Register */
struct {
__IOM uint32_t SLEN6 : 1; /*!< [0..0] This bit enables slot 6 for ADC conversions. */
__IOM uint32_t WCEN6 : 1; /*!< [1..1] This bit enables the window compare function for slot
6. */
__IM uint32_t : 6;
__IOM uint32_t CHSEL6 : 4; /*!< [11..8] Select one of the 14 channel inputs for this slot. */
__IM uint32_t : 4;
__IOM uint32_t PRMODE6 : 2; /*!< [17..16] Set the Precision Mode For Slot. */
__IM uint32_t : 6;
__IOM uint32_t ADSEL6 : 3; /*!< [26..24] Select the number of measurements to average in the
accumulate divide module for this slot. */
} SL6CFG_b;
} ;
union {
__IOM uint32_t SL7CFG; /*!< (@ 0x00000028) Slot 7 Configuration Register */
struct {
__IOM uint32_t SLEN7 : 1; /*!< [0..0] This bit enables slot 7 for ADC conversions. */
__IOM uint32_t WCEN7 : 1; /*!< [1..1] This bit enables the window compare function for slot
7. */
__IM uint32_t : 6;
__IOM uint32_t CHSEL7 : 4; /*!< [11..8] Select one of the 14 channel inputs for this slot. */
__IM uint32_t : 4;
__IOM uint32_t PRMODE7 : 2; /*!< [17..16] Set the Precision Mode For Slot. */
__IM uint32_t : 6;
__IOM uint32_t ADSEL7 : 3; /*!< [26..24] Select the number of measurements to average in the
accumulate divide module for this slot. */
} SL7CFG_b;
} ;
union {
__IOM uint32_t WULIM; /*!< (@ 0x0000002C) Window Comparator Upper Limits Register */
struct {
__IOM uint32_t ULIM : 20; /*!< [19..0] Sets the upper limit for the window comparator. */
} WULIM_b;
} ;
union {
__IOM uint32_t WLLIM; /*!< (@ 0x00000030) Window Comparator Lower Limits Register */
struct {
__IOM uint32_t LLIM : 20; /*!< [19..0] Sets the lower limit for the window comparator. */
} WLLIM_b;
} ;
union {
__IOM uint32_t SCWLIM; /*!< (@ 0x00000034) Scale Window Comparator Limits */
struct {
__IOM uint32_t SCWLIMEN : 1; /*!< [0..0] Scale the window limits compare values per precision
mode. When set to 0x0 (default), the values in the 20-bit
limits registers will compare directly with the FIFO values
regardless of the precision mode the slot is configured
to. When set to 0x1, the compare values will be divided
by the difference in precision bits while performing the
window limit comparisons. */
} SCWLIM_b;
} ;
union {
__IOM uint32_t FIFO; /*!< (@ 0x00000038) The ADC FIFO Register contains the slot number
and fifo data for the oldest conversion
data in the FIFO. The COUNT field indicates
the total number of valid entries in the
FIFO. A write to this register will pop
one of the FIFO entries off the FIFO and
decrease the COUNT by 1 if the COUNT is
greater than zero. */
struct {
__IOM uint32_t DATA : 20; /*!< [19..0] Oldest data in the FIFO. */
__IOM uint32_t COUNT : 8; /*!< [27..20] Number of valid entries in the ADC FIFO. */
__IOM uint32_t SLOTNUM : 3; /*!< [30..28] Slot number associated with this FIFO data. */
__IOM uint32_t RSVD : 1; /*!< [31..31] RESERVED. */
} FIFO_b;
} ;
union {
__IOM uint32_t FIFOPR; /*!< (@ 0x0000003C) This is a Pop Read mirrored copy of the ADCFIFO
register with the only difference being
that reading this register will result in
a simultaneous FIFO POP which is also achieved
by writing to the ADCFIFO Register. Note:
The DFIFORDEN bit must be set in the CFG
register for the the destructive read to
be enabled. */
struct {
__IOM uint32_t DATA : 20; /*!< [19..0] Oldest data in the FIFO. */
__IOM uint32_t COUNT : 8; /*!< [27..20] Number of valid entries in the ADC FIFO. */
__IOM uint32_t SLOTNUMPR : 3; /*!< [30..28] Slot number associated with this FIFO data. */
__IOM uint32_t RSVDPR : 1; /*!< [31..31] RESERVED. */
} FIFOPR_b;
} ;
__IM uint32_t RESERVED[112];
union {
__IOM uint32_t INTEN; /*!< (@ 0x00000200) Set bits in this register to allow this module
to generate the corresponding interrupt. */
struct {
__IOM uint32_t CNVCMP : 1; /*!< [0..0] ADC conversion complete interrupt. */
__IOM uint32_t SCNCMP : 1; /*!< [1..1] ADC scan complete interrupt. */
__IOM uint32_t FIFOOVR1 : 1; /*!< [2..2] FIFO 75 percent full interrupt. */
__IOM uint32_t FIFOOVR2 : 1; /*!< [3..3] FIFO 100 percent full interrupt. */
__IOM uint32_t WCEXC : 1; /*!< [4..4] Window comparator voltage excursion interrupt. */
__IOM uint32_t WCINC : 1; /*!< [5..5] Window comparator voltage incursion interrupt. */
__IOM uint32_t DCMP : 1; /*!< [6..6] DMA Transfer Complete */
__IOM uint32_t DERR : 1; /*!< [7..7] DMA Error Condition */
} INTEN_b;
} ;
union {
__IOM uint32_t INTSTAT; /*!< (@ 0x00000204) Read bits from this register to discover the
cause of a recent interrupt. */
struct {
__IOM uint32_t CNVCMP : 1; /*!< [0..0] ADC conversion complete interrupt. */
__IOM uint32_t SCNCMP : 1; /*!< [1..1] ADC scan complete interrupt. */
__IOM uint32_t FIFOOVR1 : 1; /*!< [2..2] FIFO 75 percent full interrupt. */
__IOM uint32_t FIFOOVR2 : 1; /*!< [3..3] FIFO 100 percent full interrupt. */
__IOM uint32_t WCEXC : 1; /*!< [4..4] Window comparator voltage excursion interrupt. */
__IOM uint32_t WCINC : 1; /*!< [5..5] Window comparator voltage incursion interrupt. */
__IOM uint32_t DCMP : 1; /*!< [6..6] DMA Transfer Complete */
__IOM uint32_t DERR : 1; /*!< [7..7] DMA Error Condition */
} INTSTAT_b;
} ;
union {
__IOM uint32_t INTCLR; /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
the interrupt status associated with that
bit. */
struct {
__IOM uint32_t CNVCMP : 1; /*!< [0..0] ADC conversion complete interrupt. */
__IOM uint32_t SCNCMP : 1; /*!< [1..1] ADC scan complete interrupt. */
__IOM uint32_t FIFOOVR1 : 1; /*!< [2..2] FIFO 75 percent full interrupt. */
__IOM uint32_t FIFOOVR2 : 1; /*!< [3..3] FIFO 100 percent full interrupt. */
__IOM uint32_t WCEXC : 1; /*!< [4..4] Window comparator voltage excursion interrupt. */
__IOM uint32_t WCINC : 1; /*!< [5..5] Window comparator voltage incursion interrupt. */
__IOM uint32_t DCMP : 1; /*!< [6..6] DMA Transfer Complete */
__IOM uint32_t DERR : 1; /*!< [7..7] DMA Error Condition */
} INTCLR_b;
} ;
union {
__IOM uint32_t INTSET; /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
generate an interrupt from this module.
(Generally used for testing purposes). */
struct {
__IOM uint32_t CNVCMP : 1; /*!< [0..0] ADC conversion complete interrupt. */
__IOM uint32_t SCNCMP : 1; /*!< [1..1] ADC scan complete interrupt. */
__IOM uint32_t FIFOOVR1 : 1; /*!< [2..2] FIFO 75 percent full interrupt. */
__IOM uint32_t FIFOOVR2 : 1; /*!< [3..3] FIFO 100 percent full interrupt. */
__IOM uint32_t WCEXC : 1; /*!< [4..4] Window comparator voltage excursion interrupt. */
__IOM uint32_t WCINC : 1; /*!< [5..5] Window comparator voltage incursion interrupt. */
__IOM uint32_t DCMP : 1; /*!< [6..6] DMA Transfer Complete */
__IOM uint32_t DERR : 1; /*!< [7..7] DMA Error Condition */
} INTSET_b;
} ;
__IM uint32_t RESERVED1[12];
union {
__IOM uint32_t DMATRIGEN; /*!< (@ 0x00000240) DMA Trigger Enable Register */
struct {
__IOM uint32_t DFIFO75 : 1; /*!< [0..0] Trigger DMA upon FIFO 75 percent Full */
__IOM uint32_t DFIFOFULL : 1; /*!< [1..1] Trigger DMA upon FIFO 100 percent Full */
} DMATRIGEN_b;
} ;
union {
__IOM uint32_t DMATRIGSTAT; /*!< (@ 0x00000244) DMA Trigger Status Register */
struct {
__IOM uint32_t D75STAT : 1; /*!< [0..0] Triggered DMA from FIFO 75 percent Full */
__IOM uint32_t DFULLSTAT : 1; /*!< [1..1] Triggered DMA from FIFO 100 percent Full */
} DMATRIGSTAT_b;
} ;
__IM uint32_t RESERVED2[14];
union {
__IOM uint32_t DMACFG; /*!< (@ 0x00000280) DMA Configuration Register */
struct {
__IOM uint32_t DMAEN : 1; /*!< [0..0] DMA Enable */
__IM uint32_t : 1;
__IOM uint32_t DMADIR : 1; /*!< [2..2] Direction */
__IM uint32_t : 5;
__IOM uint32_t DMAPRI : 1; /*!< [8..8] Sets the Priority of the DMA request */
__IOM uint32_t DMADYNPRI : 1; /*!< [9..9] Enables dynamic priority based on FIFO fullness. When
FIFO is full, priority is automatically set to HIGH. Otherwise,
DMAPRI is used. */
__IM uint32_t : 6;
__IOM uint32_t DMAHONSTAT : 1; /*!< [16..16] Halt New ADC conversions until DMA Status DMAERR and
DMACPL Cleared. */
__IOM uint32_t DMAMSK : 1; /*!< [17..17] Mask the FIFOCNT and SLOTNUM when transferring FIFO
contents to memory */
__IOM uint32_t DPWROFF : 1; /*!< [18..18] Power Off the ADC System upon DMACPL. */
} DMACFG_b;
} ;
__IM uint32_t RESERVED3;
union {
__IOM uint32_t DMATOTCOUNT; /*!< (@ 0x00000288) DMA Total Transfer Count */
struct {
__IM uint32_t : 2;
__IOM uint32_t TOTCOUNT : 16; /*!< [17..2] Total Transfer Count */
} DMATOTCOUNT_b;
} ;
union {
__IOM uint32_t DMATARGADDR; /*!< (@ 0x0000028C) DMA Target Address Register */
struct {
__IOM uint32_t LTARGADDR : 19; /*!< [18..0] DMA Target Address */
__IOM uint32_t UTARGADDR : 13; /*!< [31..19] SRAM Target */
} DMATARGADDR_b;
} ;
union {
__IOM uint32_t DMASTAT; /*!< (@ 0x00000290) DMA Status Register */
struct {
__IOM uint32_t DMATIP : 1; /*!< [0..0] DMA Transfer In Progress */
__IOM uint32_t DMACPL : 1; /*!< [1..1] DMA Transfer Complete */
__IOM uint32_t DMAERR : 1; /*!< [2..2] DMA Error */
} DMASTAT_b;
} ;
} ADC_Type; /*!< Size = 660 (0x294) */
/* =========================================================================================================================== */
/* ================ APBDMA ================ */
/* =========================================================================================================================== */
/**
* @brief APB DMA Register Interfaces (APBDMA)
*/
typedef struct { /*!< (@ 0x40011000) APBDMA Structure */
union {
__IOM uint32_t BBVALUE; /*!< (@ 0x00000000) Control Register */
struct {
__IOM uint32_t DATAOUT : 8; /*!< [7..0] Data Output Values */
__IM uint32_t : 8;
__IOM uint32_t PIN : 8; /*!< [23..16] PIO values */
} BBVALUE_b;
} ;
union {
__IOM uint32_t BBSETCLEAR; /*!< (@ 0x00000004) Set/Clear Register */
struct {
__IOM uint32_t SET : 8; /*!< [7..0] Write 1 to Set PIO value (set hier priority than clear
if both bit set) */
__IM uint32_t : 8;
__IOM uint32_t CLEAR : 8; /*!< [23..16] Write 1 to Clear PIO value */
} BBSETCLEAR_b;
} ;
union {
__IOM uint32_t BBINPUT; /*!< (@ 0x00000008) PIO Input Values */
struct {
__IOM uint32_t DATAIN : 8; /*!< [7..0] PIO values */
} BBINPUT_b;
} ;
__IM uint32_t RESERVED[5];
union {
__IOM uint32_t DEBUGDATA; /*!< (@ 0x00000020) PIO Input Values */
struct {
__IOM uint32_t DEBUGDATA : 32; /*!< [31..0] Debug Data */
} DEBUGDATA_b;
} ;
__IM uint32_t RESERVED1[7];
union {
__IOM uint32_t DEBUG; /*!< (@ 0x00000040) PIO Input Values */
struct {
__IOM uint32_t DEBUGEN : 4; /*!< [3..0] Debug Enable */
} DEBUG_b;
} ;
} APBDMA_Type; /*!< Size = 68 (0x44) */
/* =========================================================================================================================== */
/* ================ BLEIF ================ */
/* =========================================================================================================================== */
/**
* @brief BLE Interface (BLEIF)
*/
typedef struct { /*!< (@ 0x5000C000) BLEIF Structure */
union {
__IOM uint32_t FIFO; /*!< (@ 0x00000000) Provides direct random access to both input and
output fifos. The state of the FIFO is not
distured by reading these locations (ie
no POP will be done). FIFO0 is accessible
from addresses 0x0 - 0x1C, and is used for
data outuput from the IOM to external devices.
These FIFO locations can be read and written
directly.FIFO locations 0x20 - 0x3C provide
read only access to the input fifo. These
FIFO locations cannot be directly written
by the MCU, and are updated only by the
internal har */
struct {
__IOM uint32_t FIFO : 32; /*!< [31..0] FIFO direct access. Only locations 0 - 3F will return
valid information. */
} FIFO_b;
} ;
__IM uint32_t RESERVED[63];
union {
__IOM uint32_t FIFOPTR; /*!< (@ 0x00000100) Provides the current valid byte count of data
within the FIFO as seen from the internal
state machines. FIFO0 is dedicated to outgoing
transactions and FIFO1 is dedicated to incoming
transactions. All counts are specified in
units of bytes. */
struct {
__IOM uint32_t FIFO0SIZ : 8; /*!< [7..0] The number of valid data bytes currently in the FIFO
0 (written by MCU, read by interface) */
__IOM uint32_t FIFO0REM : 8; /*!< [15..8] The number of remaining data bytes slots currently in
FIFO 0 (written by MCU, read by interface) */
__IOM uint32_t FIFO1SIZ : 8; /*!< [23..16] The number of valid data bytes currently in FIFO 1
(written by interface, read by MCU) */
__IOM uint32_t FIFO1REM : 8; /*!< [31..24] The number of remaining data bytes slots currently
in FIFO 1 (written by interface, read by MCU) */
} FIFOPTR_b;
} ;
union {
__IOM uint32_t FIFOTHR; /*!< (@ 0x00000104) Sets the threshold values for incoming and outgoing
transactions. The threshold values are used
to assert the interrupt if enabled, and
also used during DMA to set the transfer
size as a result of DMATHR trigger.The WTHR
is used to indicate when there are more
than WTHR bytes of open fifo locations available
in the outgoing FIFO (FIFO0). The intended
use to invoke an interrupt or DMA transfer
that will refill the FIFO with a byte count
up to this value.The RTHR is used to indicate
whe */
struct {
__IOM uint32_t FIFORTHR : 6; /*!< [5..0] FIFO read threshold in bytes. A value of 0 will disable
the read FIFO level from activating the threshold interrupt.
If this field is non-zero, it will trigger a threshold
interrupt when the read fifo contains FIFORTHR valid bytes
of data, as indicated by the FIFO1SIZ field. This is intended
to signal when a data transfer of FIFORTHR bytes can be
done from the IOM module to the host via the read fifo
to support large IOM read operations. */
__IM uint32_t : 2;
__IOM uint32_t FIFOWTHR : 6; /*!< [13..8] FIFO write threshold in bytes. A value of 0 will disable
the write FIFO level from activating the threshold interrupt.
If this field is non-zero, it will trigger a threshold
interrupt when the write fifo contains FIFOWTHR free bytes,
as indicated by the FIFO0REM field. This is intended to
signal when a transfer of FIFOWTHR bytes can be done from
the host to the IOM write fifo to support large IOM write
operations. */
} FIFOTHR_b;
} ;
union {
__IOM uint32_t FIFOPOP; /*!< (@ 0x00000108) Will advance the internal read pointer of the
incoming FIFO (FIFO1) when read, if POPWR
is not active. If POPWR is active, a write
to this register is needed to advance the
internal FIFO pointer. */
struct {
__IOM uint32_t FIFODOUT : 32; /*!< [31..0] This register will return the read data indicated by
the current read pointer on reads. If the POPWR control
bit in the FIFOCTRL register is reset (0), the fifo read
pointer will be advanced by one word as a result of the
read.If the POPWR bit is set (1), the fifo read pointer
will only be advanced after a write operation to this register.
The write data is ignored for this register.If less than
a even word multiple is available, and the command is completed,
the module will return the word containing */
} FIFOPOP_b;
} ;
union {
__IOM uint32_t FIFOPUSH; /*!< (@ 0x0000010C) Will write new data into the outgoing FIFO and
advance the internal write pointer. */
struct {
__IOM uint32_t FIFODIN : 32; /*!< [31..0] This register is used to write the FIFORAM in FIFO mode
and will cause a push event to occur to the next open slot
within the FIFORAM. Writing to this register will cause
the write point to increment by 1 word(4 bytes). */
} FIFOPUSH_b;
} ;
union {
__IOM uint32_t FIFOCTRL; /*!< (@ 0x00000110) Provides controls for the operation of the internal
FIFOs. Contains fields used to control the
operation of the POP register, and also
controls to reset the internal pointers
of the FIFOs. */
struct {
__IOM uint32_t POPWR : 1; /*!< [0..0] Selects the mode in which 'pop' events are done for the
fifo read operations. A value of '1' will prevent a pop
event on a read operation, and will require a write to
the FIFOPOP register to create a pop event.A value of '0'
in this register will allow a pop event to occur on the
read of the FIFOPOP register, and may cause inadvertant
fifo pops when used in a debugging mode. */
__IOM uint32_t FIFORSTN : 1; /*!< [1..1] Active low manual reset of the fifo. Write to 0 to reset
fifo, and then write to 1 to remove the reset. */
} FIFOCTRL_b;
} ;
union {
__IOM uint32_t FIFOLOC; /*!< (@ 0x00000114) Provides a read only value of the current read
and write pointers. This register is read
only and can be used alogn with the FIFO
direct access method to determine the next
data to be used for input and output functions. */
struct {
__IOM uint32_t FIFOWPTR : 4; /*!< [3..0] Current FIFO write pointer. Value is the index into the
outgoing FIFO (FIFO0), which is used during write operations
to external devices. */
__IM uint32_t : 4;
__IOM uint32_t FIFORPTR : 4; /*!< [11..8] Current FIFO read pointer. Used to index into the incoming
FIFO (FIFO1), which is used to store read data returned
from external devices during a read operation. */
} FIFOLOC_b;
} ;
__IM uint32_t RESERVED1[58];
union {
__IOM uint32_t CLKCFG; /*!< (@ 0x00000200) Provides clock related controls used internal
to the BLEIF module, and enablement of 32KHz
clock to the BLE Core module. The internal
clock sourced is selected via the FSEL and
can be further divided by 3 using the DIV3
control.This register is also used to enable
the clock, which must be done prior to performing
any IO transactions. */
struct {
__IOM uint32_t IOCLKEN : 1; /*!< [0..0] Enable for the interface clock. Must be enabled prior
to executing any IO operations. */
__IM uint32_t : 7;
__IOM uint32_t FSEL : 3; /*!< [10..8] Select the input clock frequency. */
__IOM uint32_t CLK32KEN : 1; /*!< [11..11] Enable for the 32Khz clock to the BLE module */
__IOM uint32_t DIV3 : 1; /*!< [12..12] Enable of the divide by 3 of the source IOCLK. */
} CLKCFG_b;
} ;
__IM uint32_t RESERVED2[2];
union {
__IOM uint32_t CMD; /*!< (@ 0x0000020C) Writes to this register will start an IO transaction,
as well as set various parameters for the
command itself. Reads will return the command
value written to the CMD register.To read
the number of bytes that have yet to be
transferred, refer to the CTSIZE field within
the CMDSTAT register. */
struct {
__IOM uint32_t CMD : 5; /*!< [4..0] Command for submodule. */
__IOM uint32_t OFFSETCNT : 2; /*!< [6..5] Number of offset bytes to use for the command - 0, 1,
2, 3 are valid selections. The second (byte 1) and third
byte (byte 2) are read from the OFFSETHI register, and
the low order byte is pulled from this register in the
OFFSETLO field.Offset bytes are transmitted highest byte
first. EG if offsetcnt == 3, OFFSETHI[15:8] will be transmitted
first, then OFFSETHI[7:0] then OFFSETLO.If offsetcnt ==
2, OFFSETHI[7:0] will be transmitted, then OFFSETLO.If
offsetcnt == 1, only OFFSETLO will be transmitted. */
__IOM uint32_t CONT : 1; /*!< [7..7] Contine to hold the bus after the current transaction
if set to a 1 with a new command issued. */
__IOM uint32_t TSIZE : 12; /*!< [19..8] Defines the transaction size in bytes. The offset transfer
is not included in this size. */
__IOM uint32_t CMDSEL : 2; /*!< [21..20] Command Specific selection information */
__IM uint32_t : 2;
__IOM uint32_t OFFSETLO : 8; /*!< [31..24] This register holds the low order byte of offset to
be used in the transaction. The number of offset bytes
to use is set with bits 1:0 of the command. Offset bytes
are transferred starting from the highest byte first. */
} CMD_b;
} ;
union {
__IOM uint32_t CMDRPT; /*!< (@ 0x00000210) Will repeat the next command for CMDRPT number
of times. If CMDRPT is set to 1, the next
command will be done 2 times in series.
A repeat count of up to 31 is possible.
Each command will be done as a seperate
command, but the data willbe treated as
packed, and aligned to byte boundaries.
This differs when executing seperate commands
without the CMDRPT set, as the data for
each transaction is word aligned and any
unused byte locations will be filled with
0 for read operations, ordisca */
struct {
__IOM uint32_t CMDRPT : 5; /*!< [4..0] Count of number of times to repeat the next command. */
} CMDRPT_b;
} ;
union {
__IOM uint32_t OFFSETHI; /*!< (@ 0x00000214) Provides the high order bytes of 2 or 3 byte
offset transactions of the current command.
Usage of these bytes is dependant on the
offsetcnt field in the CMD register. If
the offsetcnt == 3, the data located at
OFFSETHI[15:0] will first be transmitted,followed
by OFFSETHI[7:0], followed by OFFSETLO (in
the CMD register) prior to sending or receiving
any transaction data (if programed via TSIZE
field in the CMD register).The offset bytes
are always transmitted MSB first for all
modules. */
struct {
__IOM uint32_t OFFSETHI : 16; /*!< [15..0] Holds the high order bytes of the 2 or 3 byte offset
phase of a transaction. */
} OFFSETHI_b;
} ;
union {
__IOM uint32_t CMDSTAT; /*!< (@ 0x00000218) Provides staus on the execution of the command
currently in progress. The fields in this
register will reflect the real time status
of the internal state machines and data
transfers within the IOM.These are read
only fields and writes to the registers
are ignored. */
struct {
__IOM uint32_t CCMD : 5; /*!< [4..0] current command that is being executed */
__IOM uint32_t CMDSTAT : 3; /*!< [7..5] The current status of the command execution. */
__IOM uint32_t CTSIZE : 12; /*!< [19..8] The current number of bytes still to be transferred
with this command. This field will count down to zero. */
} CMDSTAT_b;
} ;
__IM uint32_t RESERVED3;
union {
__IOM uint32_t INTEN; /*!< (@ 0x00000220) Set bits in this register to allow this module
to generate the corresponding interrupt. */
struct {
__IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when the current
operation has completed. For repeated commands, this will
only be asserted when the final repeated command is completed. */
__IOM uint32_t THR : 1; /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted
when the number of free bytes in the write FIFO equals
or exceeds the WTHR field.For read operations, asserted
when the number of valid bytes in the read FIFO equals
of exceeds the value set in the RTHR field. */
__IOM uint32_t FUNDFL : 1; /*!< [2..2] Read FIFO Underflow interrupt. Asserted when a pop operation
is done to a empty read FIFO. */
__IOM uint32_t FOVFL : 1; /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software
tries to write to a full fifo. The current operation does
not stop. */
__IOM uint32_t B2MST : 1; /*!< [4..4] B2M State change interrupt. Asserted on any change in
the B2M_STATE signal from the BLE Core. */
__IOM uint32_t IACC : 1; /*!< [5..5] illegal FIFO access interrupt. Asserted when there is
a overflow or underflow event */
__IOM uint32_t ICMD : 1; /*!< [6..6] illegal command interrupt. Asserted when a command is
written when an active command is in progress. */
__IOM uint32_t BLECIRQ : 1; /*!< [7..7] BLE Core IRQ signal. Asserted when the BLE_IRQ signal
from the BLE Core is asserted, indicating the availability
of read data from the BLE Core. */
__IOM uint32_t BLECSSTAT : 1; /*!< [8..8] BLE Core SPI Status interrupt. Asserted when the SPI_STATUS
signal from the BLE Core is asserted, indicating that SPI
writes can be done to the BLE Core.Transfers to the BLE
Core should only be done when this signal is high. */
__IOM uint32_t DCMP : 1; /*!< [9..9] DMA Complete. Processing of the DMA operation has completed
and the DMA submodule is returned into the idle state */
__IOM uint32_t DERR : 1; /*!< [10..10] DMA Error encountered during the processing of the
DMA command. The DMA error could occur when the memory
access specified in the DMA operation is not available
or incorrectly specified. */
__IOM uint32_t CQPAUSED : 1; /*!< [11..11] Command queue is paused due to an active event enabled
in the PAUSEEN register. The interrupt is posted when the
event is enabled within the PAUSEEN register, the mask
is active in the CQIRQMASK field and the event occurs. */
__IOM uint32_t CQUPD : 1; /*!< [12..12] Command queue write operation executed a register write
with the register address bit 0 set to 1. The low address
bits in the CQ address fields are unused and bit 0 can
be used to trigger an interrupt to indicate when this register
write is performed by the CQ operation. */
__IOM uint32_t CQERR : 1; /*!< [13..13] Command queue error during processing. When an error
occurs, the system will stop processing and halt operations
to allow software to take recovery actions */
__IOM uint32_t B2MSLEEP : 1; /*!< [14..14] The B2M_STATE from the BLE Core transitioned into the
sleep state */
__IOM uint32_t B2MACTIVE : 1; /*!< [15..15] Revision A: The B2M_STATE from the BLE Core transitioned
into the active state Revision B: Falling BLE Core IRQ
signal. Asserted when the BLE_IRQ signal from the BLE Core
is de-asserted (1 -> 0) */
__IOM uint32_t B2MSHUTDN : 1; /*!< [16..16] Revision A: The B2M_STATE from the BLE Core transitioned
into shutdown state Revision B: Falling BLE Core Status
signal. Asserted when the BLE_STATUS signal from the BLE
Core is de-asserted (1 -> 0) */
} INTEN_b;
} ;
union {
__IOM uint32_t INTSTAT; /*!< (@ 0x00000224) Read bits from this register to discover the
cause of a recent interrupt. */
struct {
__IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when the current
operation has completed. For repeated commands, this will
only be asserted when the final repeated command is completed. */
__IOM uint32_t THR : 1; /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted
when the number of free bytes in the write FIFO equals
or exceeds the WTHR field.For read operations, asserted
when the number of valid bytes in the read FIFO equals
of exceeds the value set in the RTHR field. */
__IOM uint32_t FUNDFL : 1; /*!< [2..2] Read FIFO Underflow interrupt. Asserted when a pop operation
is done to a empty read FIFO. */
__IOM uint32_t FOVFL : 1; /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software
tries to write to a full fifo. The current operation does
not stop. */
__IOM uint32_t B2MST : 1; /*!< [4..4] B2M State change interrupt. Asserted on any change in
the B2M_STATE signal from the BLE Core. */
__IOM uint32_t IACC : 1; /*!< [5..5] illegal FIFO access interrupt. Asserted when there is
a overflow or underflow event */
__IOM uint32_t ICMD : 1; /*!< [6..6] illegal command interrupt. Asserted when a command is
written when an active command is in progress. */
__IOM uint32_t BLECIRQ : 1; /*!< [7..7] BLE Core IRQ signal. Asserted when the BLE_IRQ signal
from the BLE Core is asserted, indicating the availability
of read data from the BLE Core. */
__IOM uint32_t BLECSSTAT : 1; /*!< [8..8] BLE Core SPI Status interrupt. Asserted when the SPI_STATUS
signal from the BLE Core is asserted, indicating that SPI
writes can be done to the BLE Core.Transfers to the BLE
Core should only be done when this signal is high. */
__IOM uint32_t DCMP : 1; /*!< [9..9] DMA Complete. Processing of the DMA operation has completed
and the DMA submodule is returned into the idle state */
__IOM uint32_t DERR : 1; /*!< [10..10] DMA Error encountered during the processing of the
DMA command. The DMA error could occur when the memory
access specified in the DMA operation is not available
or incorrectly specified. */
__IOM uint32_t CQPAUSED : 1; /*!< [11..11] Command queue is paused due to an active event enabled
in the PAUSEEN register. The interrupt is posted when the
event is enabled within the PAUSEEN register, the mask
is active in the CQIRQMASK field and the event occurs. */
__IOM uint32_t CQUPD : 1; /*!< [12..12] Command queue write operation executed a register write
with the register address bit 0 set to 1. The low address
bits in the CQ address fields are unused and bit 0 can
be used to trigger an interrupt to indicate when this register
write is performed by the CQ operation. */
__IOM uint32_t CQERR : 1; /*!< [13..13] Command queue error during processing. When an error
occurs, the system will stop processing and halt operations
to allow software to take recovery actions */
__IOM uint32_t B2MSLEEP : 1; /*!< [14..14] The B2M_STATE from the BLE Core transitioned into the
sleep state */
__IOM uint32_t B2MACTIVE : 1; /*!< [15..15] Revision A: The B2M_STATE from the BLE Core transitioned
into the active state Revision B: Falling BLE Core IRQ
signal. Asserted when the BLE_IRQ signal from the BLE Core
is de-asserted (1 -> 0) */
__IOM uint32_t B2MSHUTDN : 1; /*!< [16..16] Revision A: The B2M_STATE from the BLE Core transitioned
into shutdown state Revision B: Falling BLE Core Status
signal. Asserted when the BLE_STATUS signal from the BLE
Core is de-asserted (1 -> 0) */
} INTSTAT_b;
} ;
union {
__IOM uint32_t INTCLR; /*!< (@ 0x00000228) Write a 1 to a bit in this register to clear
the interrupt status associated with that
bit. */
struct {
__IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when the current
operation has completed. For repeated commands, this will
only be asserted when the final repeated command is completed. */
__IOM uint32_t THR : 1; /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted
when the number of free bytes in the write FIFO equals
or exceeds the WTHR field.For read operations, asserted
when the number of valid bytes in the read FIFO equals
of exceeds the value set in the RTHR field. */
__IOM uint32_t FUNDFL : 1; /*!< [2..2] Read FIFO Underflow interrupt. Asserted when a pop operation
is done to a empty read FIFO. */
__IOM uint32_t FOVFL : 1; /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software
tries to write to a full fifo. The current operation does
not stop. */
__IOM uint32_t B2MST : 1; /*!< [4..4] B2M State change interrupt. Asserted on any change in
the B2M_STATE signal from the BLE Core. */
__IOM uint32_t IACC : 1; /*!< [5..5] illegal FIFO access interrupt. Asserted when there is
a overflow or underflow event */
__IOM uint32_t ICMD : 1; /*!< [6..6] illegal command interrupt. Asserted when a command is
written when an active command is in progress. */
__IOM uint32_t BLECIRQ : 1; /*!< [7..7] BLE Core IRQ signal. Asserted when the BLE_IRQ signal
from the BLE Core is asserted, indicating the availability
of read data from the BLE Core. */
__IOM uint32_t BLECSSTAT : 1; /*!< [8..8] BLE Core SPI Status interrupt. Asserted when the SPI_STATUS
signal from the BLE Core is asserted, indicating that SPI
writes can be done to the BLE Core.Transfers to the BLE
Core should only be done when this signal is high. */
__IOM uint32_t DCMP : 1; /*!< [9..9] DMA Complete. Processing of the DMA operation has completed
and the DMA submodule is returned into the idle state */
__IOM uint32_t DERR : 1; /*!< [10..10] DMA Error encountered during the processing of the
DMA command. The DMA error could occur when the memory
access specified in the DMA operation is not available
or incorrectly specified. */
__IOM uint32_t CQPAUSED : 1; /*!< [11..11] Command queue is paused due to an active event enabled
in the PAUSEEN register. The interrupt is posted when the
event is enabled within the PAUSEEN register, the mask
is active in the CQIRQMASK field and the event occurs. */
__IOM uint32_t CQUPD : 1; /*!< [12..12] Command queue write operation executed a register write
with the register address bit 0 set to 1. The low address
bits in the CQ address fields are unused and bit 0 can
be used to trigger an interrupt to indicate when this register
write is performed by the CQ operation. */
__IOM uint32_t CQERR : 1; /*!< [13..13] Command queue error during processing. When an error
occurs, the system will stop processing and halt operations
to allow software to take recovery actions */
__IOM uint32_t B2MSLEEP : 1; /*!< [14..14] The B2M_STATE from the BLE Core transitioned into the
sleep state */
__IOM uint32_t B2MACTIVE : 1; /*!< [15..15] Revision A: The B2M_STATE from the BLE Core transitioned
into the active state Revision B: Falling BLE Core IRQ
signal. Asserted when the BLE_IRQ signal from the BLE Core
is de-asserted (1 -> 0) */
__IOM uint32_t B2MSHUTDN : 1; /*!< [16..16] Revision A: The B2M_STATE from the BLE Core transitioned
into shutdown state Revision B: Falling BLE Core Status
signal. Asserted when the BLE_STATUS signal from the BLE
Core is de-asserted (1 -> 0) */
} INTCLR_b;
} ;
union {
__IOM uint32_t INTSET; /*!< (@ 0x0000022C) Write a 1 to a bit in this register to instantly
generate an interrupt from this module.
(Generally used for testing purposes). */
struct {
__IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when the current
operation has completed. For repeated commands, this will
only be asserted when the final repeated command is completed. */
__IOM uint32_t THR : 1; /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted
when the number of free bytes in the write FIFO equals
or exceeds the WTHR field.For read operations, asserted
when the number of valid bytes in the read FIFO equals
of exceeds the value set in the RTHR field. */
__IOM uint32_t FUNDFL : 1; /*!< [2..2] Read FIFO Underflow interrupt. Asserted when a pop operation
is done to a empty read FIFO. */
__IOM uint32_t FOVFL : 1; /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software
tries to write to a full fifo. The current operation does
not stop. */
__IOM uint32_t B2MST : 1; /*!< [4..4] B2M State change interrupt. Asserted on any change in
the B2M_STATE signal from the BLE Core. */
__IOM uint32_t IACC : 1; /*!< [5..5] illegal FIFO access interrupt. Asserted when there is
a overflow or underflow event */
__IOM uint32_t ICMD : 1; /*!< [6..6] illegal command interrupt. Asserted when a command is
written when an active command is in progress. */
__IOM uint32_t BLECIRQ : 1; /*!< [7..7] BLE Core IRQ signal. Asserted when the BLE_IRQ signal
from the BLE Core is asserted, indicating the availability
of read data from the BLE Core. */
__IOM uint32_t BLECSSTAT : 1; /*!< [8..8] BLE Core SPI Status interrupt. Asserted when the SPI_STATUS
signal from the BLE Core is asserted, indicating that SPI
writes can be done to the BLE Core.Transfers to the BLE
Core should only be done when this signal is high. */
__IOM uint32_t DCMP : 1; /*!< [9..9] DMA Complete. Processing of the DMA operation has completed
and the DMA submodule is returned into the idle state */
__IOM uint32_t DERR : 1; /*!< [10..10] DMA Error encountered during the processing of the
DMA command. The DMA error could occur when the memory
access specified in the DMA operation is not available
or incorrectly specified. */
__IOM uint32_t CQPAUSED : 1; /*!< [11..11] Command queue is paused due to an active event enabled
in the PAUSEEN register. The interrupt is posted when the
event is enabled within the PAUSEEN register, the mask
is active in the CQIRQMASK field and the event occurs. */
__IOM uint32_t CQUPD : 1; /*!< [12..12] Command queue write operation executed a register write
with the register address bit 0 set to 1. The low address
bits in the CQ address fields are unused and bit 0 can
be used to trigger an interrupt to indicate when this register
write is performed by the CQ operation. */
__IOM uint32_t CQERR : 1; /*!< [13..13] Command queue error during processing. When an error
occurs, the system will stop processing and halt operations
to allow software to take recovery actions */
__IOM uint32_t B2MSLEEP : 1; /*!< [14..14] The B2M_STATE from the BLE Core transitioned into the
sleep state */
__IOM uint32_t B2MACTIVE : 1; /*!< [15..15] Revision A: The B2M_STATE from the BLE Core transitioned
into the active state Revision B: Falling BLE Core IRQ
signal. Asserted when the BLE_IRQ signal from the BLE Core
is de-asserted (1 -> 0) */
__IOM uint32_t B2MSHUTDN : 1; /*!< [16..16] Revision A: The B2M_STATE from the BLE Core transitioned
into shutdown state Revision B: Falling BLE Core Status
signal. Asserted when the BLE_STATUS signal from the BLE
Core is de-asserted (1 -> 0) */
} INTSET_b;
} ;
union {
__IOM uint32_t DMATRIGEN; /*!< (@ 0x00000230) Provides control on which event will trigger
the DMA transfer after the DMA operation
is setup and enabled. The trigger event
will cause a number of bytes (depending
on trigger event) to betransferred via the
DMA operation, and can be used to adjust
the latency of data to/from the IOM module
to/from the dma target. DMA transfers are
broken into smaller transfers internally
of up to16 bytes each, and multiple trigger
events can be used to complete the entire
programmed DMA transfer. */
struct {
__IOM uint32_t DCMDCMPEN : 1; /*!< [0..0] Trigger DMA upon command complete. Enables the trigger
of the DMA when a command is completed. When this event
is triggered, the number of words transferred will be the
lesser of the remaining TOTCOUNT bytes, or the number of
bytes in the FIFO when the command completed. If this is
disabled, and the number of bytes in the FIFO is equal
or greater than the TOTCOUNT bytes, a transfer of TOTCOUNT
bytes will be done to ensure read data is stored when the
DMA is completed. */
__IOM uint32_t DTHREN : 1; /*!< [1..1] Trigger DMA upon THR level reached. For M2P DMA operations
(IOM writes), the trigger will assert when the write FIFO
has (WTHR/4) number of words free in the write FIFO, and
will transfer (WTHR/4) number of wordsor, if the number
of words left to transfer is less than the WTHR value,
will transfer the remaining byte count.For P2M DMA operations,
the trigger will assert when the read FIFO has (RTHR/4)
words available in the read FIFO, and will transfer (RTHR/4)
words to SRAM. This trigger will NOT asser */
} DMATRIGEN_b;
} ;
union {
__IOM uint32_t DMATRIGSTAT; /*!< (@ 0x00000234) Provides the status of trigger events that have
occurred for the transaction. Some of the
bits are read only and some can be reset
via a write of 0. */
struct {
__IOM uint32_t DCMDCMP : 1; /*!< [0..0] Triggered DMA from Command complete event. Bit is read
only and can be cleared by disabling the DCMDCMP trigger
enable or by disabling DMA. */
__IOM uint32_t DTHR : 1; /*!< [1..1] Triggered DMA from THR event. Bit is read only and can
be cleared by disabling the DTHR trigger enable or by disabling
DMA. */
__IOM uint32_t DTOTCMP : 1; /*!< [2..2] DMA triggered when DCMDCMP = 0, and the amount of data
in the FIFO was enough to complete the DMA operation (greater
than or equal to current TOTCOUNT) when the command completed.
This trigger is default active when the DCMDCMP trigger
isdisabled and there is enough data in the FIFO to complete
the DMA operation. */
} DMATRIGSTAT_b;
} ;
union {
__IOM uint32_t DMACFG; /*!< (@ 0x00000238) Configuration control of the DMA process, including
the direction of DMA, and enablement of
DMA */
struct {
__IOM uint32_t DMAEN : 1; /*!< [0..0] DMA Enable. Setting this bit to EN will start the DMA
operation. This should be the last DMA related register
set prior to issuing the command */
__IOM uint32_t DMADIR : 1; /*!< [1..1] Direction */
__IM uint32_t : 6;
__IOM uint32_t DMAPRI : 1; /*!< [8..8] Sets the Priority of the DMA request */
__IOM uint32_t DPWROFF : 1; /*!< [9..9] Power off module after DMA is complete. If this bit is
active, the module will request to power off the supply
it is attached to. If there are other units still requiring
power from the same domain, power down will not be performed. */
} DMACFG_b;
} ;
union {
__IOM uint32_t DMATOTCOUNT; /*!< (@ 0x0000023C) Contains the number of bytes to be transferred
for this DMA transaction. This register
is decremented as the data is transferred,
and will be 0 at the completion of the DMA
operation. */
struct {
__IOM uint32_t TOTCOUNT : 12; /*!< [11..0] Triggered DMA from Command complete event occured. Bit
is read only and can be cleared by disabling the DTHR trigger
enable or by disabling DMA. */
} DMATOTCOUNT_b;
} ;
union {
__IOM uint32_t DMATARGADDR; /*!< (@ 0x00000240) The source or destination address internal the
SRAM for the DMA data. For write operations,
this can only be SRAM data (ADDR bit 28
= 1); For read operations, this can ve either
SRAM or FLASH (ADDR bit 28 = 0) */
struct {
__IOM uint32_t TARGADDR : 20; /*!< [19..0] Bits [19:0] of the target byte address for source of
DMA (either read or write). The address can be any byte
alignment, and does not have to be word aligned. In cases
of non-word aligned addresses, the DMA logic will take
care for ensuring only the target bytes are read/written. */
__IM uint32_t : 8;
__IOM uint32_t TARGADDR28 : 1; /*!< [28..28] Bit 28 of the target byte address for source of DMA
(either read or write). In cases of non-word aligned addresses,
the DMA logic will take care for ensuring only the target
bytes are read/written.Setting to '1' will select the SRAM.
Setting to '0' will select the flash */
} DMATARGADDR_b;
} ;
union {
__IOM uint32_t DMASTAT; /*!< (@ 0x00000244) Status of the DMA operation currently in progress. */
struct {
__IOM uint32_t DMATIP : 1; /*!< [0..0] DMA Transfer In Progress indicator. 1 will indicate that
a DMA transfer is active. The DMA transfer may be waiting
on data, transferring data, or waiting for priority.All
of these will be indicated with a 1. A 0 will indicate
that the DMA is fully complete and no further transactions
will be done. This bit is read only. */
__IOM uint32_t DMACPL : 1; /*!< [1..1] DMA Transfer Complete. This signals the end of the DMA
operation. This bit can be cleared by writing to 0. */
__IOM uint32_t DMAERR : 1; /*!< [2..2] DMA Error. This active high bit signals that an error
was encountered during the DMA operation. */
} DMASTAT_b;
} ;
union {
__IOM uint32_t CQCFG; /*!< (@ 0x00000248) Controls parameters and options for execution
of the command queue operation. To enable
command queue, create this in memory, set
the address, and enable it with a write
to CQEN */
struct {
__IOM uint32_t CQEN : 1; /*!< [0..0] Command queue enable. When set, will enable the processing
of the command queue and fetches of address/data pairs
will proceed from the word address within the CQADDR register.
Can be disabledusing a CQ executed write to this bit as
well. */
__IOM uint32_t CQPRI : 1; /*!< [1..1] Sets the Priority of the command queue dma request. */
} CQCFG_b;
} ;
union {
__IOM uint32_t CQADDR; /*!< (@ 0x0000024C) The SRAM address which will be fetched next execution
of the CQ operation. This register is updated
as the CQ operation progresses, and is the
live version of the register. The register
can also bewritten by the Command Queue
operation itself, allowing the relocation
of successive CQ fetches. In this case,
the new CQ address will be used for the
next CQ address/data fetch */
struct {
__IM uint32_t : 2;
__IOM uint32_t CQADDR : 18; /*!< [19..2] Bits 19:2 of target byte address for source of CQ (read
only). The buffer must be aligned on a word boundary */
__IM uint32_t : 8;
__IOM uint32_t CQADDR28 : 1; /*!< [28..28] Bit 28 of target byte address for source of CQ (read
only). Used to denote Flash (0) or SRAM (1) access */
} CQADDR_b;
} ;
union {
__IOM uint32_t CQSTAT; /*!< (@ 0x00000250) Provides the status of the command queue operation.
If the command queue is disabled, these
bits will be cleared. The bits are read
only */
struct {
__IOM uint32_t CQTIP : 1; /*!< [0..0] Command queue Transfer In Progress indicator. 1 will
indicate that a CQ transfer is active and this will remain
active even when paused waiting for external event. */
__IOM uint32_t CQPAUSED : 1; /*!< [1..1] Command queue operation is currently paused. */
__IOM uint32_t CQERR : 1; /*!< [2..2] Command queue processing Error. This active high bit
signals that an error was encountered during the CQ operation. */
} CQSTAT_b;
} ;
union {
__IOM uint32_t CQFLAGS; /*!< (@ 0x00000254) Provides the current status of the SWFLAGS (bits
7:0) and the hardware generated flags (15:8).
A '1' will pause the CQ operation if it
the same bit is enabled in the CQPAUSEEN
register */
struct {
__IOM uint32_t CQFLAGS : 16; /*!< [15..0] Current flag status (read-only). Bits [7:0] are software
controllable and bits [15:8] are hardware status. */
__IOM uint32_t CQIRQMASK : 16; /*!< [31..16] Provides for a per-bit mask of the flags used to invoke
an interrupt. A '1' in the bit position will enable the
pause event to trigger the interrupt, if the CQWT_int interrupt
is enabled.Bits definitions are the same as CQPAUSE */
} CQFLAGS_b;
} ;
union {
__IOM uint32_t CQSETCLEAR; /*!< (@ 0x00000258) Set/Clear the command queue software pause flags
on a per-bit basis. Contains 3 fields, allowing
for setting, clearing or toggling the value
in the software flags. Priority when the
same bitis enabled in each field is toggle,
then set, then clear. */
struct {
__IOM uint32_t CQFSET : 8; /*!< [7..0] Set CQFlag status bits. Will set to 1 the value of any
SWFLAG with a '1' in the corresponding bit position of
this field */
__IOM uint32_t CQFTGL : 8; /*!< [15..8] Toggle the indicated bit. Will toggle the value of any
SWFLAG with a '1' in the corresponding bit position of
this field */
__IOM uint32_t CQFCLR : 8; /*!< [23..16] Clear CQFlag status bits. Will clear to 0 any SWFLAG
with a '1' in the corresponding bit position of this field */
} CQSETCLEAR_b;
} ;
union {
__IOM uint32_t CQPAUSEEN; /*!< (@ 0x0000025C) Enables a flag to pause an active command queue
operation. If a bit is '1' and the corresponding
bit in the CQFLAG register is '1', CQ processing
will halt until either value is changed
to '0'. */
struct {
__IOM uint32_t CQPEN : 16; /*!< [15..0] Enables the specified event to pause command processing
when active */
} CQPAUSEEN_b;
} ;
union {
__IOM uint32_t CQCURIDX; /*!< (@ 0x00000260) Current index value, targeted to be written by
register write operations within the command
queue. This is compared to the CQENDIDX
and will stop the CQ operation if bit 15
of the CQPAUSEEN is '1' andthis current
index equals the CQENDIDX register value.
This will only pause when the values are
equal. */
struct {
__IOM uint32_t CQCURIDX : 8; /*!< [7..0] Holds 8 bits of data that will be compared with the CQENDIX
register field. If the values match, the IDXEQ pause event
will be activated, which will cause the pausing of command
quue operation if the IDXEQ bit is enabled in CQPAUSEEN. */
} CQCURIDX_b;
} ;
union {
__IOM uint32_t CQENDIDX; /*!< (@ 0x00000264) End index value, targeted to be written by software
to indicate the last valid register pair
contained within the command queue. rgister
write operations within the command queue.This
is compared to the CQCURIDX and will stop
the CQ operation if bit 15 of the CQPAUSEEN
is '1' andthis current index equals the
CQCURIDX register value. This will only
pause when the values are equal. */
struct {
__IOM uint32_t CQENDIDX : 8; /*!< [7..0] Holds 8 bits of data that will be compared with the CQCURIX
register field. If the values match, the IDXEQ pause event
will be activated, which will cause the pausing of command
quue operation if the IDXEQ bit is enabled in CQPAUSEEN. */
} CQENDIDX_b;
} ;
union {
__IOM uint32_t STATUS; /*!< (@ 0x00000268) General status of the IOM module command execution. */
struct {
__IOM uint32_t ERR : 1; /*!< [0..0] Bit has been deprecated. Please refer to the other error
indicators. This will always return 0. */
__IOM uint32_t CMDACT : 1; /*!< [1..1] Indicates if the active I/O Command is currently processing
a transaction, or command is complete, but the FIFO pointers
are still syncronizing internally. This bit will go high
atthe start of the transaction, and will go low when the
command is complete, and the data and pointers within the
FIFO have been syncronized. */
__IOM uint32_t IDLEST : 1; /*!< [2..2] indicates if the active I/O state machine is IDLE. Note
- The state machine could be in idle state due to holdoffs
from data availability, or as the command gets propagated
into the logic from the registers. */
} STATUS_b;
} ;
__IM uint32_t RESERVED4[37];
union {
__IOM uint32_t MSPICFG; /*!< (@ 0x00000300) Controls the configuration of the SPI master
module, including POL/PHA, LSB, flow control,
and delays for MISO and MOSI */
struct {
__IOM uint32_t SPOL : 1; /*!< [0..0] This bit selects SPI polarity. */
__IOM uint32_t SPHA : 1; /*!< [1..1] Selects the SPI phase; When 1, will shift the sampling
edge by 1/2 clock. */
__IOM uint32_t FULLDUP : 1; /*!< [2..2] Full Duplex mode. Capture read data during writes operations */
__IM uint32_t : 13;
__IOM uint32_t WTFC : 1; /*!< [16..16] Enables flow control of new write transactions based
on the SPI_STATUS signal from the BLE Core. */
__IOM uint32_t RDFC : 1; /*!< [17..17] Enables flow control of new read transactions based
on the SPI_STATUS signal from the BLE Core. */
__IM uint32_t : 3;
__IOM uint32_t WTFCPOL : 1; /*!< [21..21] Selects the write flow control signal polarity. The
transfers are halted when the selected flow control signal
is OPPOSITE polarity of this bit. (For example: WTFCPOL
= 0 will allow a SPI_STATUS=1 to pause transfers). */
__IOM uint32_t RDFCPOL : 1; /*!< [22..22] Selects the read flow control signal polarity. When
set, the clock will be held low until the flow control
is de-asserted. */
__IOM uint32_t SPILSB : 1; /*!< [23..23] Selects data transfer as MSB first (0) or LSB first
(1) for the data portion of the SPI transaction. The offset
bytes are always transmitted MSB first. */
__IOM uint32_t DINDLY : 3; /*!< [26..24] Delay tap to use for the input signal (MISO). This
gives more hold time on the input data. */
__IOM uint32_t DOUTDLY : 3; /*!< [29..27] Delay tap to use for the output signal (MOSI). This
give more hold time on the output data. */
__IOM uint32_t MSPIRST : 1; /*!< [30..30] Bit is deprecated. setting it will have no effect. */
} MSPICFG_b;
} ;
union {
__IOM uint32_t BLECFG; /*!< (@ 0x00000304) Provides control of isolation and IO signals
between the interface module and the BLE
Core. */
struct {
__IOM uint32_t PWRSMEN : 1; /*!< [0..0] Enable the power state machine for automatic sequencing
and control of power states of the BLE Core module. */
__IOM uint32_t BLERSTN : 1; /*!< [1..1] Reset line to the BLE Core. This will reset the BLE core
when asserted ('0') and must be written to '1' prior to
performing any BTLE related operations to the core. */
__IOM uint32_t WAKEUPCTL : 2; /*!< [3..2] WAKE signal override. Controls the source of the WAKE
signal to the BLE Core. */
__IOM uint32_t DCDCFLGCTL : 2; /*!< [5..4] DCDCFLG signal override. The value of this field will
be sent to the BLE Core when the PWRSM is off. Otherwise,
the value is supplied from internal logic. */
__IOM uint32_t BLEHREQCTL : 2; /*!< [7..6] BLEH power on request override. The value of this field
will be sent to the BLE Core when the PWRSM is off. Otherwise,
the value is supplied from internal logic. */
__IOM uint32_t WT4ACTOFF : 1; /*!< [8..8] Debug control of BLEIF power state machine. Allows transition
into the active state in the BLEIF state without waiting
for dcdc req from BLE Core. */
__IOM uint32_t MCUFRCSLP : 1; /*!< [9..9] Force power state machine to go to the sleep state. Intended
for debug only. Has no effect on the actual BLE Core state,
only the state of the BLEIF interface state machine. */
__IOM uint32_t FRCCLK : 1; /*!< [10..10] Force the clock in the BLEIF to be always running */
__IOM uint32_t STAYASLEEP : 1; /*!< [11..11] Set to prevent the BLE power control module from waking
up the BLE Core after going into power down. To be used
for graceful shutdown, set by software prior to powering
off and will allow assertion of reset from sleep state. */
__IOM uint32_t PWRISOCTL : 2; /*!< [13..12] Configuration of BLEH isolation control for power related
signals. */
__IOM uint32_t SPIISOCTL : 2; /*!< [15..14] Configuration of BLEH isolation controls for SPI related
signals. */
} BLECFG_b;
} ;
union {
__IOM uint32_t PWRCMD; /*!< (@ 0x00000308) Sends power related commands to the power state
machine in the BLE IF module. */
struct {
__IOM uint32_t WAKEREQ : 1; /*!< [0..0] Wake request from the MCU. When asserted (1), the BLE
Interface logic will assert the wakeup request signal to
the BLE Core. Only recognized when in the sleep state */
__IOM uint32_t RESTART : 1; /*!< [1..1] Restart the BLE Core after going into the shutdown state.
Only valid when in the shutdown state. */
} PWRCMD_b;
} ;
union {
__IOM uint32_t BSTATUS; /*!< (@ 0x0000030C) Status of the BLE Core interface signals */
struct {
__IOM uint32_t B2MSTATE : 3; /*!< [2..0] State of the BLE Core logic. */
__IOM uint32_t SPISTATUS : 1; /*!< [3..3] Value of the SPISTATUS signal from the BLE Core. The
signal is asserted when the BLE Core is able to accept
write data via the SPI interface. Data should be transmitted
to theBLE core only when this signal is 1. The hardware
will automatically wait for this signal prior to performing
a write operation if flow control is active. */
__IOM uint32_t DCDCREQ : 1; /*!< [4..4] Value of the DCDCREQ signal from the BLE Core. The DCDCREQ
signal is sent from the core to the BLEIF module when the
BLE core requires BLEH power to be active. When activated,
this isindicated by DCDCFLAG going to 1. */
__IOM uint32_t DCDCFLAG : 1; /*!< [5..5] Value of the DCDCFLAG signal to the BLE Core. The DCDCFLAG
is a signal to the BLE Core indicating that the BLEH ppower
is active. */
__IOM uint32_t WAKEUP : 1; /*!< [6..6] Value of the WAKEUP signal to the BLE Core . The WAKEUP
signals is sent from the BLEIF to the BLECORE to request
the BLE Core transition from sleep state to active state. */
__IOM uint32_t BLEIRQ : 1; /*!< [7..7] Status of the BLEIRQ signal from the BLE Core. A value
of 1 idicates that read data is available in the core and
a read operation needs to be performed. */
__IOM uint32_t PWRST : 3; /*!< [10..8] Current status of the power state machine */
__IOM uint32_t BLEHACK : 1; /*!< [11..11] Value of the BLEHACK signal from the power control
unit. If the signal is '1', the BLEH power is active and
ready for use. */
__IOM uint32_t BLEHREQ : 1; /*!< [12..12] Value of the BLEHREQ signal to the power control unit.
The BLEHREQ signal is sent from the BLEIF module to the
power control module to request the BLEH power up. When
the BLEHACK signal is asserted,BLEH power is stable and
ready for use. */
} BSTATUS_b;
} ;
__IM uint32_t RESERVED5[64];
union {
__IOM uint32_t BLEDBG; /*!< (@ 0x00000410) Debug control */
struct {
__IOM uint32_t DBGEN : 1; /*!< [0..0] Debug Enable. Setting this bit will enable the update
of data within this register, otherwise it is clock gated
for power savings */
__IOM uint32_t IOCLKON : 1; /*!< [1..1] IOCLK debug clock control. Enable IO_CLK to be active
when this bit is '1'. Otherwise, the clock is controlled
with gating from the logic as needed. */
__IOM uint32_t APBCLKON : 1; /*!< [2..2] APBCLK debug clock control. Enable APB_CLK to be active
when this bit is '1'. Otherwise, the clock is controlled
with gating from the logic as needed. */
__IOM uint32_t DBGDATA : 29; /*!< [31..3] Debug data */
} BLEDBG_b;
} ;
} BLEIF_Type; /*!< Size = 1044 (0x414) */
/* =========================================================================================================================== */
/* ================ CACHECTRL ================ */
/* =========================================================================================================================== */
/**
* @brief Flash Cache Controller (CACHECTRL)
*/
typedef struct { /*!< (@ 0x40018000) CACHECTRL Structure */
union {
__IOM uint32_t CACHECFG; /*!< (@ 0x00000000) Flash Cache Control Register */
struct {
__IOM uint32_t ENABLE : 1; /*!< [0..0] Enables the flash cache controller and enables power
to the cache SRAMs. The ICACHE_ENABLE and DCACHE_ENABLE
should be set to enable caching for each type of access. */
__IOM uint32_t LRU : 1; /*!< [1..1] Sets the cache repleacment policy. 0=LRR (least recently
replaced), 1=LRU (least recently used). LRR minimizes writes
to the TAG SRAM. */
__IOM uint32_t ENABLE_NC0 : 1; /*!< [2..2] Enable Non-cacheable region 0. See NCR0 registers to
define the region. */
__IOM uint32_t ENABLE_NC1 : 1; /*!< [3..3] Enable Non-cacheable region 1. See NCR1 registers to
define the region. */
__IOM uint32_t CONFIG : 4; /*!< [7..4] Sets the cache configuration */
__IOM uint32_t ICACHE_ENABLE : 1; /*!< [8..8] Enable Flash Instruction Caching */
__IOM uint32_t DCACHE_ENABLE : 1; /*!< [9..9] Enable Flash Data Caching. */
__IOM uint32_t CACHE_CLKGATE : 1; /*!< [10..10] Enable clock gating of cache TAG RAM. Software should
enable this bit for optimal power efficiency. */
__IOM uint32_t CACHE_LS : 1; /*!< [11..11] Enable LS (light sleep) of cache RAMs. Software should
DISABLE this bit since cache activity is too high to benefit
from LS usage. */
__IM uint32_t : 8;
__IOM uint32_t DATA_CLKGATE : 1; /*!< [20..20] Enable aggressive clock gating of entire data array.
This bit should be set to 1 for optimal power efficiency. */
__IM uint32_t : 3;
__IOM uint32_t ENABLE_MONITOR : 1; /*!< [24..24] Enable Cache Monitoring Stats. Cache monitoring consumes
additional power and should only be enabled when profiling
code and counters will increment when this bit is set.
Counter values will be retained when this is set to 0,
allowing software to enable/disable counting for multiple
code segments. */
} CACHECFG_b;
} ;
union {
__IOM uint32_t FLASHCFG; /*!< (@ 0x00000004) Flash Control Register */
struct {
__IOM uint32_t RD_WAIT : 4; /*!< [3..0] Sets read waitstates for normal (fast) operation. A value
of 1 is recommended. */
__IOM uint32_t SEDELAY : 3; /*!< [6..4] Sets SE delay (flash address setup). A value of 5 is
recommended. */
__IM uint32_t : 1;
__IOM uint32_t LPM_RD_WAIT : 4; /*!< [11..8] Sets flash waitstates when in LPM Mode 2 (RD_WAIT in
LPM mode 2 only) */
__IOM uint32_t LPMMODE : 2; /*!< [13..12] Controls flash low power modes (control of LPM pin). */
} FLASHCFG_b;
} ;
union {
__IOM uint32_t CTRL; /*!< (@ 0x00000008) Cache Control */
struct {
__IOM uint32_t INVALIDATE : 1; /*!< [0..0] Writing a 1 to this bitfield invalidates the flash cache
contents. */
__IOM uint32_t RESET_STAT : 1; /*!< [1..1] Reset Cache Statistics. When written to a 1, the cache
monitor counters will be cleared. The monitor counters
can be reset only when the CACHECFG.ENABLE_MONITOR bit
is set. */
__IOM uint32_t CACHE_READY : 1; /*!< [2..2] Cache Ready Status (enabled and not processing an invalidate
operation) */
__IM uint32_t : 1;
__IOM uint32_t FLASH0_SLM_STATUS : 1; /*!< [4..4] Flash Sleep Mode Status. 1 indicates that flash0 is in
sleep mode, 0 indicates flash0 is in normal mode. */
__IOM uint32_t FLASH0_SLM_DISABLE : 1; /*!< [5..5] Disable Flash Sleep Mode. Write 1 to wake flash0 from
sleep mode (reading the array will also automatically wake
it). */
__IOM uint32_t FLASH0_SLM_ENABLE : 1; /*!< [6..6] Enable Flash Sleep Mode. Write to 1 to put flash 0 into
sleep mode. NOTE: there is a 5us latency after waking flash
until the first access will be returned. */
__IM uint32_t : 1;
__IOM uint32_t FLASH1_SLM_STATUS : 1; /*!< [8..8] Flash Sleep Mode Status. 1 indicates that flash1 is in
sleep mode, 0 indicates flash1 is in normal mode. */
__IOM uint32_t FLASH1_SLM_DISABLE : 1; /*!< [9..9] Disable Flash Sleep Mode. Write 1 to wake flash1 from
sleep mode (reading the array will also automatically wake
it). */
__IOM uint32_t FLASH1_SLM_ENABLE : 1; /*!< [10..10] Enable Flash Sleep Mode. Write to 1 to put flash 1
into sleep mode. NOTE: there is a 5us latency after waking
flash until the first access will be returned. */
} CTRL_b;
} ;
__IM uint32_t RESERVED;
union {
__IOM uint32_t NCR0START; /*!< (@ 0x00000010) Flash Cache Noncachable Region 0 Start */
struct {
__IM uint32_t : 4;
__IOM uint32_t ADDR : 23; /*!< [26..4] Start address for non-cacheable region 0 */
} NCR0START_b;
} ;
union {
__IOM uint32_t NCR0END; /*!< (@ 0x00000014) Flash Cache Noncachable Region 0 End */
struct {
__IM uint32_t : 4;
__IOM uint32_t ADDR : 23; /*!< [26..4] End address for non-cacheable region 0 */
} NCR0END_b;
} ;
union {
__IOM uint32_t NCR1START; /*!< (@ 0x00000018) Flash Cache Noncachable Region 1 Start */
struct {
__IM uint32_t : 4;
__IOM uint32_t ADDR : 23; /*!< [26..4] Start address for non-cacheable region 1 */
} NCR1START_b;
} ;
union {
__IOM uint32_t NCR1END; /*!< (@ 0x0000001C) Flash Cache Noncachable Region 1 End */
struct {
__IM uint32_t : 4;
__IOM uint32_t ADDR : 23; /*!< [26..4] End address for non-cacheable region 1 */
} NCR1END_b;
} ;
__IM uint32_t RESERVED1[8];
union {
__IOM uint32_t DMON0; /*!< (@ 0x00000040) Data Cache Total Accesses */
struct {
__IOM uint32_t DACCESS_COUNT : 32; /*!< [31..0] Total accesses to data cache. All performance metrics
should be relative to the number of accesses performed. */
} DMON0_b;
} ;
union {
__IOM uint32_t DMON1; /*!< (@ 0x00000044) Data Cache Tag Lookups */
struct {
__IOM uint32_t DLOOKUP_COUNT : 32; /*!< [31..0] Total tag lookups from data cache. */
} DMON1_b;
} ;
union {
__IOM uint32_t DMON2; /*!< (@ 0x00000048) Data Cache Hits */
struct {
__IOM uint32_t DHIT_COUNT : 32; /*!< [31..0] Cache hits from lookup operations. */
} DMON2_b;
} ;
union {
__IOM uint32_t DMON3; /*!< (@ 0x0000004C) Data Cache Line Hits */
struct {
__IOM uint32_t DLINE_COUNT : 32; /*!< [31..0] Cache hits from line cache */
} DMON3_b;
} ;
union {
__IOM uint32_t IMON0; /*!< (@ 0x00000050) Instruction Cache Total Accesses */
struct {
__IOM uint32_t IACCESS_COUNT : 32; /*!< [31..0] Total accesses to Instruction cache */
} IMON0_b;
} ;
union {
__IOM uint32_t IMON1; /*!< (@ 0x00000054) Instruction Cache Tag Lookups */
struct {
__IOM uint32_t ILOOKUP_COUNT : 32; /*!< [31..0] Total tag lookups from Instruction cache */
} IMON1_b;
} ;
union {
__IOM uint32_t IMON2; /*!< (@ 0x00000058) Instruction Cache Hits */
struct {
__IOM uint32_t IHIT_COUNT : 32; /*!< [31..0] Cache hits from lookup operations */
} IMON2_b;
} ;
union {
__IOM uint32_t IMON3; /*!< (@ 0x0000005C) Instruction Cache Line Hits */
struct {
__IOM uint32_t ILINE_COUNT : 32; /*!< [31..0] Cache hits from line cache */
} IMON3_b;
} ;
} CACHECTRL_Type; /*!< Size = 96 (0x60) */
/* =========================================================================================================================== */
/* ================ CLKGEN ================ */
/* =========================================================================================================================== */
/**
* @brief Clock Generator (CLKGEN)
*/
typedef struct { /*!< (@ 0x40004000) CLKGEN Structure */
union {
__IOM uint32_t CALXT; /*!< (@ 0x00000000) This is the XT Oscillator Calibration value.
This value allows any derived XT clocks
to be calibrated. This means that the original
32KHz version of XT will not be changed,
but a 16KHz version (divided down version)
can be modified. This register value will
add or subtract the number of cycles programmed
in this register across a 32 seconds interval.
For example, if a value of 100 is programmed
in this register, then 100 additional clock
cycles will be added into a 16KHz clock
period acr */
struct {
__IOM uint32_t CALXT : 11; /*!< [10..0] XT Oscillator calibration value. This register will
enable the hardware to increase or decrease the number
of cycles in a 16KHz clock derived from the original 32KHz
version. The most significant bit is the sign. A '1' is
a reduction, and a '0' is an addition. This calibration
value will add or reduce the number of cycles programmed
here across a 32 second interval. The maximum value that
is effective is from -1024 to 1023. */
} CALXT_b;
} ;
union {
__IOM uint32_t CALRC; /*!< (@ 0x00000004) This is the LFRC Calibration value. Similar to
the XT calibration, it allows the derived
LFRC clock to be calibrated. The original
1024Hz clock source will not change, but
a 512Hz version (divided down version) can
be modified. This register will add or subtract
the number of cycles programmed in this
register across a 1024 seconds interval.
For example, if a value of 200 is programmed
in this register, then 200 additional clocks
will be added into the 512Hz derived clock
across a 1024 s */
struct {
__IOM uint32_t CALRC : 18; /*!< [17..0] LFRC Oscillator calibration value. This register will
enable the hardware to increase or decrease the number
of cycles in a 512 Hz clock derived from the original 1024
version. The most significant bit is the sign. A '1' is
a reduction, and a '0' is an addition. This calibration
value will add or reduce the number of cycles programmed
here across a 32 second interval. The range is from -131072
(decimal) to 131071 (decimal). This register is normally
used in conjuction with ACALCTR register. The CAL */
} CALRC_b;
} ;
union {
__IOM uint32_t ACALCTR; /*!< (@ 0x00000008) This register can be used for 2 purposes. The
first is to calibrate the LFRC clock using
the XT clock source. The second is to measure
an internal clock signal relative to the
external clock. In that case, the ACALCTR
will show the multiple of the external clock
with respect to the internal clock signal.
E.g. Fref = Fmeas x ACALCTR. Note that this
register should not be confused with the
HFRC Adjustment register, which is separately
defined in CLKGEN_HFADJ register. */
struct {
__IOM uint32_t ACALCTR : 24; /*!< [23..0] Autocalibration Counter result. Bits 17 down to 0 of
this is feed directly to the CALRC register if ACAL register
in OCTRL register is set to 1024SEC or 512SEC. */
} ACALCTR_b;
} ;
union {
__IOM uint32_t OCTRL; /*!< (@ 0x0000000C) This register includes controls for autocalibration
in addition to the RTC oscillator controls. */
struct {
__IOM uint32_t STOPXT : 1; /*!< [0..0] Stop the XT Oscillator to the RTC */
__IOM uint32_t STOPRC : 1; /*!< [1..1] Stop the LFRC Oscillator to the RTC */
__IM uint32_t : 4;
__IOM uint32_t FOS : 1; /*!< [6..6] Oscillator switch on failure function. If this is set,
then LFRC clock source will switch from XT to RC. */
__IOM uint32_t OSEL : 1; /*!< [7..7] Selects the RTC oscillator (1 => LFRC, 0 => XT) */
__IOM uint32_t ACAL : 3; /*!< [10..8] Autocalibration control. This selects the source to
be used in the autocalibration flow. This flow can also
be used to measure an internal clock against an external
clock source, with the external clock normally used as
the reference. */
} OCTRL_b;
} ;
union {
__IOM uint32_t CLKOUT; /*!< (@ 0x00000010) This register enables the CLKOUT to the GPIOs,
and selects the clock source to that. */
struct {
__IOM uint32_t CKSEL : 6; /*!< [5..0] CLKOUT signal select */
__IM uint32_t : 1;
__IOM uint32_t CKEN : 1; /*!< [7..7] Enable the CLKOUT signal */
} CLKOUT_b;
} ;
union {
__IOM uint32_t CLKKEY; /*!< (@ 0x00000014) This controls the write access to the CCTRL register.
This prevents customers from accidentally
setting the HFRC clocks to be half of what
they are set to. */
struct {
__IOM uint32_t CLKKEY : 32; /*!< [31..0] Key register value. */
} CLKKEY_b;
} ;
union {
__IOM uint32_t CCTRL; /*!< (@ 0x00000018) This register controls the main divider for HFRC
clock. If this is set, all internal HFRC
clock sources are divided by 2. */
struct {
__IOM uint32_t CORESEL : 1; /*!< [0..0] Core Clock divisor */
} CCTRL_b;
} ;
union {
__IOM uint32_t STATUS; /*!< (@ 0x0000001C) This register provides status to the XT oscillator
and the source of the RTC. */
struct {
__IOM uint32_t OMODE : 1; /*!< [0..0] Current RTC oscillator (1 => LFRC, 0 => XT). After an
RTC oscillator change, it may take up to 2 seconds for
this field to reflect the new oscillator. */
__IOM uint32_t OSCF : 1; /*!< [1..1] XT Oscillator is enabled but not oscillating */
} STATUS_b;
} ;
union {
__IOM uint32_t HFADJ; /*!< (@ 0x00000020) This register controls the HFRC adjustment. The
HFRC clock can change with temperature and
process corners, and this register controls
the HFRC adjustment logic which reduces
the fluctuations to the clock. */
struct {
__IOM uint32_t HFADJEN : 1; /*!< [0..0] HFRC adjustment control */
__IOM uint32_t HFADJCK : 3; /*!< [3..1] Repeat period for HFRC adjustment */
__IM uint32_t : 4;
__IOM uint32_t HFXTADJ : 12; /*!< [19..8] Target HFRC adjustment value. */
__IOM uint32_t HFWARMUP : 1; /*!< [20..20] XT warmup period for HFRC adjustment */
__IOM uint32_t HFADJGAIN : 3; /*!< [23..21] Gain control for HFRC adjustment */
} HFADJ_b;
} ;
__IM uint32_t RESERVED;
union {
__IOM uint32_t CLOCKENSTAT; /*!< (@ 0x00000028) This register provides the enable status to all
the peripheral clocks. */
struct {
__IOM uint32_t CLOCKENSTAT : 32; /*!< [31..0] Clock enable status */
} CLOCKENSTAT_b;
} ;
union {
__IOM uint32_t CLOCKEN2STAT; /*!< (@ 0x0000002C) This is a continuation of the clock enable status. */
struct {
__IOM uint32_t CLOCKEN2STAT : 32; /*!< [31..0] Clock enable status 2 */
} CLOCKEN2STAT_b;
} ;
union {
__IOM uint32_t CLOCKEN3STAT; /*!< (@ 0x00000030) This is a continuation of the clock enable status. */
struct {
__IOM uint32_t CLOCKEN3STAT : 32; /*!< [31..0] Clock enable status 3 */
} CLOCKEN3STAT_b;
} ;
union {
__IOM uint32_t FREQCTRL; /*!< (@ 0x00000034) This register provides the burst control and
burst status. */
struct {
__IOM uint32_t BURSTREQ : 1; /*!< [0..0] Frequency Burst Enable Request */
__IOM uint32_t BURSTACK : 1; /*!< [1..1] Frequency Burst Request Acknowledge. Frequency burst
requested is always acknowledged whether burst is granted
or not depending on feature enable. */
__IOM uint32_t BURSTSTATUS : 1; /*!< [2..2] This represents frequency burst status. */
} FREQCTRL_b;
} ;
__IM uint32_t RESERVED1;
union {
__IOM uint32_t BLEBUCKTONADJ; /*!< (@ 0x0000003C) This is the register control for BLE ton adjustment
logic. */
struct {
__IOM uint32_t TONLOWTHRESHOLD : 10; /*!< [9..0] TON ADJUST LOW THRESHOLD. Suggested values are #A(94KHz)
#15(47KHz) #53(12Khz) #14D(3Khz) */
__IOM uint32_t TONHIGHTHRESHOLD : 10; /*!< [19..10] TON ADJUST HIGH THRESHOLD. Suggested values are #15(94KHz)
#2A(47Khz) #A6(12Khz) #29A(3Khz) */
__IOM uint32_t TONADJUSTPERIOD : 2; /*!< [21..20] TON ADJUST PERIOD */
__IOM uint32_t TONADJUSTEN : 1; /*!< [22..22] TON ADJUST ENABLE */
__IOM uint32_t ZEROLENDETECTTRIM : 4; /*!< [26..23] BLEBUCK ZERO LENGTH DETECT TRIM */
__IOM uint32_t ZEROLENDETECTEN : 1; /*!< [27..27] BLEBUCK ZERO LENGTH DETECT ENABLE */
} BLEBUCKTONADJ_b;
} ;
__IM uint32_t RESERVED2[48];
union {
__IOM uint32_t INTRPTEN; /*!< (@ 0x00000100) Set bits in this register to allow this module
to generate the corresponding interrupt. */
struct {
__IOM uint32_t ACF : 1; /*!< [0..0] Autocalibration Fail interrupt */
__IOM uint32_t ACC : 1; /*!< [1..1] Autocalibration Complete interrupt */
__IOM uint32_t OF : 1; /*!< [2..2] XT Oscillator Fail interrupt */
} INTRPTEN_b;
} ;
union {
__IOM uint32_t INTRPTSTAT; /*!< (@ 0x00000104) Read bits from this register to discover the
cause of a recent interrupt. */
struct {
__IOM uint32_t ACF : 1; /*!< [0..0] Autocalibration Fail interrupt */
__IOM uint32_t ACC : 1; /*!< [1..1] Autocalibration Complete interrupt */
__IOM uint32_t OF : 1; /*!< [2..2] XT Oscillator Fail interrupt */
} INTRPTSTAT_b;
} ;
union {
__IOM uint32_t INTRPTCLR; /*!< (@ 0x00000108) Write a 1 to a bit in this register to clear
the interrupt status associated with that
bit. */
struct {
__IOM uint32_t ACF : 1; /*!< [0..0] Autocalibration Fail interrupt */
__IOM uint32_t ACC : 1; /*!< [1..1] Autocalibration Complete interrupt */
__IOM uint32_t OF : 1; /*!< [2..2] XT Oscillator Fail interrupt */
} INTRPTCLR_b;
} ;
union {
__IOM uint32_t INTRPTSET; /*!< (@ 0x0000010C) Write a 1 to a bit in this register to instantly
generate an interrupt from this module.
(Generally used for testing purposes). */
struct {
__IOM uint32_t ACF : 1; /*!< [0..0] Autocalibration Fail interrupt */
__IOM uint32_t ACC : 1; /*!< [1..1] Autocalibration Complete interrupt */
__IOM uint32_t OF : 1; /*!< [2..2] XT Oscillator Fail interrupt */
} INTRPTSET_b;
} ;
} CLKGEN_Type; /*!< Size = 272 (0x110) */
/* =========================================================================================================================== */
/* ================ CTIMER ================ */
/* =========================================================================================================================== */
/**
* @brief Counter/Timer (CTIMER)
*/
typedef struct { /*!< (@ 0x40008000) CTIMER Structure */
union {
__IOM uint32_t TMR0; /*!< (@ 0x00000000) This register holds the running time or event
count for ctimer 0. This is either for each
16 bit half or for the whole 32 bit count
when the pair is linked. If the pair is
not linked, they can be running on seperate
clocks and are completely independent. */
struct {
__IOM uint32_t CTTMRA0 : 16; /*!< [15..0] Counter/Timer A0. */
__IOM uint32_t CTTMRB0 : 16; /*!< [31..16] Counter/Timer B0. */
} TMR0_b;
} ;
union {
__IOM uint32_t CMPRA0; /*!< (@ 0x00000004) This contains the Compare limits for timer 0
A half. */
struct {
__IOM uint32_t CMPR0A0 : 16; /*!< [15..0] Counter/Timer A0 Compare Register 0. Holds the lower
limit for timer half A. */
__IOM uint32_t CMPR1A0 : 16; /*!< [31..16] Counter/Timer A0 Compare Register 1. Holds the upper
limit for timer half A. */
} CMPRA0_b;
} ;
union {
__IOM uint32_t CMPRB0; /*!< (@ 0x00000008) This contains the Compare limits for timer 0
B half. */
struct {
__IOM uint32_t CMPR0B0 : 16; /*!< [15..0] Counter/Timer B0 Compare Register 0. Holds the lower
limit for timer half B. */
__IOM uint32_t CMPR1B0 : 16; /*!< [31..16] Counter/Timer B0 Compare Register 1. Holds the upper
limit for timer half B. */
} CMPRB0_b;
} ;
union {
__IOM uint32_t CTRL0; /*!< (@ 0x0000000C) This includes the Control bit fields for both
halves of timer 0. */
struct {
__IOM uint32_t TMRA0EN : 1; /*!< [0..0] Counter/Timer A0 Enable bit. */
__IOM uint32_t TMRA0CLK : 5; /*!< [5..1] Counter/Timer A0 Clock Select. */
__IOM uint32_t TMRA0FN : 3; /*!< [8..6] Counter/Timer A0 Function Select. */
__IOM uint32_t TMRA0IE0 : 1; /*!< [9..9] Counter/Timer A0 Interrupt Enable bit based on COMPR0. */
__IOM uint32_t TMRA0IE1 : 1; /*!< [10..10] Counter/Timer A0 Interrupt Enable bit based on COMPR1. */
__IOM uint32_t TMRA0CLR : 1; /*!< [11..11] Counter/Timer A0 Clear bit. */
__IOM uint32_t TMRA0POL : 1; /*!< [12..12] Counter/Timer A0 output polarity. */
__IM uint32_t : 3;
__IOM uint32_t TMRB0EN : 1; /*!< [16..16] Counter/Timer B0 Enable bit. */
__IOM uint32_t TMRB0CLK : 5; /*!< [21..17] Counter/Timer B0 Clock Select. */
__IOM uint32_t TMRB0FN : 3; /*!< [24..22] Counter/Timer B0 Function Select. */
__IOM uint32_t TMRB0IE0 : 1; /*!< [25..25] Counter/Timer B0 Interrupt Enable bit for COMPR0. */
__IOM uint32_t TMRB0IE1 : 1; /*!< [26..26] Counter/Timer B0 Interrupt Enable bit for COMPR1. */
__IOM uint32_t TMRB0CLR : 1; /*!< [27..27] Counter/Timer B0 Clear bit. */
__IOM uint32_t TMRB0POL : 1; /*!< [28..28] Counter/Timer B0 output polarity. */
__IM uint32_t : 2;
__IOM uint32_t CTLINK0 : 1; /*!< [31..31] Counter/Timer A0/B0 Link bit. */
} CTRL0_b;
} ;
__IM uint32_t RESERVED;
union {
__IOM uint32_t CMPRAUXA0; /*!< (@ 0x00000014) Enhanced compare limits for timer half A. This
is valid if timer 0 is set to function 4
and function 5. */
struct {
__IOM uint32_t CMPR2A0 : 16; /*!< [15..0] Counter/Timer A0 Compare Register 2. Holds the lower
limit for timer half A. */
__IOM uint32_t CMPR3A0 : 16; /*!< [31..16] Counter/Timer A0 Compare Register 3. Holds the upper
limit for timer half A. */
} CMPRAUXA0_b;
} ;
union {
__IOM uint32_t CMPRAUXB0; /*!< (@ 0x00000018) Enhanced compare limits for timer half B. This
is valid if timer 0 is set to function 4
and function 5. */
struct {
__IOM uint32_t CMPR2B0 : 16; /*!< [15..0] Counter/Timer B0 Compare Register 2. Holds the lower
limit for timer half B. */
__IOM uint32_t CMPR3B0 : 16; /*!< [31..16] Counter/Timer B0 Compare Register 3. Holds the upper
limit for timer half B. */
} CMPRAUXB0_b;
} ;
union {
__IOM uint32_t AUX0; /*!< (@ 0x0000001C) Control bit fields for both halves of timer 0. */
struct {
__IOM uint32_t TMRA0LMT : 7; /*!< [6..0] Counter/Timer A0 Pattern Limit Count. */
__IOM uint32_t TMRA0TRIG : 4; /*!< [10..7] Counter/Timer A0 Trigger Select. */
__IOM uint32_t TMRA0NOSYNC : 1; /*!< [11..11] Source clock synchronization control. */
__IOM uint32_t TMRA0TINV : 1; /*!< [12..12] Counter/Timer A0 Invert on trigger. */
__IOM uint32_t TMRA0POL23 : 1; /*!< [13..13] Counter/Timer A0 Upper output polarity */
__IOM uint32_t TMRA0EN23 : 1; /*!< [14..14] Counter/Timer A0 Upper compare enable. */
__IM uint32_t : 1;
__IOM uint32_t TMRB0LMT : 6; /*!< [21..16] Counter/Timer B0 Pattern Limit Count. */
__IM uint32_t : 1;
__IOM uint32_t TMRB0TRIG : 4; /*!< [26..23] Counter/Timer B0 Trigger Select. */
__IOM uint32_t TMRB0NOSYNC : 1; /*!< [27..27] Source clock synchronization control. */
__IOM uint32_t TMRB0TINV : 1; /*!< [28..28] Counter/Timer B0 Invert on trigger. */
__IOM uint32_t TMRB0POL23 : 1; /*!< [29..29] Upper output polarity */
__IOM uint32_t TMRB0EN23 : 1; /*!< [30..30] Counter/Timer B0 Upper compare enable. */
} AUX0_b;
} ;
union {
__IOM uint32_t TMR1; /*!< (@ 0x00000020) This register holds the running time or event
count for ctimer 1. This is either for each
16 bit half or for the whole 32 bit count
when the pair is linked. If the pair is
not linked, they can be running on seperate
clocks and are completely independent. */
struct {
__IOM uint32_t CTTMRA1 : 16; /*!< [15..0] Counter/Timer A1. */
__IOM uint32_t CTTMRB1 : 16; /*!< [31..16] Counter/Timer B1. */
} TMR1_b;
} ;
union {
__IOM uint32_t CMPRA1; /*!< (@ 0x00000024) This contains the Compare limits for timer 1
A half. */
struct {
__IOM uint32_t CMPR0A1 : 16; /*!< [15..0] Counter/Timer A1 Compare Register 0. */
__IOM uint32_t CMPR1A1 : 16; /*!< [31..16] Counter/Timer A1 Compare Register 1. */
} CMPRA1_b;
} ;
union {
__IOM uint32_t CMPRB1; /*!< (@ 0x00000028) This contains the Compare limits for timer 1
B half. */
struct {
__IOM uint32_t CMPR0B1 : 16; /*!< [15..0] Counter/Timer B1 Compare Register 0. */
__IOM uint32_t CMPR1B1 : 16; /*!< [31..16] Counter/Timer B1 Compare Register 1. */
} CMPRB1_b;
} ;
union {
__IOM uint32_t CTRL1; /*!< (@ 0x0000002C) This includes the Control bit fields for both
halves of timer 1. */
struct {
__IOM uint32_t TMRA1EN : 1; /*!< [0..0] Counter/Timer A1 Enable bit. */
__IOM uint32_t TMRA1CLK : 5; /*!< [5..1] Counter/Timer A1 Clock Select. */
__IOM uint32_t TMRA1FN : 3; /*!< [8..6] Counter/Timer A1 Function Select. */
__IOM uint32_t TMRA1IE0 : 1; /*!< [9..9] Counter/Timer A1 Interrupt Enable bit based on COMPR0. */
__IOM uint32_t TMRA1IE1 : 1; /*!< [10..10] Counter/Timer A1 Interrupt Enable bit based on COMPR1. */
__IOM uint32_t TMRA1CLR : 1; /*!< [11..11] Counter/Timer A1 Clear bit. */
__IOM uint32_t TMRA1POL : 1; /*!< [12..12] Counter/Timer A1 output polarity. */
__IM uint32_t : 3;
__IOM uint32_t TMRB1EN : 1; /*!< [16..16] Counter/Timer B1 Enable bit. */
__IOM uint32_t TMRB1CLK : 5; /*!< [21..17] Counter/Timer B1 Clock Select. */
__IOM uint32_t TMRB1FN : 3; /*!< [24..22] Counter/Timer B1 Function Select. */
__IOM uint32_t TMRB1IE0 : 1; /*!< [25..25] Counter/Timer B1 Interrupt Enable bit for COMPR0. */
__IOM uint32_t TMRB1IE1 : 1; /*!< [26..26] Counter/Timer B1 Interrupt Enable bit for COMPR1. */
__IOM uint32_t TMRB1CLR : 1; /*!< [27..27] Counter/Timer B1 Clear bit. */
__IOM uint32_t TMRB1POL : 1; /*!< [28..28] Counter/Timer B1 output polarity. */
__IM uint32_t : 2;
__IOM uint32_t CTLINK1 : 1; /*!< [31..31] Counter/Timer A1/B1 Link bit. */
} CTRL1_b;
} ;
__IM uint32_t RESERVED1;
union {
__IOM uint32_t CMPRAUXA1; /*!< (@ 0x00000034) Enhanced compare limits for timer half A. This
is valid if timer 1 is set to function 4
and function 5. */
struct {
__IOM uint32_t CMPR2A1 : 16; /*!< [15..0] Counter/Timer A1 Compare Register 2. Holds the lower
limit for timer half A. */
__IOM uint32_t CMPR3A1 : 16; /*!< [31..16] Counter/Timer A1 Compare Register 3. Holds the upper
limit for timer half A. */
} CMPRAUXA1_b;
} ;
union {
__IOM uint32_t CMPRAUXB1; /*!< (@ 0x00000038) Enhanced compare limits for timer half B. This
is valid if timer 1 is set to function 4
and function 5. */
struct {
__IOM uint32_t CMPR2B1 : 16; /*!< [15..0] Counter/Timer B1 Compare Register 2. Holds the lower
limit for timer half B. */
__IOM uint32_t CMPR3B1 : 16; /*!< [31..16] Counter/Timer B1 Compare Register 3. Holds the upper
limit for timer half B. */
} CMPRAUXB1_b;
} ;
union {
__IOM uint32_t AUX1; /*!< (@ 0x0000003C) Control bit fields for both halves of timer 0. */
struct {
__IOM uint32_t TMRA1LMT : 7; /*!< [6..0] Counter/Timer A1 Pattern Limit Count. */
__IOM uint32_t TMRA1TRIG : 4; /*!< [10..7] Counter/Timer A1 Trigger Select. */
__IOM uint32_t TMRA1NOSYNC : 1; /*!< [11..11] Source clock synchronization control. */
__IOM uint32_t TMRA1TINV : 1; /*!< [12..12] Counter/Timer A1 Invert on trigger. */
__IOM uint32_t TMRA1POL23 : 1; /*!< [13..13] Counter/Timer A1 Upper output polarity */
__IOM uint32_t TMRA1EN23 : 1; /*!< [14..14] Counter/Timer A1 Upper compare enable. */
__IM uint32_t : 1;
__IOM uint32_t TMRB1LMT : 6; /*!< [21..16] Counter/Timer B1 Pattern Limit Count. */
__IM uint32_t : 1;
__IOM uint32_t TMRB1TRIG : 4; /*!< [26..23] Counter/Timer B1 Trigger Select. */
__IOM uint32_t TMRB1NOSYNC : 1; /*!< [27..27] Source clock synchronization control. */
__IOM uint32_t TMRB1TINV : 1; /*!< [28..28] Counter/Timer B1 Invert on trigger. */
__IOM uint32_t TMRB1POL23 : 1; /*!< [29..29] Upper output polarity */
__IOM uint32_t TMRB1EN23 : 1; /*!< [30..30] Counter/Timer B1 Upper compare enable. */
} AUX1_b;
} ;
union {
__IOM uint32_t TMR2; /*!< (@ 0x00000040) This register holds the running time or event
count for ctimer 2. This is either for each
16 bit half or for the whole 32 bit count
when the pair is linked. If the pair is
not linked, they can be running on seperate
clocks and are completely independent. */
struct {
__IOM uint32_t CTTMRA2 : 16; /*!< [15..0] Counter/Timer A2. */
__IOM uint32_t CTTMRB2 : 16; /*!< [31..16] Counter/Timer B2. */
} TMR2_b;
} ;
union {
__IOM uint32_t CMPRA2; /*!< (@ 0x00000044) This register holds the compare limits for timer
2 A half. */
struct {
__IOM uint32_t CMPR0A2 : 16; /*!< [15..0] Counter/Timer A2 Compare Register 0. */
__IOM uint32_t CMPR1A2 : 16; /*!< [31..16] Counter/Timer A2 Compare Register 1. */
} CMPRA2_b;
} ;
union {
__IOM uint32_t CMPRB2; /*!< (@ 0x00000048) This register holds the compare limits for timer
2 B half. */
struct {
__IOM uint32_t CMPR0B2 : 16; /*!< [15..0] Counter/Timer B2 Compare Register 0. */
__IOM uint32_t CMPR1B2 : 16; /*!< [31..16] Counter/Timer B2 Compare Register 1. */
} CMPRB2_b;
} ;
union {
__IOM uint32_t CTRL2; /*!< (@ 0x0000004C) This register holds the control bit fields for
both halves of timer 2. */
struct {
__IOM uint32_t TMRA2EN : 1; /*!< [0..0] Counter/Timer A2 Enable bit. */
__IOM uint32_t TMRA2CLK : 5; /*!< [5..1] Counter/Timer A2 Clock Select. */
__IOM uint32_t TMRA2FN : 3; /*!< [8..6] Counter/Timer A2 Function Select. */
__IOM uint32_t TMRA2IE0 : 1; /*!< [9..9] Counter/Timer A2 Interrupt Enable bit based on COMPR0. */
__IOM uint32_t TMRA2IE1 : 1; /*!< [10..10] Counter/Timer A2 Interrupt Enable bit based on COMPR1. */
__IOM uint32_t TMRA2CLR : 1; /*!< [11..11] Counter/Timer A2 Clear bit. */
__IOM uint32_t TMRA2POL : 1; /*!< [12..12] Counter/Timer A2 output polarity. */
__IM uint32_t : 3;
__IOM uint32_t TMRB2EN : 1; /*!< [16..16] Counter/Timer B2 Enable bit. */
__IOM uint32_t TMRB2CLK : 5; /*!< [21..17] Counter/Timer B2 Clock Select. */
__IOM uint32_t TMRB2FN : 3; /*!< [24..22] Counter/Timer B2 Function Select. */
__IOM uint32_t TMRB2IE0 : 1; /*!< [25..25] Counter/Timer B2 Interrupt Enable bit for COMPR0. */
__IOM uint32_t TMRB2IE1 : 1; /*!< [26..26] Counter/Timer B2 Interrupt Enable bit for COMPR1. */
__IOM uint32_t TMRB2CLR : 1; /*!< [27..27] Counter/Timer B2 Clear bit. */
__IOM uint32_t TMRB2POL : 1; /*!< [28..28] Counter/Timer B2 output polarity. */
__IM uint32_t : 2;
__IOM uint32_t CTLINK2 : 1; /*!< [31..31] Counter/Timer A2/B2 Link bit. */
} CTRL2_b;
} ;
__IM uint32_t RESERVED2;
union {
__IOM uint32_t CMPRAUXA2; /*!< (@ 0x00000054) Enhanced compare limits for timer half A. */
struct {
__IOM uint32_t CMPR2A2 : 16; /*!< [15..0] Counter/Timer A2 Compare Register 2. Holds the lower
limit for timer half A. */
__IOM uint32_t CMPR3A2 : 16; /*!< [31..16] Counter/Timer A2 Compare Register 3. Holds the upper
limit for timer half A. */
} CMPRAUXA2_b;
} ;
union {
__IOM uint32_t CMPRAUXB2; /*!< (@ 0x00000058) Enhanced compare limits for timer half B. */
struct {
__IOM uint32_t CMPR2B2 : 16; /*!< [15..0] Counter/Timer B2 Compare Register 2. Holds the lower
limit for timer half B. */
__IOM uint32_t CMPR3B2 : 16; /*!< [31..16] Counter/Timer B2 Compare Register 3. Holds the upper
limit for timer half B. */
} CMPRAUXB2_b;
} ;
union {
__IOM uint32_t AUX2; /*!< (@ 0x0000005C) Control bit fields for both halves of timer 0. */
struct {
__IOM uint32_t TMRA2LMT : 7; /*!< [6..0] Counter/Timer A2 Pattern Limit Count. */
__IOM uint32_t TMRA2TRIG : 4; /*!< [10..7] Counter/Timer A2 Trigger Select. */
__IOM uint32_t TMRA2NOSYNC : 1; /*!< [11..11] Source clock synchronization control. */
__IOM uint32_t TMRA2TINV : 1; /*!< [12..12] Counter/Timer A2 Invert on trigger. */
__IOM uint32_t TMRA2POL23 : 1; /*!< [13..13] Counter/Timer A2 Upper output polarity */
__IOM uint32_t TMRA2EN23 : 1; /*!< [14..14] Counter/Timer A2 Upper compare enable. */
__IM uint32_t : 1;
__IOM uint32_t TMRB2LMT : 6; /*!< [21..16] Counter/Timer B2 Pattern Limit Count. */
__IM uint32_t : 1;
__IOM uint32_t TMRB2TRIG : 4; /*!< [26..23] Counter/Timer B2 Trigger Select. */
__IOM uint32_t TMRB2NOSYNC : 1; /*!< [27..27] Source clock synchronization control. */
__IOM uint32_t TMRB2TINV : 1; /*!< [28..28] Counter/Timer B2 Invert on trigger. */
__IOM uint32_t TMRB2POL23 : 1; /*!< [29..29] Upper output polarity */
__IOM uint32_t TMRB2EN23 : 1; /*!< [30..30] Counter/Timer B2 Upper compare enable. */
} AUX2_b;
} ;
union {
__IOM uint32_t TMR3; /*!< (@ 0x00000060) Counter/Timer Register */
struct {
__IOM uint32_t CTTMRA3 : 16; /*!< [15..0] Counter/Timer A3. */
__IOM uint32_t CTTMRB3 : 16; /*!< [31..16] Counter/Timer B3. */
} TMR3_b;
} ;
union {
__IOM uint32_t CMPRA3; /*!< (@ 0x00000064) This register holds the compare limits for timer
half A. */
struct {
__IOM uint32_t CMPR0A3 : 16; /*!< [15..0] Counter/Timer A3 Compare Register 0. */
__IOM uint32_t CMPR1A3 : 16; /*!< [31..16] Counter/Timer A3 Compare Register 1. */
} CMPRA3_b;
} ;
union {
__IOM uint32_t CMPRB3; /*!< (@ 0x00000068) This register holds the compare limits for timer
half B. */
struct {
__IOM uint32_t CMPR0B3 : 16; /*!< [15..0] Counter/Timer B3 Compare Register 0. */
__IOM uint32_t CMPR1B3 : 16; /*!< [31..16] Counter/Timer B3 Compare Register 1. */
} CMPRB3_b;
} ;
union {
__IOM uint32_t CTRL3; /*!< (@ 0x0000006C) This register holds the control bit fields for
both halves of timer 3. */
struct {
__IOM uint32_t TMRA3EN : 1; /*!< [0..0] Counter/Timer A3 Enable bit. */
__IOM uint32_t TMRA3CLK : 5; /*!< [5..1] Counter/Timer A3 Clock Select. */
__IOM uint32_t TMRA3FN : 3; /*!< [8..6] Counter/Timer A3 Function Select. */
__IOM uint32_t TMRA3IE0 : 1; /*!< [9..9] Counter/Timer A3 Interrupt Enable bit based on COMPR0. */
__IOM uint32_t TMRA3IE1 : 1; /*!< [10..10] Counter/Timer A3 Interrupt Enable bit based on COMPR1. */
__IOM uint32_t TMRA3CLR : 1; /*!< [11..11] Counter/Timer A3 Clear bit. */
__IOM uint32_t TMRA3POL : 1; /*!< [12..12] Counter/Timer A3 output polarity. */
__IM uint32_t : 2;
__IOM uint32_t ADCEN : 1; /*!< [15..15] Special Timer A3 enable for ADC function. */
__IOM uint32_t TMRB3EN : 1; /*!< [16..16] Counter/Timer B3 Enable bit. */
__IOM uint32_t TMRB3CLK : 5; /*!< [21..17] Counter/Timer B3 Clock Select. */
__IOM uint32_t TMRB3FN : 3; /*!< [24..22] Counter/Timer B3 Function Select. */
__IOM uint32_t TMRB3IE0 : 1; /*!< [25..25] Counter/Timer B3 Interrupt Enable bit for COMPR0. */
__IOM uint32_t TMRB3IE1 : 1; /*!< [26..26] Counter/Timer B3 Interrupt Enable bit for COMPR1. */
__IOM uint32_t TMRB3CLR : 1; /*!< [27..27] Counter/Timer B3 Clear bit. */
__IOM uint32_t TMRB3POL : 1; /*!< [28..28] Counter/Timer B3 output polarity. */
__IM uint32_t : 2;
__IOM uint32_t CTLINK3 : 1; /*!< [31..31] Counter/Timer A3/B3 Link bit. */
} CTRL3_b;
} ;
__IM uint32_t RESERVED3;
union {
__IOM uint32_t CMPRAUXA3; /*!< (@ 0x00000074) Enhanced compare limits for timer half A. */
struct {
__IOM uint32_t CMPR2A3 : 16; /*!< [15..0] Counter/Timer A3 Compare Register 2. Holds the lower
limit for timer half A. */
__IOM uint32_t CMPR3A3 : 16; /*!< [31..16] Counter/Timer A3 Compare Register 3. Holds the upper
limit for timer half A. */
} CMPRAUXA3_b;
} ;
union {
__IOM uint32_t CMPRAUXB3; /*!< (@ 0x00000078) Enhanced compare limits for timer half B. */
struct {
__IOM uint32_t CMPR2B3 : 16; /*!< [15..0] Counter/Timer B3 Compare Register 2. Holds the lower
limit for timer half B. */
__IOM uint32_t CMPR3B3 : 16; /*!< [31..16] Counter/Timer B3 Compare Register 3. Holds the upper
limit for timer half B. */
} CMPRAUXB3_b;
} ;
union {
__IOM uint32_t AUX3; /*!< (@ 0x0000007C) Control bit fields for both halves of timer 0. */
struct {
__IOM uint32_t TMRA3LMT : 7; /*!< [6..0] Counter/Timer A3 Pattern Limit Count. */
__IOM uint32_t TMRA3TRIG : 4; /*!< [10..7] Counter/Timer A3 Trigger Select. */
__IOM uint32_t TMRA3NOSYNC : 1; /*!< [11..11] Source clock synchronization control. */
__IOM uint32_t TMRA3TINV : 1; /*!< [12..12] Counter/Timer A3 Invert on trigger. */
__IOM uint32_t TMRA3POL23 : 1; /*!< [13..13] Counter/Timer A3 Upper output polarity */
__IOM uint32_t TMRA3EN23 : 1; /*!< [14..14] Counter/Timer A3 Upper compare enable. */
__IM uint32_t : 1;
__IOM uint32_t TMRB3LMT : 6; /*!< [21..16] Counter/Timer B3 Pattern Limit Count. */
__IM uint32_t : 1;
__IOM uint32_t TMRB3TRIG : 4; /*!< [26..23] Counter/Timer B3 Trigger Select. */
__IOM uint32_t TMRB3NOSYNC : 1; /*!< [27..27] Source clock synchronization control. */
__IOM uint32_t TMRB3TINV : 1; /*!< [28..28] Counter/Timer B3 Invert on trigger. */
__IOM uint32_t TMRB3POL23 : 1; /*!< [29..29] Upper output polarity */
__IOM uint32_t TMRB3EN23 : 1; /*!< [30..30] Counter/Timer B3 Upper compare enable. */
} AUX3_b;
} ;
union {
__IOM uint32_t TMR4; /*!< (@ 0x00000080) This register holds the running time or event
count, either for each 16 bit half or for
the whole 32 bit count when the pair is
linked. */
struct {
__IOM uint32_t CTTMRA4 : 16; /*!< [15..0] Counter/Timer A4. */
__IOM uint32_t CTTMRB4 : 16; /*!< [31..16] Counter/Timer B4. */
} TMR4_b;
} ;
union {
__IOM uint32_t CMPRA4; /*!< (@ 0x00000084) Compare limits for timer half A. */
struct {
__IOM uint32_t CMPR0A4 : 16; /*!< [15..0] Counter/Timer A4 Compare Register 0. Holds the lower
limit for timer half A. */
__IOM uint32_t CMPR1A4 : 16; /*!< [31..16] Counter/Timer A4 Compare Register 1. Holds the upper
limit for timer half A. */
} CMPRA4_b;
} ;
union {
__IOM uint32_t CMPRB4; /*!< (@ 0x00000088) Compare limits for timer half B. */
struct {
__IOM uint32_t CMPR0B4 : 16; /*!< [15..0] Counter/Timer B4 Compare Register 0. Holds the lower
limit for timer half B. */
__IOM uint32_t CMPR1B4 : 16; /*!< [31..16] Counter/Timer B4 Compare Register 1. Holds the upper
limit for timer half B. */
} CMPRB4_b;
} ;
union {
__IOM uint32_t CTRL4; /*!< (@ 0x0000008C) Control bit fields for both halves of timer 4. */
struct {
__IOM uint32_t TMRA4EN : 1; /*!< [0..0] Counter/Timer A4 Enable bit. */
__IOM uint32_t TMRA4CLK : 5; /*!< [5..1] Counter/Timer A4 Clock Select. */
__IOM uint32_t TMRA4FN : 3; /*!< [8..6] Counter/Timer A4 Function Select. */
__IOM uint32_t TMRA4IE0 : 1; /*!< [9..9] Counter/Timer A4 Interrupt Enable bit based on COMPR0. */
__IOM uint32_t TMRA4IE1 : 1; /*!< [10..10] Counter/Timer A4 Interrupt Enable bit based on COMPR1. */
__IOM uint32_t TMRA4CLR : 1; /*!< [11..11] Counter/Timer A4 Clear bit. */
__IOM uint32_t TMRA4POL : 1; /*!< [12..12] Counter/Timer A4 output polarity. */
__IM uint32_t : 3;
__IOM uint32_t TMRB4EN : 1; /*!< [16..16] Counter/Timer B4 Enable bit. */
__IOM uint32_t TMRB4CLK : 5; /*!< [21..17] Counter/Timer B4 Clock Select. */
__IOM uint32_t TMRB4FN : 3; /*!< [24..22] Counter/Timer B4 Function Select. */
__IOM uint32_t TMRB4IE0 : 1; /*!< [25..25] Counter/Timer B4 Interrupt Enable bit for COMPR0. */
__IOM uint32_t TMRB4IE1 : 1; /*!< [26..26] Counter/Timer B4 Interrupt Enable bit for COMPR1. */
__IOM uint32_t TMRB4CLR : 1; /*!< [27..27] Counter/Timer B4 Clear bit. */
__IOM uint32_t TMRB4POL : 1; /*!< [28..28] Counter/Timer B4 output polarity. */
__IM uint32_t : 2;
__IOM uint32_t CTLINK4 : 1; /*!< [31..31] Counter/Timer A4/B4 Link bit. */
} CTRL4_b;
} ;
__IM uint32_t RESERVED4;
union {
__IOM uint32_t CMPRAUXA4; /*!< (@ 0x00000094) Enhanced compare limits for timer half A. */
struct {
__IOM uint32_t CMPR2A4 : 16; /*!< [15..0] Counter/Timer A4 Compare Register 2. Holds the lower
limit for timer half A. */
__IOM uint32_t CMPR3A4 : 16; /*!< [31..16] Counter/Timer A4 Compare Register 3. Holds the upper
limit for timer half A. */
} CMPRAUXA4_b;
} ;
union {
__IOM uint32_t CMPRAUXB4; /*!< (@ 0x00000098) Enhanced compare limits for timer half B. */
struct {
__IOM uint32_t CMPR2B4 : 16; /*!< [15..0] Counter/Timer B4 Compare Register 2. Holds the lower
limit for timer half B. */
__IOM uint32_t CMPR3B4 : 16; /*!< [31..16] Counter/Timer B4 Compare Register 3. Holds the upper
limit for timer half B. */
} CMPRAUXB4_b;
} ;
union {
__IOM uint32_t AUX4; /*!< (@ 0x0000009C) Control bit fields for both halves of timer 4. */
struct {
__IOM uint32_t TMRA4LMT : 7; /*!< [6..0] Counter/Timer A4 Pattern Limit Count. */
__IOM uint32_t TMRA4TRIG : 4; /*!< [10..7] Counter/Timer A4 Trigger Select. */
__IOM uint32_t TMRA4NOSYNC : 1; /*!< [11..11] Source clock synchronization control. */
__IOM uint32_t TMRA4TINV : 1; /*!< [12..12] Counter/Timer A4 Invert on trigger. */
__IOM uint32_t TMRA4POL23 : 1; /*!< [13..13] Counter/Timer A4 Upper output polarity */
__IOM uint32_t TMRA4EN23 : 1; /*!< [14..14] Counter/Timer A4 Upper compare enable. */
__IM uint32_t : 1;
__IOM uint32_t TMRB4LMT : 6; /*!< [21..16] Counter/Timer B4 Pattern Limit Count. */
__IM uint32_t : 1;
__IOM uint32_t TMRB4TRIG : 4; /*!< [26..23] Counter/Timer B4 Trigger Select. */
__IOM uint32_t TMRB4NOSYNC : 1; /*!< [27..27] Source clock synchronization control. */
__IOM uint32_t TMRB4TINV : 1; /*!< [28..28] Counter/Timer B4 Invert on trigger. */
__IOM uint32_t TMRB4POL23 : 1; /*!< [29..29] Upper output polarity */
__IOM uint32_t TMRB4EN23 : 1; /*!< [30..30] Counter/Timer B4 Upper compare enable. */
} AUX4_b;
} ;
union {
__IOM uint32_t TMR5; /*!< (@ 0x000000A0) This register holds the running time or event
count, either for each 16 bit half or for
the whole 32 bit count when the pair is
linked. */
struct {
__IOM uint32_t CTTMRA5 : 16; /*!< [15..0] Counter/Timer A5. */
__IOM uint32_t CTTMRB5 : 16; /*!< [31..16] Counter/Timer B5. */
} TMR5_b;
} ;
union {
__IOM uint32_t CMPRA5; /*!< (@ 0x000000A4) This register holds the compare limits for timer
half A. */
struct {
__IOM uint32_t CMPR0A5 : 16; /*!< [15..0] Counter/Timer A5 Compare Register 0. */
__IOM uint32_t CMPR1A5 : 16; /*!< [31..16] Counter/Timer A5 Compare Register 1. */
} CMPRA5_b;
} ;
union {
__IOM uint32_t CMPRB5; /*!< (@ 0x000000A8) This register holds the compare limits for timer
half B. */
struct {
__IOM uint32_t CMPR0B5 : 16; /*!< [15..0] Counter/Timer B5 Compare Register 0. */
__IOM uint32_t CMPR1B5 : 16; /*!< [31..16] Counter/Timer B5 Compare Register 1. */
} CMPRB5_b;
} ;
union {
__IOM uint32_t CTRL5; /*!< (@ 0x000000AC) Control bit fields for both halves of timer 0. */
struct {
__IOM uint32_t TMRA5EN : 1; /*!< [0..0] Counter/Timer A5 Enable bit. */
__IOM uint32_t TMRA5CLK : 5; /*!< [5..1] Counter/Timer A5 Clock Select. */
__IOM uint32_t TMRA5FN : 3; /*!< [8..6] Counter/Timer A5 Function Select. */
__IOM uint32_t TMRA5IE0 : 1; /*!< [9..9] Counter/Timer A5 Interrupt Enable bit based on COMPR0. */
__IOM uint32_t TMRA5IE1 : 1; /*!< [10..10] Counter/Timer A5 Interrupt Enable bit based on COMPR1. */
__IOM uint32_t TMRA5CLR : 1; /*!< [11..11] Counter/Timer A5 Clear bit. */
__IOM uint32_t TMRA5POL : 1; /*!< [12..12] Counter/Timer A5 output polarity. */
__IM uint32_t : 3;
__IOM uint32_t TMRB5EN : 1; /*!< [16..16] Counter/Timer B5 Enable bit. */
__IOM uint32_t TMRB5CLK : 5; /*!< [21..17] Counter/Timer B5 Clock Select. */
__IOM uint32_t TMRB5FN : 3; /*!< [24..22] Counter/Timer B5 Function Select. */
__IOM uint32_t TMRB5IE0 : 1; /*!< [25..25] Counter/Timer B5 Interrupt Enable bit for COMPR0. */
__IOM uint32_t TMRB5IE1 : 1; /*!< [26..26] Counter/Timer B5 Interrupt Enable bit for COMPR1. */
__IOM uint32_t TMRB5CLR : 1; /*!< [27..27] Counter/Timer B5 Clear bit. */
__IOM uint32_t TMRB5POL : 1; /*!< [28..28] Counter/Timer B5 output polarity. */
__IM uint32_t : 2;
__IOM uint32_t CTLINK5 : 1; /*!< [31..31] Counter/Timer A5/B5 Link bit. */
} CTRL5_b;
} ;
__IM uint32_t RESERVED5;
union {
__IOM uint32_t CMPRAUXA5; /*!< (@ 0x000000B4) Enhanced compare limits for timer half A. */
struct {
__IOM uint32_t CMPR2A5 : 16; /*!< [15..0] Counter/Timer A5 Compare Register 2. Holds the lower
limit for timer half A. */
__IOM uint32_t CMPR3A5 : 16; /*!< [31..16] Counter/Timer A5 Compare Register 3. Holds the upper
limit for timer half A. */
} CMPRAUXA5_b;
} ;
union {
__IOM uint32_t CMPRAUXB5; /*!< (@ 0x000000B8) Enhanced compare limits for timer half B. */
struct {
__IOM uint32_t CMPR2B5 : 16; /*!< [15..0] Counter/Timer B5 Compare Register 2. Holds the lower
limit for timer half B. */
__IOM uint32_t CMPR3B5 : 16; /*!< [31..16] Counter/Timer B5 Compare Register 3. Holds the upper
limit for timer half B. */
} CMPRAUXB5_b;
} ;
union {
__IOM uint32_t AUX5; /*!< (@ 0x000000BC) Control bit fields for both halves of timer 0. */
struct {
__IOM uint32_t TMRA5LMT : 7; /*!< [6..0] Counter/Timer A5 Pattern Limit Count. */
__IOM uint32_t TMRA5TRIG : 4; /*!< [10..7] Counter/Timer A5 Trigger Select. */
__IOM uint32_t TMRA5NOSYNC : 1; /*!< [11..11] Source clock synchronization control. */
__IOM uint32_t TMRA5TINV : 1; /*!< [12..12] Counter/Timer A5 Invert on trigger. */
__IOM uint32_t TMRA5POL23 : 1; /*!< [13..13] Counter/Timer A5 Upper output polarity */
__IOM uint32_t TMRA5EN23 : 1; /*!< [14..14] Counter/Timer A5 Upper compare enable. */
__IM uint32_t : 1;
__IOM uint32_t TMRB5LMT : 6; /*!< [21..16] Counter/Timer B5 Pattern Limit Count. */
__IM uint32_t : 1;
__IOM uint32_t TMRB5TRIG : 4; /*!< [26..23] Counter/Timer B5 Trigger Select. */
__IOM uint32_t TMRB5NOSYNC : 1; /*!< [27..27] Source clock synchronization control. */
__IOM uint32_t TMRB5TINV : 1; /*!< [28..28] Counter/Timer B5 Invert on trigger. */
__IOM uint32_t TMRB5POL23 : 1; /*!< [29..29] Upper output polarity */
__IOM uint32_t TMRB5EN23 : 1; /*!< [30..30] Counter/Timer B5 Upper compare enable. */
} AUX5_b;
} ;
union {
__IOM uint32_t TMR6; /*!< (@ 0x000000C0) Counter/Timer Register */
struct {
__IOM uint32_t CTTMRA6 : 16; /*!< [15..0] Counter/Timer A6. */
__IOM uint32_t CTTMRB6 : 16; /*!< [31..16] Counter/Timer B6. */
} TMR6_b;
} ;
union {
__IOM uint32_t CMPRA6; /*!< (@ 0x000000C4) This register holds the compare limits for timer
half A. */
struct {
__IOM uint32_t CMPR0A6 : 16; /*!< [15..0] Counter/Timer A6 Compare Register 0. */
__IOM uint32_t CMPR1A6 : 16; /*!< [31..16] Counter/Timer A6 Compare Register 1. */
} CMPRA6_b;
} ;
union {
__IOM uint32_t CMPRB6; /*!< (@ 0x000000C8) This register holds the compare limits for timer
half B. */
struct {
__IOM uint32_t CMPR0B6 : 16; /*!< [15..0] Counter/Timer B6 Compare Register 0. */
__IOM uint32_t CMPR1B6 : 16; /*!< [31..16] Counter/Timer B6 Compare Register 1. */
} CMPRB6_b;
} ;
union {
__IOM uint32_t CTRL6; /*!< (@ 0x000000CC) This register holds the control bit fields for
both halves of timer 6. */
struct {
__IOM uint32_t TMRA6EN : 1; /*!< [0..0] Counter/Timer A6 Enable bit. */
__IOM uint32_t TMRA6CLK : 5; /*!< [5..1] Counter/Timer A6 Clock Select. */
__IOM uint32_t TMRA6FN : 3; /*!< [8..6] Counter/Timer A6 Function Select. */
__IOM uint32_t TMRA6IE0 : 1; /*!< [9..9] Counter/Timer A6 Interrupt Enable bit based on COMPR0. */
__IOM uint32_t TMRA6IE1 : 1; /*!< [10..10] Counter/Timer A6 Interrupt Enable bit based on COMPR1. */
__IOM uint32_t TMRA6CLR : 1; /*!< [11..11] Counter/Timer A6 Clear bit. */
__IOM uint32_t TMRA6POL : 1; /*!< [12..12] Counter/Timer A6 output polarity. */
__IM uint32_t : 3;
__IOM uint32_t TMRB6EN : 1; /*!< [16..16] Counter/Timer B6 Enable bit. */
__IOM uint32_t TMRB6CLK : 5; /*!< [21..17] Counter/Timer B6 Clock Select. */
__IOM uint32_t TMRB6FN : 3; /*!< [24..22] Counter/Timer B6 Function Select. */
__IOM uint32_t TMRB6IE0 : 1; /*!< [25..25] Counter/Timer B6 Interrupt Enable bit for COMPR0. */
__IOM uint32_t TMRB6IE1 : 1; /*!< [26..26] Counter/Timer B6 Interrupt Enable bit for COMPR1. */
__IOM uint32_t TMRB6CLR : 1; /*!< [27..27] Counter/Timer B6 Clear bit. */
__IOM uint32_t TMRB6POL : 1; /*!< [28..28] Counter/Timer B6 output polarity. */
__IM uint32_t : 2;
__IOM uint32_t CTLINK6 : 1; /*!< [31..31] Counter/Timer A6/B6 Link bit. */
} CTRL6_b;
} ;
__IM uint32_t RESERVED6;
union {
__IOM uint32_t CMPRAUXA6; /*!< (@ 0x000000D4) Enhanced compare limits for timer half A. */
struct {
__IOM uint32_t CMPR2A6 : 16; /*!< [15..0] Counter/Timer A6 Compare Register 2. Holds the lower
limit for timer half A. */
__IOM uint32_t CMPR3A6 : 16; /*!< [31..16] Counter/Timer A6 Compare Register 3. Holds the upper
limit for timer half A. */
} CMPRAUXA6_b;
} ;
union {
__IOM uint32_t CMPRAUXB6; /*!< (@ 0x000000D8) Enhanced compare limits for timer half B. */
struct {
__IOM uint32_t CMPR2B6 : 16; /*!< [15..0] Counter/Timer B6 Compare Register 2. Holds the lower
limit for timer half B. */
__IOM uint32_t CMPR3B6 : 16; /*!< [31..16] Counter/Timer B6 Compare Register 3. Holds the upper
limit for timer half B. */
} CMPRAUXB6_b;
} ;
union {
__IOM uint32_t AUX6; /*!< (@ 0x000000DC) Control bit fields for both halves of timer 0. */
struct {
__IOM uint32_t TMRA6LMT : 7; /*!< [6..0] Counter/Timer A6 Pattern Limit Count. */
__IOM uint32_t TMRA6TRIG : 4; /*!< [10..7] Counter/Timer A6 Trigger Select. */
__IOM uint32_t TMRA6NOSYNC : 1; /*!< [11..11] Source clock synchronization control. */
__IOM uint32_t TMRA6TINV : 1; /*!< [12..12] Counter/Timer A6 Invert on trigger. */
__IOM uint32_t TMRA6POL23 : 1; /*!< [13..13] Counter/Timer A6 Upper output polarity */
__IOM uint32_t TMRA6EN23 : 1; /*!< [14..14] Counter/Timer A6 Upper compare enable. */
__IM uint32_t : 1;
__IOM uint32_t TMRB6LMT : 6; /*!< [21..16] Counter/Timer B6 Pattern Limit Count. */
__IM uint32_t : 1;
__IOM uint32_t TMRB6TRIG : 4; /*!< [26..23] Counter/Timer B6 Trigger Select. */
__IOM uint32_t TMRB6NOSYNC : 1; /*!< [27..27] Source clock synchronization control. */
__IOM uint32_t TMRB6TINV : 1; /*!< [28..28] Counter/Timer B6 Invert on trigger. */
__IOM uint32_t TMRB6POL23 : 1; /*!< [29..29] Upper output polarity */
__IOM uint32_t TMRB6EN23 : 1; /*!< [30..30] Counter/Timer B6 Upper compare enable. */
} AUX6_b;
} ;
union {
__IOM uint32_t TMR7; /*!< (@ 0x000000E0) Counter/Timer Register */
struct {
__IOM uint32_t CTTMRA7 : 16; /*!< [15..0] Counter/Timer A7. */
__IOM uint32_t CTTMRB7 : 16; /*!< [31..16] Counter/Timer B7. */
} TMR7_b;
} ;
union {
__IOM uint32_t CMPRA7; /*!< (@ 0x000000E4) This register holds the compare limits for timer
half A. */
struct {
__IOM uint32_t CMPR0A7 : 16; /*!< [15..0] Counter/Timer A7 Compare Register 0. */
__IOM uint32_t CMPR1A7 : 16; /*!< [31..16] Counter/Timer A7 Compare Register 1. */
} CMPRA7_b;
} ;
union {
__IOM uint32_t CMPRB7; /*!< (@ 0x000000E8) This register holds the compare limits for timer
half B. */
struct {
__IOM uint32_t CMPR0B7 : 16; /*!< [15..0] Counter/Timer B3 Compare Register 0. */
__IOM uint32_t CMPR1B7 : 16; /*!< [31..16] Counter/Timer B3 Compare Register 1. */
} CMPRB7_b;
} ;
union {
__IOM uint32_t CTRL7; /*!< (@ 0x000000EC) This register holds the control bit fields for
both halves of timer 7. */
struct {
__IOM uint32_t TMRA7EN : 1; /*!< [0..0] Counter/Timer A7 Enable bit. */
__IOM uint32_t TMRA7CLK : 5; /*!< [5..1] Counter/Timer A7 Clock Select. */
__IOM uint32_t TMRA7FN : 3; /*!< [8..6] Counter/Timer A7 Function Select. */
__IOM uint32_t TMRA7IE0 : 1; /*!< [9..9] Counter/Timer A7 Interrupt Enable bit based on COMPR0. */
__IOM uint32_t TMRA7IE1 : 1; /*!< [10..10] Counter/Timer A7 Interrupt Enable bit based on COMPR1. */
__IOM uint32_t TMRA7CLR : 1; /*!< [11..11] Counter/Timer A7 Clear bit. */
__IOM uint32_t TMRA7POL : 1; /*!< [12..12] Counter/Timer A7 output polarity. */
__IM uint32_t : 3;
__IOM uint32_t TMRB7EN : 1; /*!< [16..16] Counter/Timer B7 Enable bit. */
__IOM uint32_t TMRB7CLK : 5; /*!< [21..17] Counter/Timer B7 Clock Select. */
__IOM uint32_t TMRB7FN : 3; /*!< [24..22] Counter/Timer B7 Function Select. */
__IOM uint32_t TMRB7IE0 : 1; /*!< [25..25] Counter/Timer B7 Interrupt Enable bit for COMPR0. */
__IOM uint32_t TMRB7IE1 : 1; /*!< [26..26] Counter/Timer B7 Interrupt Enable bit for COMPR1. */
__IOM uint32_t TMRB7CLR : 1; /*!< [27..27] Counter/Timer B7 Clear bit. */
__IOM uint32_t TMRB7POL : 1; /*!< [28..28] Counter/Timer B7 output polarity. */
__IM uint32_t : 2;
__IOM uint32_t CTLINK7 : 1; /*!< [31..31] Counter/Timer A7/B7 Link bit. */
} CTRL7_b;
} ;
__IM uint32_t RESERVED7;
union {
__IOM uint32_t CMPRAUXA7; /*!< (@ 0x000000F4) Enhanced compare limits for timer half A. */
struct {
__IOM uint32_t CMPR2A7 : 16; /*!< [15..0] Counter/Timer A7 Compare Register 2. Holds the lower
limit for timer half A. */
__IOM uint32_t CMPR3A7 : 16; /*!< [31..16] Counter/Timer A7 Compare Register 3. Holds the upper
limit for timer half A. */
} CMPRAUXA7_b;
} ;
union {
__IOM uint32_t CMPRAUXB7; /*!< (@ 0x000000F8) Enhanced compare limits for timer half B. */
struct {
__IOM uint32_t CMPR2B7 : 16; /*!< [15..0] Counter/Timer B7 Compare Register 2. Holds the lower
limit for timer half B. */
__IOM uint32_t CMPR3B7 : 16; /*!< [31..16] Counter/Timer B7 Compare Register 3. Holds the upper
limit for timer half B. */
} CMPRAUXB7_b;
} ;
union {
__IOM uint32_t AUX7; /*!< (@ 0x000000FC) Control bit fields for both halves of timer 0. */
struct {
__IOM uint32_t TMRA7LMT : 7; /*!< [6..0] Counter/Timer A7 Pattern Limit Count. */
__IOM uint32_t TMRA7TRIG : 4; /*!< [10..7] Counter/Timer A7 Trigger Select. */
__IOM uint32_t TMRA7NOSYNC : 1; /*!< [11..11] Source clock synchronization control. */
__IOM uint32_t TMRA7TINV : 1; /*!< [12..12] Counter/Timer A7 Invert on trigger. */
__IOM uint32_t TMRA7POL23 : 1; /*!< [13..13] Counter/Timer A7 Upper output polarity */
__IOM uint32_t TMRA7EN23 : 1; /*!< [14..14] Counter/Timer A7 Upper compare enable. */
__IM uint32_t : 1;
__IOM uint32_t TMRB7LMT : 6; /*!< [21..16] Counter/Timer B7 Pattern Limit Count. */
__IM uint32_t : 1;
__IOM uint32_t TMRB7TRIG : 4; /*!< [26..23] Counter/Timer B7 Trigger Select. */
__IOM uint32_t TMRB7NOSYNC : 1; /*!< [27..27] Source clock synchronization control. */
__IOM uint32_t TMRB7TINV : 1; /*!< [28..28] Counter/Timer B7 Invert on trigger. */
__IOM uint32_t TMRB7POL23 : 1; /*!< [29..29] Upper output polarity */
__IOM uint32_t TMRB7EN23 : 1; /*!< [30..30] Counter/Timer B7 Upper compare enable. */
} AUX7_b;
} ;
union {
__IOM uint32_t GLOBEN; /*!< (@ 0x00000100) Alternate enables for all CTIMERs. */
struct {
__IOM uint32_t ENA0 : 1; /*!< [0..0] Alternate enable for A0 */
__IOM uint32_t ENB0 : 1; /*!< [1..1] Alternate enable for B0 */
__IOM uint32_t ENA1 : 1; /*!< [2..2] Alternate enable for A1 */
__IOM uint32_t ENB1 : 1; /*!< [3..3] Alternate enable for B1 */
__IOM uint32_t ENA2 : 1; /*!< [4..4] Alternate enable for A2 */
__IOM uint32_t ENB2 : 1; /*!< [5..5] Alternate enable for B2 */
__IOM uint32_t ENA3 : 1; /*!< [6..6] Alternate enable for A3 */
__IOM uint32_t ENB3 : 1; /*!< [7..7] Alternate enable for B3. */
__IOM uint32_t ENA4 : 1; /*!< [8..8] Alternate enable for A4 */
__IOM uint32_t ENB4 : 1; /*!< [9..9] Alternate enable for B4 */
__IOM uint32_t ENA5 : 1; /*!< [10..10] Alternate enable for A5 */
__IOM uint32_t ENB5 : 1; /*!< [11..11] Alternate enable for B5 */
__IOM uint32_t ENA6 : 1; /*!< [12..12] Alternate enable for A6 */
__IOM uint32_t ENB6 : 1; /*!< [13..13] Alternate enable for B6 */
__IOM uint32_t ENA7 : 1; /*!< [14..14] Alternate enable for A7 */
__IOM uint32_t ENB7 : 1; /*!< [15..15] Alternate enable for B7. */
} GLOBEN_b;
} ;
union {
__IOM uint32_t OUTCFG0; /*!< (@ 0x00000104) Pad output configuration 0. */
struct {
__IOM uint32_t CFG0 : 3; /*!< [2..0] Pad output 0 configuration */
__IOM uint32_t CFG1 : 3; /*!< [5..3] Pad output 1 configuration */
__IOM uint32_t CFG2 : 3; /*!< [8..6] Pad output 2 configuration */
__IOM uint32_t CFG3 : 3; /*!< [11..9] Pad output 3 configuration */
__IOM uint32_t CFG4 : 3; /*!< [14..12] Pad output 4 configuration */
__IM uint32_t : 1;
__IOM uint32_t CFG5 : 3; /*!< [18..16] Pad output 5 configuration */
__IOM uint32_t CFG6 : 3; /*!< [21..19] Pad output 6 configuration */
__IOM uint32_t CFG7 : 3; /*!< [24..22] Pad output 7 configuration */
__IOM uint32_t CFG8 : 3; /*!< [27..25] Pad output 8 configuration */
__IOM uint32_t CFG9 : 3; /*!< [30..28] Pad output 9 configuration */
} OUTCFG0_b;
} ;
union {
__IOM uint32_t OUTCFG1; /*!< (@ 0x00000108) Pad output configuration 1. */
struct {
__IOM uint32_t CFG10 : 3; /*!< [2..0] Pad output 10 configuration */
__IOM uint32_t CFG11 : 3; /*!< [5..3] Pad output 11 configuration */
__IOM uint32_t CFG12 : 3; /*!< [8..6] Pad output 12 configuration */
__IOM uint32_t CFG13 : 3; /*!< [11..9] Pad output 13 configuration */
__IOM uint32_t CFG14 : 3; /*!< [14..12] Pad output 14 configuration */
__IM uint32_t : 1;
__IOM uint32_t CFG15 : 3; /*!< [18..16] Pad output 15 configuration */
__IOM uint32_t CFG16 : 3; /*!< [21..19] Pad output 16 configuration */
__IOM uint32_t CFG17 : 3; /*!< [24..22] Pad output 17 configuration */
__IOM uint32_t CFG18 : 3; /*!< [27..25] Pad output 18 configuration */
__IOM uint32_t CFG19 : 3; /*!< [30..28] Pad output 19 configuration */
} OUTCFG1_b;
} ;
union {
__IOM uint32_t OUTCFG2; /*!< (@ 0x0000010C) Pad output configuration 2. */
struct {
__IOM uint32_t CFG20 : 3; /*!< [2..0] Pad output 20 configuration */
__IOM uint32_t CFG21 : 3; /*!< [5..3] Pad output 21 configuration */
__IOM uint32_t CFG22 : 3; /*!< [8..6] Pad output 22 configuration */
__IOM uint32_t CFG23 : 3; /*!< [11..9] Pad output 23 configuration */
__IOM uint32_t CFG24 : 3; /*!< [14..12] Pad output 24 configuration */
__IM uint32_t : 1;
__IOM uint32_t CFG25 : 3; /*!< [18..16] Pad output 25 configuration */
__IOM uint32_t CFG26 : 3; /*!< [21..19] Pad output 26 configuration */
__IOM uint32_t CFG27 : 3; /*!< [24..22] Pad output 27 configuration */
__IOM uint32_t CFG28 : 3; /*!< [27..25] Pad output 28 configuration */
__IOM uint32_t CFG29 : 3; /*!< [30..28] Pad output 29 configuration */
} OUTCFG2_b;
} ;
__IM uint32_t RESERVED8;
union {
__IOM uint32_t OUTCFG3; /*!< (@ 0x00000114) Pad output configuration 3. */
struct {
__IOM uint32_t CFG30 : 3; /*!< [2..0] Pad output 30 configuration */
__IOM uint32_t CFG31 : 3; /*!< [5..3] Pad output 31 configuration */
} OUTCFG3_b;
} ;
union {
__IOM uint32_t INCFG; /*!< (@ 0x00000118) Pad input configuration. */
struct {
__IOM uint32_t CFGA0 : 1; /*!< [0..0] CTIMER A0 input configuration */
__IOM uint32_t CFGB0 : 1; /*!< [1..1] CTIMER B0 input configuration */
__IOM uint32_t CFGA1 : 1; /*!< [2..2] CTIMER A1 input configuration */
__IOM uint32_t CFGB1 : 1; /*!< [3..3] CTIMER B1 input configuration */
__IOM uint32_t CFGA2 : 1; /*!< [4..4] CTIMER A2 input configuration */
__IOM uint32_t CFGB2 : 1; /*!< [5..5] CTIMER B2 input configuration */
__IOM uint32_t CFGA3 : 1; /*!< [6..6] CTIMER A3 input configuration */
__IOM uint32_t CFGB3 : 1; /*!< [7..7] CTIMER B3 input configuration */
__IOM uint32_t CFGA4 : 1; /*!< [8..8] CTIMER A4 input configuration */
__IOM uint32_t CFGB4 : 1; /*!< [9..9] CTIMER B4 input configuration */
__IOM uint32_t CFGA5 : 1; /*!< [10..10] CTIMER A5 input configuration */
__IOM uint32_t CFGB5 : 1; /*!< [11..11] CTIMER B5 input configuration */
__IOM uint32_t CFGA6 : 1; /*!< [12..12] CTIMER A6 input configuration */
__IOM uint32_t CFGB6 : 1; /*!< [13..13] CTIMER B6 input configuration */
__IOM uint32_t CFGA7 : 1; /*!< [14..14] CTIMER A7 input configuration */
__IOM uint32_t CFGB7 : 1; /*!< [15..15] CTIMER B7 input configuration */
} INCFG_b;
} ;
__IM uint32_t RESERVED9[9];
union {
__IOM uint32_t STCFG; /*!< (@ 0x00000140) The STIMER Configuration Register contains the
software control for selecting the clock
divider and source feeding the system timer. */
struct {
__IOM uint32_t CLKSEL : 4; /*!< [3..0] Selects an appropriate clock source and divider to use
for the System Timer clock. */
__IM uint32_t : 4;
__IOM uint32_t COMPARE_A_EN : 1; /*!< [8..8] Selects whether compare is enabled for the corresponding
SCMPR register. If compare is enabled, the interrupt status
is set once the comparision is met. */
__IOM uint32_t COMPARE_B_EN : 1; /*!< [9..9] Selects whether compare is enabled for the corresponding
SCMPR register. If compare is enabled, the interrupt status
is set once the comparision is met. */
__IOM uint32_t COMPARE_C_EN : 1; /*!< [10..10] Selects whether compare is enabled for the corresponding
SCMPR register. If compare is enabled, the interrupt status
is set once the comparision is met. */
__IOM uint32_t COMPARE_D_EN : 1; /*!< [11..11] Selects whether compare is enabled for the corresponding
SCMPR register. If compare is enabled, the interrupt status
is set once the comparision is met. */
__IOM uint32_t COMPARE_E_EN : 1; /*!< [12..12] Selects whether compare is enabled for the corresponding
SCMPR register. If compare is enabled, the interrupt status
is set once the comparision is met. */
__IOM uint32_t COMPARE_F_EN : 1; /*!< [13..13] Selects whether compare is enabled for the corresponding
SCMPR register. If compare is enabled, the interrupt status
is set once the comparision is met. */
__IOM uint32_t COMPARE_G_EN : 1; /*!< [14..14] Selects whether compare is enabled for the corresponding
SCMPR register. If compare is enabled, the interrupt status
is set once the comparision is met. */
__IOM uint32_t COMPARE_H_EN : 1; /*!< [15..15] Selects whether compare is enabled for the corresponding
SCMPR register. If compare is enabled, the interrupt status
is set once the comparision is met. */
__IM uint32_t : 14;
__IOM uint32_t CLEAR : 1; /*!< [30..30] Set this bit to one to clear the System Timer register.
If this bit is set to '1', the system timer register will
stay cleared. It needs to be set to '0' for the system
timer to start running. */
__IOM uint32_t FREEZE : 1; /*!< [31..31] Set this bit to one to freeze the clock input to the
COUNTER register. Once frozen, the value can be safely
written from the MCU. Unfreeze to resume. */
} STCFG_b;
} ;
union {
__IOM uint32_t STTMR; /*!< (@ 0x00000144) The COUNTER Register contains the running count
of time as maintained by incrementing for
every rising clock edge of the clock source
selected in the configuration register.
It is this counter value that captured in
the capture registers and it is this counter
value that is compared against the various
compare registers. This register cannot
be written, but can be cleared to 0 for
a deterministic value. Use the FREEZE bit
will stop this counter from incrementing. */
struct {
__IOM uint32_t STTMR : 32; /*!< [31..0] Value of the 32-bit counter as it ticks over. */
} STTMR_b;
} ;
union {
__IOM uint32_t CAPTURECONTROL; /*!< (@ 0x00000148) The STIMER Capture Control Register controls
each of the 4 capture registers. It selects
their GPIO pin number for a trigger source,
enables a capture operation and sets the
input polarity for the capture. NOTE: 8-bit
writes can control individual capture registers
atomically. */
struct {
__IOM uint32_t CAPTURE0 : 1; /*!< [0..0] Selects whether capture is enabled for the specified
capture register. */
__IOM uint32_t CAPTURE1 : 1; /*!< [1..1] Selects whether capture is enabled for the specified
capture register. */
__IOM uint32_t CAPTURE2 : 1; /*!< [2..2] Selects whether capture is enabled for the specified
capture register. */
__IOM uint32_t CAPTURE3 : 1; /*!< [3..3] Selects whether capture is enabled for the specified
capture register. */
} CAPTURECONTROL_b;
} ;
__IM uint32_t RESERVED10;
union {
__IOM uint32_t SCMPR0; /*!< (@ 0x00000150) The VALUE in this bit field is used to compare
against the VALUE in the COUNTER register.
If the match criterion in the configuration
register is met then a corresponding interrupt
status bit is set. The match criterion is
defined as COUNTER equal to COMPARE. To
establish a desired value in this COMPARE
register, write the number of ticks in the
future to this register to indicate when
to interrupt. The hardware does the addition
to the COUNTER value in the STIMER clock
domain so that the m */
struct {
__IOM uint32_t SCMPR0 : 32; /*!< [31..0] Compare this value to the value in the COUNTER register
according to the match criterion, as selected in the COMPARE_A_EN
bit in the REG_CTIMER_STCGF register. */
} SCMPR0_b;
} ;
union {
__IOM uint32_t SCMPR1; /*!< (@ 0x00000154) The VALUE in this bit field is used to compare
against the VALUE in the COUNTER register.
If the match criterion in the configuration
register is met then a corresponding interrupt
status bit is set. The match criterion is
defined as COUNTER equal to COMPARE. To
establish a desired value in this COMPARE
register, write the number of ticks in the
future to this register to indicate when
to interrupt. The hardware does the addition
to the COUNTER value in the STIMER clock
domain so that the m */
struct {
__IOM uint32_t SCMPR1 : 32; /*!< [31..0] Compare this value to the value in the COUNTER register
according to the match criterion, as selected in the COMPARE_B_EN
bit in the REG_CTIMER_STCGF register. */
} SCMPR1_b;
} ;
union {
__IOM uint32_t SCMPR2; /*!< (@ 0x00000158) The VALUE in this bit field is used to compare
against the VALUE in the COUNTER register.
If the match criterion in the configuration
register is met then a corresponding interrupt
status bit is set. The match criterion is
defined as COUNTER equal to COMPARE. To
establish a desired value in this COMPARE
register, write the number of ticks in the
future to this register to indicate when
to interrupt. The hardware does the addition
to the COUNTER value in the STIMER clock
domain so that the m */
struct {
__IOM uint32_t SCMPR2 : 32; /*!< [31..0] Compare this value to the value in the COUNTER register
according to the match criterion, as selected in the COMPARE_C_EN
bit in the REG_CTIMER_STCGF register. */
} SCMPR2_b;
} ;
union {
__IOM uint32_t SCMPR3; /*!< (@ 0x0000015C) The VALUE in this bit field is used to compare
against the VALUE in the COUNTER register.
If the match criterion in the configuration
register is met then a corresponding interrupt
status bit is set. The match criterion is
defined as COUNTER equal to COMPARE. To
establish a desired value in this COMPARE
register, write the number of ticks in the
future to this register to indicate when
to interrupt. The hardware does the addition
to the COUNTER value in the STIMER clock
domain so that the m */
struct {
__IOM uint32_t SCMPR3 : 32; /*!< [31..0] Compare this value to the value in the COUNTER register
according to the match criterion, as selected in the COMPARE_D_EN
bit in the REG_CTIMER_STCGF register. */
} SCMPR3_b;
} ;
union {
__IOM uint32_t SCMPR4; /*!< (@ 0x00000160) The VALUE in this bit field is used to compare
against the VALUE in the COUNTER register.
If the match criterion in the configuration
register is met then a corresponding interrupt
status bit is set. The match criterion is
defined as COUNTER equal to COMPARE. To
establish a desired value in this COMPARE
register, write the number of ticks in the
future to this register to indicate when
to interrupt. The hardware does the addition
to the COUNTER value in the STIMER clock
domain so that the m */
struct {
__IOM uint32_t SCMPR4 : 32; /*!< [31..0] Compare this value to the value in the COUNTER register
according to the match criterion, as selected in the COMPARE_E_EN
bit in the REG_CTIMER_STCGF register. */
} SCMPR4_b;
} ;
union {
__IOM uint32_t SCMPR5; /*!< (@ 0x00000164) The VALUE in this bit field is used to compare
against the VALUE in the COUNTER register.
If the match criterion in the configuration
register is met then a corresponding interrupt
status bit is set. The match criterion is
defined as COUNTER equal to COMPARE. To
establish a desired value in this COMPARE
register, write the number of ticks in the
future to this register to indicate when
to interrupt. The hardware does the addition
to the COUNTER value in the STIMER clock
domain so that the m */
struct {
__IOM uint32_t SCMPR5 : 32; /*!< [31..0] Compare this value to the value in the COUNTER register
according to the match criterion, as selected in the COMPARE_F_EN
bit in the REG_CTIMER_STCGF register. */
} SCMPR5_b;
} ;
union {
__IOM uint32_t SCMPR6; /*!< (@ 0x00000168) The VALUE in this bit field is used to compare
against the VALUE in the COUNTER register.
If the match criterion in the configuration
register is met then a corresponding interrupt
status bit is set. The match criterion is
defined as COUNTER equal to COMPARE. To
establish a desired value in this COMPARE
register, write the number of ticks in the
future to this register to indicate when
to interrupt. The hardware does the addition
to the COUNTER value in the STIMER clock
domain so that the m */
struct {
__IOM uint32_t SCMPR6 : 32; /*!< [31..0] Compare this value to the value in the COUNTER register
according to the match criterion, as selected in the COMPARE_G_EN
bit in the REG_CTIMER_STCGF register. */
} SCMPR6_b;
} ;
union {
__IOM uint32_t SCMPR7; /*!< (@ 0x0000016C) The VALUE in this bit field is used to compare
against the VALUE in the COUNTER register.
If the match criterion in the configuration
register is met then a corresponding interrupt
status bit is set. The match criterion is
defined as COUNTER equal to COMPARE. To
establish a desired value in this COMPARE
register, write the number of ticks in the
future to this register to indicate when
to interrupt. The hardware does the addition
to the COUNTER value in the STIMER clock
domain so that the m */
struct {
__IOM uint32_t SCMPR7 : 32; /*!< [31..0] Compare this value to the value in the COUNTER register
according to the match criterion, as selected in the COMPARE_H_EN
bit in the REG_CTIMER_STCGF register. */
} SCMPR7_b;
} ;
__IM uint32_t RESERVED11[28];
union {
__IOM uint32_t SCAPT0; /*!< (@ 0x000001E0) The STIMER capture Register A grabs the VALUE
in the COUNTER register whenever capture
condition (event) A is asserted. This register
holds a time stamp for the event. */
struct {
__IOM uint32_t SCAPT0 : 32; /*!< [31..0] Whenever the event is detected, the value in the COUNTER
is copied into this register and the corresponding interrupt
status bit is set. */
} SCAPT0_b;
} ;
union {
__IOM uint32_t SCAPT1; /*!< (@ 0x000001E4) The STIMER capture Register B grabs the VALUE
in the COUNTER register whenever capture
condition (event) B is asserted. This register
holds a time stamp for the event. */
struct {
__IOM uint32_t SCAPT1 : 32; /*!< [31..0] Whenever the event is detected, the value in the COUNTER
is copied into this register and the corresponding interrupt
status bit is set. */
} SCAPT1_b;
} ;
union {
__IOM uint32_t SCAPT2; /*!< (@ 0x000001E8) The STIMER capture Register C grabs the VALUE
in the COUNTER register whenever capture
condition (event) C is asserted. This register
holds a time stamp for the event. */
struct {
__IOM uint32_t SCAPT2 : 32; /*!< [31..0] Whenever the event is detected, the value in the COUNTER
is copied into this register and the corresponding interrupt
status bit is set. */
} SCAPT2_b;
} ;
union {
__IOM uint32_t SCAPT3; /*!< (@ 0x000001EC) The STIMER capture Register D grabs the VALUE
in the COUNTER register whenever capture
condition (event) D is asserted. This register
holds a time stamp for the event. */
struct {
__IOM uint32_t SCAPT3 : 32; /*!< [31..0] Whenever the event is detected, the value in the COUNTER
is copied into this register and the corresponding interrupt
status bit is set. */
} SCAPT3_b;
} ;
union {
__IOM uint32_t SNVR0; /*!< (@ 0x000001F0) The NVRAM_A Register contains a portion of the
stored epoch offset associated with the
time in the COUNTER register. This register
is only reset by POI not by HRESETn. Its
contents are intended to survive all reset
level except POI and full power cycles. */
struct {
__IOM uint32_t SNVR0 : 32; /*!< [31..0] Value of the 32-bit counter as it ticks over. */
} SNVR0_b;
} ;
union {
__IOM uint32_t SNVR1; /*!< (@ 0x000001F4) The NVRAM_B Register contains a portion of the
stored epoch offset associated with the
time in the COUNTER register. This register
is only reset by POI not by HRESETn. Its
contents are intended to survive all reset
level except POI and full power cycles. */
struct {
__IOM uint32_t SNVR1 : 32; /*!< [31..0] Value of the 32-bit counter as it ticks over. */
} SNVR1_b;
} ;
union {
__IOM uint32_t SNVR2; /*!< (@ 0x000001F8) The NVRAM_C Register contains a portion of the
stored epoch offset associated with the
time in the COUNTER register. This register
is only reset by POI not by HRESETn. Its
contents are intended to survive all reset
level except POI and full power cycles. */
struct {
__IOM uint32_t SNVR2 : 32; /*!< [31..0] Value of the 32-bit counter as it ticks over. */
} SNVR2_b;
} ;
union {
__IOM uint32_t SNVR3; /*!< (@ 0x000001FC) The NVRAM_D Register contains a portion of the
stored epoch offset associated with the
time in the COUNTER register. This register
is only reset by POI not by HRESETn. Its
contents are intended to survive all reset
level except POI and full power cycles. */
struct {
__IOM uint32_t SNVR3 : 32; /*!< [31..0] Value of the 32-bit counter as it ticks over. */
} SNVR3_b;
} ;
union {
__IOM uint32_t INTEN; /*!< (@ 0x00000200) Set bits in this register to allow this module
to generate the corresponding interrupt. */
struct {
__IOM uint32_t CTMRA0C0INT : 1; /*!< [0..0] Counter/Timer A0 interrupt based on COMPR0. */
__IOM uint32_t CTMRB0C0INT : 1; /*!< [1..1] Counter/Timer B0 interrupt based on COMPR0. */
__IOM uint32_t CTMRA1C0INT : 1; /*!< [2..2] Counter/Timer A1 interrupt based on COMPR0. */
__IOM uint32_t CTMRB1C0INT : 1; /*!< [3..3] Counter/Timer B1 interrupt based on COMPR0. */
__IOM uint32_t CTMRA2C0INT : 1; /*!< [4..4] Counter/Timer A2 interrupt based on COMPR0. */
__IOM uint32_t CTMRB2C0INT : 1; /*!< [5..5] Counter/Timer B2 interrupt based on COMPR0. */
__IOM uint32_t CTMRA3C0INT : 1; /*!< [6..6] Counter/Timer A3 interrupt based on COMPR0. */
__IOM uint32_t CTMRB3C0INT : 1; /*!< [7..7] Counter/Timer B3 interrupt based on COMPR0. */
__IOM uint32_t CTMRA4C0INT : 1; /*!< [8..8] Counter/Timer A4 interrupt based on COMPR0. */
__IOM uint32_t CTMRB4C0INT : 1; /*!< [9..9] Counter/Timer B4 interrupt based on COMPR0. */
__IOM uint32_t CTMRA5C0INT : 1; /*!< [10..10] Counter/Timer A5 interrupt based on COMPR0. */
__IOM uint32_t CTMRB5C0INT : 1; /*!< [11..11] Counter/Timer B5 interrupt based on COMPR0. */
__IOM uint32_t CTMRA6C0INT : 1; /*!< [12..12] Counter/Timer A6 interrupt based on COMPR0. */
__IOM uint32_t CTMRB6C0INT : 1; /*!< [13..13] Counter/Timer B6 interrupt based on COMPR0. */
__IOM uint32_t CTMRA7C0INT : 1; /*!< [14..14] Counter/Timer A7 interrupt based on COMPR0. */
__IOM uint32_t CTMRB7C0INT : 1; /*!< [15..15] Counter/Timer B7 interrupt based on COMPR0. */
__IOM uint32_t CTMRA0C1INT : 1; /*!< [16..16] Counter/Timer A0 interrupt based on COMPR1. */
__IOM uint32_t CTMRB0C1INT : 1; /*!< [17..17] Counter/Timer B0 interrupt based on COMPR1. */
__IOM uint32_t CTMRA1C1INT : 1; /*!< [18..18] Counter/Timer A1 interrupt based on COMPR1. */
__IOM uint32_t CTMRB1C1INT : 1; /*!< [19..19] Counter/Timer B1 interrupt based on COMPR1. */
__IOM uint32_t CTMRA2C1INT : 1; /*!< [20..20] Counter/Timer A2 interrupt based on COMPR1. */
__IOM uint32_t CTMRB2C1INT : 1; /*!< [21..21] Counter/Timer B2 interrupt based on COMPR1. */
__IOM uint32_t CTMRA3C1INT : 1; /*!< [22..22] Counter/Timer A3 interrupt based on COMPR1. */
__IOM uint32_t CTMRB3C1INT : 1; /*!< [23..23] Counter/Timer B3 interrupt based on COMPR1. */
__IOM uint32_t CTMRA4C1INT : 1; /*!< [24..24] Counter/Timer A4 interrupt based on COMPR1. */
__IOM uint32_t CTMRB4C1INT : 1; /*!< [25..25] Counter/Timer B4 interrupt based on COMPR1. */
__IOM uint32_t CTMRA5C1INT : 1; /*!< [26..26] Counter/Timer A5 interrupt based on COMPR1. */
__IOM uint32_t CTMRB5C1INT : 1; /*!< [27..27] Counter/Timer B5 interrupt based on COMPR1. */
__IOM uint32_t CTMRA6C1INT : 1; /*!< [28..28] Counter/Timer A6 interrupt based on COMPR1. */
__IOM uint32_t CTMRB6C1INT : 1; /*!< [29..29] Counter/Timer B6 interrupt based on COMPR1. */
__IOM uint32_t CTMRA7C1INT : 1; /*!< [30..30] Counter/Timer A7 interrupt based on COMPR1. */
__IOM uint32_t CTMRB7C1INT : 1; /*!< [31..31] Counter/Timer B7 interrupt based on COMPR1. */
} INTEN_b;
} ;
union {
__IOM uint32_t INTSTAT; /*!< (@ 0x00000204) Read bits from this register to discover the
cause of a recent interrupt. */
struct {
__IOM uint32_t CTMRA0C0INT : 1; /*!< [0..0] Counter/Timer A0 interrupt based on COMPR0. */
__IOM uint32_t CTMRB0C0INT : 1; /*!< [1..1] Counter/Timer B0 interrupt based on COMPR0. */
__IOM uint32_t CTMRA1C0INT : 1; /*!< [2..2] Counter/Timer A1 interrupt based on COMPR0. */
__IOM uint32_t CTMRB1C0INT : 1; /*!< [3..3] Counter/Timer B1 interrupt based on COMPR0. */
__IOM uint32_t CTMRA2C0INT : 1; /*!< [4..4] Counter/Timer A2 interrupt based on COMPR0. */
__IOM uint32_t CTMRB2C0INT : 1; /*!< [5..5] Counter/Timer B2 interrupt based on COMPR0. */
__IOM uint32_t CTMRA3C0INT : 1; /*!< [6..6] Counter/Timer A3 interrupt based on COMPR0. */
__IOM uint32_t CTMRB3C0INT : 1; /*!< [7..7] Counter/Timer B3 interrupt based on COMPR0. */
__IOM uint32_t CTMRA4C0INT : 1; /*!< [8..8] Counter/Timer A4 interrupt based on COMPR0. */
__IOM uint32_t CTMRB4C0INT : 1; /*!< [9..9] Counter/Timer B4 interrupt based on COMPR0. */
__IOM uint32_t CTMRA5C0INT : 1; /*!< [10..10] Counter/Timer A5 interrupt based on COMPR0. */
__IOM uint32_t CTMRB5C0INT : 1; /*!< [11..11] Counter/Timer B5 interrupt based on COMPR0. */
__IOM uint32_t CTMRA6C0INT : 1; /*!< [12..12] Counter/Timer A6 interrupt based on COMPR0. */
__IOM uint32_t CTMRB6C0INT : 1; /*!< [13..13] Counter/Timer B6 interrupt based on COMPR0. */
__IOM uint32_t CTMRA7C0INT : 1; /*!< [14..14] Counter/Timer A7 interrupt based on COMPR0. */
__IOM uint32_t CTMRB7C0INT : 1; /*!< [15..15] Counter/Timer B7 interrupt based on COMPR0. */
__IOM uint32_t CTMRA0C1INT : 1; /*!< [16..16] Counter/Timer A0 interrupt based on COMPR1. */
__IOM uint32_t CTMRB0C1INT : 1; /*!< [17..17] Counter/Timer B0 interrupt based on COMPR1. */
__IOM uint32_t CTMRA1C1INT : 1; /*!< [18..18] Counter/Timer A1 interrupt based on COMPR1. */
__IOM uint32_t CTMRB1C1INT : 1; /*!< [19..19] Counter/Timer B1 interrupt based on COMPR1. */
__IOM uint32_t CTMRA2C1INT : 1; /*!< [20..20] Counter/Timer A2 interrupt based on COMPR1. */
__IOM uint32_t CTMRB2C1INT : 1; /*!< [21..21] Counter/Timer B2 interrupt based on COMPR1. */
__IOM uint32_t CTMRA3C1INT : 1; /*!< [22..22] Counter/Timer A3 interrupt based on COMPR1. */
__IOM uint32_t CTMRB3C1INT : 1; /*!< [23..23] Counter/Timer B3 interrupt based on COMPR1. */
__IOM uint32_t CTMRA4C1INT : 1; /*!< [24..24] Counter/Timer A4 interrupt based on COMPR1. */
__IOM uint32_t CTMRB4C1INT : 1; /*!< [25..25] Counter/Timer B4 interrupt based on COMPR1. */
__IOM uint32_t CTMRA5C1INT : 1; /*!< [26..26] Counter/Timer A5 interrupt based on COMPR1. */
__IOM uint32_t CTMRB5C1INT : 1; /*!< [27..27] Counter/Timer B5 interrupt based on COMPR1. */
__IOM uint32_t CTMRA6C1INT : 1; /*!< [28..28] Counter/Timer A6 interrupt based on COMPR1. */
__IOM uint32_t CTMRB6C1INT : 1; /*!< [29..29] Counter/Timer B6 interrupt based on COMPR1. */
__IOM uint32_t CTMRA7C1INT : 1; /*!< [30..30] Counter/Timer A7 interrupt based on COMPR1. */
__IOM uint32_t CTMRB7C1INT : 1; /*!< [31..31] Counter/Timer B7 interrupt based on COMPR1. */
} INTSTAT_b;
} ;
union {
__IOM uint32_t INTCLR; /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
the interrupt status associated with that
bit. */
struct {
__IOM uint32_t CTMRA0C0INT : 1; /*!< [0..0] Counter/Timer A0 interrupt based on COMPR0. */
__IOM uint32_t CTMRB0C0INT : 1; /*!< [1..1] Counter/Timer B0 interrupt based on COMPR0. */
__IOM uint32_t CTMRA1C0INT : 1; /*!< [2..2] Counter/Timer A1 interrupt based on COMPR0. */
__IOM uint32_t CTMRB1C0INT : 1; /*!< [3..3] Counter/Timer B1 interrupt based on COMPR0. */
__IOM uint32_t CTMRA2C0INT : 1; /*!< [4..4] Counter/Timer A2 interrupt based on COMPR0. */
__IOM uint32_t CTMRB2C0INT : 1; /*!< [5..5] Counter/Timer B2 interrupt based on COMPR0. */
__IOM uint32_t CTMRA3C0INT : 1; /*!< [6..6] Counter/Timer A3 interrupt based on COMPR0. */
__IOM uint32_t CTMRB3C0INT : 1; /*!< [7..7] Counter/Timer B3 interrupt based on COMPR0. */
__IOM uint32_t CTMRA4C0INT : 1; /*!< [8..8] Counter/Timer A4 interrupt based on COMPR0. */
__IOM uint32_t CTMRB4C0INT : 1; /*!< [9..9] Counter/Timer B4 interrupt based on COMPR0. */
__IOM uint32_t CTMRA5C0INT : 1; /*!< [10..10] Counter/Timer A5 interrupt based on COMPR0. */
__IOM uint32_t CTMRB5C0INT : 1; /*!< [11..11] Counter/Timer B5 interrupt based on COMPR0. */
__IOM uint32_t CTMRA6C0INT : 1; /*!< [12..12] Counter/Timer A6 interrupt based on COMPR0. */
__IOM uint32_t CTMRB6C0INT : 1; /*!< [13..13] Counter/Timer B6 interrupt based on COMPR0. */
__IOM uint32_t CTMRA7C0INT : 1; /*!< [14..14] Counter/Timer A7 interrupt based on COMPR0. */
__IOM uint32_t CTMRB7C0INT : 1; /*!< [15..15] Counter/Timer B7 interrupt based on COMPR0. */
__IOM uint32_t CTMRA0C1INT : 1; /*!< [16..16] Counter/Timer A0 interrupt based on COMPR1. */
__IOM uint32_t CTMRB0C1INT : 1; /*!< [17..17] Counter/Timer B0 interrupt based on COMPR1. */
__IOM uint32_t CTMRA1C1INT : 1; /*!< [18..18] Counter/Timer A1 interrupt based on COMPR1. */
__IOM uint32_t CTMRB1C1INT : 1; /*!< [19..19] Counter/Timer B1 interrupt based on COMPR1. */
__IOM uint32_t CTMRA2C1INT : 1; /*!< [20..20] Counter/Timer A2 interrupt based on COMPR1. */
__IOM uint32_t CTMRB2C1INT : 1; /*!< [21..21] Counter/Timer B2 interrupt based on COMPR1. */
__IOM uint32_t CTMRA3C1INT : 1; /*!< [22..22] Counter/Timer A3 interrupt based on COMPR1. */
__IOM uint32_t CTMRB3C1INT : 1; /*!< [23..23] Counter/Timer B3 interrupt based on COMPR1. */
__IOM uint32_t CTMRA4C1INT : 1; /*!< [24..24] Counter/Timer A4 interrupt based on COMPR1. */
__IOM uint32_t CTMRB4C1INT : 1; /*!< [25..25] Counter/Timer B4 interrupt based on COMPR1. */
__IOM uint32_t CTMRA5C1INT : 1; /*!< [26..26] Counter/Timer A5 interrupt based on COMPR1. */
__IOM uint32_t CTMRB5C1INT : 1; /*!< [27..27] Counter/Timer B5 interrupt based on COMPR1. */
__IOM uint32_t CTMRA6C1INT : 1; /*!< [28..28] Counter/Timer A6 interrupt based on COMPR1. */
__IOM uint32_t CTMRB6C1INT : 1; /*!< [29..29] Counter/Timer B6 interrupt based on COMPR1. */
__IOM uint32_t CTMRA7C1INT : 1; /*!< [30..30] Counter/Timer A7 interrupt based on COMPR1. */
__IOM uint32_t CTMRB7C1INT : 1; /*!< [31..31] Counter/Timer B7 interrupt based on COMPR1. */
} INTCLR_b;
} ;
union {
__IOM uint32_t INTSET; /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
generate an interrupt from this module.
(Generally used for testing purposes). */
struct {
__IOM uint32_t CTMRA0C0INT : 1; /*!< [0..0] Counter/Timer A0 interrupt based on COMPR0. */
__IOM uint32_t CTMRB0C0INT : 1; /*!< [1..1] Counter/Timer B0 interrupt based on COMPR0. */
__IOM uint32_t CTMRA1C0INT : 1; /*!< [2..2] Counter/Timer A1 interrupt based on COMPR0. */
__IOM uint32_t CTMRB1C0INT : 1; /*!< [3..3] Counter/Timer B1 interrupt based on COMPR0. */
__IOM uint32_t CTMRA2C0INT : 1; /*!< [4..4] Counter/Timer A2 interrupt based on COMPR0. */
__IOM uint32_t CTMRB2C0INT : 1; /*!< [5..5] Counter/Timer B2 interrupt based on COMPR0. */
__IOM uint32_t CTMRA3C0INT : 1; /*!< [6..6] Counter/Timer A3 interrupt based on COMPR0. */
__IOM uint32_t CTMRB3C0INT : 1; /*!< [7..7] Counter/Timer B3 interrupt based on COMPR0. */
__IOM uint32_t CTMRA4C0INT : 1; /*!< [8..8] Counter/Timer A4 interrupt based on COMPR0. */
__IOM uint32_t CTMRB4C0INT : 1; /*!< [9..9] Counter/Timer B4 interrupt based on COMPR0. */
__IOM uint32_t CTMRA5C0INT : 1; /*!< [10..10] Counter/Timer A5 interrupt based on COMPR0. */
__IOM uint32_t CTMRB5C0INT : 1; /*!< [11..11] Counter/Timer B5 interrupt based on COMPR0. */
__IOM uint32_t CTMRA6C0INT : 1; /*!< [12..12] Counter/Timer A6 interrupt based on COMPR0. */
__IOM uint32_t CTMRB6C0INT : 1; /*!< [13..13] Counter/Timer B6 interrupt based on COMPR0. */
__IOM uint32_t CTMRA7C0INT : 1; /*!< [14..14] Counter/Timer A7 interrupt based on COMPR0. */
__IOM uint32_t CTMRB7C0INT : 1; /*!< [15..15] Counter/Timer B7 interrupt based on COMPR0. */
__IOM uint32_t CTMRA0C1INT : 1; /*!< [16..16] Counter/Timer A0 interrupt based on COMPR1. */
__IOM uint32_t CTMRB0C1INT : 1; /*!< [17..17] Counter/Timer B0 interrupt based on COMPR1. */
__IOM uint32_t CTMRA1C1INT : 1; /*!< [18..18] Counter/Timer A1 interrupt based on COMPR1. */
__IOM uint32_t CTMRB1C1INT : 1; /*!< [19..19] Counter/Timer B1 interrupt based on COMPR1. */
__IOM uint32_t CTMRA2C1INT : 1; /*!< [20..20] Counter/Timer A2 interrupt based on COMPR1. */
__IOM uint32_t CTMRB2C1INT : 1; /*!< [21..21] Counter/Timer B2 interrupt based on COMPR1. */
__IOM uint32_t CTMRA3C1INT : 1; /*!< [22..22] Counter/Timer A3 interrupt based on COMPR1. */
__IOM uint32_t CTMRB3C1INT : 1; /*!< [23..23] Counter/Timer B3 interrupt based on COMPR1. */
__IOM uint32_t CTMRA4C1INT : 1; /*!< [24..24] Counter/Timer A4 interrupt based on COMPR1. */
__IOM uint32_t CTMRB4C1INT : 1; /*!< [25..25] Counter/Timer B4 interrupt based on COMPR1. */
__IOM uint32_t CTMRA5C1INT : 1; /*!< [26..26] Counter/Timer A5 interrupt based on COMPR1. */
__IOM uint32_t CTMRB5C1INT : 1; /*!< [27..27] Counter/Timer B5 interrupt based on COMPR1. */
__IOM uint32_t CTMRA6C1INT : 1; /*!< [28..28] Counter/Timer A6 interrupt based on COMPR1. */
__IOM uint32_t CTMRB6C1INT : 1; /*!< [29..29] Counter/Timer B6 interrupt based on COMPR1. */
__IOM uint32_t CTMRA7C1INT : 1; /*!< [30..30] Counter/Timer A7 interrupt based on COMPR1. */
__IOM uint32_t CTMRB7C1INT : 1; /*!< [31..31] Counter/Timer B7 interrupt based on COMPR1. */
} INTSET_b;
} ;
__IM uint32_t RESERVED12[60];
union {
__IOM uint32_t STMINTEN; /*!< (@ 0x00000300) Set bits in this register to allow this module
to generate the corresponding interrupt. */
struct {
__IOM uint32_t COMPAREA : 1; /*!< [0..0] COUNTER is greater than or equal to COMPARE register
A. */
__IOM uint32_t COMPAREB : 1; /*!< [1..1] COUNTER is greater than or equal to COMPARE register
B. */
__IOM uint32_t COMPAREC : 1; /*!< [2..2] COUNTER is greater than or equal to COMPARE register
C. */
__IOM uint32_t COMPARED : 1; /*!< [3..3] COUNTER is greater than or equal to COMPARE register
D. */
__IOM uint32_t COMPAREE : 1; /*!< [4..4] COUNTER is greater than or equal to COMPARE register
E. */
__IOM uint32_t COMPAREF : 1; /*!< [5..5] COUNTER is greater than or equal to COMPARE register
F. */
__IOM uint32_t COMPAREG : 1; /*!< [6..6] COUNTER is greater than or equal to COMPARE register
G. */
__IOM uint32_t COMPAREH : 1; /*!< [7..7] COUNTER is greater than or equal to COMPARE register
H. */
__IOM uint32_t OVERFLOW : 1; /*!< [8..8] COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. */
__IOM uint32_t CAPTUREA : 1; /*!< [9..9] CAPTURE register A has grabbed the value in the counter */
__IOM uint32_t CAPTUREB : 1; /*!< [10..10] CAPTURE register B has grabbed the value in the counter */
__IOM uint32_t CAPTUREC : 1; /*!< [11..11] CAPTURE register C has grabbed the value in the counter */
__IOM uint32_t CAPTURED : 1; /*!< [12..12] CAPTURE register D has grabbed the value in the counter */
} STMINTEN_b;
} ;
union {
__IOM uint32_t STMINTSTAT; /*!< (@ 0x00000304) Read bits from this register to discover the
cause of a recent interrupt. */
struct {
__IOM uint32_t COMPAREA : 1; /*!< [0..0] COUNTER is greater than or equal to COMPARE register
A. */
__IOM uint32_t COMPAREB : 1; /*!< [1..1] COUNTER is greater than or equal to COMPARE register
B. */
__IOM uint32_t COMPAREC : 1; /*!< [2..2] COUNTER is greater than or equal to COMPARE register
C. */
__IOM uint32_t COMPARED : 1; /*!< [3..3] COUNTER is greater than or equal to COMPARE register
D. */
__IOM uint32_t COMPAREE : 1; /*!< [4..4] COUNTER is greater than or equal to COMPARE register
E. */
__IOM uint32_t COMPAREF : 1; /*!< [5..5] COUNTER is greater than or equal to COMPARE register
F. */
__IOM uint32_t COMPAREG : 1; /*!< [6..6] COUNTER is greater than or equal to COMPARE register
G. */
__IOM uint32_t COMPAREH : 1; /*!< [7..7] COUNTER is greater than or equal to COMPARE register
H. */
__IOM uint32_t OVERFLOW : 1; /*!< [8..8] COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. */
__IOM uint32_t CAPTUREA : 1; /*!< [9..9] CAPTURE register A has grabbed the value in the counter */
__IOM uint32_t CAPTUREB : 1; /*!< [10..10] CAPTURE register B has grabbed the value in the counter */
__IOM uint32_t CAPTUREC : 1; /*!< [11..11] CAPTURE register C has grabbed the value in the counter */
__IOM uint32_t CAPTURED : 1; /*!< [12..12] CAPTURE register D has grabbed the value in the counter */
} STMINTSTAT_b;
} ;
union {
__IOM uint32_t STMINTCLR; /*!< (@ 0x00000308) Write a 1 to a bit in this register to clear
the interrupt status associated with that
bit. */
struct {
__IOM uint32_t COMPAREA : 1; /*!< [0..0] COUNTER is greater than or equal to COMPARE register
A. */
__IOM uint32_t COMPAREB : 1; /*!< [1..1] COUNTER is greater than or equal to COMPARE register
B. */
__IOM uint32_t COMPAREC : 1; /*!< [2..2] COUNTER is greater than or equal to COMPARE register
C. */
__IOM uint32_t COMPARED : 1; /*!< [3..3] COUNTER is greater than or equal to COMPARE register
D. */
__IOM uint32_t COMPAREE : 1; /*!< [4..4] COUNTER is greater than or equal to COMPARE register
E. */
__IOM uint32_t COMPAREF : 1; /*!< [5..5] COUNTER is greater than or equal to COMPARE register
F. */
__IOM uint32_t COMPAREG : 1; /*!< [6..6] COUNTER is greater than or equal to COMPARE register
G. */
__IOM uint32_t COMPAREH : 1; /*!< [7..7] COUNTER is greater than or equal to COMPARE register
H. */
__IOM uint32_t OVERFLOW : 1; /*!< [8..8] COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. */
__IOM uint32_t CAPTUREA : 1; /*!< [9..9] CAPTURE register A has grabbed the value in the counter */
__IOM uint32_t CAPTUREB : 1; /*!< [10..10] CAPTURE register B has grabbed the value in the counter */
__IOM uint32_t CAPTUREC : 1; /*!< [11..11] CAPTURE register C has grabbed the value in the counter */
__IOM uint32_t CAPTURED : 1; /*!< [12..12] CAPTURE register D has grabbed the value in the counter */
} STMINTCLR_b;
} ;
union {
__IOM uint32_t STMINTSET; /*!< (@ 0x0000030C) Write a 1 to a bit in this register to instantly
generate an interrupt from this module.
(Generally used for testing purposes). */
struct {
__IOM uint32_t COMPAREA : 1; /*!< [0..0] COUNTER is greater than or equal to COMPARE register
A. */
__IOM uint32_t COMPAREB : 1; /*!< [1..1] COUNTER is greater than or equal to COMPARE register
B. */
__IOM uint32_t COMPAREC : 1; /*!< [2..2] COUNTER is greater than or equal to COMPARE register
C. */
__IOM uint32_t COMPARED : 1; /*!< [3..3] COUNTER is greater than or equal to COMPARE register
D. */
__IOM uint32_t COMPAREE : 1; /*!< [4..4] COUNTER is greater than or equal to COMPARE register
E. */
__IOM uint32_t COMPAREF : 1; /*!< [5..5] COUNTER is greater than or equal to COMPARE register
F. */
__IOM uint32_t COMPAREG : 1; /*!< [6..6] COUNTER is greater than or equal to COMPARE register
G. */
__IOM uint32_t COMPAREH : 1; /*!< [7..7] COUNTER is greater than or equal to COMPARE register
H. */
__IOM uint32_t OVERFLOW : 1; /*!< [8..8] COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. */
__IOM uint32_t CAPTUREA : 1; /*!< [9..9] CAPTURE register A has grabbed the value in the counter */
__IOM uint32_t CAPTUREB : 1; /*!< [10..10] CAPTURE register B has grabbed the value in the counter */
__IOM uint32_t CAPTUREC : 1; /*!< [11..11] CAPTURE register C has grabbed the value in the counter */
__IOM uint32_t CAPTURED : 1; /*!< [12..12] CAPTURE register D has grabbed the value in the counter */
} STMINTSET_b;
} ;
} CTIMER_Type; /*!< Size = 784 (0x310) */
/* =========================================================================================================================== */
/* ================ GPIO ================ */
/* =========================================================================================================================== */
/**
* @brief General Purpose IO (GPIO)
*/
typedef struct { /*!< (@ 0x40010000) GPIO Structure */
union {
__IOM uint32_t PADREGA; /*!< (@ 0x00000000) This register controls the pad configuration
controls for PAD3 through PAD0. Writes to
this register must be unlocked by the PADKEY
register. */
struct {
__IOM uint32_t PAD0PULL : 1; /*!< [0..0] Pad 0 pullup enable */
__IOM uint32_t PAD0INPEN : 1; /*!< [1..1] Pad 0 input enable */
__IOM uint32_t PAD0STRNG : 1; /*!< [2..2] Pad 0 drive strength */
__IOM uint32_t PAD0FNCSEL : 3; /*!< [5..3] Pad 0 function select */
__IOM uint32_t PAD0RSEL : 2; /*!< [7..6] Pad 0 pullup resistor selection. */
__IOM uint32_t PAD1PULL : 1; /*!< [8..8] Pad 1 pullup enable */
__IOM uint32_t PAD1INPEN : 1; /*!< [9..9] Pad 1 input enable */
__IOM uint32_t PAD1STRNG : 1; /*!< [10..10] Pad 1 drive strength */
__IOM uint32_t PAD1FNCSEL : 3; /*!< [13..11] Pad 1 function select */
__IOM uint32_t PAD1RSEL : 2; /*!< [15..14] Pad 1 pullup resistor selection. */
__IOM uint32_t PAD2PULL : 1; /*!< [16..16] Pad 2 pullup enable */
__IOM uint32_t PAD2INPEN : 1; /*!< [17..17] Pad 2 input enable */
__IOM uint32_t PAD2STRNG : 1; /*!< [18..18] Pad 2 drive strength */
__IOM uint32_t PAD2FNCSEL : 3; /*!< [21..19] Pad 2 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD3PULL : 1; /*!< [24..24] Pad 3 pullup enable */
__IOM uint32_t PAD3INPEN : 1; /*!< [25..25] Pad 3 input enable. */
__IOM uint32_t PAD3STRNG : 1; /*!< [26..26] Pad 3 drive strength. */
__IOM uint32_t PAD3FNCSEL : 3; /*!< [29..27] Pad 3 function select */
__IOM uint32_t PAD3PWRUP : 1; /*!< [30..30] Pad 3 VDD power switch enable */
} PADREGA_b;
} ;
union {
__IOM uint32_t PADREGB; /*!< (@ 0x00000004) This register controls the pad configuration
controls for PAD7 through PAD4. Writes to
this register must be unlocked by the PADKEY
register. */
struct {
__IOM uint32_t PAD4PULL : 1; /*!< [0..0] Pad 4 pullup enable */
__IOM uint32_t PAD4INPEN : 1; /*!< [1..1] Pad 4 input enable */
__IOM uint32_t PAD4STRNG : 1; /*!< [2..2] Pad 4 drive strength */
__IOM uint32_t PAD4FNCSEL : 3; /*!< [5..3] Pad 4 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD5PULL : 1; /*!< [8..8] Pad 5 pullup enable */
__IOM uint32_t PAD5INPEN : 1; /*!< [9..9] Pad 5 input enable */
__IOM uint32_t PAD5STRNG : 1; /*!< [10..10] Pad 5 drive strength */
__IOM uint32_t PAD5FNCSEL : 3; /*!< [13..11] Pad 5 function select */
__IOM uint32_t PAD5RSEL : 2; /*!< [15..14] Pad 5 pullup resistor selection. */
__IOM uint32_t PAD6PULL : 1; /*!< [16..16] Pad 6 pullup enable */
__IOM uint32_t PAD6INPEN : 1; /*!< [17..17] Pad 6 input enable */
__IOM uint32_t PAD6STRNG : 1; /*!< [18..18] Pad 6 drive strength */
__IOM uint32_t PAD6FNCSEL : 3; /*!< [21..19] Pad 6 function select */
__IOM uint32_t PAD6RSEL : 2; /*!< [23..22] Pad 6 pullup resistor selection. */
__IOM uint32_t PAD7PULL : 1; /*!< [24..24] Pad 7 pullup enable */
__IOM uint32_t PAD7INPEN : 1; /*!< [25..25] Pad 7 input enable */
__IOM uint32_t PAD7STRNG : 1; /*!< [26..26] Pad 7 drive strength */
__IOM uint32_t PAD7FNCSEL : 3; /*!< [29..27] Pad 7 function select */
} PADREGB_b;
} ;
union {
__IOM uint32_t PADREGC; /*!< (@ 0x00000008) This register controls the pad configuration
controls for PAD11 through PAD8. Writes
to this register must be unlocked by the
PADKEY register. */
struct {
__IOM uint32_t PAD8PULL : 1; /*!< [0..0] Pad 8 pullup enable */
__IOM uint32_t PAD8INPEN : 1; /*!< [1..1] Pad 8 input enable */
__IOM uint32_t PAD8STRNG : 1; /*!< [2..2] Pad 8 drive strength */
__IOM uint32_t PAD8FNCSEL : 3; /*!< [5..3] Pad 8 function select */
__IOM uint32_t PAD8RSEL : 2; /*!< [7..6] Pad 8 pullup resistor selection. */
__IOM uint32_t PAD9PULL : 1; /*!< [8..8] Pad 9 pullup enable */
__IOM uint32_t PAD9INPEN : 1; /*!< [9..9] Pad 9 input enable */
__IOM uint32_t PAD9STRNG : 1; /*!< [10..10] Pad 9 drive strength */
__IOM uint32_t PAD9FNCSEL : 3; /*!< [13..11] Pad 9 function select */
__IOM uint32_t PAD9RSEL : 2; /*!< [15..14] Pad 9 pullup resistor selection */
__IOM uint32_t PAD10PULL : 1; /*!< [16..16] Pad 10 pullup enable */
__IOM uint32_t PAD10INPEN : 1; /*!< [17..17] Pad 10 input enable */
__IOM uint32_t PAD10STRNG : 1; /*!< [18..18] Pad 10 drive strength */
__IOM uint32_t PAD10FNCSEL : 3; /*!< [21..19] Pad 10 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD11PULL : 1; /*!< [24..24] Pad 11 pullup enable */
__IOM uint32_t PAD11INPEN : 1; /*!< [25..25] Pad 11 input enable */
__IOM uint32_t PAD11STRNG : 1; /*!< [26..26] Pad 11 drive strength */
__IOM uint32_t PAD11FNCSEL : 3; /*!< [29..27] Pad 11 function select */
} PADREGC_b;
} ;
union {
__IOM uint32_t PADREGD; /*!< (@ 0x0000000C) This register controls the pad configuration
controls for PAD15 through PAD12. Writes
to this register must be unlocked by the
PADKEY register. */
struct {
__IOM uint32_t PAD12PULL : 1; /*!< [0..0] Pad 12 pullup enable */
__IOM uint32_t PAD12INPEN : 1; /*!< [1..1] Pad 12 input enable */
__IOM uint32_t PAD12STRNG : 1; /*!< [2..2] Pad 12 drive strength */
__IOM uint32_t PAD12FNCSEL : 3; /*!< [5..3] Pad 12 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD13PULL : 1; /*!< [8..8] Pad 13 pullup enable */
__IOM uint32_t PAD13INPEN : 1; /*!< [9..9] Pad 13 input enable */
__IOM uint32_t PAD13STRNG : 1; /*!< [10..10] Pad 13 drive strength */
__IOM uint32_t PAD13FNCSEL : 3; /*!< [13..11] Pad 13 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD14PULL : 1; /*!< [16..16] Pad 14 pullup enable */
__IOM uint32_t PAD14INPEN : 1; /*!< [17..17] Pad 14 input enable */
__IOM uint32_t PAD14STRNG : 1; /*!< [18..18] Pad 14 drive strength */
__IOM uint32_t PAD14FNCSEL : 3; /*!< [21..19] Pad 14 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD15PULL : 1; /*!< [24..24] Pad 15 pullup enable */
__IOM uint32_t PAD15INPEN : 1; /*!< [25..25] Pad 15 input enable */
__IOM uint32_t PAD15STRNG : 1; /*!< [26..26] Pad 15 drive strength */
__IOM uint32_t PAD15FNCSEL : 3; /*!< [29..27] Pad 15 function select */
} PADREGD_b;
} ;
union {
__IOM uint32_t PADREGE; /*!< (@ 0x00000010) This register controls the pad configuration
controls for PAD19 through PAD16. Writes
to this register must be unlocked by the
PADKEY register. */
struct {
__IOM uint32_t PAD16PULL : 1; /*!< [0..0] Pad 16 pullup enable */
__IOM uint32_t PAD16INPEN : 1; /*!< [1..1] Pad 16 input enable */
__IOM uint32_t PAD16STRNG : 1; /*!< [2..2] Pad 16 drive strength */
__IOM uint32_t PAD16FNCSEL : 3; /*!< [5..3] Pad 16 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD17PULL : 1; /*!< [8..8] Pad 17 pullup enable */
__IOM uint32_t PAD17INPEN : 1; /*!< [9..9] Pad 17 input enable */
__IOM uint32_t PAD17STRNG : 1; /*!< [10..10] Pad 17 drive strength */
__IOM uint32_t PAD17FNCSEL : 3; /*!< [13..11] Pad 17 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD18PULL : 1; /*!< [16..16] Pad 18 pullup enable */
__IOM uint32_t PAD18INPEN : 1; /*!< [17..17] Pad 18 input enable */
__IOM uint32_t PAD18STRNG : 1; /*!< [18..18] Pad 18 drive strength */
__IOM uint32_t PAD18FNCSEL : 3; /*!< [21..19] Pad 18 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD19PULL : 1; /*!< [24..24] Pad 19 pullup enable */
__IOM uint32_t PAD19INPEN : 1; /*!< [25..25] Pad 19 input enable */
__IOM uint32_t PAD19STRNG : 1; /*!< [26..26] Pad 19 drive strength */
__IOM uint32_t PAD19FNCSEL : 3; /*!< [29..27] Pad 19 function select */
} PADREGE_b;
} ;
union {
__IOM uint32_t PADREGF; /*!< (@ 0x00000014) This register controls the pad configuration
controls for PAD23 through PAD20. Writes
to this register must be unlocked by the
PADKEY register. */
struct {
__IOM uint32_t PAD20PULL : 1; /*!< [0..0] Pad 20 pulldown enable */
__IOM uint32_t PAD20INPEN : 1; /*!< [1..1] Pad 20 input enable */
__IOM uint32_t PAD20STRNG : 1; /*!< [2..2] Pad 20 drive strength */
__IOM uint32_t PAD20FNCSEL : 3; /*!< [5..3] Pad 20 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD21PULL : 1; /*!< [8..8] Pad 21 pullup enable */
__IOM uint32_t PAD21INPEN : 1; /*!< [9..9] Pad 21 input enable */
__IOM uint32_t PAD21STRNG : 1; /*!< [10..10] Pad 21 drive strength */
__IOM uint32_t PAD21FNCSEL : 3; /*!< [13..11] Pad 21 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD22PULL : 1; /*!< [16..16] Pad 22 pullup enable */
__IOM uint32_t PAD22INPEN : 1; /*!< [17..17] Pad 22 input enable */
__IOM uint32_t PAD22STRNG : 1; /*!< [18..18] Pad 22 drive strength */
__IOM uint32_t PAD22FNCSEL : 3; /*!< [21..19] Pad 22 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD23PULL : 1; /*!< [24..24] Pad 23 pullup enable */
__IOM uint32_t PAD23INPEN : 1; /*!< [25..25] Pad 23 input enable */
__IOM uint32_t PAD23STRNG : 1; /*!< [26..26] Pad 23 drive strength */
__IOM uint32_t PAD23FNCSEL : 3; /*!< [29..27] Pad 23 function select */
} PADREGF_b;
} ;
union {
__IOM uint32_t PADREGG; /*!< (@ 0x00000018) This register controls the pad configuration
controls for PAD27 through PAD24. Writes
to this register must be unlocked by the
PADKEY register. */
struct {
__IOM uint32_t PAD24PULL : 1; /*!< [0..0] Pad 24 pullup enable */
__IOM uint32_t PAD24INPEN : 1; /*!< [1..1] Pad 24 input enable */
__IOM uint32_t PAD24STRNG : 1; /*!< [2..2] Pad 24 drive strength */
__IOM uint32_t PAD24FNCSEL : 3; /*!< [5..3] Pad 24 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD25PULL : 1; /*!< [8..8] Pad 25 pullup enable */
__IOM uint32_t PAD25INPEN : 1; /*!< [9..9] Pad 25 input enable */
__IOM uint32_t PAD25STRNG : 1; /*!< [10..10] Pad 25 drive strength */
__IOM uint32_t PAD25FNCSEL : 3; /*!< [13..11] Pad 25 function select */
__IOM uint32_t PAD25RSEL : 2; /*!< [15..14] Pad 25 pullup resistor selection. */
__IOM uint32_t PAD26PULL : 1; /*!< [16..16] Pad 26 pullup enable */
__IOM uint32_t PAD26INPEN : 1; /*!< [17..17] Pad 26 input enable */
__IOM uint32_t PAD26STRNG : 1; /*!< [18..18] Pad 26 drive strength */
__IOM uint32_t PAD26FNCSEL : 3; /*!< [21..19] Pad 26 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD27PULL : 1; /*!< [24..24] Pad 27 pullup enable */
__IOM uint32_t PAD27INPEN : 1; /*!< [25..25] Pad 27 input enable */
__IOM uint32_t PAD27STRNG : 1; /*!< [26..26] Pad 27 drive strength */
__IOM uint32_t PAD27FNCSEL : 3; /*!< [29..27] Pad 27 function select */
__IOM uint32_t PAD27RSEL : 2; /*!< [31..30] Pad 27 pullup resistor selection. */
} PADREGG_b;
} ;
union {
__IOM uint32_t PADREGH; /*!< (@ 0x0000001C) This register controls the pad configuration
controls for PAD31 through PAD28. Writes
to this register must be unlocked by the
PADKEY register. */
struct {
__IOM uint32_t PAD28PULL : 1; /*!< [0..0] Pad 28 pullup enable */
__IOM uint32_t PAD28INPEN : 1; /*!< [1..1] Pad 28 input enable */
__IOM uint32_t PAD28STRNG : 1; /*!< [2..2] Pad 28 drive strength */
__IOM uint32_t PAD28FNCSEL : 3; /*!< [5..3] Pad 28 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD29PULL : 1; /*!< [8..8] Pad 29 pullup enable */
__IOM uint32_t PAD29INPEN : 1; /*!< [9..9] Pad 29 input enable */
__IOM uint32_t PAD29STRNG : 1; /*!< [10..10] Pad 29 drive strength */
__IOM uint32_t PAD29FNCSEL : 3; /*!< [13..11] Pad 29 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD30PULL : 1; /*!< [16..16] Pad 30 pullup enable */
__IOM uint32_t PAD30INPEN : 1; /*!< [17..17] Pad 30 input enable */
__IOM uint32_t PAD30STRNG : 1; /*!< [18..18] Pad 30 drive strength */
__IOM uint32_t PAD30FNCSEL : 3; /*!< [21..19] Pad 30 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD31PULL : 1; /*!< [24..24] Pad 31 pullup enable */
__IOM uint32_t PAD31INPEN : 1; /*!< [25..25] Pad 31 input enable */
__IOM uint32_t PAD31STRNG : 1; /*!< [26..26] Pad 31 drive strength */
__IOM uint32_t PAD31FNCSEL : 3; /*!< [29..27] Pad 31 function select */
} PADREGH_b;
} ;
union {
__IOM uint32_t PADREGI; /*!< (@ 0x00000020) This register controls the pad configuration
controls for PAD35 through PAD32. Writes
to this register must be unlocked by the
PADKEY register. */
struct {
__IOM uint32_t PAD32PULL : 1; /*!< [0..0] Pad 32 pullup enable */
__IOM uint32_t PAD32INPEN : 1; /*!< [1..1] Pad 32 input enable */
__IOM uint32_t PAD32STRNG : 1; /*!< [2..2] Pad 32 drive strength */
__IOM uint32_t PAD32FNCSEL : 3; /*!< [5..3] Pad 32 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD33PULL : 1; /*!< [8..8] Pad 33 pullup enable */
__IOM uint32_t PAD33INPEN : 1; /*!< [9..9] Pad 33 input enable */
__IOM uint32_t PAD33STRNG : 1; /*!< [10..10] Pad 33 drive strength */
__IOM uint32_t PAD33FNCSEL : 3; /*!< [13..11] Pad 33 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD34PULL : 1; /*!< [16..16] Pad 34 pullup enable */
__IOM uint32_t PAD34INPEN : 1; /*!< [17..17] Pad 34 input enable */
__IOM uint32_t PAD34STRNG : 1; /*!< [18..18] Pad 34 drive strength */
__IOM uint32_t PAD34FNCSEL : 3; /*!< [21..19] Pad 34 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD35PULL : 1; /*!< [24..24] Pad 35 pullup enable */
__IOM uint32_t PAD35INPEN : 1; /*!< [25..25] Pad 35 input enable */
__IOM uint32_t PAD35STRNG : 1; /*!< [26..26] Pad 35 drive strength */
__IOM uint32_t PAD35FNCSEL : 3; /*!< [29..27] Pad 35 function select */
} PADREGI_b;
} ;
union {
__IOM uint32_t PADREGJ; /*!< (@ 0x00000024) This register controls the pad configuration
controls for PAD39 through PAD36. Writes
to this register must be unlocked by the
PADKEY register. */
struct {
__IOM uint32_t PAD36PULL : 1; /*!< [0..0] Pad 36 pullup enable */
__IOM uint32_t PAD36INPEN : 1; /*!< [1..1] Pad 36 input enable */
__IOM uint32_t PAD36STRNG : 1; /*!< [2..2] Pad 36 drive strength */
__IOM uint32_t PAD36FNCSEL : 3; /*!< [5..3] Pad 36 function select */
__IOM uint32_t PAD36PWRUP : 1; /*!< [6..6] Pad 36 VDD power switch enable */
__IM uint32_t : 1;
__IOM uint32_t PAD37PULL : 1; /*!< [8..8] Pad 37 pullup enable */
__IOM uint32_t PAD37INPEN : 1; /*!< [9..9] Pad 37 input enable */
__IOM uint32_t PAD37STRNG : 1; /*!< [10..10] Pad 37 drive strength */
__IOM uint32_t PAD37FNCSEL : 3; /*!< [13..11] Pad 37 function select */
__IM uint32_t : 1;
__IOM uint32_t PAD37PWRDN : 1; /*!< [15..15] Pad 37 VSS power switch enable */
__IOM uint32_t PAD38PULL : 1; /*!< [16..16] Pad 38 pullup enable */
__IOM uint32_t PAD38INPEN : 1; /*!< [17..17] Pad 38 input enable */
__IOM uint32_t PAD38STRNG : 1; /*!< [18..18] Pad 38 drive strength */
__IOM uint32_t PAD38FNCSEL : 3; /*!< [21..19] Pad 38 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD39PULL : 1; /*!< [24..24] Pad 39 pullup enable */
__IOM uint32_t PAD39INPEN : 1; /*!< [25..25] Pad 39 input enable */
__IOM uint32_t PAD39STRNG : 1; /*!< [26..26] Pad 39 drive strength */
__IOM uint32_t PAD39FNCSEL : 3; /*!< [29..27] Pad 39 function select */
__IOM uint32_t PAD39RSEL : 2; /*!< [31..30] Pad 39 pullup resistor selection. */
} PADREGJ_b;
} ;
union {
__IOM uint32_t PADREGK; /*!< (@ 0x00000028) This register controls the pad configuration
controls for PAD43 through PAD40. Writes
to this register must be unlocked by the
PADKEY register. */
struct {
__IOM uint32_t PAD40PULL : 1; /*!< [0..0] Pad 40 pullup enable */
__IOM uint32_t PAD40INPEN : 1; /*!< [1..1] Pad 40 input enable */
__IOM uint32_t PAD40STRNG : 1; /*!< [2..2] Pad 40 drive strength */
__IOM uint32_t PAD40FNCSEL : 3; /*!< [5..3] Pad 40 function select */
__IOM uint32_t PAD40RSEL : 2; /*!< [7..6] Pad 40 pullup resistor selection. */
__IOM uint32_t PAD41PULL : 1; /*!< [8..8] Pad 41 pullup enable */
__IOM uint32_t PAD41INPEN : 1; /*!< [9..9] Pad 41 input enable */
__IOM uint32_t PAD41STRNG : 1; /*!< [10..10] Pad 41 drive strength */
__IOM uint32_t PAD41FNCSEL : 3; /*!< [13..11] Pad 41 function select */
__IM uint32_t : 1;
__IOM uint32_t PAD41PWRDN : 1; /*!< [15..15] Pad 41 power switch enable */
__IOM uint32_t PAD42PULL : 1; /*!< [16..16] Pad 42 pullup enable */
__IOM uint32_t PAD42INPEN : 1; /*!< [17..17] Pad 42 input enable */
__IOM uint32_t PAD42STRNG : 1; /*!< [18..18] Pad 42 drive strength */
__IOM uint32_t PAD42FNCSEL : 3; /*!< [21..19] Pad 42 function select */
__IOM uint32_t PAD42RSEL : 2; /*!< [23..22] Pad 42 pullup resistor selection. */
__IOM uint32_t PAD43PULL : 1; /*!< [24..24] Pad 43 pullup enable */
__IOM uint32_t PAD43INPEN : 1; /*!< [25..25] Pad 43 input enable */
__IOM uint32_t PAD43STRNG : 1; /*!< [26..26] Pad 43 drive strength */
__IOM uint32_t PAD43FNCSEL : 3; /*!< [29..27] Pad 43 function select */
__IOM uint32_t PAD43RSEL : 2; /*!< [31..30] Pad 43 pullup resistor selection. */
} PADREGK_b;
} ;
union {
__IOM uint32_t PADREGL; /*!< (@ 0x0000002C) This register controls the pad configuration
controls for PAD47 through PAD44. Writes
to this register must be unlocked by the
PADKEY register. */
struct {
__IOM uint32_t PAD44PULL : 1; /*!< [0..0] Pad 44 pullup enable */
__IOM uint32_t PAD44INPEN : 1; /*!< [1..1] Pad 44 input enable */
__IOM uint32_t PAD44STRNG : 1; /*!< [2..2] Pad 44 drive strength */
__IOM uint32_t PAD44FNCSEL : 3; /*!< [5..3] Pad 44 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD45PULL : 1; /*!< [8..8] Pad 45 pullup enable */
__IOM uint32_t PAD45INPEN : 1; /*!< [9..9] Pad 45 input enable */
__IOM uint32_t PAD45STRNG : 1; /*!< [10..10] Pad 45 drive strength */
__IOM uint32_t PAD45FNCSEL : 3; /*!< [13..11] Pad 45 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD46PULL : 1; /*!< [16..16] Pad 46 pullup enable */
__IOM uint32_t PAD46INPEN : 1; /*!< [17..17] Pad 46 input enable */
__IOM uint32_t PAD46STRNG : 1; /*!< [18..18] Pad 46 drive strength */
__IOM uint32_t PAD46FNCSEL : 3; /*!< [21..19] Pad 46 function select */
__IM uint32_t : 2;
__IOM uint32_t PAD47PULL : 1; /*!< [24..24] Pad 47 pullup enable */
__IOM uint32_t PAD47INPEN : 1; /*!< [25..25] Pad 47 input enable */
__IOM uint32_t PAD47STRNG : 1; /*!< [26..26] Pad 47 drive strength */
__IOM uint32_t PAD47FNCSEL : 3; /*!< [29..27] Pad 47 function select */
} PADREGL_b;
} ;
union {
__IOM uint32_t PADREGM; /*!< (@ 0x00000030) This register controls the pad configuration
controls for PAD49 through PAD48. Writes
to this register must be unlocked by the
PADKEY register. */
struct {
__IOM uint32_t PAD48PULL : 1; /*!< [0..0] Pad 48 pullup enable */
__IOM uint32_t PAD48INPEN : 1; /*!< [1..1] Pad 48 input enable */
__IOM uint32_t PAD48STRNG : 1; /*!< [2..2] Pad 48 drive strength */
__IOM uint32_t PAD48FNCSEL : 3; /*!< [5..3] Pad 48 function select */
__IOM uint32_t PAD48RSEL : 2; /*!< [7..6] Pad 48 pullup resistor selection. */
__IOM uint32_t PAD49PULL : 1; /*!< [8..8] Pad 49 pullup enable */
__IOM uint32_t PAD49INPEN : 1; /*!< [9..9] Pad 49 input enable */
__IOM uint32_t PAD49STRNG : 1; /*!< [10..10] Pad 49 drive strength */
__IOM uint32_t PAD49FNCSEL : 3; /*!< [13..11] Pad 49 function select */
__IOM uint32_t PAD49RSEL : 2; /*!< [15..14] Pad 49 pullup resistor selection. */
} PADREGM_b;
} ;
__IM uint32_t RESERVED[3];
union {
__IOM uint32_t CFGA; /*!< (@ 0x00000040) GPIO configuration controls for GPIO[7:0]. Writes
to this register must be unlocked by the
PADKEY register. */
struct {
__IOM uint32_t GPIO0INCFG : 1; /*!< [0..0] GPIO0 input enable. */
__IOM uint32_t GPIO0OUTCFG : 2; /*!< [2..1] GPIO0 output configuration. */
__IOM uint32_t GPIO0INTD : 1; /*!< [3..3] GPIO0 interrupt direction. */
__IOM uint32_t GPIO1INCFG : 1; /*!< [4..4] GPIO1 input enable. */
__IOM uint32_t GPIO1OUTCFG : 2; /*!< [6..5] GPIO1 output configuration. */
__IOM uint32_t GPIO1INTD : 1; /*!< [7..7] GPIO1 interrupt direction. */
__IOM uint32_t GPIO2INCFG : 1; /*!< [8..8] GPIO2 input enable. */
__IOM uint32_t GPIO2OUTCFG : 2; /*!< [10..9] GPIO2 output configuration. */
__IOM uint32_t GPIO2INTD : 1; /*!< [11..11] GPIO2 interrupt direction. */
__IOM uint32_t GPIO3INCFG : 1; /*!< [12..12] GPIO3 input enable. */
__IOM uint32_t GPIO3OUTCFG : 2; /*!< [14..13] GPIO3 output configuration. */
__IOM uint32_t GPIO3INTD : 1; /*!< [15..15] GPIO3 interrupt direction. */
__IOM uint32_t GPIO4INCFG : 1; /*!< [16..16] GPIO4 input enable. */
__IOM uint32_t GPIO4OUTCFG : 2; /*!< [18..17] GPIO4 output configuration. */
__IOM uint32_t GPIO4INTD : 1; /*!< [19..19] GPIO4 interrupt direction. */
__IOM uint32_t GPIO5INCFG : 1; /*!< [20..20] GPIO5 input enable. */
__IOM uint32_t GPIO5OUTCFG : 2; /*!< [22..21] GPIO5 output configuration. */
__IOM uint32_t GPIO5INTD : 1; /*!< [23..23] GPIO5 interrupt direction. */
__IOM uint32_t GPIO6INCFG : 1; /*!< [24..24] GPIO6 input enable. */
__IOM uint32_t GPIO6OUTCFG : 2; /*!< [26..25] GPIO6 output configuration. */
__IOM uint32_t GPIO6INTD : 1; /*!< [27..27] GPIO6 interrupt direction. */
__IOM uint32_t GPIO7INCFG : 1; /*!< [28..28] GPIO7 input enable. */
__IOM uint32_t GPIO7OUTCFG : 2; /*!< [30..29] GPIO7 output configuration. */
__IOM uint32_t GPIO7INTD : 1; /*!< [31..31] GPIO7 interrupt direction, nCE polarity. */
} CFGA_b;
} ;
union {
__IOM uint32_t CFGB; /*!< (@ 0x00000044) GPIO configuration controls for GPIO[15:8]. Writes
to this register must be unlocked by the
PADKEY register. */
struct {
__IOM uint32_t GPIO8INCFG : 1; /*!< [0..0] GPIO8 input enable. */
__IOM uint32_t GPIO8OUTCFG : 2; /*!< [2..1] GPIO8 output configuration. */
__IOM uint32_t GPIO8INTD : 1; /*!< [3..3] GPIO8 interrupt direction. */
__IOM uint32_t GPIO9INCFG : 1; /*!< [4..4] GPIO9 input enable. */
__IOM uint32_t GPIO9OUTCFG : 2; /*!< [6..5] GPIO9 output configuration. */
__IOM uint32_t GPIO9INTD : 1; /*!< [7..7] GPIO9 interrupt direction. */
__IOM uint32_t GPIO10INCFG : 1; /*!< [8..8] GPIO10 input enable. */
__IOM uint32_t GPIO10OUTCFG : 2; /*!< [10..9] GPIO10 output configuration. */
__IOM uint32_t GPIO10INTD : 1; /*!< [11..11] GPIO10 interrupt direction. */
__IOM uint32_t GPIO11INCFG : 1; /*!< [12..12] GPIO11 input enable. */
__IOM uint32_t GPIO11OUTCFG : 2; /*!< [14..13] GPIO11 output configuration. */
__IOM uint32_t GPIO11INTD : 1; /*!< [15..15] GPIO11 interrupt direction. */
__IOM uint32_t GPIO12INCFG : 1; /*!< [16..16] GPIO12 input enable. */
__IOM uint32_t GPIO12OUTCFG : 2; /*!< [18..17] GPIO12 output configuration. */
__IOM uint32_t GPIO12INTD : 1; /*!< [19..19] GPIO12 interrupt direction. */
__IOM uint32_t GPIO13INCFG : 1; /*!< [20..20] GPIO13 input enable. */
__IOM uint32_t GPIO13OUTCFG : 2; /*!< [22..21] GPIO13 output configuration. */
__IOM uint32_t GPIO13INTD : 1; /*!< [23..23] GPIO13 interrupt direction. */
__IOM uint32_t GPIO14INCFG : 1; /*!< [24..24] GPIO14 input enable. */
__IOM uint32_t GPIO14OUTCFG : 2; /*!< [26..25] GPIO14 output configuration. */
__IOM uint32_t GPIO14INTD : 1; /*!< [27..27] GPIO14 interrupt direction. */
__IOM uint32_t GPIO15INCFG : 1; /*!< [28..28] GPIO15 input enable. */
__IOM uint32_t GPIO15OUTCFG : 2; /*!< [30..29] GPIO15 output configuration. */
__IOM uint32_t GPIO15INTD : 1; /*!< [31..31] GPIO15 interrupt direction. */
} CFGB_b;
} ;
union {
__IOM uint32_t CFGC; /*!< (@ 0x00000048) GPIO configuration controls for GPIO[23:16].
Writes to this register must be unlocked
by the PADKEY register. */
struct {
__IOM uint32_t GPIO16INCFG : 1; /*!< [0..0] GPIO16 input enable. */
__IOM uint32_t GPIO16OUTCFG : 2; /*!< [2..1] GPIO16 output configuration. */
__IOM uint32_t GPIO16INTD : 1; /*!< [3..3] GPIO16 interrupt direction. */
__IOM uint32_t GPIO17INCFG : 1; /*!< [4..4] GPIO17 input enable. */
__IOM uint32_t GPIO17OUTCFG : 2; /*!< [6..5] GPIO17 output configuration. */
__IOM uint32_t GPIO17INTD : 1; /*!< [7..7] GPIO17 interrupt direction. */
__IOM uint32_t GPIO18INCFG : 1; /*!< [8..8] GPIO18 input enable. */
__IOM uint32_t GPIO18OUTCFG : 2; /*!< [10..9] GPIO18 output configuration. */
__IOM uint32_t GPIO18INTD : 1; /*!< [11..11] GPIO18 interrupt direction. */
__IOM uint32_t GPIO19INCFG : 1; /*!< [12..12] GPIO19 input enable. */
__IOM uint32_t GPIO19OUTCFG : 2; /*!< [14..13] GPIO19 output configuration. */
__IOM uint32_t GPIO19INTD : 1; /*!< [15..15] GPIO19 interrupt direction. */
__IOM uint32_t GPIO20INCFG : 1; /*!< [16..16] GPIO20 input enable. */
__IOM uint32_t GPIO20OUTCFG : 2; /*!< [18..17] GPIO20 output configuration. */
__IOM uint32_t GPIO20INTD : 1; /*!< [19..19] GPIO20 interrupt direction. */
__IOM uint32_t GPIO21INCFG : 1; /*!< [20..20] GPIO21 input enable. */
__IOM uint32_t GPIO21OUTCFG : 2; /*!< [22..21] GPIO21 output configuration. */
__IOM uint32_t GPIO21INTD : 1; /*!< [23..23] GPIO21 interrupt direction. */
__IOM uint32_t GPIO22INCFG : 1; /*!< [24..24] GPIO22 input enable. */
__IOM uint32_t GPIO22OUTCFG : 2; /*!< [26..25] GPIO22 output configuration. */
__IOM uint32_t GPIO22INTD : 1; /*!< [27..27] GPIO22 interrupt direction. */
__IOM uint32_t GPIO23INCFG : 1; /*!< [28..28] GPIO23 input enable. */
__IOM uint32_t GPIO23OUTCFG : 2; /*!< [30..29] GPIO23 output configuration. */
__IOM uint32_t GPIO23INTD : 1; /*!< [31..31] GPIO23 interrupt direction. */
} CFGC_b;
} ;
union {
__IOM uint32_t CFGD; /*!< (@ 0x0000004C) GPIO configuration controls for GPIO[31:24].
Writes to this register must be unlocked
by the PADKEY register. */
struct {
__IOM uint32_t GPIO24INCFG : 1; /*!< [0..0] GPIO24 input enable. */
__IOM uint32_t GPIO24OUTCFG : 2; /*!< [2..1] GPIO24 output configuration. */
__IOM uint32_t GPIO24INTD : 1; /*!< [3..3] GPIO24 interrupt direction. */
__IOM uint32_t GPIO25INCFG : 1; /*!< [4..4] GPIO25 input enable. */
__IOM uint32_t GPIO25OUTCFG : 2; /*!< [6..5] GPIO25 output configuration. */
__IOM uint32_t GPIO25INTD : 1; /*!< [7..7] GPIO25 interrupt direction. */
__IOM uint32_t GPIO26INCFG : 1; /*!< [8..8] GPIO26 input enable. */
__IOM uint32_t GPIO26OUTCFG : 2; /*!< [10..9] GPIO26 output configuration. */
__IOM uint32_t GPIO26INTD : 1; /*!< [11..11] GPIO26 interrupt direction. */
__IOM uint32_t GPIO27INCFG : 1; /*!< [12..12] GPIO27 input enable. */
__IOM uint32_t GPIO27OUTCFG : 2; /*!< [14..13] GPIO27 output configuration. */
__IOM uint32_t GPIO27INTD : 1; /*!< [15..15] GPIO27 interrupt direction. */
__IOM uint32_t GPIO28INCFG : 1; /*!< [16..16] GPIO28 input enable. */
__IOM uint32_t GPIO28OUTCFG : 2; /*!< [18..17] GPIO28 output configuration. */
__IOM uint32_t GPIO28INTD : 1; /*!< [19..19] GPIO28 interrupt direction. */
__IOM uint32_t GPIO29INCFG : 1; /*!< [20..20] GPIO29 input enable. */
__IOM uint32_t GPIO29OUTCFG : 2; /*!< [22..21] GPIO29 output configuration. */
__IOM uint32_t GPIO29INTD : 1; /*!< [23..23] GPIO29 interrupt direction. */
__IOM uint32_t GPIO30INCFG : 1; /*!< [24..24] GPIO30 input enable. */
__IOM uint32_t GPIO30OUTCFG : 2; /*!< [26..25] GPIO30 output configuration. */
__IOM uint32_t GPIO30INTD : 1; /*!< [27..27] GPIO30 interrupt direction. */
__IOM uint32_t GPIO31INCFG : 1; /*!< [28..28] GPIO31 input enable. */
__IOM uint32_t GPIO31OUTCFG : 2; /*!< [30..29] GPIO31 output configuration. */
__IOM uint32_t GPIO31INTD : 1; /*!< [31..31] GPIO31 interrupt direction. */
} CFGD_b;
} ;
union {
__IOM uint32_t CFGE; /*!< (@ 0x00000050) GPIO configuration controls for GPIO[39:32].
Writes to this register must be unlocked
by the PADKEY register. */
struct {
__IOM uint32_t GPIO32INCFG : 1; /*!< [0..0] GPIO32 input enable. */
__IOM uint32_t GPIO32OUTCFG : 2; /*!< [2..1] GPIO32 output configuration. */
__IOM uint32_t GPIO32INTD : 1; /*!< [3..3] GPIO32 interrupt direction. */
__IOM uint32_t GPIO33INCFG : 1; /*!< [4..4] GPIO33 input enable. */
__IOM uint32_t GPIO33OUTCFG : 2; /*!< [6..5] GPIO33 output configuration. */
__IOM uint32_t GPIO33INTD : 1; /*!< [7..7] GPIO33 interrupt direction. */
__IOM uint32_t GPIO34INCFG : 1; /*!< [8..8] GPIO34 input enable. */
__IOM uint32_t GPIO34OUTCFG : 2; /*!< [10..9] GPIO34 output configuration. */
__IOM uint32_t GPIO34INTD : 1; /*!< [11..11] GPIO34 interrupt direction. */
__IOM uint32_t GPIO35INCFG : 1; /*!< [12..12] GPIO35 input enable. */
__IOM uint32_t GPIO35OUTCFG : 2; /*!< [14..13] GPIO35 output configuration. */
__IOM uint32_t GPIO35INTD : 1; /*!< [15..15] GPIO35 interrupt direction. */
__IOM uint32_t GPIO36INCFG : 1; /*!< [16..16] GPIO36 input enable. */
__IOM uint32_t GPIO36OUTCFG : 2; /*!< [18..17] GPIO36 output configuration. */
__IOM uint32_t GPIO36INTD : 1; /*!< [19..19] GPIO36 interrupt direction. */
__IOM uint32_t GPIO37INCFG : 1; /*!< [20..20] GPIO37 input enable. */
__IOM uint32_t GPIO37OUTCFG : 2; /*!< [22..21] GPIO37 output configuration. */
__IOM uint32_t GPIO37INTD : 1; /*!< [23..23] GPIO37 interrupt direction. */
__IOM uint32_t GPIO38INCFG : 1; /*!< [24..24] GPIO38 input enable. */
__IOM uint32_t GPIO38OUTCFG : 2; /*!< [26..25] GPIO38 output configuration. */
__IOM uint32_t GPIO38INTD : 1; /*!< [27..27] GPIO38 interrupt direction. */
__IOM uint32_t GPIO39INCFG : 1; /*!< [28..28] GPIO39 input enable. */
__IOM uint32_t GPIO39OUTCFG : 2; /*!< [30..29] GPIO39 output configuration. */
__IOM uint32_t GPIO39INTD : 1; /*!< [31..31] GPIO39 interrupt direction. */
} CFGE_b;
} ;
union {
__IOM uint32_t CFGF; /*!< (@ 0x00000054) GPIO configuration controls for GPIO[47:40].
Writes to this register must be unlocked
by the PADKEY register. */
struct {
__IOM uint32_t GPIO40INCFG : 1; /*!< [0..0] GPIO40 input enable. */
__IOM uint32_t GPIO40OUTCFG : 2; /*!< [2..1] GPIO40 output configuration. */
__IOM uint32_t GPIO40INTD : 1; /*!< [3..3] GPIO40 interrupt direction. */
__IOM uint32_t GPIO41INCFG : 1; /*!< [4..4] GPIO41 input enable. */
__IOM uint32_t GPIO41OUTCFG : 2; /*!< [6..5] GPIO41 output configuration. */
__IOM uint32_t GPIO41INTD : 1; /*!< [7..7] GPIO41 interrupt direction. */
__IOM uint32_t GPIO42INCFG : 1; /*!< [8..8] GPIO42 input enable. */
__IOM uint32_t GPIO42OUTCFG : 2; /*!< [10..9] GPIO42 output configuration. */
__IOM uint32_t GPIO42INTD : 1; /*!< [11..11] GPIO42 interrupt direction. */
__IOM uint32_t GPIO43INCFG : 1; /*!< [12..12] GPIO43 input enable. */
__IOM uint32_t GPIO43OUTCFG : 2; /*!< [14..13] GPIO43 output configuration. */
__IOM uint32_t GPIO43INTD : 1; /*!< [15..15] GPIO43 interrupt direction. */
__IOM uint32_t GPIO44INCFG : 1; /*!< [16..16] GPIO44 input enable. */
__IOM uint32_t GPIO44OUTCFG : 2; /*!< [18..17] GPIO44 output configuration. */
__IOM uint32_t GPIO44INTD : 1; /*!< [19..19] GPIO44 interrupt direction. */
__IOM uint32_t GPIO45INCFG : 1; /*!< [20..20] GPIO45 input enable. */
__IOM uint32_t GPIO45OUTCFG : 2; /*!< [22..21] GPIO45 output configuration. */
__IOM uint32_t GPIO45INTD : 1; /*!< [23..23] GPIO45 interrupt direction. */
__IOM uint32_t GPIO46INCFG : 1; /*!< [24..24] GPIO46 input enable. */
__IOM uint32_t GPIO46OUTCFG : 2; /*!< [26..25] GPIO46 output configuration. */
__IOM uint32_t GPIO46INTD : 1; /*!< [27..27] GPIO46 interrupt direction. */
__IOM uint32_t GPIO47INCFG : 1; /*!< [28..28] GPIO47 input enable. */
__IOM uint32_t GPIO47OUTCFG : 2; /*!< [30..29] GPIO47 output configuration. */
__IOM uint32_t GPIO47INTD : 1; /*!< [31..31] GPIO47 interrupt direction. */
} CFGF_b;
} ;
union {
__IOM uint32_t CFGG; /*!< (@ 0x00000058) GPIO configuration controls for GPIO[49:48].
Writes to this register must be unlocked
by the PADKEY register. */
struct {
__IOM uint32_t GPIO48INCFG : 1; /*!< [0..0] GPIO48 input enable. */
__IOM uint32_t GPIO48OUTCFG : 2; /*!< [2..1] GPIO48 output configuration. */
__IOM uint32_t GPIO48INTD : 1; /*!< [3..3] GPIO48 interrupt direction. */
__IOM uint32_t GPIO49INCFG : 1; /*!< [4..4] GPIO49 input enable. */
__IOM uint32_t GPIO49OUTCFG : 2; /*!< [6..5] GPIO49 output configuration. */
__IOM uint32_t GPIO49INTD : 1; /*!< [7..7] GPIO49 interrupt direction. */
} CFGG_b;
} ;
__IM uint32_t RESERVED1;
union {
__IOM uint32_t PADKEY; /*!< (@ 0x00000060) Lock state of the PINCFG and GPIO configuration
registers. Write a value of 0x73 to unlock
write access to the PAD and GPIO configuration
registers. Write any other value to lock
access to PAD and GPIO registers. This register
also indicates lock status when read. When
in the unlccked state (i.e. 0x73 has been
written), it reads as 1. When in the locked
state, it reads as 0. */
struct {
__IOM uint32_t PADKEY : 32; /*!< [31..0] Key register value. */
} PADKEY_b;
} ;
__IM uint32_t RESERVED2[7];
union {
__IOM uint32_t RDA; /*!< (@ 0x00000080) GPIO Input Register A (31-0) */
struct {
__IOM uint32_t RDA : 32; /*!< [31..0] GPIO31-0 read data. */
} RDA_b;
} ;
union {
__IOM uint32_t RDB; /*!< (@ 0x00000084) GPIO Input Register B (49-32) */
struct {
__IOM uint32_t RDB : 18; /*!< [17..0] GPIO49-32 read data. */
} RDB_b;
} ;
union {
__IOM uint32_t WTA; /*!< (@ 0x00000088) GPIO Output Register A (31-0) */
struct {
__IOM uint32_t WTA : 32; /*!< [31..0] GPIO31-0 write data. */
} WTA_b;
} ;
union {
__IOM uint32_t WTB; /*!< (@ 0x0000008C) GPIO Output Register B (49-32) */
struct {
__IOM uint32_t WTB : 18; /*!< [17..0] GPIO49-32 write data. */
} WTB_b;
} ;
union {
__IOM uint32_t WTSA; /*!< (@ 0x00000090) GPIO Output Register A Set (31-0) */
struct {
__IOM uint32_t WTSA : 32; /*!< [31..0] Set the GPIO31-0 write data. */
} WTSA_b;
} ;
union {
__IOM uint32_t WTSB; /*!< (@ 0x00000094) GPIO Output Register B Set (49-32) */
struct {
__IOM uint32_t WTSB : 18; /*!< [17..0] Set the GPIO49-32 write data. */
} WTSB_b;
} ;
union {
__IOM uint32_t WTCA; /*!< (@ 0x00000098) GPIO Output Register A Clear (31-0) */
struct {
__IOM uint32_t WTCA : 32; /*!< [31..0] Clear the GPIO31-0 write data. */
} WTCA_b;
} ;
union {
__IOM uint32_t WTCB; /*!< (@ 0x0000009C) GPIO Output Register B Clear (49-32) */
struct {
__IOM uint32_t WTCB : 18; /*!< [17..0] Clear the GPIO49-32 write data. */
} WTCB_b;
} ;
union {
__IOM uint32_t ENA; /*!< (@ 0x000000A0) GPIO Enable Register A (31-0) */
struct {
__IOM uint32_t ENA : 32; /*!< [31..0] GPIO31-0 output enables */
} ENA_b;
} ;
union {
__IOM uint32_t ENB; /*!< (@ 0x000000A4) GPIO Enable Register B (49-32) */
struct {
__IOM uint32_t ENB : 18; /*!< [17..0] GPIO49-32 output enables */
} ENB_b;
} ;
union {
__IOM uint32_t ENSA; /*!< (@ 0x000000A8) GPIO Enable Register A Set (31-0) */
struct {
__IOM uint32_t ENSA : 32; /*!< [31..0] Set the GPIO31-0 output enables */
} ENSA_b;
} ;
union {
__IOM uint32_t ENSB; /*!< (@ 0x000000AC) GPIO Enable Register B Set (49-32) */
struct {
__IOM uint32_t ENSB : 18; /*!< [17..0] Set the GPIO49-32 output enables */
} ENSB_b;
} ;
__IM uint32_t RESERVED3;
union {
__IOM uint32_t ENCA; /*!< (@ 0x000000B4) GPIO Enable Register A Clear (31-0) */
struct {
__IOM uint32_t ENCA : 32; /*!< [31..0] Clear the GPIO31-0 output enables */
} ENCA_b;
} ;
union {
__IOM uint32_t ENCB; /*!< (@ 0x000000B8) GPIO Enable Register B Clear (49-32) */
struct {
__IOM uint32_t ENCB : 18; /*!< [17..0] Clear the GPIO49-32 output enables */
} ENCB_b;
} ;
union {
__IOM uint32_t STMRCAP; /*!< (@ 0x000000BC) STIMER Capture trigger select and enable. */
struct {
__IOM uint32_t STSEL0 : 6; /*!< [5..0] STIMER Capture 0 Select. */
__IOM uint32_t STPOL0 : 1; /*!< [6..6] STIMER Capture 0 Polarity. */
__IM uint32_t : 1;
__IOM uint32_t STSEL1 : 6; /*!< [13..8] STIMER Capture 1 Select. */
__IOM uint32_t STPOL1 : 1; /*!< [14..14] STIMER Capture 1 Polarity. */
__IM uint32_t : 1;
__IOM uint32_t STSEL2 : 6; /*!< [21..16] STIMER Capture 2 Select. */
__IOM uint32_t STPOL2 : 1; /*!< [22..22] STIMER Capture 2 Polarity. */
__IM uint32_t : 1;
__IOM uint32_t STSEL3 : 6; /*!< [29..24] STIMER Capture 3 Select. */
__IOM uint32_t STPOL3 : 1; /*!< [30..30] STIMER Capture 3 Polarity. */
} STMRCAP_b;
} ;
union {
__IOM uint32_t IOM0IRQ; /*!< (@ 0x000000C0) IOMSTR0 IRQ select for flow control. */
struct {
__IOM uint32_t IOM0IRQ : 6; /*!< [5..0] IOMSTR0 IRQ pad select. */
} IOM0IRQ_b;
} ;
union {
__IOM uint32_t IOM1IRQ; /*!< (@ 0x000000C4) IOMSTR1 IRQ select for flow control. */
struct {
__IOM uint32_t IOM1IRQ : 6; /*!< [5..0] IOMSTR1 IRQ pad select. */
} IOM1IRQ_b;
} ;
union {
__IOM uint32_t IOM2IRQ; /*!< (@ 0x000000C8) IOMSTR2 IRQ select for flow control. */
struct {
__IOM uint32_t IOM2IRQ : 6; /*!< [5..0] IOMSTR2 IRQ pad select. */
} IOM2IRQ_b;
} ;
union {
__IOM uint32_t IOM3IRQ; /*!< (@ 0x000000CC) IOMSTR3 IRQ select for flow control. */
struct {
__IOM uint32_t IOM3IRQ : 6; /*!< [5..0] IOMSTR3 IRQ pad select. */
} IOM3IRQ_b;
} ;
union {
__IOM uint32_t IOM4IRQ; /*!< (@ 0x000000D0) IOMSTR4 IRQ select for flow control. */
struct {
__IOM uint32_t IOM4IRQ : 6; /*!< [5..0] IOMSTR4 IRQ pad select. */
} IOM4IRQ_b;
} ;
union {
__IOM uint32_t IOM5IRQ; /*!< (@ 0x000000D4) IOMSTR5 IRQ select for flow control. */
struct {
__IOM uint32_t IOM5IRQ : 6; /*!< [5..0] IOMSTR5 IRQ pad select. */
} IOM5IRQ_b;
} ;
union {
__IOM uint32_t BLEIFIRQ; /*!< (@ 0x000000D8) BLE IF IRQ select for flow control. */
struct {
__IOM uint32_t BLEIFIRQ : 6; /*!< [5..0] BLEIF IRQ pad select. */
} BLEIFIRQ_b;
} ;
union {
__IOM uint32_t GPIOOBS; /*!< (@ 0x000000DC) GPIO Observation mode sample register */
struct {
__IOM uint32_t OBS_DATA : 16; /*!< [15..0] Sample of the data output on the GPIO observation port.
May have async sampling issues, as the data is not synronized
to the read operation. Intended for debug purposes only */
} GPIOOBS_b;
} ;
union {
__IOM uint32_t ALTPADCFGA; /*!< (@ 0x000000E0) This register has additional configuration control
for pads 3, 2, 1, 0 */
struct {
__IOM uint32_t PAD0_DS1 : 1; /*!< [0..0] Pad 0 high order drive strength selection. Used in conjunction
with PAD0STRNG field to set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD0_SR : 1; /*!< [4..4] Pad 0 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD1_DS1 : 1; /*!< [8..8] Pad 1 high order drive strength selection. Used in conjunction
with PAD1STRNG field to set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD1_SR : 1; /*!< [12..12] Pad 1 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD2_DS1 : 1; /*!< [16..16] Pad 2 high order drive strength selection. Used in
conjunction with PAD2STRNG field to set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD2_SR : 1; /*!< [20..20] Pad 2 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD3_DS1 : 1; /*!< [24..24] Pad 3 high order drive strength selection. Used in
conjunction with PAD3STRNG field to set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD3_SR : 1; /*!< [28..28] Pad 3 slew rate selection. */
} ALTPADCFGA_b;
} ;
union {
__IOM uint32_t ALTPADCFGB; /*!< (@ 0x000000E4) This register has additional configuration control
for pads 7, 6, 5, 4 */
struct {
__IOM uint32_t PAD4_DS1 : 1; /*!< [0..0] Pad 4 high order drive strength selection. Used in conjunction
with PAD4STRNG field to set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD4_SR : 1; /*!< [4..4] Pad 4 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD5_DS1 : 1; /*!< [8..8] Pad 5 high order drive strength selection. Used in conjunction
with PAD5STRNG field to set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD5_SR : 1; /*!< [12..12] Pad 5 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD6_DS1 : 1; /*!< [16..16] Pad 6 high order drive strength selection. Used in
conjunction with PAD6STRNG field to set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD6_SR : 1; /*!< [20..20] Pad 6 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD7_DS1 : 1; /*!< [24..24] Pad 7 high order drive strength selection. Used in
conjunction with PAD7STRNG field to set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD7_SR : 1; /*!< [28..28] Pad 7 slew rate selection. */
} ALTPADCFGB_b;
} ;
union {
__IOM uint32_t ALTPADCFGC; /*!< (@ 0x000000E8) This register has additional configuration control
for pads 11, 10, 9, 8 */
struct {
__IOM uint32_t PAD8_DS1 : 1; /*!< [0..0] Pad 8 high order drive strength selection. Used in conjunction
with PAD8STRNG field to set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD8_SR : 1; /*!< [4..4] Pad 8 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD9_DS1 : 1; /*!< [8..8] Pad 9 high order drive strength selection. Used in conjunction
with PAD9STRNG field to set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD9_SR : 1; /*!< [12..12] Pad 9 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD10_DS1 : 1; /*!< [16..16] Pad 10 high order drive strength selection. Used in
conjunction with PAD10STRNG field to set the pad drive
strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD10_SR : 1; /*!< [20..20] Pad 10 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD11_DS1 : 1; /*!< [24..24] Pad 11 high order drive strength selection. Used in
conjunction with PAD11STRNG field to set the pad drive
strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD11_SR : 1; /*!< [28..28] Pad 11 slew rate selection. */
} ALTPADCFGC_b;
} ;
union {
__IOM uint32_t ALTPADCFGD; /*!< (@ 0x000000EC) This register has additional configuration control
for pads 15, 14, 13, 12 */
struct {
__IOM uint32_t PAD12_DS1 : 1; /*!< [0..0] Pad 12 high order drive strength selection. Used in conjunction
with PAD12STRNG field to set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD12_SR : 1; /*!< [4..4] Pad 12 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD13_DS1 : 1; /*!< [8..8] Pad 13 high order drive strength selection. Used in conjunction
with PAD13STRNG field to set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD13_SR : 1; /*!< [12..12] Pad 13 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD14_DS1 : 1; /*!< [16..16] Pad 14 high order drive strength selection. Used in
conjunction with PAD14STRNG field to set the pad drive
strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD14_SR : 1; /*!< [20..20] Pad 14 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD15_DS1 : 1; /*!< [24..24] Pad 15 high order drive strength selection. Used in
conjunction with PAD15STRNG field to set the pad drive
strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD15_SR : 1; /*!< [28..28] Pad 15 slew rate selection. */
} ALTPADCFGD_b;
} ;
union {
__IOM uint32_t ALTPADCFGE; /*!< (@ 0x000000F0) This register has additional configuration control
for pads 19, 18, 17, 16 */
struct {
__IOM uint32_t PAD16_DS1 : 1; /*!< [0..0] Pad 16 high order drive strength selection. Used in conjunction
with PAD16STRNG field to set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD16_SR : 1; /*!< [4..4] Pad 16 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD17_DS1 : 1; /*!< [8..8] Pad 17 high order drive strength selection. Used in conjunction
with PAD17STRNG field to set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD17_SR : 1; /*!< [12..12] Pad 17 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD18_DS1 : 1; /*!< [16..16] Pad 18 high order drive strength selection. Used in
conjunction with PAD18STRNG field to set the pad drive
strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD18_SR : 1; /*!< [20..20] Pad 18 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD19_DS1 : 1; /*!< [24..24] Pad 19 high order drive strength selection. Used in
conjunction with PAD19STRNG field to set the pad drive
strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD19_SR : 1; /*!< [28..28] Pad 19 slew rate selection. */
} ALTPADCFGE_b;
} ;
union {
__IOM uint32_t ALTPADCFGF; /*!< (@ 0x000000F4) This register has additional configuration control
for pads 23, 22, 21, 20 */
struct {
__IOM uint32_t PAD20_DS1 : 1; /*!< [0..0] Pad 20 high order drive strength selection. Used in conjunction
with PAD20STRNG field to set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD20_SR : 1; /*!< [4..4] Pad 20 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD21_DS1 : 1; /*!< [8..8] Pad 21 high order drive strength selection. Used in conjunction
with PAD21STRNG field to set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD21_SR : 1; /*!< [12..12] Pad 21 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD22_DS1 : 1; /*!< [16..16] Pad 22 high order drive strength selection. Used in
conjunction with PAD22STRNG field to set the pad drive
strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD22_SR : 1; /*!< [20..20] Pad 22 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD23_DS1 : 1; /*!< [24..24] Pad 23 high order drive strength selection. Used in
conjunction with PAD23STRNG field to set the pad drive
strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD23_SR : 1; /*!< [28..28] Pad 23 slew rate selection. */
} ALTPADCFGF_b;
} ;
union {
__IOM uint32_t ALTPADCFGG; /*!< (@ 0x000000F8) This register has additional configuration control
for pads 27, 26, 25, 24 */
struct {
__IOM uint32_t PAD24_DS1 : 1; /*!< [0..0] Pad 24 high order drive strength selection. Used in conjunction
with PAD24STRNG field to set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD24_SR : 1; /*!< [4..4] Pad 24 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD25_DS1 : 1; /*!< [8..8] Pad 25 high order drive strength selection. Used in conjunction
with PAD25STRNG field to set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD25_SR : 1; /*!< [12..12] Pad 25 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD26_DS1 : 1; /*!< [16..16] Pad 26 high order drive strength selection. Used in
conjunction with PAD26STRNG field to set the pad drive
strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD26_SR : 1; /*!< [20..20] Pad 26 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD27_DS1 : 1; /*!< [24..24] Pad 27 high order drive strength selection. Used in
conjunction with PAD27STRNG field to set the pad drive
strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD27_SR : 1; /*!< [28..28] Pad 27 slew rate selection. */
} ALTPADCFGG_b;
} ;
union {
__IOM uint32_t ALTPADCFGH; /*!< (@ 0x000000FC) This register has additional configuration control
for pads 31, 30, 29, 28 */
struct {
__IOM uint32_t PAD28_DS1 : 1; /*!< [0..0] Pad 28 high order drive strength selection. Used in conjunction
with PAD28STRNG field to set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD28_SR : 1; /*!< [4..4] Pad 28 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD29_DS1 : 1; /*!< [8..8] Pad 29 high order drive strength selection. Used in conjunction
with PAD29STRNG field to set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD29_SR : 1; /*!< [12..12] Pad 29 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD30_DS1 : 1; /*!< [16..16] Pad 30 high order drive strength selection. Used in
conjunction with PAD30STRNG field to set the pad drive
strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD30_SR : 1; /*!< [20..20] Pad 30 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD31_DS1 : 1; /*!< [24..24] Pad 31 high order drive strength selection. Used in
conjunction with PAD31STRNG field to set the pad drive
strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD31_SR : 1; /*!< [28..28] Pad 31 slew rate selection. */
} ALTPADCFGH_b;
} ;
union {
__IOM uint32_t ALTPADCFGI; /*!< (@ 0x00000100) This register has additional configuration control
for pads 35, 34, 33, 32 */
struct {
__IOM uint32_t PAD32_DS1 : 1; /*!< [0..0] Pad 32 high order drive strength selection. Used in conjunction
with PAD32STRNG field to set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD32_SR : 1; /*!< [4..4] Pad 32 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD33_DS1 : 1; /*!< [8..8] Pad 33 high order drive strength selection. Used in conjunction
with PAD33STRNG field to set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD33_SR : 1; /*!< [12..12] Pad 33 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD34_DS1 : 1; /*!< [16..16] Pad 34 high order drive strength selection. Used in
conjunction with PAD34STRNG field to set the pad drive
strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD34_SR : 1; /*!< [20..20] Pad 34 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD35_DS1 : 1; /*!< [24..24] Pad 35 high order drive strength selection. Used in
conjunction with PAD35STRNG field to set the pad drive
strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD35_SR : 1; /*!< [28..28] Pad 35 slew rate selection. */
} ALTPADCFGI_b;
} ;
union {
__IOM uint32_t ALTPADCFGJ; /*!< (@ 0x00000104) This register has additional configuration control
for pads 39, 38, 37, 36 */
struct {
__IOM uint32_t PAD36_DS1 : 1; /*!< [0..0] Pad 36 high order drive strength selection. Used in conjunction
with PAD36STRNG field to set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD36_SR : 1; /*!< [4..4] Pad 36 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD37_DS1 : 1; /*!< [8..8] Pad 37 high order drive strength selection. Used in conjunction
with PAD37STRNG field to set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD37_SR : 1; /*!< [12..12] Pad 37 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD38_DS1 : 1; /*!< [16..16] Pad 38 high order drive strength selection. Used in
conjunction with PAD38STRNG field to set the pad drive
strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD38_SR : 1; /*!< [20..20] Pad 38 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD39_DS1 : 1; /*!< [24..24] Pad 39 high order drive strength selection. Used in
conjunction with PAD39STRNG field to set the pad drive
strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD39_SR : 1; /*!< [28..28] Pad 39 slew rate selection. */
} ALTPADCFGJ_b;
} ;
union {
__IOM uint32_t ALTPADCFGK; /*!< (@ 0x00000108) This register has additional configuration control
for pads 43, 42, 41, 40 */
struct {
__IOM uint32_t PAD40_DS1 : 1; /*!< [0..0] Pad 40 high order drive strength selection. Used in conjunction
with PAD40STRNG field to set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD40_SR : 1; /*!< [4..4] Pad 40 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD41_DS1 : 1; /*!< [8..8] Pad 41 high order drive strength selection. Used in conjunction
with PAD41STRNG field to set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD41_SR : 1; /*!< [12..12] Pad 41 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD42_DS1 : 1; /*!< [16..16] Pad 42 high order drive strength selection. Used in
conjunction with PAD42STRNG field to set the pad drive
strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD42_SR : 1; /*!< [20..20] Pad 42 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD43_DS1 : 1; /*!< [24..24] Pad 43 high order drive strength selection. Used in
conjunction with PAD43STRNG field to set the pad drive
strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD43_SR : 1; /*!< [28..28] Pad 43 slew rate selection. */
} ALTPADCFGK_b;
} ;
union {
__IOM uint32_t ALTPADCFGL; /*!< (@ 0x0000010C) This register has additional configuration control
for pads 47, 46, 45, 44 */
struct {
__IOM uint32_t PAD44_DS1 : 1; /*!< [0..0] Pad 44 high order drive strength selection. Used in conjunction
with PAD44STRNG field to set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD44_SR : 1; /*!< [4..4] Pad 44 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD45_DS1 : 1; /*!< [8..8] Pad 45 high order drive strength selection. Used in conjunction
with PAD45STRNG field to set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD45_SR : 1; /*!< [12..12] Pad 45 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD46_DS1 : 1; /*!< [16..16] Pad 46 high order drive strength selection. Used in
conjunction with PAD46STRNG field to set the pad drive
strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD46_SR : 1; /*!< [20..20] Pad 46 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD47_DS1 : 1; /*!< [24..24] Pad 47 high order drive strength selection. Used in
conjunction with PAD47STRNG field to set the pad drive
strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD47_SR : 1; /*!< [28..28] Pad 47 slew rate selection. */
} ALTPADCFGL_b;
} ;
union {
__IOM uint32_t ALTPADCFGM; /*!< (@ 0x00000110) This register has additional configuration control
for pads 49, 48 */
struct {
__IOM uint32_t PAD48_DS1 : 1; /*!< [0..0] Pad 48 high order drive strength selection. Used in conjunction
with PAD48STRNG field to set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD48_SR : 1; /*!< [4..4] Pad 48 slew rate selection. */
__IM uint32_t : 3;
__IOM uint32_t PAD49_DS1 : 1; /*!< [8..8] Pad 49 high order drive strength selection. Used in conjunction
with PAD49STRNG field to set the pad drive strength. */
__IM uint32_t : 3;
__IOM uint32_t PAD49_SR : 1; /*!< [12..12] Pad 49 slew rate selection. */
} ALTPADCFGM_b;
} ;
union {
__IOM uint32_t SCDET; /*!< (@ 0x00000114) Scard card detect select. */
struct {
__IOM uint32_t SCDET : 6; /*!< [5..0] SCARD card detect pad select. */
} SCDET_b;
} ;
union {
__IOM uint32_t CTENCFG; /*!< (@ 0x00000118) Pad enable configuration. */
struct {
__IOM uint32_t EN0 : 1; /*!< [0..0] CT0 Enable */
__IOM uint32_t EN1 : 1; /*!< [1..1] CT1 Enable */
__IOM uint32_t EN2 : 1; /*!< [2..2] CT2 Enable */
__IOM uint32_t EN3 : 1; /*!< [3..3] CT3 Enable */
__IOM uint32_t EN4 : 1; /*!< [4..4] CT4 Enable */
__IOM uint32_t EN5 : 1; /*!< [5..5] CT5 Enable */
__IOM uint32_t EN6 : 1; /*!< [6..6] CT6 Enable */
__IOM uint32_t EN7 : 1; /*!< [7..7] CT7 Enable */
__IOM uint32_t EN8 : 1; /*!< [8..8] CT8 Enable */
__IOM uint32_t EN9 : 1; /*!< [9..9] CT9 Enable */
__IOM uint32_t EN10 : 1; /*!< [10..10] CT10 Enable */
__IOM uint32_t EN11 : 1; /*!< [11..11] CT11 Enable */
__IOM uint32_t EN12 : 1; /*!< [12..12] CT12 Enable */
__IOM uint32_t EN13 : 1; /*!< [13..13] CT13 Enable */
__IOM uint32_t EN14 : 1; /*!< [14..14] CT14 Enable */
__IOM uint32_t EN15 : 1; /*!< [15..15] CT15 Enable */
__IOM uint32_t EN16 : 1; /*!< [16..16] CT16 Enable */
__IOM uint32_t EN17 : 1; /*!< [17..17] CT17 Enable */
__IOM uint32_t EN18 : 1; /*!< [18..18] CT18 Enable */
__IOM uint32_t EN19 : 1; /*!< [19..19] CT19 Enable */
__IOM uint32_t EN20 : 1; /*!< [20..20] CT20 Enable */
__IOM uint32_t EN21 : 1; /*!< [21..21] CT21 Enable */
__IOM uint32_t EN22 : 1; /*!< [22..22] CT22 Enable */
__IOM uint32_t EN23 : 1; /*!< [23..23] CT23 Enable */
__IOM uint32_t EN24 : 1; /*!< [24..24] CT24 Enable */
__IOM uint32_t EN25 : 1; /*!< [25..25] CT25 Enable */
__IOM uint32_t EN26 : 1; /*!< [26..26] CT26 Enable */
__IOM uint32_t EN27 : 1; /*!< [27..27] CT27 Enable */
__IOM uint32_t EN28 : 1; /*!< [28..28] CT28 Enable */
__IOM uint32_t EN29 : 1; /*!< [29..29] CT29 Enable */
__IOM uint32_t EN30 : 1; /*!< [30..30] CT30 Enable */
__IOM uint32_t EN31 : 1; /*!< [31..31] CT31 Enable */
} CTENCFG_b;
} ;
__IM uint32_t RESERVED4[57];
union {
__IOM uint32_t INT0EN; /*!< (@ 0x00000200) Set bits in this register to allow this module
to generate the corresponding interrupt. */
struct {
__IOM uint32_t GPIO0 : 1; /*!< [0..0] GPIO0 interrupt. */
__IOM uint32_t GPIO1 : 1; /*!< [1..1] GPIO1 interrupt. */
__IOM uint32_t GPIO2 : 1; /*!< [2..2] GPIO2 interrupt. */
__IOM uint32_t GPIO3 : 1; /*!< [3..3] GPIO3 interrupt. */
__IOM uint32_t GPIO4 : 1; /*!< [4..4] GPIO4 interrupt. */
__IOM uint32_t GPIO5 : 1; /*!< [5..5] GPIO5 interrupt. */
__IOM uint32_t GPIO6 : 1; /*!< [6..6] GPIO6 interrupt. */
__IOM uint32_t GPIO7 : 1; /*!< [7..7] GPIO7 interrupt. */
__IOM uint32_t GPIO8 : 1; /*!< [8..8] GPIO8 interrupt. */
__IOM uint32_t GPIO9 : 1; /*!< [9..9] GPIO9 interrupt. */
__IOM uint32_t GPIO10 : 1; /*!< [10..10] GPIO10 interrupt. */
__IOM uint32_t GPIO11 : 1; /*!< [11..11] GPIO11 interrupt. */
__IOM uint32_t GPIO12 : 1; /*!< [12..12] GPIO12 interrupt. */
__IOM uint32_t GPIO13 : 1; /*!< [13..13] GPIO13 interrupt. */
__IOM uint32_t GPIO14 : 1; /*!< [14..14] GPIO14 interrupt. */
__IOM uint32_t GPIO15 : 1; /*!< [15..15] GPIO15 interrupt. */
__IOM uint32_t GPIO16 : 1; /*!< [16..16] GPIO16 interrupt. */
__IOM uint32_t GPIO17 : 1; /*!< [17..17] GPIO17 interrupt. */
__IOM uint32_t GPIO18 : 1; /*!< [18..18] GPIO18interrupt. */
__IOM uint32_t GPIO19 : 1; /*!< [19..19] GPIO19 interrupt. */
__IOM uint32_t GPIO20 : 1; /*!< [20..20] GPIO20 interrupt. */
__IOM uint32_t GPIO21 : 1; /*!< [21..21] GPIO21 interrupt. */
__IOM uint32_t GPIO22 : 1; /*!< [22..22] GPIO22 interrupt. */
__IOM uint32_t GPIO23 : 1; /*!< [23..23] GPIO23 interrupt. */
__IOM uint32_t GPIO24 : 1; /*!< [24..24] GPIO24 interrupt. */
__IOM uint32_t GPIO25 : 1; /*!< [25..25] GPIO25 interrupt. */
__IOM uint32_t GPIO26 : 1; /*!< [26..26] GPIO26 interrupt. */
__IOM uint32_t GPIO27 : 1; /*!< [27..27] GPIO27 interrupt. */
__IOM uint32_t GPIO28 : 1; /*!< [28..28] GPIO28 interrupt. */
__IOM uint32_t GPIO29 : 1; /*!< [29..29] GPIO29 interrupt. */
__IOM uint32_t GPIO30 : 1; /*!< [30..30] GPIO30 interrupt. */
__IOM uint32_t GPIO31 : 1; /*!< [31..31] GPIO31 interrupt. */
} INT0EN_b;
} ;
union {
__IOM uint32_t INT0STAT; /*!< (@ 0x00000204) Read bits from this register to discover the
cause of a recent interrupt. */
struct {
__IOM uint32_t GPIO0 : 1; /*!< [0..0] GPIO0 interrupt. */
__IOM uint32_t GPIO1 : 1; /*!< [1..1] GPIO1 interrupt. */
__IOM uint32_t GPIO2 : 1; /*!< [2..2] GPIO2 interrupt. */
__IOM uint32_t GPIO3 : 1; /*!< [3..3] GPIO3 interrupt. */
__IOM uint32_t GPIO4 : 1; /*!< [4..4] GPIO4 interrupt. */
__IOM uint32_t GPIO5 : 1; /*!< [5..5] GPIO5 interrupt. */
__IOM uint32_t GPIO6 : 1; /*!< [6..6] GPIO6 interrupt. */
__IOM uint32_t GPIO7 : 1; /*!< [7..7] GPIO7 interrupt. */
__IOM uint32_t GPIO8 : 1; /*!< [8..8] GPIO8 interrupt. */
__IOM uint32_t GPIO9 : 1; /*!< [9..9] GPIO9 interrupt. */
__IOM uint32_t GPIO10 : 1; /*!< [10..10] GPIO10 interrupt. */
__IOM uint32_t GPIO11 : 1; /*!< [11..11] GPIO11 interrupt. */
__IOM uint32_t GPIO12 : 1; /*!< [12..12] GPIO12 interrupt. */
__IOM uint32_t GPIO13 : 1; /*!< [13..13] GPIO13 interrupt. */
__IOM uint32_t GPIO14 : 1; /*!< [14..14] GPIO14 interrupt. */
__IOM uint32_t GPIO15 : 1; /*!< [15..15] GPIO15 interrupt. */
__IOM uint32_t GPIO16 : 1; /*!< [16..16] GPIO16 interrupt. */
__IOM uint32_t GPIO17 : 1; /*!< [17..17] GPIO17 interrupt. */
__IOM uint32_t GPIO18 : 1; /*!< [18..18] GPIO18interrupt. */
__IOM uint32_t GPIO19 : 1; /*!< [19..19] GPIO19 interrupt. */
__IOM uint32_t GPIO20 : 1; /*!< [20..20] GPIO20 interrupt. */
__IOM uint32_t GPIO21 : 1; /*!< [21..21] GPIO21 interrupt. */
__IOM uint32_t GPIO22 : 1; /*!< [22..22] GPIO22 interrupt. */
__IOM uint32_t GPIO23 : 1; /*!< [23..23] GPIO23 interrupt. */
__IOM uint32_t GPIO24 : 1; /*!< [24..24] GPIO24 interrupt. */
__IOM uint32_t GPIO25 : 1; /*!< [25..25] GPIO25 interrupt. */
__IOM uint32_t GPIO26 : 1; /*!< [26..26] GPIO26 interrupt. */
__IOM uint32_t GPIO27 : 1; /*!< [27..27] GPIO27 interrupt. */
__IOM uint32_t GPIO28 : 1; /*!< [28..28] GPIO28 interrupt. */
__IOM uint32_t GPIO29 : 1; /*!< [29..29] GPIO29 interrupt. */
__IOM uint32_t GPIO30 : 1; /*!< [30..30] GPIO30 interrupt. */
__IOM uint32_t GPIO31 : 1; /*!< [31..31] GPIO31 interrupt. */
} INT0STAT_b;
} ;
union {
__IOM uint32_t INT0CLR; /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
the interrupt status associated with that
bit. */
struct {
__IOM uint32_t GPIO0 : 1; /*!< [0..0] GPIO0 interrupt. */
__IOM uint32_t GPIO1 : 1; /*!< [1..1] GPIO1 interrupt. */
__IOM uint32_t GPIO2 : 1; /*!< [2..2] GPIO2 interrupt. */
__IOM uint32_t GPIO3 : 1; /*!< [3..3] GPIO3 interrupt. */
__IOM uint32_t GPIO4 : 1; /*!< [4..4] GPIO4 interrupt. */
__IOM uint32_t GPIO5 : 1; /*!< [5..5] GPIO5 interrupt. */
__IOM uint32_t GPIO6 : 1; /*!< [6..6] GPIO6 interrupt. */
__IOM uint32_t GPIO7 : 1; /*!< [7..7] GPIO7 interrupt. */
__IOM uint32_t GPIO8 : 1; /*!< [8..8] GPIO8 interrupt. */
__IOM uint32_t GPIO9 : 1; /*!< [9..9] GPIO9 interrupt. */
__IOM uint32_t GPIO10 : 1; /*!< [10..10] GPIO10 interrupt. */
__IOM uint32_t GPIO11 : 1; /*!< [11..11] GPIO11 interrupt. */
__IOM uint32_t GPIO12 : 1; /*!< [12..12] GPIO12 interrupt. */
__IOM uint32_t GPIO13 : 1; /*!< [13..13] GPIO13 interrupt. */
__IOM uint32_t GPIO14 : 1; /*!< [14..14] GPIO14 interrupt. */
__IOM uint32_t GPIO15 : 1; /*!< [15..15] GPIO15 interrupt. */
__IOM uint32_t GPIO16 : 1; /*!< [16..16] GPIO16 interrupt. */
__IOM uint32_t GPIO17 : 1; /*!< [17..17] GPIO17 interrupt. */
__IOM uint32_t GPIO18 : 1; /*!< [18..18] GPIO18interrupt. */
__IOM uint32_t GPIO19 : 1; /*!< [19..19] GPIO19 interrupt. */
__IOM uint32_t GPIO20 : 1; /*!< [20..20] GPIO20 interrupt. */
__IOM uint32_t GPIO21 : 1; /*!< [21..21] GPIO21 interrupt. */
__IOM uint32_t GPIO22 : 1; /*!< [22..22] GPIO22 interrupt. */
__IOM uint32_t GPIO23 : 1; /*!< [23..23] GPIO23 interrupt. */
__IOM uint32_t GPIO24 : 1; /*!< [24..24] GPIO24 interrupt. */
__IOM uint32_t GPIO25 : 1; /*!< [25..25] GPIO25 interrupt. */
__IOM uint32_t GPIO26 : 1; /*!< [26..26] GPIO26 interrupt. */
__IOM uint32_t GPIO27 : 1; /*!< [27..27] GPIO27 interrupt. */
__IOM uint32_t GPIO28 : 1; /*!< [28..28] GPIO28 interrupt. */
__IOM uint32_t GPIO29 : 1; /*!< [29..29] GPIO29 interrupt. */
__IOM uint32_t GPIO30 : 1; /*!< [30..30] GPIO30 interrupt. */
__IOM uint32_t GPIO31 : 1; /*!< [31..31] GPIO31 interrupt. */
} INT0CLR_b;
} ;
union {
__IOM uint32_t INT0SET; /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
generate an interrupt from this module.
(Generally used for testing purposes). */
struct {
__IOM uint32_t GPIO0 : 1; /*!< [0..0] GPIO0 interrupt. */
__IOM uint32_t GPIO1 : 1; /*!< [1..1] GPIO1 interrupt. */
__IOM uint32_t GPIO2 : 1; /*!< [2..2] GPIO2 interrupt. */
__IOM uint32_t GPIO3 : 1; /*!< [3..3] GPIO3 interrupt. */
__IOM uint32_t GPIO4 : 1; /*!< [4..4] GPIO4 interrupt. */
__IOM uint32_t GPIO5 : 1; /*!< [5..5] GPIO5 interrupt. */
__IOM uint32_t GPIO6 : 1; /*!< [6..6] GPIO6 interrupt. */
__IOM uint32_t GPIO7 : 1; /*!< [7..7] GPIO7 interrupt. */
__IOM uint32_t GPIO8 : 1; /*!< [8..8] GPIO8 interrupt. */
__IOM uint32_t GPIO9 : 1; /*!< [9..9] GPIO9 interrupt. */
__IOM uint32_t GPIO10 : 1; /*!< [10..10] GPIO10 interrupt. */
__IOM uint32_t GPIO11 : 1; /*!< [11..11] GPIO11 interrupt. */
__IOM uint32_t GPIO12 : 1; /*!< [12..12] GPIO12 interrupt. */
__IOM uint32_t GPIO13 : 1; /*!< [13..13] GPIO13 interrupt. */
__IOM uint32_t GPIO14 : 1; /*!< [14..14] GPIO14 interrupt. */
__IOM uint32_t GPIO15 : 1; /*!< [15..15] GPIO15 interrupt. */
__IOM uint32_t GPIO16 : 1; /*!< [16..16] GPIO16 interrupt. */
__IOM uint32_t GPIO17 : 1; /*!< [17..17] GPIO17 interrupt. */
__IOM uint32_t GPIO18 : 1; /*!< [18..18] GPIO18interrupt. */
__IOM uint32_t GPIO19 : 1; /*!< [19..19] GPIO19 interrupt. */
__IOM uint32_t GPIO20 : 1; /*!< [20..20] GPIO20 interrupt. */
__IOM uint32_t GPIO21 : 1; /*!< [21..21] GPIO21 interrupt. */
__IOM uint32_t GPIO22 : 1; /*!< [22..22] GPIO22 interrupt. */
__IOM uint32_t GPIO23 : 1; /*!< [23..23] GPIO23 interrupt. */
__IOM uint32_t GPIO24 : 1; /*!< [24..24] GPIO24 interrupt. */
__IOM uint32_t GPIO25 : 1; /*!< [25..25] GPIO25 interrupt. */
__IOM uint32_t GPIO26 : 1; /*!< [26..26] GPIO26 interrupt. */
__IOM uint32_t GPIO27 : 1; /*!< [27..27] GPIO27 interrupt. */
__IOM uint32_t GPIO28 : 1; /*!< [28..28] GPIO28 interrupt. */
__IOM uint32_t GPIO29 : 1; /*!< [29..29] GPIO29 interrupt. */
__IOM uint32_t GPIO30 : 1; /*!< [30..30] GPIO30 interrupt. */
__IOM uint32_t GPIO31 : 1; /*!< [31..31] GPIO31 interrupt. */
} INT0SET_b;
} ;
union {
__IOM uint32_t INT1EN; /*!< (@ 0x00000210) Set bits in this register to allow this module
to generate the corresponding interrupt. */
struct {
__IOM uint32_t GPIO32 : 1; /*!< [0..0] GPIO32 interrupt. */
__IOM uint32_t GPIO33 : 1; /*!< [1..1] GPIO33 interrupt. */
__IOM uint32_t GPIO34 : 1; /*!< [2..2] GPIO34 interrupt. */
__IOM uint32_t GPIO35 : 1; /*!< [3..3] GPIO35 interrupt. */
__IOM uint32_t GPIO36 : 1; /*!< [4..4] GPIO36 interrupt. */
__IOM uint32_t GPIO37 : 1; /*!< [5..5] GPIO37 interrupt. */
__IOM uint32_t GPIO38 : 1; /*!< [6..6] GPIO38 interrupt. */
__IOM uint32_t GPIO39 : 1; /*!< [7..7] GPIO39 interrupt. */
__IOM uint32_t GPIO40 : 1; /*!< [8..8] GPIO40 interrupt. */
__IOM uint32_t GPIO41 : 1; /*!< [9..9] GPIO41 interrupt. */
__IOM uint32_t GPIO42 : 1; /*!< [10..10] GPIO42 interrupt. */
__IOM uint32_t GPIO43 : 1; /*!< [11..11] GPIO43 interrupt. */
__IOM uint32_t GPIO44 : 1; /*!< [12..12] GPIO44 interrupt. */
__IOM uint32_t GPIO45 : 1; /*!< [13..13] GPIO45 interrupt. */
__IOM uint32_t GPIO46 : 1; /*!< [14..14] GPIO46 interrupt. */
__IOM uint32_t GPIO47 : 1; /*!< [15..15] GPIO47 interrupt. */
__IOM uint32_t GPIO48 : 1; /*!< [16..16] GPIO48 interrupt. */
__IOM uint32_t GPIO49 : 1; /*!< [17..17] GPIO49 interrupt. */
} INT1EN_b;
} ;
union {
__IOM uint32_t INT1STAT; /*!< (@ 0x00000214) Read bits from this register to discover the
cause of a recent interrupt. */
struct {
__IOM uint32_t GPIO32 : 1; /*!< [0..0] GPIO32 interrupt. */
__IOM uint32_t GPIO33 : 1; /*!< [1..1] GPIO33 interrupt. */
__IOM uint32_t GPIO34 : 1; /*!< [2..2] GPIO34 interrupt. */
__IOM uint32_t GPIO35 : 1; /*!< [3..3] GPIO35 interrupt. */
__IOM uint32_t GPIO36 : 1; /*!< [4..4] GPIO36 interrupt. */
__IOM uint32_t GPIO37 : 1; /*!< [5..5] GPIO37 interrupt. */
__IOM uint32_t GPIO38 : 1; /*!< [6..6] GPIO38 interrupt. */
__IOM uint32_t GPIO39 : 1; /*!< [7..7] GPIO39 interrupt. */
__IOM uint32_t GPIO40 : 1; /*!< [8..8] GPIO40 interrupt. */
__IOM uint32_t GPIO41 : 1; /*!< [9..9] GPIO41 interrupt. */
__IOM uint32_t GPIO42 : 1; /*!< [10..10] GPIO42 interrupt. */
__IOM uint32_t GPIO43 : 1; /*!< [11..11] GPIO43 interrupt. */
__IOM uint32_t GPIO44 : 1; /*!< [12..12] GPIO44 interrupt. */
__IOM uint32_t GPIO45 : 1; /*!< [13..13] GPIO45 interrupt. */
__IOM uint32_t GPIO46 : 1; /*!< [14..14] GPIO46 interrupt. */
__IOM uint32_t GPIO47 : 1; /*!< [15..15] GPIO47 interrupt. */
__IOM uint32_t GPIO48 : 1; /*!< [16..16] GPIO48 interrupt. */
__IOM uint32_t GPIO49 : 1; /*!< [17..17] GPIO49 interrupt. */
} INT1STAT_b;
} ;
union {
__IOM uint32_t INT1CLR; /*!< (@ 0x00000218) Write a 1 to a bit in this register to clear
the interrupt status associated with that
bit. */
struct {
__IOM uint32_t GPIO32 : 1; /*!< [0..0] GPIO32 interrupt. */
__IOM uint32_t GPIO33 : 1; /*!< [1..1] GPIO33 interrupt. */
__IOM uint32_t GPIO34 : 1; /*!< [2..2] GPIO34 interrupt. */
__IOM uint32_t GPIO35 : 1; /*!< [3..3] GPIO35 interrupt. */
__IOM uint32_t GPIO36 : 1; /*!< [4..4] GPIO36 interrupt. */
__IOM uint32_t GPIO37 : 1; /*!< [5..5] GPIO37 interrupt. */
__IOM uint32_t GPIO38 : 1; /*!< [6..6] GPIO38 interrupt. */
__IOM uint32_t GPIO39 : 1; /*!< [7..7] GPIO39 interrupt. */
__IOM uint32_t GPIO40 : 1; /*!< [8..8] GPIO40 interrupt. */
__IOM uint32_t GPIO41 : 1; /*!< [9..9] GPIO41 interrupt. */
__IOM uint32_t GPIO42 : 1; /*!< [10..10] GPIO42 interrupt. */
__IOM uint32_t GPIO43 : 1; /*!< [11..11] GPIO43 interrupt. */
__IOM uint32_t GPIO44 : 1; /*!< [12..12] GPIO44 interrupt. */
__IOM uint32_t GPIO45 : 1; /*!< [13..13] GPIO45 interrupt. */
__IOM uint32_t GPIO46 : 1; /*!< [14..14] GPIO46 interrupt. */
__IOM uint32_t GPIO47 : 1; /*!< [15..15] GPIO47 interrupt. */
__IOM uint32_t GPIO48 : 1; /*!< [16..16] GPIO48 interrupt. */
__IOM uint32_t GPIO49 : 1; /*!< [17..17] GPIO49 interrupt. */
} INT1CLR_b;
} ;
union {
__IOM uint32_t INT1SET; /*!< (@ 0x0000021C) Write a 1 to a bit in this register to instantly
generate an interrupt from this module.
(Generally used for testing purposes). */
struct {
__IOM uint32_t GPIO32 : 1; /*!< [0..0] GPIO32 interrupt. */
__IOM uint32_t GPIO33 : 1; /*!< [1..1] GPIO33 interrupt. */
__IOM uint32_t GPIO34 : 1; /*!< [2..2] GPIO34 interrupt. */
__IOM uint32_t GPIO35 : 1; /*!< [3..3] GPIO35 interrupt. */
__IOM uint32_t GPIO36 : 1; /*!< [4..4] GPIO36 interrupt. */
__IOM uint32_t GPIO37 : 1; /*!< [5..5] GPIO37 interrupt. */
__IOM uint32_t GPIO38 : 1; /*!< [6..6] GPIO38 interrupt. */
__IOM uint32_t GPIO39 : 1; /*!< [7..7] GPIO39 interrupt. */
__IOM uint32_t GPIO40 : 1; /*!< [8..8] GPIO40 interrupt. */
__IOM uint32_t GPIO41 : 1; /*!< [9..9] GPIO41 interrupt. */
__IOM uint32_t GPIO42 : 1; /*!< [10..10] GPIO42 interrupt. */
__IOM uint32_t GPIO43 : 1; /*!< [11..11] GPIO43 interrupt. */
__IOM uint32_t GPIO44 : 1; /*!< [12..12] GPIO44 interrupt. */
__IOM uint32_t GPIO45 : 1; /*!< [13..13] GPIO45 interrupt. */
__IOM uint32_t GPIO46 : 1; /*!< [14..14] GPIO46 interrupt. */
__IOM uint32_t GPIO47 : 1; /*!< [15..15] GPIO47 interrupt. */
__IOM uint32_t GPIO48 : 1; /*!< [16..16] GPIO48 interrupt. */
__IOM uint32_t GPIO49 : 1; /*!< [17..17] GPIO49 interrupt. */
} INT1SET_b;
} ;
} GPIO_Type; /*!< Size = 544 (0x220) */
/* =========================================================================================================================== */
/* ================ IOM0 ================ */
/* =========================================================================================================================== */
/**
* @brief IO Peripheral Master (IOM0)
*/
typedef struct { /*!< (@ 0x50004000) IOM0 Structure */
union {
__IOM uint32_t FIFO; /*!< (@ 0x00000000) Provides direct random access to both output
and input FIFOs. The state of the FIFO is
not disturbed by reading these locations
(ie no POP will be done). FIFO0 is accessible
from addresses 0x0 - 0x1C, and is used for
data output from the IOM to external devices.
These FIFO locations can be read and written
directly.FIFO1 locations 0x20 - 0x3C provide
read only access to the input FIFO. These
FIFO locations cannot be directly written
by the MCU and are updated only by the internal
har */
struct {
__IOM uint32_t FIFO : 32; /*!< [31..0] FIFO direct access. Only locations 0 - 3F will return
valid information. */
} FIFO_b;
} ;
__IM uint32_t RESERVED[63];
union {
__IOM uint32_t FIFOPTR; /*!< (@ 0x00000100) Provides the current valid byte count of data
within the FIFO as seen from the internal
state machines. FIFO0 is dedicated to outgoing
transactions and FIFO1 is dedicated to incoming
transactions. All counts are specified in
units of bytes. */
struct {
__IOM uint32_t FIFO0SIZ : 8; /*!< [7..0] The number of valid data bytes currently in the FIFO
0 (written by MCU, read by interface) */
__IOM uint32_t FIFO0REM : 8; /*!< [15..8] The number of remaining data bytes slots currently in
FIFO 0 (written by MCU, read by interface) */
__IOM uint32_t FIFO1SIZ : 8; /*!< [23..16] The number of valid data bytes currently in FIFO 1
(written by interface, read by MCU) */
__IOM uint32_t FIFO1REM : 8; /*!< [31..24] The number of remaining data bytes slots currently
in FIFO 1 (written by interface, read by MCU) */
} FIFOPTR_b;
} ;
union {
__IOM uint32_t FIFOTHR; /*!< (@ 0x00000104) Sets the threshold values for incoming and outgoing
transactions. The threshold values are used
to assert the interrupt if enabled, and
also used during DMA to set the transfer
size as a result of DMATHR trigger.The WTHR
is used to indicate when there are more
than WTHR bytes of open fifo locations available
in the outgoing FIFO (FIFO0). The intended
use to invoke an interrupt or DMA transfer
that will refill the FIFO with a byte count
up to this value.The RTHR is used to indicate
whe */
struct {
__IOM uint32_t FIFORTHR : 6; /*!< [5..0] FIFO read threshold in bytes. A value of 0 will disable
the read FIFO level from activating the threshold interrupt.
If this field is non-zero, it will trigger a threshold
interrupt when the read fifo contains FIFORTHR valid bytes
of data, as indicated by the FIFO1SIZ field. This is intended
to signal when a data transfer of FIFORTHR bytes can be
done from the IOM module to the host via the read fifo
to support large IOM read operations. */
__IM uint32_t : 2;
__IOM uint32_t FIFOWTHR : 6; /*!< [13..8] FIFO write threshold in bytes. A value of 0 will disable
the write FIFO level from activating the threshold interrupt.
If this field is non-zero, it will trigger a threshold
interrupt when the write fifo contains FIFOWTHR free bytes,
as indicated by the FIFO0REM field. This is intended to
signal when a transfer of FIFOWTHR bytes can be done from
the host to the IOM write fifo to support large IOM write
operations. */
} FIFOTHR_b;
} ;
union {
__IOM uint32_t FIFOPOP; /*!< (@ 0x00000108) Will advance the internal read pointer of the
incoming FIFO (FIFO1) when read, if POPWR
is not active. If POPWR is active, a write
to this register is needed to advance the
internal FIFO pointer. */
struct {
__IOM uint32_t FIFODOUT : 32; /*!< [31..0] This register will return the read data indicated by
the current read pointer on reads. If the POPWR control
bit in the FIFOCTRL register is reset (0), the fifo read
pointer will be advanced by one word as a result of the
read.If the POPWR bit is set (1), the fifo read pointer
will only be advanced after a write operation to this register.
The write data is ignored for this register.If less than
a even word multiple is available, and the command is completed,
the module will return the word containing */
} FIFOPOP_b;
} ;
union {
__IOM uint32_t FIFOPUSH; /*!< (@ 0x0000010C) Will write new data into the outgoing FIFO and
advance the internal write pointer. */
struct {
__IOM uint32_t FIFODIN : 32; /*!< [31..0] This register is used to write the FIFORAM in FIFO mode
and will cause a push event to occur to the next open slot
within the FIFORAM. Writing to this register will cause
the write point to increment by 1 word(4 bytes). */
} FIFOPUSH_b;
} ;
union {
__IOM uint32_t FIFOCTRL; /*!< (@ 0x00000110) Provides controls for the operation of the internal
FIFOs. Contains fields used to control the
operation of the POP register, and also
controls to reset the internal pointers
of the FIFOs. */
struct {
__IOM uint32_t POPWR : 1; /*!< [0..0] Selects the mode in which 'pop' events are done for the
fifo read operations. A value of '1' will prevent a pop
event on a read operation, and will require a write to
the FIFOPOP register to create a pop event.A value of '0'
in this register will allow a pop event to occur on the
read of the FIFOPOP register, and may cause inadvertant
fifo pops when used in a debugging mode. */
__IOM uint32_t FIFORSTN : 1; /*!< [1..1] Active low manual reset of the fifo. Write to 0 to reset
fifo, and then write to 1 to remove the reset. */
} FIFOCTRL_b;
} ;
union {
__IOM uint32_t FIFOLOC; /*!< (@ 0x00000114) Provides a read only value of the current read
and write pointers. This register is read
only and can be used alogn with the FIFO
direct access method to determine the next
data to be used for input and output functions. */
struct {
__IOM uint32_t FIFOWPTR : 4; /*!< [3..0] Current FIFO write pointer. Value is the index into the
outgoing FIFO (FIFO0), which is used during write operations
to external devices. */
__IM uint32_t : 4;
__IOM uint32_t FIFORPTR : 4; /*!< [11..8] Current FIFO read pointer. Used to index into the incoming
FIFO (FIFO1), which is used to store read data returned
from external devices during a read operation. */
} FIFOLOC_b;
} ;
__IM uint32_t RESERVED1[58];
union {
__IOM uint32_t INTEN; /*!< (@ 0x00000200) Set bits in this register to allow this module
to generate the corresponding interrupt. */
struct {
__IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when the current
operation has completed. For repeated commands, this will
only be asserted when the final repeated command is completed. */
__IOM uint32_t THR : 1; /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted
when the number of free bytes in the write FIFO equals
or exceeds the WTHR field.For read operations, asserted
when the number of valid bytes in the read FIFO equals
of exceeds the value set in the RTHR field. */
__IOM uint32_t FUNDFL : 1; /*!< [2..2] Read FIFO Underflow interrupt. This occurs when software
tries to pop from an empty fifo. */
__IOM uint32_t FOVFL : 1; /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software
tries to write to a full fifo. The current operation does
not stop. */
__IOM uint32_t NAK : 1; /*!< [4..4] I2C NAK interrupt. Asserted when an unexpected NAK has
been received on the I2C bus. */
__IOM uint32_t IACC : 1; /*!< [5..5] illegal FIFO access interrupt. Asserted when there is
a overflow or underflow event */
__IOM uint32_t ICMD : 1; /*!< [6..6] illegal command interrupt. Asserted when a command is
written when an active command is in progress. */
__IOM uint32_t START : 1; /*!< [7..7] START command interrupt. Asserted when another master
on the bus has signaled a START command. */
__IOM uint32_t STOP : 1; /*!< [8..8] STOP command interrupt. Asserted when another master
on the bus has signaled a STOP command. */
__IOM uint32_t ARB : 1; /*!< [9..9] Arbitration loss interrupt. Asserted when arbitration
is enabled and has been lost to another master on the bus. */
__IOM uint32_t DCMP : 1; /*!< [10..10] DMA Complete. Processing of the DMA operation has completed
and the DMA submodule is returned into the idle state */
__IOM uint32_t DERR : 1; /*!< [11..11] DMA Error encountered during the processing of the
DMA command. The DMA error could occur when the memory
access specified in the DMA operation is not available
or incorrectly specified. */
__IOM uint32_t CQPAUSED : 1; /*!< [12..12] Command queue is paused due to an active event enabled
in the PAUSEEN register. The interrupt is posted when the
event is enabled within the PAUSEEN register, the mask
is active in the CQIRQMASK field and the event occurs. */
__IOM uint32_t CQUPD : 1; /*!< [13..13] CQ write operation performed a register write with
the register address bit 0 set to 1. The low address bits
in the CQ address fields are unused and bit 0 can be used
to trigger an interrupt to indicate when this register
write is performed by the CQ operation. */
__IOM uint32_t CQERR : 1; /*!< [14..14] Error during command queue operations */
} INTEN_b;
} ;
union {
__IOM uint32_t INTSTAT; /*!< (@ 0x00000204) Read bits from this register to discover the
cause of a recent interrupt. */
struct {
__IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when the current
operation has completed. For repeated commands, this will
only be asserted when the final repeated command is completed. */
__IOM uint32_t THR : 1; /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted
when the number of free bytes in the write FIFO equals
or exceeds the WTHR field.For read operations, asserted
when the number of valid bytes in the read FIFO equals
of exceeds the value set in the RTHR field. */
__IOM uint32_t FUNDFL : 1; /*!< [2..2] Read FIFO Underflow interrupt. This occurs when software
tries to pop from an empty fifo. */
__IOM uint32_t FOVFL : 1; /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software
tries to write to a full fifo. The current operation does
not stop. */
__IOM uint32_t NAK : 1; /*!< [4..4] I2C NAK interrupt. Asserted when an unexpected NAK has
been received on the I2C bus. */
__IOM uint32_t IACC : 1; /*!< [5..5] illegal FIFO access interrupt. Asserted when there is
a overflow or underflow event */
__IOM uint32_t ICMD : 1; /*!< [6..6] illegal command interrupt. Asserted when a command is
written when an active command is in progress. */
__IOM uint32_t START : 1; /*!< [7..7] START command interrupt. Asserted when another master
on the bus has signaled a START command. */
__IOM uint32_t STOP : 1; /*!< [8..8] STOP command interrupt. Asserted when another master
on the bus has signaled a STOP command. */
__IOM uint32_t ARB : 1; /*!< [9..9] Arbitration loss interrupt. Asserted when arbitration
is enabled and has been lost to another master on the bus. */
__IOM uint32_t DCMP : 1; /*!< [10..10] DMA Complete. Processing of the DMA operation has completed
and the DMA submodule is returned into the idle state */
__IOM uint32_t DERR : 1; /*!< [11..11] DMA Error encountered during the processing of the
DMA command. The DMA error could occur when the memory
access specified in the DMA operation is not available
or incorrectly specified. */
__IOM uint32_t CQPAUSED : 1; /*!< [12..12] Command queue is paused due to an active event enabled
in the PAUSEEN register. The interrupt is posted when the
event is enabled within the PAUSEEN register, the mask
is active in the CQIRQMASK field and the event occurs. */
__IOM uint32_t CQUPD : 1; /*!< [13..13] CQ write operation performed a register write with
the register address bit 0 set to 1. The low address bits
in the CQ address fields are unused and bit 0 can be used
to trigger an interrupt to indicate when this register
write is performed by the CQ operation. */
__IOM uint32_t CQERR : 1; /*!< [14..14] Error during command queue operations */
} INTSTAT_b;
} ;
union {
__IOM uint32_t INTCLR; /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
the interrupt status associated with that
bit. */
struct {
__IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when the current
operation has completed. For repeated commands, this will
only be asserted when the final repeated command is completed. */
__IOM uint32_t THR : 1; /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted
when the number of free bytes in the write FIFO equals
or exceeds the WTHR field.For read operations, asserted
when the number of valid bytes in the read FIFO equals
of exceeds the value set in the RTHR field. */
__IOM uint32_t FUNDFL : 1; /*!< [2..2] Read FIFO Underflow interrupt. This occurs when software
tries to pop from an empty fifo. */
__IOM uint32_t FOVFL : 1; /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software
tries to write to a full fifo. The current operation does
not stop. */
__IOM uint32_t NAK : 1; /*!< [4..4] I2C NAK interrupt. Asserted when an unexpected NAK has
been received on the I2C bus. */
__IOM uint32_t IACC : 1; /*!< [5..5] illegal FIFO access interrupt. Asserted when there is
a overflow or underflow event */
__IOM uint32_t ICMD : 1; /*!< [6..6] illegal command interrupt. Asserted when a command is
written when an active command is in progress. */
__IOM uint32_t START : 1; /*!< [7..7] START command interrupt. Asserted when another master
on the bus has signaled a START command. */
__IOM uint32_t STOP : 1; /*!< [8..8] STOP command interrupt. Asserted when another master
on the bus has signaled a STOP command. */
__IOM uint32_t ARB : 1; /*!< [9..9] Arbitration loss interrupt. Asserted when arbitration
is enabled and has been lost to another master on the bus. */
__IOM uint32_t DCMP : 1; /*!< [10..10] DMA Complete. Processing of the DMA operation has completed
and the DMA submodule is returned into the idle state */
__IOM uint32_t DERR : 1; /*!< [11..11] DMA Error encountered during the processing of the
DMA command. The DMA error could occur when the memory
access specified in the DMA operation is not available
or incorrectly specified. */
__IOM uint32_t CQPAUSED : 1; /*!< [12..12] Command queue is paused due to an active event enabled
in the PAUSEEN register. The interrupt is posted when the
event is enabled within the PAUSEEN register, the mask
is active in the CQIRQMASK field and the event occurs. */
__IOM uint32_t CQUPD : 1; /*!< [13..13] CQ write operation performed a register write with
the register address bit 0 set to 1. The low address bits
in the CQ address fields are unused and bit 0 can be used
to trigger an interrupt to indicate when this register
write is performed by the CQ operation. */
__IOM uint32_t CQERR : 1; /*!< [14..14] Error during command queue operations */
} INTCLR_b;
} ;
union {
__IOM uint32_t INTSET; /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
generate an interrupt from this module.
(Generally used for testing purposes). */
struct {
__IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when the current
operation has completed. For repeated commands, this will
only be asserted when the final repeated command is completed. */
__IOM uint32_t THR : 1; /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted
when the number of free bytes in the write FIFO equals
or exceeds the WTHR field.For read operations, asserted
when the number of valid bytes in the read FIFO equals
of exceeds the value set in the RTHR field. */
__IOM uint32_t FUNDFL : 1; /*!< [2..2] Read FIFO Underflow interrupt. This occurs when software
tries to pop from an empty fifo. */
__IOM uint32_t FOVFL : 1; /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software
tries to write to a full fifo. The current operation does
not stop. */
__IOM uint32_t NAK : 1; /*!< [4..4] I2C NAK interrupt. Asserted when an unexpected NAK has
been received on the I2C bus. */
__IOM uint32_t IACC : 1; /*!< [5..5] illegal FIFO access interrupt. Asserted when there is
a overflow or underflow event */
__IOM uint32_t ICMD : 1; /*!< [6..6] illegal command interrupt. Asserted when a command is
written when an active command is in progress. */
__IOM uint32_t START : 1; /*!< [7..7] START command interrupt. Asserted when another master
on the bus has signaled a START command. */
__IOM uint32_t STOP : 1; /*!< [8..8] STOP command interrupt. Asserted when another master
on the bus has signaled a STOP command. */
__IOM uint32_t ARB : 1; /*!< [9..9] Arbitration loss interrupt. Asserted when arbitration
is enabled and has been lost to another master on the bus. */
__IOM uint32_t DCMP : 1; /*!< [10..10] DMA Complete. Processing of the DMA operation has completed
and the DMA submodule is returned into the idle state */
__IOM uint32_t DERR : 1; /*!< [11..11] DMA Error encountered during the processing of the
DMA command. The DMA error could occur when the memory
access specified in the DMA operation is not available
or incorrectly specified. */
__IOM uint32_t CQPAUSED : 1; /*!< [12..12] Command queue is paused due to an active event enabled
in the PAUSEEN register. The interrupt is posted when the
event is enabled within the PAUSEEN register, the mask
is active in the CQIRQMASK field and the event occurs. */
__IOM uint32_t CQUPD : 1; /*!< [13..13] CQ write operation performed a register write with
the register address bit 0 set to 1. The low address bits
in the CQ address fields are unused and bit 0 can be used
to trigger an interrupt to indicate when this register
write is performed by the CQ operation. */
__IOM uint32_t CQERR : 1; /*!< [14..14] Error during command queue operations */
} INTSET_b;
} ;
union {
__IOM uint32_t CLKCFG; /*!< (@ 0x00000210) Provides clock related controls used internal
to the BLEIF module, and enablement of 32KHz
clock to the BLE Core module. The internal
clock sourced is selected via the FSEL and
can be further divided by 3 using the DIV3
control.This register is also used to enable
the clock, which must be done prior to performing
any IO transactions. */
struct {
__IOM uint32_t IOCLKEN : 1; /*!< [0..0] Enable for the interface clock. Must be enabled prior
to executing any IO operations. */
__IM uint32_t : 7;
__IOM uint32_t FSEL : 3; /*!< [10..8] Select the input clock frequency. */
__IOM uint32_t DIV3 : 1; /*!< [11..11] Enable divide by 3 of the source IOCLK. Division by
3 is done before the DIVEN programmable divider, and if
enabledwill provide the divided by 3 clock as the source
to the programmable divider. */
__IOM uint32_t DIVEN : 1; /*!< [12..12] Enable clock division by TOTPER and LOWPER */
__IM uint32_t : 3;
__IOM uint32_t LOWPER : 8; /*!< [23..16] Clock low clock count minus 1. This provides the number
of clocks the divided clock will be low when the DIVEN
= 1.Only applicable when DIVEN = 1. */
__IOM uint32_t TOTPER : 8; /*!< [31..24] Clock total clock count minus 1. This provides the
total period of the divided clock -1 when the DIVEN is
active. Thesource clock is selected by FSEL. Only applicable
when DIVEN = 1. */
} CLKCFG_b;
} ;
union {
__IOM uint32_t SUBMODCTRL; /*!< (@ 0x00000214) Provides enable for each submodule. Only a sigle
submodule can be enabled at one time. */
struct {
__IOM uint32_t SMOD0EN : 1; /*!< [0..0] Submodule 0 enable (1) or disable (0) */
__IOM uint32_t SMOD0TYPE : 3; /*!< [3..1] Submodule 0 module type. This is the SPI Master interface. */
__IOM uint32_t SMOD1EN : 1; /*!< [4..4] Submodule 1 enable (1) or disable (0) */
__IOM uint32_t SMOD1TYPE : 3; /*!< [7..5] Submodule 0 module type. This is the I2C Master interface */
} SUBMODCTRL_b;
} ;
union {
__IOM uint32_t CMD; /*!< (@ 0x00000218) Writes to this register will start an IO transaction,
as well as set various parameters for the
command itself. Reads will return the command
value written to the CMD register.To read
the number of bytes that have yet to be
transferred, refer to the CTSIZE field within
the CMDSTAT register. */
struct {
__IOM uint32_t CMD : 5; /*!< [4..0] Command for submodule. */
__IOM uint32_t OFFSETCNT : 2; /*!< [6..5] Number of offset bytes to use for the command - 0, 1,
2, 3 are valid selections. The second (byte 1) and third
byte (byte 2) are read from the OFFSETHI register, and
the low order byte is pulled from this register in the
OFFSETLO field.Offset bytes are transmitted highest byte
first. EG if offsetcnt == 3, OFFSETHI[15:8] will be transmitted
first, then OFFSETHI[7:0] then OFFSETLO.If offsetcnt ==
2, OFFSETHI[7:0] will be transmitted, then OFFSETLO.If
offsetcnt == 1, only OFFSETLO will be transmitted. */
__IOM uint32_t CONT : 1; /*!< [7..7] Contine to hold the bus after the current transaction
if set to a 1 with a new command issued. */
__IOM uint32_t TSIZE : 12; /*!< [19..8] Defines the transaction size in bytes. The offset transfer
is not included in this size. */
__IOM uint32_t CMDSEL : 2; /*!< [21..20] Command Specific selection information. Not used in
Master I2C. Used as CEn select for Master SPI transactions */
__IM uint32_t : 2;
__IOM uint32_t OFFSETLO : 8; /*!< [31..24] This register holds the low order byte of offset to
be used in the transaction. The number of offset bytes
to use is set with bits 1:0 of the command. */
} CMD_b;
} ;
union {
__IOM uint32_t DCX; /*!< (@ 0x0000021C) Enables use of CE signals to transmit DCX level
for SPI transactions. Only used in Apollo3
Revision B. For Revision A, this register
MUST NOT be programmed! */
struct {
__IOM uint32_t CE0OUT : 1; /*!< [0..0] Revision A: MUST NOT be programmed! Revision B: Enable
DCX output for CE0 output. */
__IOM uint32_t CE1OUT : 1; /*!< [1..1] Revision A: MUST NOT be programmed! Revision B: Enable
DCX output for CE1 output. */
__IOM uint32_t CE2OUT : 1; /*!< [2..2] Revision A: MUST NOT be programmed! Revision B: Enable
DCX output for CE2 output. */
__IOM uint32_t CE3OUT : 1; /*!< [3..3] Revision A: MUST NOT be programmed! Revision B: Enable
DCX output for CE3 output. */
__IOM uint32_t DCXEN : 1; /*!< [4..4] Revision A: MUST NOT be programmed! Revision B: Bit 4:
DCX Signaling Enable via other CE signals. The selected
DCX signal (unused CE pin) will be driven low during write
of offset byte, and high during transmission of data bytes. */
} DCX_b;
} ;
union {
__IOM uint32_t OFFSETHI; /*!< (@ 0x00000220) High order 2 bytes of 3 byte offset for IO transaction */
struct {
__IOM uint32_t OFFSETHI : 16; /*!< [15..0] Holds the high order 2 bytes of the 3 byte addressing/offset
field to use with IO commands. The number of offset bytes
to use is specified in the command register */
} OFFSETHI_b;
} ;
union {
__IOM uint32_t CMDSTAT; /*!< (@ 0x00000224) Provides staus on the execution of the command
currently in progress. The fields in this
register will reflect the real time status
of the internal state machines and data
transfers within the IOM.These are read
only fields and writes to the registers
are ignored. */
struct {
__IOM uint32_t CCMD : 5; /*!< [4..0] current command that is being executed */
__IOM uint32_t CMDSTAT : 3; /*!< [7..5] The current status of the command execution. */
__IOM uint32_t CTSIZE : 12; /*!< [19..8] The current number of bytes still to be transferred
with this command. This field will count down to zero. */
} CMDSTAT_b;
} ;
__IM uint32_t RESERVED2[6];
union {
__IOM uint32_t DMATRIGEN; /*!< (@ 0x00000240) Provides control on which event will trigger
the DMA transfer after the DMA operation
is setup and enabled. The trigger event
will cause a number of bytes (depending
on trigger event) to betransferred via the
DMA operation, and can be used to adjust
the latency of data to/from the IOM module
to/from the dma target. DMA transfers are
broken into smaller transfers internally
of up to16 bytes each, and multiple trigger
events can be used to complete the entire
programmed DMA transfer. */
struct {
__IOM uint32_t DCMDCMPEN : 1; /*!< [0..0] Trigger DMA upon command complete. Enables the trigger
of the DMA when a command is completed. When this event
is triggered, the number of words transferred will be the
lesser of the remaining TOTCOUNT bytes, or */
__IOM uint32_t DTHREN : 1; /*!< [1..1] Trigger DMA upon THR level reached. For M2P DMA operations
(IOM writes), the trigger will assert when the write FIFO
has (WTHR/4) number of words free in the write FIFO, and
will transfer (WTHR/4) number of wordsor, if the number
of words left to transfer is less than the WTHR value,
will transfer the remaining byte count.For P2M DMA operations,
the trigger will assert when the read FIFO has (RTHR/4)
words available in the read FIFO, and will transfer (RTHR/4)
words to SRAM. This trigger will NOT asser */
} DMATRIGEN_b;
} ;
union {
__IOM uint32_t DMATRIGSTAT; /*!< (@ 0x00000244) Provides the status of trigger events that have
occurred for the transaction. Some of the
bits are read only and some can be reset
via a write of 0. */
struct {
__IOM uint32_t DCMDCMP : 1; /*!< [0..0] Triggered DMA from Command complete event. Bit is read
only and can be cleared by disabling the DCMDCMP trigger
enable or by disabling DMA. */
__IOM uint32_t DTHR : 1; /*!< [1..1] Triggered DMA from THR event. Bit is read only and can
be cleared by disabling the DTHR trigger enable or by disabling
DMA. */
__IOM uint32_t DTOTCMP : 1; /*!< [2..2] DMA triggered when DCMDCMP = 0, and the amount of data
in the FIFO was enough to complete the DMA operation (greater
than or equal to current TOTCOUNT) when the command completed.
This trigger is default active when the DCMDCMP trigger
isdisabled and there is enough data in the FIFO to complete
the DMA operation. */
} DMATRIGSTAT_b;
} ;
__IM uint32_t RESERVED3[14];
union {
__IOM uint32_t DMACFG; /*!< (@ 0x00000280) Configuration control of the DMA process, including
the direction of DMA, and enablement of
DMA */
struct {
__IOM uint32_t DMAEN : 1; /*!< [0..0] DMA Enable. Setting this bit to EN will start the DMA
operation. This should be the last DMA related register
set prior to issuing the command */
__IOM uint32_t DMADIR : 1; /*!< [1..1] Direction */
__IM uint32_t : 6;
__IOM uint32_t DMAPRI : 1; /*!< [8..8] Sets the Priority of the DMA request */
__IOM uint32_t DPWROFF : 1; /*!< [9..9] Power off module after DMA is complete. If this bit is
active, the module will request to power off the supply
it is attached to. If there are other units still requiring
power from the same domain, power down will not be performed. */
} DMACFG_b;
} ;
__IM uint32_t RESERVED4;
union {
__IOM uint32_t DMATOTCOUNT; /*!< (@ 0x00000288) Contains the number of bytes to be transferred
for this DMA transaction. This register
is decremented as the data is transferred,
and will be 0 at the completion of the DMA
operation. */
struct {
__IOM uint32_t TOTCOUNT : 12; /*!< [11..0] Triggered DMA from Command complete event occured. Bit
is read only and can be cleared by disabling the DTHR trigger
enable or by disabling DMA. */
} DMATOTCOUNT_b;
} ;
union {
__IOM uint32_t DMATARGADDR; /*!< (@ 0x0000028C) The source or destination address internal the
SRAM for the DMA data. For write operations,
this can only be SRAM data (ADDR bit 28
= 1); For read operations, this can ve either
SRAM or FLASH (ADDR bit 28 = 0) */
struct {
__IOM uint32_t TARGADDR : 20; /*!< [19..0] Bits [19:0] of the target byte address for source of
DMA (either read or write). The address can be any byte
alignment, and does not have to be word aligned. In cases
of non-word aligned addresses, the DMA logic will take
care for ensuring only the target bytes are read/written. */
__IM uint32_t : 8;
__IOM uint32_t TARGADDR28 : 1; /*!< [28..28] Bit 28 of the target byte address for source of DMA
(either read or write). In cases of non-word aligned addresses,
the DMA logic will take care for ensuring only the target
bytes are read/written.Setting to '1' will select the SRAM.
Setting to '0' will select the flash */
} DMATARGADDR_b;
} ;
union {
__IOM uint32_t DMASTAT; /*!< (@ 0x00000290) Status of the DMA operation currently in progress. */
struct {
__IOM uint32_t DMATIP : 1; /*!< [0..0] DMA Transfer In Progress indicator. 1 will indicate that
a DMA transfer is active. The DMA transfer may be waiting
on data, transferring data, or waiting for priority.All
of these will be indicated with a 1. A 0 will indicate
that the DMA is fully complete and no further transactions
will be done. This bit is read only. */
__IOM uint32_t DMACPL : 1; /*!< [1..1] DMA Transfer Complete. This signals the end of the DMA
operation. This bit can be cleared by writing to 0, and
will also be cleared when a new DMA is started. */
__IOM uint32_t DMAERR : 1; /*!< [2..2] DMA Error. This active high bit signals an error was
encountered during the DMA operation. The bit can be cleared
by writing to 0. Once set, this bit will remain set until
cleared by software. */
} DMASTAT_b;
} ;
union {
__IOM uint32_t CQCFG; /*!< (@ 0x00000294) Controls parameters and options for execution
of the command queue operation. To enable
command queue, create this in memory, set
the address, and enable it with a write
to CQEN */
struct {
__IOM uint32_t CQEN : 1; /*!< [0..0] Command queue enable. When set, will enable the processing
of the command queue and fetches of address/data pairs
will proceed from the word address within the CQADDR register.
Can be disabled using a CQ executed write to this bit as
well. */
__IOM uint32_t CQPRI : 1; /*!< [1..1] Sets the Priority of the command queue dma request */
} CQCFG_b;
} ;
union {
__IOM uint32_t CQADDR; /*!< (@ 0x00000298) The SRAM address which will be fetched next execution
of the CQ operation. This register is updated
as the CQ operation progresses, and is the
live version of the register. The register
can also be written by the Command Queue
operation itself, allowing the relocation
of successive CQ fetches. In this case,
the new CQ address will be used for the
next CQ address/data fetch. */
struct {
__IM uint32_t : 2;
__IOM uint32_t CQADDR : 18; /*!< [19..2] Bits 19:2 of target byte address for source of CQ. The
buffer must be aligned on a word boundary */
__IM uint32_t : 8;
__IOM uint32_t CQADDR28 : 1; /*!< [28..28] Bit 28 of target byte address for source of CQ. Used
to denote Flash (0) or SRAM (1) access */
} CQADDR_b;
} ;
union {
__IOM uint32_t CQSTAT; /*!< (@ 0x0000029C) Provides the status of the command queue operation.
If the command queue is disabled, these
bits will be cleared. The bits are read
only */
struct {
__IOM uint32_t CQTIP : 1; /*!< [0..0] Command queue Transfer In Progress indicator. 1 will
indicate that a CQ transfer is active and this will remain
active even when paused waiting for external event. */
__IOM uint32_t CQPAUSED : 1; /*!< [1..1] Command queue operation is currently paused. */
__IOM uint32_t CQERR : 1; /*!< [2..2] Command queue processing Error. This active high bit
signals that an error was encountered during the CQ operation. */
} CQSTAT_b;
} ;
union {
__IOM uint32_t CQFLAGS; /*!< (@ 0x000002A0) Command Queue Flag Register */
struct {
__IOM uint32_t CQFLAGS : 16; /*!< [15..0] Current flag status (read-only). Bits [7:0] are software
controllable and bits [15:8] are hardware status. */
__IOM uint32_t CQIRQMASK : 16; /*!< [31..16] Mask the bits used to generate the command queue interrupt.
A '1' in the bit position will enable the pause event to
trigger the interrupt, if the CQWT_int interrupt is enabled.
Bits definitions are the same as CQPAUSE */
} CQFLAGS_b;
} ;
union {
__IOM uint32_t CQSETCLEAR; /*!< (@ 0x000002A4) Set/Clear the command queue software pause flags
on a per-bit basis. Contains 3 fields, allowing
for setting, clearing or toggling the value
in the software flags. Priority when the
same bitis enabled in each field is toggle,
then set, then clear. */
struct {
__IOM uint32_t CQFSET : 8; /*!< [7..0] Set CQFlag status bits. Will set to 1 the value of any
SWFLAG with a '1' in the corresponding bit position of
this field */
__IOM uint32_t CQFTGL : 8; /*!< [15..8] Toggle the indicated bit. Will toggle the value of any
SWFLAG with a '1' in the corresponding bit position of
this field */
__IOM uint32_t CQFCLR : 8; /*!< [23..16] Clear CQFlag status bits. Will clear to 0 any SWFLAG
with a '1' in the corresponding bit position of this field */
} CQSETCLEAR_b;
} ;
union {
__IOM uint32_t CQPAUSEEN; /*!< (@ 0x000002A8) Enables a flag to pause an active command queue
operation. If a bit is '1' and the corresponding
bit in the CQFLAG register is '1', CQ processing
will halt until either value is changed
to '0'. */
struct {
__IOM uint32_t CQPEN : 16; /*!< [15..0] Enables the specified event to pause command processing
when active */
} CQPAUSEEN_b;
} ;
union {
__IOM uint32_t CQCURIDX; /*!< (@ 0x000002AC) Current index value, targeted to be written by
register write operations within the command
queue. This is compared to the CQENDIDX
and will stop the CQ operation if bit 15
of the CQPAUSEEN is '1' andthis current
index equals the CQENDIDX register value.
This will only pause when the values are
equal. */
struct {
__IOM uint32_t CQCURIDX : 8; /*!< [7..0] Holds 8 bits of data that will be compared with the CQENDIX
register field. If the values match, the IDXEQ pause event
will be activated, which will cause the pausing of command
quue operation if the IDXEQ bit is enabled in CQPAUSEEN. */
} CQCURIDX_b;
} ;
union {
__IOM uint32_t CQENDIDX; /*!< (@ 0x000002B0) End index value, targeted to be written by software
to indicate the last valid register pair
contained within the command queue. rgister
write operations within the command queue.This
is compared to the CQCURIDX and will stop
the CQ operation if bit 15 of the CQPAUSEEN
is '1' andthis current index equals the
CQCURIDX register value. This will only
pause when the values are equal. */
struct {
__IOM uint32_t CQENDIDX : 8; /*!< [7..0] Holds 8 bits of data that will be compared with the CQCURIX
register field. If the values match, the IDXEQ pause event
will be activated, which will cause the pausing of command
quue operation if the IDXEQ bit is enabled in CQPAUSEEN. */
} CQENDIDX_b;
} ;
union {
__IOM uint32_t STATUS; /*!< (@ 0x000002B4) IOM Module Status Register */
struct {
__IOM uint32_t ERR : 1; /*!< [0..0] Bit has been deprecated. Please refer to the other error
indicators. This will always return 0. */
__IOM uint32_t CMDACT : 1; /*!< [1..1] Indicates if the active I/O Command is currently processing
a transaction, or command is complete, but the FIFO pointers
are still syncronizing internally. This bit will go high
atthe start of the transaction, and will go low when the
command is complete, and the data and pointers within the
FIFO have been syncronized. */
__IOM uint32_t IDLEST : 1; /*!< [2..2] indicates if the active I/O state machine is IDLE. Note
- The state machine could be in idle state due to holdoffs
from data availability, or as the command gets propagated
into the logic from the registers. */
} STATUS_b;
} ;
__IM uint32_t RESERVED5[18];
union {
__IOM uint32_t MSPICFG; /*!< (@ 0x00000300) Controls the configuration of the SPI master
module, including POL/PHA, LSB, flow control,
and delays for MISO and MOSI */
struct {
__IOM uint32_t SPOL : 1; /*!< [0..0] selects SPI polarity. */
__IOM uint32_t SPHA : 1; /*!< [1..1] selects SPI phase. */
__IOM uint32_t FULLDUP : 1; /*!< [2..2] Enables full duplex mode for Master SPI write operations.
Data will be captured simultaneously into the read fifo */
__IM uint32_t : 13;
__IOM uint32_t WTFC : 1; /*!< [16..16] enables write mode flow control. */
__IOM uint32_t RDFC : 1; /*!< [17..17] enables read mode flow control. */
__IOM uint32_t MOSIINV : 1; /*!< [18..18] inverts MOSI when flow control is enabled. */
__IM uint32_t : 1;
__IOM uint32_t WTFCIRQ : 1; /*!< [20..20] selects the write mode flow control signal. */
__IOM uint32_t WTFCPOL : 1; /*!< [21..21] selects the write flow control signal polarity. The
transfers are halted when the selected flow control signal
is OPPOSITE polarity of bit. (For example: WTFCPOL = 0
will allow a IRQ=1 to pause transfers). */
__IOM uint32_t RDFCPOL : 1; /*!< [22..22] selects the read flow control signal polarity. */
__IOM uint32_t SPILSB : 1; /*!< [23..23] Selects data transfer as MSB first (0) or LSB first
(1) for the data portion of the SPI transaction. The offset
bytes are always transmitted MSB first. */
__IOM uint32_t DINDLY : 3; /*!< [26..24] Delay tap to use for the input signal (MISO). This
gives more hold time on the input data. */
__IOM uint32_t DOUTDLY : 3; /*!< [29..27] Delay tap to use for the output signal (MOSI). This
give more hold time on the output data */
__IOM uint32_t MSPIRST : 1; /*!< [30..30] Not used. To reset the module, toggle the SMOD_EN for
the module */
} MSPICFG_b;
} ;
__IM uint32_t RESERVED6[63];
union {
__IOM uint32_t MI2CCFG; /*!< (@ 0x00000400) Controls the configuration of the I2C bus master. */
struct {
__IOM uint32_t ADDRSZ : 1; /*!< [0..0] Sets the I2C master device address size to either 7b
(0) or 10b (1). */
__IOM uint32_t I2CLSB : 1; /*!< [1..1] Direction of data transmit and receive, MSB(0) or LSB(1)
first. Default per I2C specification is MSB first. This
applies to both read and write data, and read data will
be bit */
__IOM uint32_t ARBEN : 1; /*!< [2..2] Enables multi-master arbitration for the I2C master.
If the bus is known to have only a single master, this
function can be disabled to save clock cycles on I2C transactions */
__IM uint32_t : 1;
__IOM uint32_t SDADLY : 2; /*!< [5..4] Delay to enable on the SDA output. Values are 0x0-0x3. */
__IOM uint32_t MI2CRST : 1; /*!< [6..6] Not used. To reset the module, toggle the SMOD_EN for
the module */
__IM uint32_t : 1;
__IOM uint32_t SCLENDLY : 4; /*!< [11..8] Number of IOCLK cycles to delay the rising edge of the
SCL output en (clock will go low on this edge). Used to
allow clock shaping. */
__IOM uint32_t SDAENDLY : 4; /*!< [15..12] Number of IOCLK cycles to delay the SDA output en (all
transitions affected). Used to delay data relative to clock */
__IOM uint32_t SMPCNT : 8; /*!< [23..16] Number of Base clk cycles to wait before sampling the
SCL clock to determine if a clock stretch event has occured */
__IOM uint32_t STRDIS : 1; /*!< [24..24] Disable detection of clock stretch events smaller than
1 cycle */
} MI2CCFG_b;
} ;
union {
__IOM uint32_t DEVCFG; /*!< (@ 0x00000404) Contains the I2C device address. */
struct {
__IOM uint32_t DEVADDR : 10; /*!< [9..0] I2C address of the device that the Master will use to
target for read/write operations. This can be either a
7b or 10b address. */
} DEVCFG_b;
} ;
__IM uint32_t RESERVED7[2];
union {
__IOM uint32_t IOMDBG; /*!< (@ 0x00000410) Debug control */
struct {
__IOM uint32_t DBGEN : 1; /*!< [0..0] Debug Enable. Setting bit will enable the update of data
within this register, otherwise it is clock gated for power
savings */
__IOM uint32_t IOCLKON : 1; /*!< [1..1] IOCLK debug clock control. Enable IO_CLK to be active
when this bit is '1'. Otherwise, the clock is controlled
with gating from the logic as needed. */
__IOM uint32_t APBCLKON : 1; /*!< [2..2] APBCLK debug clock control. Enable APB_CLK to be active
when this bit is '1'. Otherwise, the clock is controlled
with gating from the logic as needed. */
__IOM uint32_t DBGDATA : 29; /*!< [31..3] Debug control for various options. DBGDATA[1:0] is used
to select between different debug data available in the
DBG0 and DBG1 registers. */
} IOMDBG_b;
} ;
} IOM0_Type; /*!< Size = 1044 (0x414) */
/* =========================================================================================================================== */
/* ================ IOSLAVE ================ */
/* =========================================================================================================================== */
/**
* @brief I2C/SPI Slave (IOSLAVE)
*/
typedef struct { /*!< (@ 0x50000000) IOSLAVE Structure */
__IM uint32_t RESERVED[64];
union {
__IOM uint32_t FIFOPTR; /*!< (@ 0x00000100) Current FIFO Pointer */
struct {
__IOM uint32_t FIFOPTR : 8; /*!< [7..0] Current FIFO pointer. */
__IOM uint32_t FIFOSIZ : 8; /*!< [15..8] The number of bytes currently in the hardware FIFO. */
} FIFOPTR_b;
} ;
union {
__IOM uint32_t FIFOCFG; /*!< (@ 0x00000104) FIFO Configuration */
struct {
__IOM uint32_t FIFOBASE : 5; /*!< [4..0] These bits hold the base address of the I/O FIFO in 8
byte segments. The IO Slave FIFO is situated in LRAM at
(FIFOBASE*8) to (FIFOMAX*8-1). */
__IM uint32_t : 3;
__IOM uint32_t FIFOMAX : 6; /*!< [13..8] These bits hold the maximum FIFO address in 8 byte segments.
It is also the beginning of the RAM area of the LRAM. Note
that no RAM area is configured if FIFOMAX is set to 0x1F. */
__IM uint32_t : 10;
__IOM uint32_t ROBASE : 6; /*!< [29..24] Defines the read-only area. The IO Slave read-only
area is situated in LRAM at (ROBASE*8) to (FIFOBASE*8-1) */
} FIFOCFG_b;
} ;
union {
__IOM uint32_t FIFOTHR; /*!< (@ 0x00000108) FIFO Threshold Configuration */
struct {
__IOM uint32_t FIFOTHR : 8; /*!< [7..0] FIFO size interrupt threshold. */
} FIFOTHR_b;
} ;
union {
__IOM uint32_t FUPD; /*!< (@ 0x0000010C) FIFO Update Status */
struct {
__IOM uint32_t FIFOUPD : 1; /*!< [0..0] This bit indicates that a FIFO update is underway. */
__IOM uint32_t IOREAD : 1; /*!< [1..1] This bitfield indicates an IO read is active. */
} FUPD_b;
} ;
union {
__IOM uint32_t FIFOCTR; /*!< (@ 0x00000110) Overall FIFO Counter */
struct {
__IOM uint32_t FIFOCTR : 10; /*!< [9..0] Virtual FIFO byte count */
} FIFOCTR_b;
} ;
union {
__IOM uint32_t FIFOINC; /*!< (@ 0x00000114) Overall FIFO Counter Increment */
struct {
__IOM uint32_t FIFOINC : 10; /*!< [9..0] Increment the Overall FIFO Counter by this value on a
write */
} FIFOINC_b;
} ;
union {
__IOM uint32_t CFG; /*!< (@ 0x00000118) I/O Slave Configuration */
struct {
__IOM uint32_t IFCSEL : 1; /*!< [0..0] This bit selects the I/O interface. */
__IOM uint32_t SPOL : 1; /*!< [1..1] This bit selects SPI polarity. */
__IOM uint32_t LSB : 1; /*!< [2..2] This bit selects the transfer bit ordering. */
__IM uint32_t : 1;
__IOM uint32_t STARTRD : 1; /*!< [4..4] This bit holds the cycle to initiate an I/O RAM read. */
__IM uint32_t : 3;
__IOM uint32_t I2CADDR : 12; /*!< [19..8] 7-bit or 10-bit I2C device address. */
__IM uint32_t : 11;
__IOM uint32_t IFCEN : 1; /*!< [31..31] IOSLAVE interface enable. */
} CFG_b;
} ;
union {
__IOM uint32_t PRENC; /*!< (@ 0x0000011C) I/O Slave Interrupt Priority Encode */
struct {
__IOM uint32_t PRENC : 5; /*!< [4..0] These bits hold the priority encode of the REGACC interrupts. */
} PRENC_b;
} ;
union {
__IOM uint32_t IOINTCTL; /*!< (@ 0x00000120) I/O Interrupt Control */
struct {
__IOM uint32_t IOINTEN : 8; /*!< [7..0] These read-only bits indicate whether the IOINT interrupts
are enabled. */
__IOM uint32_t IOINT : 8; /*!< [15..8] These bits read the IOINT interrupts. */
__IOM uint32_t IOINTCLR : 1; /*!< [16..16] This bit clears all of the IOINT interrupts when written
with a 1. */
__IM uint32_t : 7;
__IOM uint32_t IOINTSET : 8; /*!< [31..24] These bits set the IOINT interrupts when written with
a 1. */
} IOINTCTL_b;
} ;
union {
__IOM uint32_t GENADD; /*!< (@ 0x00000124) General Address Data */
struct {
__IOM uint32_t GADATA : 8; /*!< [7..0] The data supplied on the last General Address reference. */
} GENADD_b;
} ;
__IM uint32_t RESERVED1[54];
union {
__IOM uint32_t INTEN; /*!< (@ 0x00000200) Set bits in this register to allow this module
to generate the corresponding interrupt. */
struct {
__IOM uint32_t FSIZE : 1; /*!< [0..0] FIFO Size interrupt. */
__IOM uint32_t FOVFL : 1; /*!< [1..1] FIFO Overflow interrupt. */
__IOM uint32_t FUNDFL : 1; /*!< [2..2] FIFO Underflow interrupt. */
__IOM uint32_t FRDERR : 1; /*!< [3..3] FIFO Read Error interrupt. */
__IOM uint32_t GENAD : 1; /*!< [4..4] I2C General Address interrupt. */
__IOM uint32_t IOINTW : 1; /*!< [5..5] IO Write interrupt. */
__IOM uint32_t XCMPRF : 1; /*!< [6..6] Transfer complete interrupt, read from FIFO space. */
__IOM uint32_t XCMPRR : 1; /*!< [7..7] Transfer complete interrupt, read from register space. */
__IOM uint32_t XCMPWF : 1; /*!< [8..8] Transfer complete interrupt, write to FIFO space. */
__IOM uint32_t XCMPWR : 1; /*!< [9..9] Transfer complete interrupt, write to register space. */
} INTEN_b;
} ;
union {
__IOM uint32_t INTSTAT; /*!< (@ 0x00000204) Read bits from this register to discover the
cause of a recent interrupt. */
struct {
__IOM uint32_t FSIZE : 1; /*!< [0..0] FIFO Size interrupt. */
__IOM uint32_t FOVFL : 1; /*!< [1..1] FIFO Overflow interrupt. */
__IOM uint32_t FUNDFL : 1; /*!< [2..2] FIFO Underflow interrupt. */
__IOM uint32_t FRDERR : 1; /*!< [3..3] FIFO Read Error interrupt. */
__IOM uint32_t GENAD : 1; /*!< [4..4] I2C General Address interrupt. */
__IOM uint32_t IOINTW : 1; /*!< [5..5] IO Write interrupt. */
__IOM uint32_t XCMPRF : 1; /*!< [6..6] Transfer complete interrupt, read from FIFO space. */
__IOM uint32_t XCMPRR : 1; /*!< [7..7] Transfer complete interrupt, read from register space. */
__IOM uint32_t XCMPWF : 1; /*!< [8..8] Transfer complete interrupt, write to FIFO space. */
__IOM uint32_t XCMPWR : 1; /*!< [9..9] Transfer complete interrupt, write to register space. */
} INTSTAT_b;
} ;
union {
__IOM uint32_t INTCLR; /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
the interrupt status associated with that
bit. */
struct {
__IOM uint32_t FSIZE : 1; /*!< [0..0] FIFO Size interrupt. */
__IOM uint32_t FOVFL : 1; /*!< [1..1] FIFO Overflow interrupt. */
__IOM uint32_t FUNDFL : 1; /*!< [2..2] FIFO Underflow interrupt. */
__IOM uint32_t FRDERR : 1; /*!< [3..3] FIFO Read Error interrupt. */
__IOM uint32_t GENAD : 1; /*!< [4..4] I2C General Address interrupt. */
__IOM uint32_t IOINTW : 1; /*!< [5..5] IO Write interrupt. */
__IOM uint32_t XCMPRF : 1; /*!< [6..6] Transfer complete interrupt, read from FIFO space. */
__IOM uint32_t XCMPRR : 1; /*!< [7..7] Transfer complete interrupt, read from register space. */
__IOM uint32_t XCMPWF : 1; /*!< [8..8] Transfer complete interrupt, write to FIFO space. */
__IOM uint32_t XCMPWR : 1; /*!< [9..9] Transfer complete interrupt, write to register space. */
} INTCLR_b;
} ;
union {
__IOM uint32_t INTSET; /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
generate an interrupt from this module.
(Generally used for testing purposes). */
struct {
__IOM uint32_t FSIZE : 1; /*!< [0..0] FIFO Size interrupt. */
__IOM uint32_t FOVFL : 1; /*!< [1..1] FIFO Overflow interrupt. */
__IOM uint32_t FUNDFL : 1; /*!< [2..2] FIFO Underflow interrupt. */
__IOM uint32_t FRDERR : 1; /*!< [3..3] FIFO Read Error interrupt. */
__IOM uint32_t GENAD : 1; /*!< [4..4] I2C General Address interrupt. */
__IOM uint32_t IOINTW : 1; /*!< [5..5] IO Write interrupt. */
__IOM uint32_t XCMPRF : 1; /*!< [6..6] Transfer complete interrupt, read from FIFO space. */
__IOM uint32_t XCMPRR : 1; /*!< [7..7] Transfer complete interrupt, read from register space. */
__IOM uint32_t XCMPWF : 1; /*!< [8..8] Transfer complete interrupt, write to FIFO space. */
__IOM uint32_t XCMPWR : 1; /*!< [9..9] Transfer complete interrupt, write to register space. */
} INTSET_b;
} ;
union {
__IOM uint32_t REGACCINTEN; /*!< (@ 0x00000210) Set bits in this register to allow this module
to generate the corresponding interrupt. */
struct {
__IOM uint32_t REGACC : 32; /*!< [31..0] Register access interrupts. */
} REGACCINTEN_b;
} ;
union {
__IOM uint32_t REGACCINTSTAT; /*!< (@ 0x00000214) Read bits from this register to discover the
cause of a recent interrupt. */
struct {
__IOM uint32_t REGACC : 32; /*!< [31..0] Register access interrupts. */
} REGACCINTSTAT_b;
} ;
union {
__IOM uint32_t REGACCINTCLR; /*!< (@ 0x00000218) Write a 1 to a bit in this register to clear
the interrupt status associated with that
bit. */
struct {
__IOM uint32_t REGACC : 32; /*!< [31..0] Register access interrupts. */
} REGACCINTCLR_b;
} ;
union {
__IOM uint32_t REGACCINTSET; /*!< (@ 0x0000021C) Write a 1 to a bit in this register to instantly
generate an interrupt from this module.
(Generally used for testing purposes). */
struct {
__IOM uint32_t REGACC : 32; /*!< [31..0] Register access interrupts. */
} REGACCINTSET_b;
} ;
} IOSLAVE_Type; /*!< Size = 544 (0x220) */
/* =========================================================================================================================== */
/* ================ MCUCTRL ================ */
/* =========================================================================================================================== */
/**
* @brief MCU Miscellaneous Control Logic (MCUCTRL)
*/
typedef struct { /*!< (@ 0x40020000) MCUCTRL Structure */
union {
__IOM uint32_t CHIPPN; /*!< (@ 0x00000000) Chip Information Register */
struct {
__IOM uint32_t PARTNUM : 32; /*!< [31..0] BCD part number. */
} CHIPPN_b;
} ;
union {
__IOM uint32_t CHIPID0; /*!< (@ 0x00000004) Unique Chip ID 0 */
struct {
__IOM uint32_t CHIPID0 : 32; /*!< [31..0] Unique chip ID 0. */
} CHIPID0_b;
} ;
union {
__IOM uint32_t CHIPID1; /*!< (@ 0x00000008) Unique Chip ID 1 */
struct {
__IOM uint32_t CHIPID1 : 32; /*!< [31..0] Unique chip ID 1. */
} CHIPID1_b;
} ;
union {
__IOM uint32_t CHIPREV; /*!< (@ 0x0000000C) Chip Revision */
struct {
__IOM uint32_t REVMIN : 4; /*!< [3..0] Minor Revision ID. */
__IOM uint32_t REVMAJ : 4; /*!< [7..4] Major Revision ID. */
__IOM uint32_t SIPART : 12; /*!< [19..8] Silicon Part ID */
} CHIPREV_b;
} ;
union {
__IOM uint32_t VENDORID; /*!< (@ 0x00000010) Unique Vendor ID */
struct {
__IOM uint32_t VENDORID : 32; /*!< [31..0] Unique Vendor ID */
} VENDORID_b;
} ;
union {
__IOM uint32_t SKU; /*!< (@ 0x00000014) Unique Chip SKU */
struct {
__IOM uint32_t ALLOWBURST : 1; /*!< [0..0] Allow Burst feature */
__IOM uint32_t ALLOWBLE : 1; /*!< [1..1] Allow BLE feature */
__IOM uint32_t SECBOOT : 1; /*!< [2..2] Secure boot feature allowed */
} SKU_b;
} ;
union {
__IOM uint32_t FEATUREENABLE; /*!< (@ 0x00000018) Feature Enable on Burst and BLE */
struct {
__IOM uint32_t BLEREQ : 1; /*!< [0..0] Controls the BLE functionality */
__IOM uint32_t BLEACK : 1; /*!< [1..1] ACK for BLEREQ */
__IOM uint32_t BLEAVAIL : 1; /*!< [2..2] AVAILABILITY of the BLE functionality */
__IM uint32_t : 1;
__IOM uint32_t BURSTREQ : 1; /*!< [4..4] Controls the Burst functionality */
__IOM uint32_t BURSTACK : 1; /*!< [5..5] ACK for BURSTREQ */
__IOM uint32_t BURSTAVAIL : 1; /*!< [6..6] Availability of Burst functionality */
} FEATUREENABLE_b;
} ;
__IM uint32_t RESERVED;
union {
__IOM uint32_t DEBUGGER; /*!< (@ 0x00000020) Debugger Control */
struct {
__IOM uint32_t LOCKOUT : 1; /*!< [0..0] Lockout of debugger (SWD). */
} DEBUGGER_b;
} ;
__IM uint32_t RESERVED1[55];
union {
__IOM uint32_t BODCTRL; /*!< (@ 0x00000100) BOD control Register */
struct {
__IOM uint32_t BODLPWD : 1; /*!< [0..0] BODL Power Down. */
__IOM uint32_t BODHPWD : 1; /*!< [1..1] BODH Power Down. */
__IOM uint32_t BODCPWD : 1; /*!< [2..2] BODC Power Down. */
__IOM uint32_t BODFPWD : 1; /*!< [3..3] BODF Power Down. */
__IOM uint32_t BODLVREFSEL : 1; /*!< [4..4] BODL External Reference Select. Note: the SWE mux select
in PWRSEQ2SWE must be set for this to take effect. */
__IOM uint32_t BODHVREFSEL : 1; /*!< [5..5] BODH External Reference Select. Note: the SWE mux select
in PWRSEQ2SWE must be set for this to take effect. */
} BODCTRL_b;
} ;
union {
__IOM uint32_t ADCPWRDLY; /*!< (@ 0x00000104) ADC Power Up Delay Control */
struct {
__IOM uint32_t ADCPWR0 : 8; /*!< [7..0] ADC Reference Buffer Power Enable delay in 64 ADC CLK
increments for ADC_CLKSEL = 0x1, 32 ADC CLOCK increments
for ADC_CLKSEL = 0x2. */
__IOM uint32_t ADCPWR1 : 8; /*!< [15..8] ADC Reference Keeper enable delay in 16 ADC CLK increments
for ADC_CLKSEL = 0x1, 8 ADC CLOCK increments for ADC_CLKSEL
= 0x2. */
} ADCPWRDLY_b;
} ;
__IM uint32_t RESERVED2;
union {
__IOM uint32_t ADCCAL; /*!< (@ 0x0000010C) ADC Calibration Control */
struct {
__IOM uint32_t CALONPWRUP : 1; /*!< [0..0] Run ADC Calibration on initial power up sequence */
__IOM uint32_t ADCCALIBRATED : 1; /*!< [1..1] Status for ADC Calibration */
} ADCCAL_b;
} ;
union {
__IOM uint32_t ADCBATTLOAD; /*!< (@ 0x00000110) ADC Battery Load Enable */
struct {
__IOM uint32_t BATTLOAD : 1; /*!< [0..0] Enable the ADC battery load resistor */
} ADCBATTLOAD_b;
} ;
__IM uint32_t RESERVED3;
union {
__IOM uint32_t ADCTRIM; /*!< (@ 0x00000118) ADC Trims */
struct {
__IOM uint32_t ADCREFKEEPIBTRIM : 2; /*!< [1..0] ADC Reference Ibias trim */
__IM uint32_t : 4;
__IOM uint32_t ADCREFBUFTRIM : 5; /*!< [10..6] ADC Reference buffer trim */
__IOM uint32_t ADCRFBUFIBTRIM : 2; /*!< [12..11] ADC reference buffer input bias trim */
} ADCTRIM_b;
} ;
union {
__IOM uint32_t ADCREFCOMP; /*!< (@ 0x0000011C) ADC Reference Keeper and Comparator Control */
struct {
__IOM uint32_t ADC_REFCOMP_OUT : 1; /*!< [0..0] Output of the ADC reference comparator */
__IM uint32_t : 7;
__IOM uint32_t ADCREFKEEPTRIM : 5; /*!< [12..8] ADC Reference Keeper Trim */
__IM uint32_t : 3;
__IOM uint32_t ADCRFCMPEN : 1; /*!< [16..16] ADC Reference comparator power down */
} ADCREFCOMP_b;
} ;
union {
__IOM uint32_t XTALCTRL; /*!< (@ 0x00000120) XTAL Oscillator Control */
struct {
__IOM uint32_t XTALSWE : 1; /*!< [0..0] XTAL Software Override Enable. */
__IOM uint32_t FDBKDSBLXTAL : 1; /*!< [1..1] XTAL Oscillator Disable Feedback. */
__IOM uint32_t BYPCMPRXTAL : 1; /*!< [2..2] XTAL Oscillator Bypass Comparator. */
__IOM uint32_t PDNBCOREXTAL : 1; /*!< [3..3] XTAL Oscillator Power Down Core. */
__IOM uint32_t PDNBCMPRXTAL : 1; /*!< [4..4] XTAL Oscillator Power Down Comparator. */
__IOM uint32_t PWDBODXTAL : 1; /*!< [5..5] XTAL Power down on brown out. */
__IOM uint32_t XTALIBUFTRIM : 2; /*!< [7..6] XTAL IBUFF trim */
__IOM uint32_t XTALICOMPTRIM : 2; /*!< [9..8] XTAL ICOMP trim */
} XTALCTRL_b;
} ;
union {
__IOM uint32_t XTALGENCTRL; /*!< (@ 0x00000124) XTAL Oscillator General Control */
struct {
__IOM uint32_t ACWARMUP : 2; /*!< [1..0] Auto-calibration delay control */
__IOM uint32_t XTALBIASTRIM : 6; /*!< [7..2] XTAL BIAS trim */
__IOM uint32_t XTALKSBIASTRIM : 6; /*!< [13..8] XTAL IBIAS Kick start trim. This trim value is used
during the startup process to enable a faster lock. */
} XTALGENCTRL_b;
} ;
__IM uint32_t RESERVED4[28];
union {
__IOM uint32_t MISCCTRL; /*!< (@ 0x00000198) Miscellaneous control register. */
struct {
__IOM uint32_t RESERVED_RW_0 : 5; /*!< [4..0] Reserved bits, always leave unchanged. The MISCCTRL register
must be modified via atomic RMW, leaving this bit field
completely unmodified. Failure to do so will result in
unpredictable behavior. */
__IOM uint32_t BLE_RESETN : 1; /*!< [5..5] BLE reset signal. */
} MISCCTRL_b;
} ;
__IM uint32_t RESERVED5;
union {
__IOM uint32_t BOOTLOADER; /*!< (@ 0x000001A0) Bootloader and secure boot functions */
struct {
__IOM uint32_t BOOTLOADERLOW : 1; /*!< [0..0] Determines whether the bootloader code is visible at
address 0x00000000 or not. Resets to 1, write 1 to clear. */
__IOM uint32_t SBLOCK : 1; /*!< [1..1] Secure boot lock. Always resets to 1, write 1 to clear.
Enables system visibility to bootloader until set. */
__IOM uint32_t PROTLOCK : 1; /*!< [2..2] Flash protection lock. Always resets to 1, write 1 to
clear. Enables writes to flash protection register set. */
__IM uint32_t : 23;
__IOM uint32_t SECBOOTFEATURE : 2; /*!< [27..26] Indicates whether the secure boot feature is enabled. */
__IOM uint32_t SECBOOT : 2; /*!< [29..28] Indicates whether the secure boot on cold reset is
enabled */
__IOM uint32_t SECBOOTONRST : 2; /*!< [31..30] Indicates whether the secure boot on warm reset is
enabled */
} BOOTLOADER_b;
} ;
union {
__IOM uint32_t SHADOWVALID; /*!< (@ 0x000001A4) Register to indicate whether the shadow registers
have been successfully loaded from the Flash
Information Space. */
struct {
__IOM uint32_t VALID : 1; /*!< [0..0] Indicates whether the shadow registers contain valid
data from the Flash Information Space. */
__IOM uint32_t BLDSLEEP : 1; /*!< [1..1] Indicates whether the bootloader should sleep or deep
sleep if no image loaded. */
__IOM uint32_t INFO0_VALID : 1; /*!< [2..2] Indicates whether INFO0 contains valid data */
} SHADOWVALID_b;
} ;
__IM uint32_t RESERVED6[2];
union {
__IOM uint32_t SCRATCH0; /*!< (@ 0x000001B0) Scratch register that is not reset by any reset */
struct {
__IOM uint32_t SCRATCH0 : 32; /*!< [31..0] Scratch register 0. */
} SCRATCH0_b;
} ;
union {
__IOM uint32_t SCRATCH1; /*!< (@ 0x000001B4) Scratch register that is not reset by any reset */
struct {
__IOM uint32_t SCRATCH1 : 32; /*!< [31..0] Scratch register 1. */
} SCRATCH1_b;
} ;
__IM uint32_t RESERVED7[2];
union {
__IOM uint32_t ICODEFAULTADDR; /*!< (@ 0x000001C0) ICODE bus address which was present when a bus
fault occurred. */
struct {
__IOM uint32_t ICODEFAULTADDR : 32; /*!< [31..0] The ICODE bus address observed when a Bus Fault occurred.
Once an address is captured in this field, it is held until
the corresponding Fault Observed bit is cleared in the
FAULTSTATUS register. */
} ICODEFAULTADDR_b;
} ;
union {
__IOM uint32_t DCODEFAULTADDR; /*!< (@ 0x000001C4) DCODE bus address which was present when a bus
fault occurred. */
struct {
__IOM uint32_t DCODEFAULTADDR : 32; /*!< [31..0] The DCODE bus address observed when a Bus Fault occurred.
Once an address is captured in this field, it is held until
the corresponding Fault Observed bit is cleared in the
FAULTSTATUS register. */
} DCODEFAULTADDR_b;
} ;
union {
__IOM uint32_t SYSFAULTADDR; /*!< (@ 0x000001C8) System bus address which was present when a bus
fault occurred. */
struct {
__IOM uint32_t SYSFAULTADDR : 32; /*!< [31..0] SYS bus address observed when a Bus Fault occurred.
Once an address is captured in this field, it is held until
the corresponding Fault Observed bit is cleared in the
FAULTSTATUS register. */
} SYSFAULTADDR_b;
} ;
union {
__IOM uint32_t FAULTSTATUS; /*!< (@ 0x000001CC) Reflects the status of the bus decoders' fault
detection. Any write to this register will
clear all of the status bits within the
register. */
struct {
__IOM uint32_t ICODEFAULT : 1; /*!< [0..0] The ICODE Bus Decoder Fault Detected bit. When set, a
fault has been detected, and the ICODEFAULTADDR register
will contain the bus address which generated the fault. */
__IOM uint32_t DCODEFAULT : 1; /*!< [1..1] DCODE Bus Decoder Fault Detected bit. When set, a fault
has been detected, and the DCODEFAULTADDR register will
contain the bus address which generated the fault. */
__IOM uint32_t SYSFAULT : 1; /*!< [2..2] SYS Bus Decoder Fault Detected bit. When set, a fault
has been detected, and the SYSFAULTADDR register will contain
the bus address which generated the fault. */
} FAULTSTATUS_b;
} ;
union {
__IOM uint32_t FAULTCAPTUREEN; /*!< (@ 0x000001D0) Enable the fault capture registers */
struct {
__IOM uint32_t FAULTCAPTUREEN : 1; /*!< [0..0] Fault Capture Enable field. When set, the Fault Capture
monitors are enabled and addresses which generate a hard
fault are captured into the FAULTADDR registers. */
} FAULTCAPTUREEN_b;
} ;
__IM uint32_t RESERVED8[11];
union {
__IOM uint32_t DBGR1; /*!< (@ 0x00000200) Read-only debug register 1 */
struct {
__IOM uint32_t ONETO8 : 32; /*!< [31..0] Read-only register for communication validation */
} DBGR1_b;
} ;
union {
__IOM uint32_t DBGR2; /*!< (@ 0x00000204) Read-only debug register 2 */
struct {
__IOM uint32_t COOLCODE : 32; /*!< [31..0] Read-only register for communication validation */
} DBGR2_b;
} ;
__IM uint32_t RESERVED9[6];
union {
__IOM uint32_t PMUENABLE; /*!< (@ 0x00000220) Control bit to enable/disable the PMU */
struct {
__IOM uint32_t ENABLE : 1; /*!< [0..0] PMU Enable Control bit. When set, the MCU's PMU will
place the MCU into the lowest power consuming Deep Sleep
mode upon execution of a WFI instruction (dependent on
the setting of the SLEEPDEEP bit in the ARM SCR register).
When cleared, regardless of the requested sleep mode, the
PMU will not enter the lowest power Deep Sleep mode, instead
entering the Sleep mode. */
} PMUENABLE_b;
} ;
__IM uint32_t RESERVED10[11];
union {
__IOM uint32_t TPIUCTRL; /*!< (@ 0x00000250) TPIU Control Register. Determines the clock enable
and frequency for the M4's TPIU interface. */
struct {
__IOM uint32_t ENABLE : 1; /*!< [0..0] TPIU Enable field. When set, the ARM M4 TPIU is enabled
and data can be streamed out of the MCU's SWO port using
the ARM ITM and TPIU modules. */
__IM uint32_t : 7;
__IOM uint32_t CLKSEL : 3; /*!< [10..8] This field selects the frequency of the ARM M4 TPIU
port. */
} TPIUCTRL_b;
} ;
__IM uint32_t RESERVED11[4];
union {
__IOM uint32_t OTAPOINTER; /*!< (@ 0x00000264) OTA (Over the Air) Update Pointer/Status. Reset
only by POA */
struct {
__IOM uint32_t OTAVALID : 1; /*!< [0..0] Indicates that an OTA update is valid */
__IOM uint32_t OTASBLUPDATE : 1; /*!< [1..1] Indicates that the sbl_init has been updated */
__IOM uint32_t OTAPOINTER : 30; /*!< [31..2] Flash page pointer with updated OTA image */
} OTAPOINTER_b;
} ;
__IM uint32_t RESERVED12[6];
union {
__IOM uint32_t APBDMACTRL; /*!< (@ 0x00000280) DMA Control Register. Determines misc settings
for DMA operation */
struct {
__IOM uint32_t DMA_ENABLE : 1; /*!< [0..0] Enable the DMA controller. When disabled, DMA requests
will be ignored by the controller */
__IOM uint32_t DECODEABORT : 1; /*!< [1..1] APB Decode Abort. When set, the APB bridge will issue
a data abort (bus fault) on transactions to peripherals
that are powered down. When set to 0, writes are quietly
discarded and reads return 0. */
__IM uint32_t : 6;
__IOM uint32_t HYSTERESIS : 8; /*!< [15..8] This field determines how long the DMA will remain active
during deep sleep before shutting down and returning the
system to full deep sleep. Values are based on a 94KHz
clock and are roughly 10 us increments for a range of ~10
us to 2.55 ms */
} APBDMACTRL_b;
} ;
union {
__IOM uint32_t SRAMMODE; /*!< (@ 0x00000284) SRAM Controller mode bits */
struct {
__IOM uint32_t IPREFETCH : 1; /*!< [0..0] When set, instruction accesses to the SRAM banks will
be pre-fetched (normally 2 cycle read access). Generally,
this mode bit should be set for improved performance when
executing instructions from SRAM. */
__IOM uint32_t IPREFETCH_CACHE : 1; /*!< [1..1] Secondary pre-fetch feature that will cache pre-fetched
data across bus wait states (requires IPREFETCH to be set). */
__IM uint32_t : 2;
__IOM uint32_t DPREFETCH : 1; /*!< [4..4] When set, data bus accesses to the SRAM banks will be
pre-fetched (normally 2 cycle read access). Use of this
mode bit is only recommended if the work flow has a large
number of sequential accesses. */
__IOM uint32_t DPREFETCH_CACHE : 1; /*!< [5..5] Secondary pre-fetch feature that will cache pre-fetched
data across bus wait states (requires DPREFETCH to be set). */
} SRAMMODE_b;
} ;
__IM uint32_t RESERVED13[48];
union {
__IOM uint32_t KEXTCLKSEL; /*!< (@ 0x00000348) Locks the state of the EXTCLKSEL register from
writes. This is done to prevent errant writes
to the register, as this could cause the
chip to halt. Write a value of 0x53 to unlock
write access to the EXTCLKSEL register.
Once unlocked, the register will read back
a 1 to indicate this is unlocked. Writing
the register with any other value other
than 0x53 will enable the lock. */
struct {
__IOM uint32_t KEXTCLKSEL : 32; /*!< [31..0] Key register value. */
} KEXTCLKSEL_b;
} ;
__IM uint32_t RESERVED14;
union {
__IOM uint32_t SIMOBUCK1; /*!< (@ 0x00000350) SIMO Buck Control Reg 1 */
struct {
__IOM uint32_t RESERVED_RW_00 : 22; /*!< [21..0] Reserved bits, always leave unchanged. The SIMOBUCK1
register must be modified via atomic RMW, leaving this
bit field completely unmodified. Failure to do so will
result in unpredictable behavior. */
__IOM uint32_t SIMOBUCKMEMLPTRIM : 6; /*!< [27..22] simobuck_mem_lp_trim */
__IOM uint32_t RESERVED_RW_23 : 4; /*!< [31..28] Reserved bits, always leave unchanged. The SIMOBUCK1
register must be modified via atomic RMW, leaving this
bit field completely unmodified. Failure to do so will
result in unpredictable behavior. */
} SIMOBUCK1_b;
} ;
union {
__IOM uint32_t SIMOBUCK2; /*!< (@ 0x00000354) SIMO Buck Control Reg 2 */
struct {
__IOM uint32_t SIMOBUCKTONGENTRIM : 5; /*!< [4..0] simobuck_tongen_trim */
__IOM uint32_t RESERVED_RW_5 : 11; /*!< [15..5] Reserved bits, always leave unchanged. The SIMOBUCK2
register must be modified via atomic RMW, leaving this
bit field completely unmodified. Failure to do so will
result in unpredictable behavior. */
__IOM uint32_t SIMOBUCKCORELPHIGHTONTRIM : 4;/*!< [19..16] simobuck_core_lp_high_ton_trim */
__IOM uint32_t SIMOBUCKCORELPLOWTONTRIM : 4;/*!< [23..20] simobuck_core_lp_low_ton_trim */
__IOM uint32_t RESERVED_RW_24 : 4; /*!< [27..24] Reserved bits, always leave unchanged. The SIMOBUCK2
register must be modified via atomic RMW, leaving this
bit field completely unmodified. Failure to do so will
result in unpredictable behavior. */
__IOM uint32_t SIMOBUCKCORELEAKAGETRIM : 2;/*!< [29..28] simobuck_core_leakage_trim */
__IOM uint32_t RESERVED_RW_30 : 2; /*!< [31..30] Reserved bits, always leave unchanged. The SIMOBUCK2
register must be modified via atomic RMW, leaving this
bit field completely unmodified. Failure to do so will
result in unpredictable behavior. */
} SIMOBUCK2_b;
} ;
union {
__IOM uint32_t SIMOBUCK3; /*!< (@ 0x00000358) SIMO Buck Control Reg 3 */
struct {
__IOM uint32_t SIMOBUCKCORELPHIGHTOFFTRIM : 4;/*!< [3..0] simobuck_core_lp_high_toff_trim */
__IOM uint32_t SIMOBUCKCORELPLOWTOFFTRIM : 4;/*!< [7..4] simobuck_core_lp_low_toff_trim */
__IOM uint32_t SIMOBUCKMEMLPHIGHTOFFTRIM : 4;/*!< [11..8] simobuck_mem_lp_high_toff_trim */
__IOM uint32_t SIMOBUCKMEMLPLOWTOFFTRIM : 4;/*!< [15..12] simobuck_mem_lp_low_toff_trim */
__IOM uint32_t RESERVED_RW_16 : 11; /*!< [26..16] Reserved bits, always leave unchanged. The SIMOBUCK3
register must be modified via atomic RMW, leaving this
bit field completely unmodified. Failure to do so will
result in unpredictable behavior. */
__IOM uint32_t SIMOBUCKMEMLPHIGHTONTRIM : 4;/*!< [30..27] simobuck_mem_lp_high_ton_trim */
__IOM uint32_t RESERVED_RW_31 : 1; /*!< [31..31] Reserved bits, always leave unchanged. The SIMOBUCK2
register must be modified via atomic RMW, leaving this
bit field completely unmodified. Failure to do so will
result in unpredictable behavior. */
} SIMOBUCK3_b;
} ;
union {
__IOM uint32_t SIMOBUCK4; /*!< (@ 0x0000035C) SIMO Buck Control Reg 4 */
struct {
__IOM uint32_t SIMOBUCKMEMLPLOWTONTRIM : 4;/*!< [3..0] simobuck_mem_lp_low_ton_trim */
__IM uint32_t : 17;
__IOM uint32_t SIMOBUCKCLKDIVSEL : 2; /*!< [22..21] simobuck_clkdiv_sel */
__IOM uint32_t SIMOBUCKCOMP2LPEN : 1; /*!< [23..23] simobuck_comp2_lp_en */
__IOM uint32_t SIMOBUCKCOMP2TIMEOUTEN : 1;/*!< [24..24] simobuck_comp2_timeout_en */
} SIMOBUCK4_b;
} ;
__IM uint32_t RESERVED15[2];
union {
__IOM uint32_t BLEBUCK2; /*!< (@ 0x00000368) BLEBUCK2 Control Reg */
struct {
__IOM uint32_t BLEBUCKTONLOWTRIM : 6; /*!< [5..0] blebuck_ton_low_trim */
__IOM uint32_t BLEBUCKTONHITRIM : 6; /*!< [11..6] blebuck_ton_hi_trim */
__IOM uint32_t BLEBUCKTOND2ATRIM : 6; /*!< [17..12] blebuck_ton_trim */
} BLEBUCK2_b;
} ;
__IM uint32_t RESERVED16[13];
union {
__IOM uint32_t FLASHWPROT0; /*!< (@ 0x000003A0) These bits write-protect flash in 16KB chunks. */
struct {
__IOM uint32_t FW0BITS : 32; /*!< [31..0] Write protect flash 0x00000000 - 0x0007FFFF. Each bit
provides write protection for 16KB chunks of flash data
space. Bits are cleared by writing a 1 to the bit. When
read, 0 indicates the region is protected. Bits are sticky
(can be set when PROTLOCK is 1, but only cleared by reset) */
} FLASHWPROT0_b;
} ;
union {
__IOM uint32_t FLASHWPROT1; /*!< (@ 0x000003A4) These bits write-protect flash in 16KB chunks. */
struct {
__IOM uint32_t FW1BITS : 32; /*!< [31..0] Write protect flash 0x00080000 - 0x000FFFFF. Each bit
provides write protection for 16KB chunks of flash data
space. Bits are cleared by writing a 1 to the bit. When
read, 0 indicates the region is protected. Bits are sticky
(can be set when PROTLOCK is 1, but only cleared by reset) */
} FLASHWPROT1_b;
} ;
__IM uint32_t RESERVED17[2];
union {
__IOM uint32_t FLASHRPROT0; /*!< (@ 0x000003B0) These bits read-protect flash in 16KB chunks. */
struct {
__IOM uint32_t FR0BITS : 32; /*!< [31..0] Copy (read) protect flash 0x00000000 - 0x0007FFFF. Each
bit provides read protection for 16KB chunks of flash.
Bits are cleared by writing a 1 to the bit. When read,
0 indicates the region is protected. Bits are sticky (can
be set when PROTLOCK is 1, but only cleared by reset) */
} FLASHRPROT0_b;
} ;
union {
__IOM uint32_t FLASHRPROT1; /*!< (@ 0x000003B4) These bits read-protect flash in 16KB chunks. */
struct {
__IOM uint32_t FR1BITS : 32; /*!< [31..0] Copy (read) protect flash 0x00080000 - 0x000FFFFF. Each
bit provides read protection for 16KB chunks of flash.
Bits are cleared by writing a 1 to the bit. When read,
0 indicates the region is protected. Bits are sticky (can
be set when PROTLOCK is 1, but only cleared by reset) */
} FLASHRPROT1_b;
} ;
__IM uint32_t RESERVED18[2];
union {
__IOM uint32_t DMASRAMWRITEPROTECT0; /*!< (@ 0x000003C0) These bits write-protect system SRAM from DMA
operations in 8KB chunks. */
struct {
__IOM uint32_t DMA_WPROT0 : 32; /*!< [31..0] Write protect SRAM from DMA. Each bit provides write
protection for an 8KB region of memory. When set to 1,
the region will be protected from DMA writes, when set
to 0, DMA may write the region. */
} DMASRAMWRITEPROTECT0_b;
} ;
union {
__IOM uint32_t DMASRAMWRITEPROTECT1; /*!< (@ 0x000003C4) These bits write-protect system SRAM from DMA
operations in 8KB chunks. */
struct {
__IOM uint32_t DMA_WPROT1 : 16; /*!< [15..0] Write protect SRAM from DMA. Each bit provides write
protection for an 8KB region of memory. When set to 1,
the region will be protected from DMA writes, when set
to 0, DMA may write the region. */
} DMASRAMWRITEPROTECT1_b;
} ;
__IM uint32_t RESERVED19[2];
union {
__IOM uint32_t DMASRAMREADPROTECT0; /*!< (@ 0x000003D0) These bits read-protect system SRAM from DMA
operations in 8KB chunks. */
struct {
__IOM uint32_t DMA_RPROT0 : 32; /*!< [31..0] Read protect SRAM from DMA. Each bit provides write
protection for an 8KB region of memory. When set to 1,
the region will be protected from DMA reads, when set to
0, DMA may read the region. */
} DMASRAMREADPROTECT0_b;
} ;
union {
__IOM uint32_t DMASRAMREADPROTECT1; /*!< (@ 0x000003D4) These bits read-protect system SRAM from DMA
operations in 8KB chunks. */
struct {
__IOM uint32_t DMA_RPROT1 : 16; /*!< [15..0] Read protect SRAM from DMA. Each bit provides write
protection for an 8KB region of memory. When set to 1,
the region will be protected from DMA reads, when set to
0, DMA may read the region. */
} DMASRAMREADPROTECT1_b;
} ;
} MCUCTRL_Type; /*!< Size = 984 (0x3d8) */
/* =========================================================================================================================== */
/* ================ MSPI ================ */
/* =========================================================================================================================== */
/**
* @brief Multi-bit SPI Master (MSPI)
*/
typedef struct { /*!< (@ 0x50014000) MSPI Structure */
union {
__IOM uint32_t CTRL; /*!< (@ 0x00000000) This register is used to enable individual PIO
based transactions to a device on the bus.
The CFG register must be programmed properly
for the transfer, and the ADDR and INSTR
registers should be programmed if the SENDI
and SENDA fields are enabled. */
struct {
__IOM uint32_t START : 1; /*!< [0..0] Write to 1 to initiate a PIO transaction on the bus (typically
the entire register should be written at once with this
bit set). */
__IOM uint32_t STATUS : 1; /*!< [1..1] Command status: 1 indicates command has completed. Cleared
by writing 1 to this bit or starting a new transfer. */
__IOM uint32_t BUSY : 1; /*!< [2..2] Command status: 1 indicates controller is busy (command
in progress) */
__IOM uint32_t QUADCMD : 1; /*!< [3..3] Flag indicating that the operation is a command that
should be replicated to both devices in paired QUAD mode.
This is typically only used when reading/writing configuration
registers in paired flash devices (do not set for memory
transfers). */
__IM uint32_t : 2;
__IOM uint32_t BIGENDIAN : 1; /*!< [6..6] 1 indicates data in FIFO is in big endian format (MSB
first); 0 indicates little endian data (default, LSB first). */
__IOM uint32_t ENTURN : 1; /*!< [7..7] Indicates whether TX->RX turnaround cycles should be
enabled for this operation (see TURNAROUND field in CFG
register). */
__IOM uint32_t SENDA : 1; /*!< [8..8] Indicates whether an address phase should be sent (see
ADDR register and ASIZE field in CFG register) */
__IOM uint32_t SENDI : 1; /*!< [9..9] Indicates whether an instruction phase should be sent
(see INSTR field and ISIZE field in CFG register) */
__IOM uint32_t TXRX : 1; /*!< [10..10] 1 Indicates a TX operation, 0 indicates an RX operation
of XFERBYTES */
__IOM uint32_t PIOSCRAMBLE : 1; /*!< [11..11] Enables data scrambling for PIO operations. This should
only be used for data operations and never for commands
to a device. */
__IM uint32_t : 4;
__IOM uint32_t XFERBYTES : 16; /*!< [31..16] Number of bytes to transmit or receive (based on TXRX
bit) */
} CTRL_b;
} ;
union {
__IOM uint32_t CFG; /*!< (@ 0x00000004) Command formatting for PIO based transactions
(initiated by writes to CTRL register) */
struct {
__IOM uint32_t DEVCFG : 4; /*!< [3..0] Flash configuration for XIP and AUTO DMA operations.
Controls value for SER (Slave Enable) for XIP operations
and address generation for DMA/XIP modes. Also used to
configure SPIFRF (frame format). */
__IOM uint32_t ASIZE : 2; /*!< [5..4] Address Size. Address bytes to send from ADDR register */
__IOM uint32_t ISIZE : 1; /*!< [6..6] Instruction Sizeenum name = I8 value = 0x0 desc = Instruction
is 1 byteenum name = I16 value = 0x1 desc = Instruction
is 2 bytes */
__IOM uint32_t SEPIO : 1; /*!< [7..7] Separate IO configuration. This bit should be set when
the target device has separate MOSI and MISO pins. Respective
IN/OUT bits below should be set to map pins. */
__IOM uint32_t TURNAROUND : 6; /*!< [13..8] Number of turnaround cycles (for TX->RX transitions).
Qualified by ENTURN or XIPENTURN bit field. */
__IM uint32_t : 2;
__IOM uint32_t CPHA : 1; /*!< [16..16] Serial clock phase. */
__IOM uint32_t CPOL : 1; /*!< [17..17] Serial clock polarity. */
} CFG_b;
} ;
union {
__IOM uint32_t ADDR; /*!< (@ 0x00000008) Optional Address field to send for PIO transfers */
struct {
__IOM uint32_t ADDR : 32; /*!< [31..0] Optional Address field to send (after optional instruction
field) - qualified by ASIZE in CMD register. NOTE: This
register is aliased to DMADEVADDR. */
} ADDR_b;
} ;
union {
__IOM uint32_t INSTR; /*!< (@ 0x0000000C) Optional Instruction field to send for PIO transfers */
struct {
__IOM uint32_t INSTR : 16; /*!< [15..0] Optional Instruction field to send (1st byte) - qualified
by ISEND/ISIZE */
} INSTR_b;
} ;
union {
__IOM uint32_t TXFIFO; /*!< (@ 0x00000010) TX Data FIFO */
struct {
__IOM uint32_t TXFIFO : 32; /*!< [31..0] Data to be transmitted. Data should normally be aligned
to the LSB (pad the upper bits with zeros) unless BIGENDIAN
is set. */
} TXFIFO_b;
} ;
union {
__IOM uint32_t RXFIFO; /*!< (@ 0x00000014) RX Data FIFO */
struct {
__IOM uint32_t RXFIFO : 32; /*!< [31..0] Receive data. Data is aligned to the LSB (padded zeros
on upper bits) unless BIGENDIAN is set. */
} RXFIFO_b;
} ;
union {
__IOM uint32_t TXENTRIES; /*!< (@ 0x00000018) Number of words in TX FIFO */
struct {
__IOM uint32_t TXENTRIES : 5; /*!< [4..0] Number of 32-bit words/entries in TX FIFO */
} TXENTRIES_b;
} ;
union {
__IOM uint32_t RXENTRIES; /*!< (@ 0x0000001C) Number of words in RX FIFO */
struct {
__IOM uint32_t RXENTRIES : 5; /*!< [4..0] Number of 32-bit words/entries in RX FIFO */
} RXENTRIES_b;
} ;
union {
__IOM uint32_t THRESHOLD; /*!< (@ 0x00000020) Threshold levels that trigger RXFull and TXEmpty
interrupts */
struct {
__IOM uint32_t TXTHRESH : 5; /*!< [4..0] Number of entries in TX FIFO that cause TXF interrupt */
__IM uint32_t : 3;
__IOM uint32_t RXTHRESH : 5; /*!< [12..8] Number of entries in TX FIFO that cause RXE interrupt */
} THRESHOLD_b;
} ;
__IM uint32_t RESERVED[55];
union {
__IOM uint32_t MSPICFG; /*!< (@ 0x00000100) Timing configuration bits for the MSPI module.
PRSTN, IPRSTN, and FIFORESET can be used
to reset portions of the MSPI interface
in order to clear error conditions. The
remaining bits control clock frequency and
TX/RX capture timings. */
struct {
__IOM uint32_t APBCLK : 1; /*!< [0..0] Enable continuous APB clock. For power-efficient operation,
APBCLK should be set to 0. */
__IOM uint32_t RXCAP : 1; /*!< [1..1] Controls RX data capture phase. A setting of 0 (NORMAL)
captures read data at the normal capture point relative
to the internal clock launch point. However, to accommodate
chip/pad/board delays, a setting of RXCAP of 1 is expected
to be used to align the capture point with the return data
window. This bit is used in conjunction with RXNEG to provide
4 unique capture points, all about 10 ns apart. */
__IOM uint32_t RXNEG : 1; /*!< [2..2] Adjusts the RX capture phase to the negedge of the 48MHz
internal clock (~10 ns early). For normal operation, it
is expected that RXNEG will be set to 0. */
__IOM uint32_t TXNEG : 1; /*!< [3..3] Launches TX data a half clock cycle (~10 ns) early. This
should normally be programmed to zero (NORMAL). */
__IOM uint32_t IOMSEL : 3; /*!< [6..4] Selects which IOM is selected for CQ handshake status. */
__IM uint32_t : 1;
__IOM uint32_t CLKDIV : 6; /*!< [13..8] Clock Divider. Allows dividing 48 MHz base clock by
integer multiples. Enumerations are provided for common
frequency, but any integer divide from 48 MHz is allowed.
Odd divide ratios will result in a 33/66 percent duty cycle
with a long low clock pulse (to allow longer round-trip
for read data). */
__IM uint32_t : 15;
__IOM uint32_t FIFORESET : 1; /*!< [29..29] Reset MSPI FIFO (active high). 1=reset FIFO, 0=normal
operation. May be used to manually flush the FIFO in error
handling. */
__IOM uint32_t IPRSTN : 1; /*!< [30..30] IP block reset. Write to 0 to put the transfer module
in reset or 1 for normal operation. This may be required
after error conditions to clear the transfer on the bus. */
__IOM uint32_t PRSTN : 1; /*!< [31..31] Peripheral reset. Master reset to the entire MSPI module
(DMA, XIP, and transfer state machines). 1=normal operation,
0=in reset. */
} MSPICFG_b;
} ;
union {
__IOM uint32_t PADCFG; /*!< (@ 0x00000104) Configuration bits for the MSPI pads. Allows
pads associated with the upper quad to be
mapped to corresponding bits on the lower
quad. Use of Quad0 pins is recommended for
optimal timing. */
struct {
__IOM uint32_t OUT3 : 1; /*!< [0..0] Output pad 3 configuration. 0=data[3] 1=CLK */
__IOM uint32_t OUT4 : 1; /*!< [1..1] Output pad 4 configuration. 0=data[4] 1=data[0] */
__IOM uint32_t OUT5 : 1; /*!< [2..2] Output pad 5 configuration. 0=data[5] 1=data[1] */
__IOM uint32_t OUT6 : 1; /*!< [3..3] Output pad 6 configuration. 0=data[6] 1=data[2] */
__IOM uint32_t OUT7 : 1; /*!< [4..4] Output pad 7 configuration. 0=data[7] 1=data[3] */
__IM uint32_t : 11;
__IOM uint32_t IN0 : 2; /*!< [17..16] Data Input pad 0 pin muxing: 0=pad[0] 1=pad[4] 2=pad[1]
3=pad[5] */
__IOM uint32_t IN1 : 1; /*!< [18..18] Data Input pad 1 pin muxing: 0=pad[1] 1=pad[5] */
__IOM uint32_t IN2 : 1; /*!< [19..19] Data Input pad 2 pin muxing: 0=pad[2] 1=pad[6] */
__IOM uint32_t IN3 : 1; /*!< [20..20] Data Input pad 3 pin muxing: 0=pad[3] 1=pad[7] */
__IOM uint32_t REVCS : 1; /*!< [21..21] Reverse CS connections. Allows CS1 to be associated
with lower data lanes and CS0 to be associated with upper
data lines */
} PADCFG_b;
} ;
union {
__IOM uint32_t PADOUTEN; /*!< (@ 0x00000108) Enable bits for the MSPI output pads. Each active
MSPI line should be set to 1 in the OUTEN
field below. */
struct {
__IOM uint32_t OUTEN : 9; /*!< [8..0] Output pad enable configuration. Indicates which pads
should be driven. Bits [3:0] are Quad0 data, [7:4] are
Quad1 data, and [8] is clock. */
} PADOUTEN_b;
} ;
union {
__IOM uint32_t FLASH; /*!< (@ 0x0000010C) When any SPI flash is configured, this register
must be properly programmed before XIP or
AUTO DMA operations commence. */
struct {
__IOM uint32_t XIPEN : 1; /*!< [0..0] Enable the XIP (eXecute In Place) function which effectively
enables the address decoding of the MSPI device in the
flash/cache address space at address 0x04000000-0x07FFFFFF. */
__IM uint32_t : 1;
__IOM uint32_t XIPACK : 2; /*!< [3..2] Controls transmission of Micron XIP acknowledge cycles
(Micron Flash devices only) */
__IOM uint32_t XIPBIGENDIAN : 1; /*!< [4..4] Indicates whether XIP/AUTO DMA data transfers are in
big or little endian format */
__IOM uint32_t XIPENTURN : 1; /*!< [5..5] Indicates whether XIP/AUTO DMA operations should enable
TX->RX turnaround cycles */
__IOM uint32_t XIPSENDA : 1; /*!< [6..6] Indicates whether XIP/AUTO DMA operations should send
an an address phase (see DMADEVADDR register and ASIZE
field in CFG) */
__IOM uint32_t XIPSENDI : 1; /*!< [7..7] Indicates whether XIP/AUTO DMA operations should send
an instruction (see READINSTR field and ISIZE field in
CFG) */
__IOM uint32_t XIPMIXED : 3; /*!< [10..8] Reserved. Set to 0x0 */
__IM uint32_t : 5;
__IOM uint32_t WRITEINSTR : 8; /*!< [23..16] Write command sent for DMA operations */
__IOM uint32_t READINSTR : 8; /*!< [31..24] Read command sent to flash for DMA/XIP operations */
} FLASH_b;
} ;
__IM uint32_t RESERVED1[4];
union {
__IOM uint32_t SCRAMBLING; /*!< (@ 0x00000120) Enables data scrambling for the specified range
external flash addresses. Scrambling does
not impact flash access performance. */
struct {
__IOM uint32_t SCRSTART : 10; /*!< [9..0] Scrambling region start address [25:16] (64K block granularity).
The START block is the FIRST block included in the scrambled
address range. */
__IM uint32_t : 6;
__IOM uint32_t SCREND : 10; /*!< [25..16] Scrambling region end address [25:16] (64K block granularity).
The END block is the LAST block included in the scrambled
address range. */
__IM uint32_t : 5;
__IOM uint32_t SCRENABLE : 1; /*!< [31..31] Enables Data Scrambling Region. When 1 reads and writes
to the range will be scrambled. When 0, data will be read/written
unmodified. Address range is specified in 64K granularity
and the START/END ranges are included within the range. */
} SCRAMBLING_b;
} ;
__IM uint32_t RESERVED2[55];
union {
__IOM uint32_t INTEN; /*!< (@ 0x00000200) Set bits in this register to allow this module
to generate the corresponding interrupt. */
struct {
__IOM uint32_t CMDCMP : 1; /*!< [0..0] Transfer complete. Note that DMA and CQ operations are
layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously. */
__IOM uint32_t TXE : 1; /*!< [1..1] Transmit FIFO empty. */
__IOM uint32_t TXO : 1; /*!< [2..2] Transmit FIFO Overflow (only occurs when SW writes to
a full FIFO). */
__IOM uint32_t RXU : 1; /*!< [3..3] Receive FIFO underflow (only occurs when SW reads from
an empty FIFO) */
__IOM uint32_t RXO : 1; /*!< [4..4] Receive FIFO overflow (cannot happen in MSPI design --
MSPI bus pins will stall) */
__IOM uint32_t RXF : 1; /*!< [5..5] Receive FIFO full */
__IOM uint32_t DCMP : 1; /*!< [6..6] DMA Complete Interrupt */
__IOM uint32_t DERR : 1; /*!< [7..7] DMA Error Interrupt */
__IOM uint32_t CQCMP : 1; /*!< [8..8] Command Queue Complete Interrupt */
__IOM uint32_t CQUPD : 1; /*!< [9..9] Command Queue Update Interrupt. Issued whenever the CQ
performs an operation where address bit[0] is set. Useful
for triggering CURIDX interrupts. */
__IOM uint32_t CQPAUSED : 1; /*!< [10..10] Command Queue is Paused. */
__IOM uint32_t CQERR : 1; /*!< [11..11] Command Queue Error Interrupt */
__IOM uint32_t SCRERR : 1; /*!< [12..12] Scrambling Alignment Error. Scrambling operations must
be aligned to word (4-byte) start address. */
} INTEN_b;
} ;
union {
__IOM uint32_t INTSTAT; /*!< (@ 0x00000204) Read bits from this register to discover the
cause of a recent interrupt. */
struct {
__IOM uint32_t CMDCMP : 1; /*!< [0..0] Transfer complete. Note that DMA and CQ operations are
layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously. */
__IOM uint32_t TXE : 1; /*!< [1..1] Transmit FIFO empty. */
__IOM uint32_t TXO : 1; /*!< [2..2] Transmit FIFO Overflow (only occurs when SW writes to
a full FIFO). */
__IOM uint32_t RXU : 1; /*!< [3..3] Receive FIFO underflow (only occurs when SW reads from
an empty FIFO) */
__IOM uint32_t RXO : 1; /*!< [4..4] Receive FIFO overflow (cannot happen in MSPI design --
MSPI bus pins will stall) */
__IOM uint32_t RXF : 1; /*!< [5..5] Receive FIFO full */
__IOM uint32_t DCMP : 1; /*!< [6..6] DMA Complete Interrupt */
__IOM uint32_t DERR : 1; /*!< [7..7] DMA Error Interrupt */
__IOM uint32_t CQCMP : 1; /*!< [8..8] Command Queue Complete Interrupt */
__IOM uint32_t CQUPD : 1; /*!< [9..9] Command Queue Update Interrupt. Issued whenever the CQ
performs an operation where address bit[0] is set. Useful
for triggering CURIDX interrupts. */
__IOM uint32_t CQPAUSED : 1; /*!< [10..10] Command Queue is Paused. */
__IOM uint32_t CQERR : 1; /*!< [11..11] Command Queue Error Interrupt */
__IOM uint32_t SCRERR : 1; /*!< [12..12] Scrambling Alignment Error. Scrambling operations must
be aligned to word (4-byte) start address. */
} INTSTAT_b;
} ;
union {
__IOM uint32_t INTCLR; /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
the interrupt status associated with that
bit. */
struct {
__IOM uint32_t CMDCMP : 1; /*!< [0..0] Transfer complete. Note that DMA and CQ operations are
layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously. */
__IOM uint32_t TXE : 1; /*!< [1..1] Transmit FIFO empty. */
__IOM uint32_t TXO : 1; /*!< [2..2] Transmit FIFO Overflow (only occurs when SW writes to
a full FIFO). */
__IOM uint32_t RXU : 1; /*!< [3..3] Receive FIFO underflow (only occurs when SW reads from
an empty FIFO) */
__IOM uint32_t RXO : 1; /*!< [4..4] Receive FIFO overflow (cannot happen in MSPI design --
MSPI bus pins will stall) */
__IOM uint32_t RXF : 1; /*!< [5..5] Receive FIFO full */
__IOM uint32_t DCMP : 1; /*!< [6..6] DMA Complete Interrupt */
__IOM uint32_t DERR : 1; /*!< [7..7] DMA Error Interrupt */
__IOM uint32_t CQCMP : 1; /*!< [8..8] Command Queue Complete Interrupt */
__IOM uint32_t CQUPD : 1; /*!< [9..9] Command Queue Update Interrupt. Issued whenever the CQ
performs an operation where address bit[0] is set. Useful
for triggering CURIDX interrupts. */
__IOM uint32_t CQPAUSED : 1; /*!< [10..10] Command Queue is Paused. */
__IOM uint32_t CQERR : 1; /*!< [11..11] Command Queue Error Interrupt */
__IOM uint32_t SCRERR : 1; /*!< [12..12] Scrambling Alignment Error. Scrambling operations must
be aligned to word (4-byte) start address. */
} INTCLR_b;
} ;
union {
__IOM uint32_t INTSET; /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
generate an interrupt from this module.
(Generally used for testing purposes). */
struct {
__IOM uint32_t CMDCMP : 1; /*!< [0..0] Transfer complete. Note that DMA and CQ operations are
layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously. */
__IOM uint32_t TXE : 1; /*!< [1..1] Transmit FIFO empty. */
__IOM uint32_t TXO : 1; /*!< [2..2] Transmit FIFO Overflow (only occurs when SW writes to
a full FIFO). */
__IOM uint32_t RXU : 1; /*!< [3..3] Receive FIFO underflow (only occurs when SW reads from
an empty FIFO) */
__IOM uint32_t RXO : 1; /*!< [4..4] Receive FIFO overflow (cannot happen in MSPI design --
MSPI bus pins will stall) */
__IOM uint32_t RXF : 1; /*!< [5..5] Receive FIFO full */
__IOM uint32_t DCMP : 1; /*!< [6..6] DMA Complete Interrupt */
__IOM uint32_t DERR : 1; /*!< [7..7] DMA Error Interrupt */
__IOM uint32_t CQCMP : 1; /*!< [8..8] Command Queue Complete Interrupt */
__IOM uint32_t CQUPD : 1; /*!< [9..9] Command Queue Update Interrupt. Issued whenever the CQ
performs an operation where address bit[0] is set. Useful
for triggering CURIDX interrupts. */
__IOM uint32_t CQPAUSED : 1; /*!< [10..10] Command Queue is Paused. */
__IOM uint32_t CQERR : 1; /*!< [11..11] Command Queue Error Interrupt */
__IOM uint32_t SCRERR : 1; /*!< [12..12] Scrambling Alignment Error. Scrambling operations must
be aligned to word (4-byte) start address. */
} INTSET_b;
} ;
__IM uint32_t RESERVED3[16];
union {
__IOM uint32_t DMACFG; /*!< (@ 0x00000250) DMA Configuration */
struct {
__IOM uint32_t DMAEN : 2; /*!< [1..0] DMA Enable. Setting this bit to EN will start the DMA
operation */
__IOM uint32_t DMADIR : 1; /*!< [2..2] Direction */
__IOM uint32_t DMAPRI : 2; /*!< [4..3] Sets the Priority of the DMA request */
__IM uint32_t : 13;
__IOM uint32_t DMAPWROFF : 1; /*!< [18..18] Power off MSPI domain upon completion of DMA operation. */
} DMACFG_b;
} ;
union {
__IOM uint32_t DMASTAT; /*!< (@ 0x00000254) DMA Status */
struct {
__IOM uint32_t DMATIP : 1; /*!< [0..0] DMA Transfer In Progress indicator. 1 will indicate that
a DMA transfer is active. The DMA transfer may be waiting
on data, transferring data, or waiting for priority. All
of these will be indicated with a 1. A 0 will indicate
that the DMA is fully complete and no further transactions
will be done. */
__IOM uint32_t DMACPL : 1; /*!< [1..1] DMA Transfer Complete. This signals the end of the DMA
operation. */
__IOM uint32_t DMAERR : 1; /*!< [2..2] DMA Error. This active high bit signals that an error
was encountered during the DMA operation. */
__IOM uint32_t SCRERR : 1; /*!< [3..3] Scrambling Access Alignment Error. This active high bit
signals that a scrambling operation was specified for a
non-word aligned DEVADDR. */
} DMASTAT_b;
} ;
union {
__IOM uint32_t DMATARGADDR; /*!< (@ 0x00000258) DMA Target Address */
struct {
__IOM uint32_t TARGADDR : 32; /*!< [31..0] Target byte address for source of DMA (either read or
write). In cases of non-word aligned addresses, the DMA
logic will take care for ensuring only the target bytes
are read/written. */
} DMATARGADDR_b;
} ;
union {
__IOM uint32_t DMADEVADDR; /*!< (@ 0x0000025C) DMA Device Address */
struct {
__IOM uint32_t DEVADDR : 32; /*!< [31..0] SPI Device address for automated DMA transactions (both
read and write). */
} DMADEVADDR_b;
} ;
union {
__IOM uint32_t DMATOTCOUNT; /*!< (@ 0x00000260) DMA Total Transfer Count */
struct {
__IOM uint32_t TOTCOUNT : 16; /*!< [15..0] Total Transfer Count in bytes. */
} DMATOTCOUNT_b;
} ;
union {
__IOM uint32_t DMABCOUNT; /*!< (@ 0x00000264) DMA BYTE Transfer Count */
struct {
__IOM uint32_t BCOUNT : 8; /*!< [7..0] Burst transfer size in bytes. This is the number of bytes
transferred when a FIFO trigger event occurs. Recommended
values are 16 or 32. */
} DMABCOUNT_b;
} ;
__IM uint32_t RESERVED4[4];
union {
__IOM uint32_t DMATHRESH; /*!< (@ 0x00000278) Indicates FIFO level at which a DMA should be
triggered. For most configurations, a setting
of 8 is recommended for both read and write
operations. */
struct {
__IOM uint32_t DMATHRESH : 4; /*!< [3..0] DMA transfer FIFO level trigger. For read operations,
DMA is triggered when the FIFO level is greater than this
value. For write operations, DMA is triggered when the
FIFO level is less than this level. Each DMA operation
will consist of BCOUNT bytes. */
} DMATHRESH_b;
} ;
__IM uint32_t RESERVED5[9];
union {
__IOM uint32_t CQCFG; /*!< (@ 0x000002A0) This register controls Command Queuing (CQ) operations
in a manner similar to the DMACFG register. */
struct {
__IOM uint32_t CQEN : 1; /*!< [0..0] Command queue enable. When set, will enable the processing
of the command queue */
__IOM uint32_t CQPRI : 1; /*!< [1..1] Sets the Priority of the command queue DMA request */
__IOM uint32_t CQPWROFF : 1; /*!< [2..2] Power off MSPI domain upon completion of DMA operation. */
__IOM uint32_t CQAUTOCLEARMASK : 1; /*!< [3..3] Enable clear of CQMASK after each pause operation. This
may be useful when using software flags to pause CQ. */
} CQCFG_b;
} ;
__IM uint32_t RESERVED6;
union {
__IOM uint32_t CQADDR; /*!< (@ 0x000002A8) Location of the command queue in SRAM or flash
memory. This register will increment as
CQ operations commence. Software should
only write CQADDR when CQEN is disabled,
however the command queue script itself
may update CQADDR in order to perform queue
management functions (like resetting the
pointers) */
struct {
__IOM uint32_t CQADDR : 29; /*!< [28..0] Address of command queue buffer in SRAM or flash. The
buffer address must be aligned to a word boundary. */
} CQADDR_b;
} ;
union {
__IOM uint32_t CQSTAT; /*!< (@ 0x000002AC) Command Queue Status */
struct {
__IOM uint32_t CQTIP : 1; /*!< [0..0] Command queue Transfer In Progress indicator. 1 will
indicate that a CQ transfer is active and this will remain
active even when paused waiting for external event. */
__IOM uint32_t CQCPL : 1; /*!< [1..1] Command queue operation Complete. This signals the end
of the command queue operation. */
__IOM uint32_t CQERR : 1; /*!< [2..2] Command queue processing Error. This active high bit
signals that an error was encountered during the CQ operation. */
__IOM uint32_t CQPAUSED : 1; /*!< [3..3] Command queue is currently paused status. */
} CQSTAT_b;
} ;
union {
__IOM uint32_t CQFLAGS; /*!< (@ 0x000002B0) Command Queue Flags */
struct {
__IOM uint32_t CQFLAGS : 16; /*!< [15..0] Current flag status (read-only). Bits [7:0] are software
controllable and bits [15:8] are hardware status. */
} CQFLAGS_b;
} ;
union {
__IOM uint32_t CQSETCLEAR; /*!< (@ 0x000002B4) Command Queue Flag Set/Clear */
struct {
__IOM uint32_t CQFSET : 8; /*!< [7..0] Set CQFlag status bits. Set has priority over clear if
both are high. */
__IOM uint32_t CQFTOGGLE : 8; /*!< [15..8] Toggle CQFlag status bits */
__IOM uint32_t CQFCLR : 8; /*!< [23..16] Clear CQFlag status bits. */
} CQSETCLEAR_b;
} ;
union {
__IOM uint32_t CQPAUSE; /*!< (@ 0x000002B8) Command Queue Pause Mask */
struct {
__IOM uint32_t CQMASK : 16; /*!< [15..0] CQ will pause processing when ALL specified events are
satisfied -- i.e. when (CQMASK and CQPAUSE)==CQMASK. */
} CQPAUSE_b;
} ;
__IM uint32_t RESERVED7;
union {
__IOM uint32_t CQCURIDX; /*!< (@ 0x000002C0) This register can be used in conjunction with
the CQENDIDX register to manage the command
queue. Typically software will initialize
the CQCURIDX and CQENDIDX to the same value,
which will cause the CQ to be paused when
enabled. Software may then add entries to
the command queue (in SRAM) and update CQENDIDX.
The command queue operations will then increment
CQCURIDX as it processes operations. Once
CQCURIDX==CQENDIDX, the command queue hardware
will automatically pause since no additional
ope */
struct {
__IOM uint32_t CQCURIDX : 8; /*!< [7..0] Can be used to indicate the current position of the command
queue by having CQ operations write this field. A CQ hardware
status flag indicates when CURIDX and ENDIDX are not equal,
allowing SW to pause the CQ processing until the end index
is updated. */
} CQCURIDX_b;
} ;
union {
__IOM uint32_t CQENDIDX; /*!< (@ 0x000002C4) Command Queue End Index */
struct {
__IOM uint32_t CQENDIDX : 8; /*!< [7..0] Can be used to indicate the end position of the command
queue. A CQ hardware status bit indices when CURIDX !=
ENDIDX so that the CQ can be paused when it reaches the
end pointer. */
} CQENDIDX_b;
} ;
} MSPI_Type; /*!< Size = 712 (0x2c8) */
/* =========================================================================================================================== */
/* ================ PDM ================ */
/* =========================================================================================================================== */
/**
* @brief PDM Audio (PDM)
*/
typedef struct { /*!< (@ 0x50011000) PDM Structure */
union {
__IOM uint32_t PCFG; /*!< (@ 0x00000000) PDM Configuration Register */
struct {
__IOM uint32_t PDMCOREEN : 1; /*!< [0..0] Data Streaming Control. */
__IOM uint32_t SOFTMUTE : 1; /*!< [1..1] Soft mute control. */
__IOM uint32_t CYCLES : 3; /*!< [4..2] Number of clocks during gain-setting changes. */
__IOM uint32_t HPCUTOFF : 4; /*!< [8..5] High pass filter coefficients. */
__IOM uint32_t ADCHPD : 1; /*!< [9..9] High pass filter control. */
__IOM uint32_t SINCRATE : 7; /*!< [16..10] SINC decimation rate. */
__IOM uint32_t MCLKDIV : 2; /*!< [18..17] PDM_CLK frequency divisor. */
__IM uint32_t : 2;
__IOM uint32_t PGALEFT : 5; /*!< [25..21] Left channel PGA gain. */
__IOM uint32_t PGARIGHT : 5; /*!< [30..26] Right channel PGA gain. */
__IOM uint32_t LRSWAP : 1; /*!< [31..31] Left/right channel swap. */
} PCFG_b;
} ;
union {
__IOM uint32_t VCFG; /*!< (@ 0x00000004) Voice Configuration Register */
struct {
__IM uint32_t : 3;
__IOM uint32_t CHSET : 2; /*!< [4..3] Set PCM channels. */
__IM uint32_t : 3;
__IOM uint32_t PCMPACK : 1; /*!< [8..8] PCM data packing enable. */
__IM uint32_t : 7;
__IOM uint32_t SELAP : 1; /*!< [16..16] Select PDM input clock source. */
__IOM uint32_t DMICKDEL : 1; /*!< [17..17] PDM clock sampling delay. */
__IM uint32_t : 1;
__IOM uint32_t BCLKINV : 1; /*!< [19..19] I2S BCLK input inversion. */
__IOM uint32_t I2SEN : 1; /*!< [20..20] I2S interface enable. */
__IM uint32_t : 5;
__IOM uint32_t PDMCLKEN : 1; /*!< [26..26] Enable the serial clock. */
__IOM uint32_t PDMCLKSEL : 3; /*!< [29..27] Select the PDM input clock. */
__IOM uint32_t RSTB : 1; /*!< [30..30] Reset the IP core. */
__IOM uint32_t IOCLKEN : 1; /*!< [31..31] Enable the IO clock. */
} VCFG_b;
} ;
union {
__IOM uint32_t VOICESTAT; /*!< (@ 0x00000008) Voice Status Register */
struct {
__IOM uint32_t FIFOCNT : 6; /*!< [5..0] Valid 32-bit entries currently in the FIFO. */
} VOICESTAT_b;
} ;
union {
__IOM uint32_t FIFOREAD; /*!< (@ 0x0000000C) FIFO Read */
struct {
__IOM uint32_t FIFOREAD : 32; /*!< [31..0] FIFO read data. */
} FIFOREAD_b;
} ;
union {
__IOM uint32_t FIFOFLUSH; /*!< (@ 0x00000010) FIFO Flush */
struct {
__IOM uint32_t FIFOFLUSH : 1; /*!< [0..0] FIFO FLUSH. */
} FIFOFLUSH_b;
} ;
union {
__IOM uint32_t FIFOTHR; /*!< (@ 0x00000014) FIFO Threshold */
struct {
__IOM uint32_t FIFOTHR : 5; /*!< [4..0] FIFO Threshold value. When the FIFO count is equal to,
or larger than this value (in words), a THR interrupt is
generated (if enabled) */
} FIFOTHR_b;
} ;
__IM uint32_t RESERVED[122];
union {
__IOM uint32_t INTEN; /*!< (@ 0x00000200) Set bits in this register to allow this module
to generate the corresponding interrupt. */
struct {
__IOM uint32_t THR : 1; /*!< [0..0] This is the FIFO threshold interrupt. */
__IOM uint32_t OVF : 1; /*!< [1..1] This is the FIFO overflow interrupt. */
__IOM uint32_t UNDFL : 1; /*!< [2..2] This is the FIFO underflow interrupt. */
__IOM uint32_t DCMP : 1; /*!< [3..3] DMA completed a transfer */
__IOM uint32_t DERR : 1; /*!< [4..4] DMA Error receieved */
} INTEN_b;
} ;
union {
__IOM uint32_t INTSTAT; /*!< (@ 0x00000204) Read bits from this register to discover the
cause of a recent interrupt. */
struct {
__IOM uint32_t THR : 1; /*!< [0..0] This is the FIFO threshold interrupt. */
__IOM uint32_t OVF : 1; /*!< [1..1] This is the FIFO overflow interrupt. */
__IOM uint32_t UNDFL : 1; /*!< [2..2] This is the FIFO underflow interrupt. */
__IOM uint32_t DCMP : 1; /*!< [3..3] DMA completed a transfer */
__IOM uint32_t DERR : 1; /*!< [4..4] DMA Error receieved */
} INTSTAT_b;
} ;
union {
__IOM uint32_t INTCLR; /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
the interrupt status associated with that
bit. */
struct {
__IOM uint32_t THR : 1; /*!< [0..0] This is the FIFO threshold interrupt. */
__IOM uint32_t OVF : 1; /*!< [1..1] This is the FIFO overflow interrupt. */
__IOM uint32_t UNDFL : 1; /*!< [2..2] This is the FIFO underflow interrupt. */
__IOM uint32_t DCMP : 1; /*!< [3..3] DMA completed a transfer */
__IOM uint32_t DERR : 1; /*!< [4..4] DMA Error receieved */
} INTCLR_b;
} ;
union {
__IOM uint32_t INTSET; /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
generate an interrupt from this module.
(Generally used for testing purposes). */
struct {
__IOM uint32_t THR : 1; /*!< [0..0] This is the FIFO threshold interrupt. */
__IOM uint32_t OVF : 1; /*!< [1..1] This is the FIFO overflow interrupt. */
__IOM uint32_t UNDFL : 1; /*!< [2..2] This is the FIFO underflow interrupt. */
__IOM uint32_t DCMP : 1; /*!< [3..3] DMA completed a transfer */
__IOM uint32_t DERR : 1; /*!< [4..4] DMA Error receieved */
} INTSET_b;
} ;
__IM uint32_t RESERVED1[12];
union {
__IOM uint32_t DMATRIGEN; /*!< (@ 0x00000240) DMA Trigger Enable Register */
struct {
__IOM uint32_t DTHR : 1; /*!< [0..0] Trigger DMA upon when FIFO iss filled to level indicated
by the FIFO THRESHOLD,at granularity of 16 bytes only */
__IOM uint32_t DTHR90 : 1; /*!< [1..1] Trigger DMA at FIFO 90 percent full. This signal is also
used internally for AUTOHIP function */
} DMATRIGEN_b;
} ;
union {
__IOM uint32_t DMATRIGSTAT; /*!< (@ 0x00000244) DMA Trigger Status Register */
struct {
__IOM uint32_t DTHRSTAT : 1; /*!< [0..0] Triggered DMA from FIFO reaching threshold */
__IOM uint32_t DTHR90STAT : 1; /*!< [1..1] Triggered DMA from FIFO reaching 90 percent full */
} DMATRIGSTAT_b;
} ;
__IM uint32_t RESERVED2[14];
union {
__IOM uint32_t DMACFG; /*!< (@ 0x00000280) DMA Configuration Register */
struct {
__IOM uint32_t DMAEN : 1; /*!< [0..0] DMA Enable */
__IM uint32_t : 1;
__IOM uint32_t DMADIR : 1; /*!< [2..2] Direction */
__IM uint32_t : 5;
__IOM uint32_t DMAPRI : 1; /*!< [8..8] Sets the Priority of the DMA request */
__IOM uint32_t DAUTOHIP : 1; /*!< [9..9] Raise priority to high on fifo full, and DMAPRI set to
low */
__IOM uint32_t DPWROFF : 1; /*!< [10..10] Power Off the ADC System upon DMACPL. */
} DMACFG_b;
} ;
__IM uint32_t RESERVED3;
union {
__IOM uint32_t DMATOTCOUNT; /*!< (@ 0x00000288) DMA Total Transfer Count */
struct {
__IOM uint32_t TOTCOUNT : 20; /*!< [19..0] Total Transfer Count. The transfer count must be a multiple
of the THR setting to avoid DMA overruns. */
} DMATOTCOUNT_b;
} ;
union {
__IOM uint32_t DMATARGADDR; /*!< (@ 0x0000028C) DMA Target Address Register */
struct {
__IOM uint32_t LTARGADDR : 20; /*!< [19..0] DMA Target Address. This register is not updated with
the current address of the DMA, but will remain static
with the original address during the DMA transfer. */
__IOM uint32_t UTARGADDR : 12; /*!< [31..20] SRAM Target */
} DMATARGADDR_b;
} ;
union {
__IOM uint32_t DMASTAT; /*!< (@ 0x00000290) DMA Status Register */
struct {
__IOM uint32_t DMATIP : 1; /*!< [0..0] DMA Transfer In Progress */
__IOM uint32_t DMACPL : 1; /*!< [1..1] DMA Transfer Complete */
__IOM uint32_t DMAERR : 1; /*!< [2..2] DMA Error */
} DMASTAT_b;
} ;
} PDM_Type; /*!< Size = 660 (0x294) */
/* =========================================================================================================================== */
/* ================ PWRCTRL ================ */
/* =========================================================================================================================== */
/**
* @brief PWR Controller Register Bank (PWRCTRL)
*/
typedef struct { /*!< (@ 0x40021000) PWRCTRL Structure */
union {
__IOM uint32_t SUPPLYSRC; /*!< (@ 0x00000000) This register controls the enable for BLE BUCK. */
struct {
__IOM uint32_t BLEBUCKEN : 1; /*!< [0..0] Enables and Selects the BLE Buck as the supply for the
BLE power domain or for Burst LDO. It takes the initial
value from Customer INFO space. Buck will be powered up
only if there is an active request for BLEH domain or Burst
mode and appropriate feature is allowed. */
} SUPPLYSRC_b;
} ;
union {
__IOM uint32_t SUPPLYSTATUS; /*!< (@ 0x00000004) Provides an indicator for the BLE BUCK and SIMO
BUCK status. Once the SIMO BUCK is powered
up MEM and CORE LDOs are disabled. */
struct {
__IOM uint32_t SIMOBUCKON : 1; /*!< [0..0] Indicates whether the Core/Mem low-voltage domains are
supplied from the LDO or the Buck. */
__IOM uint32_t BLEBUCKON : 1; /*!< [1..1] Indicates whether the BLE (if supported) domain and burst
(if supported) domain is supplied from the LDO or the Buck.
Buck will be powered up only if there is an active request
for BLEH domain or Burst mode and appropriate feature is
allowed. */
} SUPPLYSTATUS_b;
} ;
union {
__IOM uint32_t DEVPWREN; /*!< (@ 0x00000008) This enables various peripherals power domains. */
struct {
__IOM uint32_t PWRIOS : 1; /*!< [0..0] Power up IO Slave */
__IOM uint32_t PWRIOM0 : 1; /*!< [1..1] Power up IO Master 0 */
__IOM uint32_t PWRIOM1 : 1; /*!< [2..2] Power up IO Master 1 */
__IOM uint32_t PWRIOM2 : 1; /*!< [3..3] Power up IO Master 2 */
__IOM uint32_t PWRIOM3 : 1; /*!< [4..4] Power up IO Master 3 */
__IOM uint32_t PWRIOM4 : 1; /*!< [5..5] Power up IO Master 4 */
__IOM uint32_t PWRIOM5 : 1; /*!< [6..6] Power up IO Master 5 */
__IOM uint32_t PWRUART0 : 1; /*!< [7..7] Power up UART Controller 0 */
__IOM uint32_t PWRUART1 : 1; /*!< [8..8] Power up UART Controller 1 */
__IOM uint32_t PWRADC : 1; /*!< [9..9] Power up ADC Digital Controller */
__IOM uint32_t PWRSCARD : 1; /*!< [10..10] Power up SCARD Controller */
__IOM uint32_t PWRMSPI : 1; /*!< [11..11] Power up MSPI Controller */
__IOM uint32_t PWRPDM : 1; /*!< [12..12] Power up PDM block */
__IOM uint32_t PWRBLEL : 1; /*!< [13..13] Power up BLE controller */
} DEVPWREN_b;
} ;
union {
__IOM uint32_t MEMPWDINSLEEP; /*!< (@ 0x0000000C) This controls the power down of the SRAM banks
in deep sleep mode. If this is set, then
the power for that SRAM bank will be gated
when the core goes into deep sleep. Upon
wake, the data within the SRAMs will be
erased. If this is not set, retention voltage
will be applied to the SRAM bank when the
core goes into deep sleep. Upon wake, the
data within the SRAMs are retained. Do not
set this if the SRAM bank is used as the
target for DMA transfer while CPU in deep
sleep. */
struct {
__IOM uint32_t DTCMPWDSLP : 3; /*!< [2..0] power down DTCM in deep sleep */
__IOM uint32_t SRAMPWDSLP : 10; /*!< [12..3] Selects which SRAM banks are powered down in deep sleep
mode, causing the contents of the bank to be lost. */
__IOM uint32_t FLASH0PWDSLP : 1; /*!< [13..13] Power-down FLASH0 in deep sleep */
__IOM uint32_t FLASH1PWDSLP : 1; /*!< [14..14] Power-down FLASH1 in deep sleep */
__IM uint32_t : 16;
__IOM uint32_t CACHEPWDSLP : 1; /*!< [31..31] power down cache in deep sleep */
} MEMPWDINSLEEP_b;
} ;
union {
__IOM uint32_t MEMPWREN; /*!< (@ 0x00000010) This register enables the individual banks for
the memories. When set, power will be enabled
to the banks. This register works in conjunction
with the MEMPWDINSLEEP register. When this
register is set, then the MEMPWRINSLEEP
register will determine whether power is
enabled to the SRAMs in deep sleep. If this
register is not set, then power will always
be disabled to the memory bank. */
struct {
__IOM uint32_t DTCM : 3; /*!< [2..0] Power up DTCM */
__IOM uint32_t SRAM : 10; /*!< [12..3] Power up SRAM groups */
__IOM uint32_t FLASH0 : 1; /*!< [13..13] Power up FLASH0 */
__IOM uint32_t FLASH1 : 1; /*!< [14..14] Power up FLASH1 */
__IM uint32_t : 15;
__IOM uint32_t CACHEB0 : 1; /*!< [30..30] Power up Cache Bank 0. This works in conjunction with
Cache enable from flash_cache module. To power up cache
bank 0, cache has to be enabled and this bit has to be
set. */
__IOM uint32_t CACHEB2 : 1; /*!< [31..31] Power up Cache Bank 2. This works in conjunction with
Cache enable from flash_cache module. To power up cache
bank 2, cache has to be enabled and this bit has to be
set. */
} MEMPWREN_b;
} ;
union {
__IOM uint32_t MEMPWRSTATUS; /*!< (@ 0x00000014) It provides the power status for all the memory
banks including- caches, FLASH (0 and 1)
and all the SRAM groups. The status here
should reflect the enable provided by the
MEMPWREN register. There may be a lag time
between setting the bits in MEMPWREN register
and MEMPWRSTATUS register, due to the need
to cycle the power gate and isolation sequences
to the memory banks. */
struct {
__IOM uint32_t DTCM00 : 1; /*!< [0..0] This bit is 1 if power is supplied to DTCM GROUP0_0 */
__IOM uint32_t DTCM01 : 1; /*!< [1..1] This bit is 1 if power is supplied to DTCM GROUP0_1 */
__IOM uint32_t DTCM1 : 1; /*!< [2..2] This bit is 1 if power is supplied to DTCM GROUP1 */
__IOM uint32_t SRAM0 : 1; /*!< [3..3] This bit is 1 if power is supplied to SRAM GROUP0 */
__IOM uint32_t SRAM1 : 1; /*!< [4..4] This bit is 1 if power is supplied to SRAM GROUP1 */
__IOM uint32_t SRAM2 : 1; /*!< [5..5] This bit is 1 if power is supplied to SRAM GROUP2 */
__IOM uint32_t SRAM3 : 1; /*!< [6..6] This bit is 1 if power is supplied to SRAM GROUP3 */
__IOM uint32_t SRAM4 : 1; /*!< [7..7] This bit is 1 if power is supplied to SRAM GROUP4 */
__IOM uint32_t SRAM5 : 1; /*!< [8..8] This bit is 1 if power is supplied to SRAM GROUP5 */
__IOM uint32_t SRAM6 : 1; /*!< [9..9] This bit is 1 if power is supplied to SRAM GROUP6 */
__IOM uint32_t SRAM7 : 1; /*!< [10..10] This bit is 1 if power is supplied to SRAM GROUP7 */
__IOM uint32_t SRAM8 : 1; /*!< [11..11] This bit is 1 if power is supplied to SRAM GROUP8 */
__IOM uint32_t SRAM9 : 1; /*!< [12..12] This bit is 1 if power is supplied to SRAM GROUP9 */
__IOM uint32_t FLASH0 : 1; /*!< [13..13] This bit is 1 if power is supplied to FLASH 0 */
__IOM uint32_t FLASH1 : 1; /*!< [14..14] This bit is 1 if power is supplied to FLASH 1 */
__IOM uint32_t CACHEB0 : 1; /*!< [15..15] This bit is 1 if power is supplied to Cache Bank 0 */
__IOM uint32_t CACHEB2 : 1; /*!< [16..16] This bit is 1 if power is supplied to Cache Bank 2 */
} MEMPWRSTATUS_b;
} ;
union {
__IOM uint32_t DEVPWRSTATUS; /*!< (@ 0x00000018) This provides the power status for the peripheral
devices- BLEL, PDM, PDM, MSPI, SCARD, ADC,
UART0 and 1, IOM5 to 0, IOSLAVE and MCUL
(DMA and Fabrics) and MCUH (ARM core). The
status here should reflect the enable provided
by the DEVPWREN register. There may be a
lag time between setting the bits in DEVPWREN
register and DEVPWRSTATUS register, due
to the need to cycle the power gate, isolation
and reset sequences to the device power
domains. */
struct {
__IOM uint32_t MCUL : 1; /*!< [0..0] This bit is 1 if power is supplied to MCUL */
__IOM uint32_t MCUH : 1; /*!< [1..1] This bit is 1 if power is supplied to MCUH */
__IOM uint32_t HCPA : 1; /*!< [2..2] This bit is 1 if power is supplied to HCPA domain (IO
SLAVE, UART0, UART1, SCARD) */
__IOM uint32_t HCPB : 1; /*!< [3..3] This bit is 1 if power is supplied to HCPB domain (IO
MASTER 0, 1, 2) */
__IOM uint32_t HCPC : 1; /*!< [4..4] This bit is 1 if power is supplied to HCPC domain (IO
MASTER4, 5, 6) */
__IOM uint32_t PWRADC : 1; /*!< [5..5] This bit is 1 if power is supplied to ADC */
__IOM uint32_t PWRMSPI : 1; /*!< [6..6] This bit is 1 if power is supplied to MSPI */
__IOM uint32_t PWRPDM : 1; /*!< [7..7] This bit is 1 if power is supplied to PDM */
__IOM uint32_t BLEL : 1; /*!< [8..8] This bit is 1 if power is supplied to BLEL */
__IOM uint32_t BLEH : 1; /*!< [9..9] This bit is 1 if power is supplied to BLEH */
} DEVPWRSTATUS_b;
} ;
union {
__IOM uint32_t SRAMCTRL; /*!< (@ 0x0000001C) This register provides additional fine-tune power
management controls for the SRAMs and the
SRAM controller. This includes enabling
light sleep for the SRAM and TCM banks,
and clock gating for reduced dynamic power. */
struct {
__IM uint32_t : 1;
__IOM uint32_t SRAMCLKGATE : 1; /*!< [1..1] This bit is 1 if clock gating is allowed for individual
system SRAMs */
__IOM uint32_t SRAMMASTERCLKGATE : 1; /*!< [2..2] This bit is 1 when the master clock gate is enabled (top-level
clock gate for entire SRAM block) */
__IM uint32_t : 5;
__IOM uint32_t SRAMLIGHTSLEEP : 12; /*!< [19..8] Light Sleep enable for each TCM/SRAM bank. When 1, corresponding
bank will be put into light sleep. For optimal power, banks
should be put into light sleep while the system is active
but the bank has minimal or no accesses. */
} SRAMCTRL_b;
} ;
union {
__IOM uint32_t ADCSTATUS; /*!< (@ 0x00000020) This provides the power status for various blocks
within the ADC. These status comes directly
from the ADC module and is captured through
this interface. */
struct {
__IOM uint32_t ADCPWD : 1; /*!< [0..0] This bit indicates that the ADC is powered down */
__IOM uint32_t BGTPWD : 1; /*!< [1..1] This bit indicates that the ADC Band Gap is powered down */
__IOM uint32_t VPTATPWD : 1; /*!< [2..2] This bit indicates that the ADC temperature sensor input
buffer is powered down */
__IOM uint32_t VBATPWD : 1; /*!< [3..3] This bit indicates that the ADC VBAT resistor divider
is powered down */
__IOM uint32_t REFKEEPPWD : 1; /*!< [4..4] This bit indicates that the ADC REFKEEP is powered down */
__IOM uint32_t REFBUFPWD : 1; /*!< [5..5] This bit indicates that the ADC REFBUF is powered down */
} ADCSTATUS_b;
} ;
union {
__IOM uint32_t MISC; /*!< (@ 0x00000024) This register includes additional debug control
bits. This is an internal Ambiq-only register.
Customers should not attempt to change this
or else functionality cannot be guaranteed. */
struct {
__IM uint32_t : 3;
__IOM uint32_t FORCEMEMVRLPTIMERS : 1; /*!< [3..3] Control Bit to force Mem VR to LP mode in deep sleep
even when hfrc based ctimer or stimer is running. */
__IM uint32_t : 2;
__IOM uint32_t MEMVRLPBLE : 1; /*!< [6..6] Control Bit to let Mem VR go to lp mode in deep sleep
even when BLEL or BLEH is powered on given none of the
other domains require it. */
} MISC_b;
} ;
union {
__IOM uint32_t DEVPWREVENTEN; /*!< (@ 0x00000028) This register controls which feature trigger
will result in an event to the CPU. It includes
all the power on status for the core domains,
as well as the Burst event. If any bits
are set, then if the domain is turned on,
it will result in an event to the ARM core. */
struct {
__IOM uint32_t MCULEVEN : 1; /*!< [0..0] Control MCUL power-on status event */
__IOM uint32_t MCUHEVEN : 1; /*!< [1..1] Control MCUH power-on status event */
__IOM uint32_t HCPAEVEN : 1; /*!< [2..2] Control HCPA power-on status event */
__IOM uint32_t HCPBEVEN : 1; /*!< [3..3] Control HCPB power-on status event */
__IOM uint32_t HCPCEVEN : 1; /*!< [4..4] Control HCPC power-on status event */
__IOM uint32_t ADCEVEN : 1; /*!< [5..5] Control ADC power-on status event */
__IOM uint32_t MSPIEVEN : 1; /*!< [6..6] Control MSPI power-on status event */
__IOM uint32_t PDMEVEN : 1; /*!< [7..7] Control PDM power-on status event */
__IOM uint32_t BLELEVEN : 1; /*!< [8..8] Control BLE power-on status event */
__IM uint32_t : 20;
__IOM uint32_t BLEFEATUREEVEN : 1; /*!< [29..29] Control BLEFEATURE status event */
__IOM uint32_t BURSTFEATUREEVEN : 1; /*!< [30..30] Control BURSTFEATURE status event */
__IOM uint32_t BURSTEVEN : 1; /*!< [31..31] Control BURST status event */
} DEVPWREVENTEN_b;
} ;
union {
__IOM uint32_t MEMPWREVENTEN; /*!< (@ 0x0000002C) This register controls which power enable for
the memories will result in an event to
the CPU. It includes all the power on status
for the memory domains. If any bits are
set, then if the domain is turned on, it
will result in an event to the ARM core. */
struct {
__IOM uint32_t DTCMEN : 3; /*!< [2..0] Enable DTCM power-on status event */
__IOM uint32_t SRAMEN : 10; /*!< [12..3] Control SRAM power-on status event */
__IOM uint32_t FLASH0EN : 1; /*!< [13..13] Control FLASH power-on status event */
__IOM uint32_t FLASH1EN : 1; /*!< [14..14] Control FLASH power-on status event */
__IM uint32_t : 15;
__IOM uint32_t CACHEB0EN : 1; /*!< [30..30] Control CACHE BANK 0 power-on status event */
__IOM uint32_t CACHEB2EN : 1; /*!< [31..31] Control CACHEB2 power-on status event */
} MEMPWREVENTEN_b;
} ;
} PWRCTRL_Type; /*!< Size = 48 (0x30) */
/* =========================================================================================================================== */
/* ================ RSTGEN ================ */
/* =========================================================================================================================== */
/**
* @brief MCU Reset Generator (RSTGEN)
*/
typedef struct { /*!< (@ 0x40000000) RSTGEN Structure */
union {
__IOM uint32_t CFG; /*!< (@ 0x00000000) Reset configuration register. This controls the
reset enables for brownout condition, and
for the expiration of the watch dog timer. */
struct {
__IOM uint32_t BODHREN : 1; /*!< [0..0] Brown out high (2.1v) reset enable. */
__IOM uint32_t WDREN : 1; /*!< [1..1] Watchdog Timer Reset Enable. NOTE: The WDT module must
also be configured for WDT reset. This includes enabling
the RESEN bit in WDTCFG register in Watch dog timer block. */
} CFG_b;
} ;
union {
__IOM uint32_t SWPOI; /*!< (@ 0x00000004) This is the software POI reset. writing the key
value to this register will trigger a POI
to the system. This will cause a reset to
all blocks except for registers in clock
gen, RTC and the stimer. */
struct {
__IOM uint32_t SWPOIKEY : 8; /*!< [7..0] 0x1B generates a software POI reset. This is a write-only
register. Reading from this register will yield only all
0s. */
} SWPOI_b;
} ;
union {
__IOM uint32_t SWPOR; /*!< (@ 0x00000008) This is the software POR reset. Writing the key
value to this register will trigger a POR
to the system. This will cause a reset to
all blocks except for registers in clock
gen, RTC, power management unit, the stimer,
and the power management unit. */
struct {
__IOM uint32_t SWPORKEY : 8; /*!< [7..0] 0xD4 generates a software POR reset. */
} SWPOR_b;
} ;
__IM uint32_t RESERVED[2];
union {
__IOM uint32_t TPIURST; /*!< (@ 0x00000014) This will trigger a reset for the TPIU unit. */
struct {
__IOM uint32_t TPIURST : 1; /*!< [0..0] Static reset for the TPIU. Write to '1' to assert reset
to TPIU. Write to '0' to clear the reset. */
} TPIURST_b;
} ;
__IM uint32_t RESERVED1[122];
union {
__IOM uint32_t INTEN; /*!< (@ 0x00000200) Set bits in this register to allow this module
to generate the corresponding interrupt. */
struct {
__IOM uint32_t BODH : 1; /*!< [0..0] Enables an interrupt that triggers when VCC is below
BODH level. */
} INTEN_b;
} ;
union {
__IOM uint32_t INTSTAT; /*!< (@ 0x00000204) Read bits from this register to discover the
cause of a recent interrupt. */
struct {
__IOM uint32_t BODH : 1; /*!< [0..0] Enables an interrupt that triggers when VCC is below
BODH level. */
} INTSTAT_b;
} ;
union {
__IOM uint32_t INTCLR; /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
the interrupt status associated with that
bit. */
struct {
__IOM uint32_t BODH : 1; /*!< [0..0] Enables an interrupt that triggers when VCC is below
BODH level. */
} INTCLR_b;
} ;
union {
__IOM uint32_t INTSET; /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
generate an interrupt from this module.
(Generally used for testing purposes). */
struct {
__IOM uint32_t BODH : 1; /*!< [0..0] Enables an interrupt that triggers when VCC is below
BODH level. */
} INTSET_b;
} ;
__IM uint32_t RESERVED2[67107708];
union {
__IOM uint32_t STAT; /*!< (@ 0x0FFFF000) This register contains the status for brownout
events and the causes for resets.
NOTE 1: All bits in this register, including
reserved bits, are writable. Therefore care
should be taken not to write this register.
NOTE 2: This register does not retain its
value across a core deepsleep cycle. Therefore
applications needing to use this value after
deep sleep must copy and save this register
to SRAM before initiating the first deep
sleep cycle. */
struct {
__IOM uint32_t EXRSTAT : 1; /*!< [0..0] Reset was initiated by an External Reset (SBL). */
__IOM uint32_t PORSTAT : 1; /*!< [1..1] Reset was initiated by a Power-On Reset (SBL). */
__IOM uint32_t BORSTAT : 1; /*!< [2..2] Reset was initiated by a Brown-Out Reset (SBL). */
__IOM uint32_t SWRSTAT : 1; /*!< [3..3] Reset was a initiated by SW POR or AIRCR Reset (SBL). */
__IOM uint32_t POIRSTAT : 1; /*!< [4..4] Reset was a initiated by Software POI Reset (SBL). */
__IOM uint32_t DBGRSTAT : 1; /*!< [5..5] Reset was a initiated by Debugger Reset (SBL). */
__IOM uint32_t WDRSTAT : 1; /*!< [6..6] Reset was initiated by a Watchdog Timer Reset (SBL). */
__IOM uint32_t BOUSTAT : 1; /*!< [7..7] An Unregulated Supply Brownout Event occurred (SBL). */
__IOM uint32_t BOCSTAT : 1; /*!< [8..8] A Core Regulator Brownout Event occurred (SBL). */
__IOM uint32_t BOFSTAT : 1; /*!< [9..9] A Memory Regulator Brownout Event occurred (SBL). */
__IOM uint32_t BOBSTAT : 1; /*!< [10..10] A BLE/Burst Regulator Brownout Event occurred (SBL). */
__IM uint32_t : 19;
__IOM uint32_t FBOOT : 1; /*!< [30..30] Set if current boot was initiated by soft reset and
resulted in Fast Boot (SBL). */
__IOM uint32_t SBOOT : 1; /*!< [31..31] Set when booting securely (SBL). */
} STAT_b;
} ;
} RSTGEN_Type; /*!< Size = 268431364 (0xffff004) */
/* =========================================================================================================================== */
/* ================ RTC ================ */
/* =========================================================================================================================== */
/**
* @brief Real Time Clock (RTC)
*/
typedef struct { /*!< (@ 0x40004200) RTC Structure */
__IM uint32_t RESERVED[16];
union {
__IOM uint32_t CTRLOW; /*!< (@ 0x00000040) This counter contains the values for hour, minutes,
seconds and 100ths of a second Counter. */
struct {
__IOM uint32_t CTR100 : 8; /*!< [7..0] 100ths of a second Counter */
__IOM uint32_t CTRSEC : 7; /*!< [14..8] Seconds Counter */
__IM uint32_t : 1;
__IOM uint32_t CTRMIN : 7; /*!< [22..16] Minutes Counter */
__IM uint32_t : 1;
__IOM uint32_t CTRHR : 6; /*!< [29..24] Hours Counter */
} CTRLOW_b;
} ;
union {
__IOM uint32_t CTRUP; /*!< (@ 0x00000044) This register contains the day, month and year
information. It contains which day in the
week, and the century as well. The information
of the century can also be derived from
the year information. The 31st bit contains
the error bit. See description in the register
bit for condition when error is triggered. */
struct {
__IOM uint32_t CTRDATE : 6; /*!< [5..0] Date Counter */
__IM uint32_t : 2;
__IOM uint32_t CTRMO : 5; /*!< [12..8] Months Counter */
__IM uint32_t : 3;
__IOM uint32_t CTRYR : 8; /*!< [23..16] Years Counter */
__IOM uint32_t CTRWKDY : 3; /*!< [26..24] Weekdays Counter */
__IOM uint32_t CB : 1; /*!< [27..27] Century */
__IOM uint32_t CEB : 1; /*!< [28..28] Century enable */
__IM uint32_t : 2;
__IOM uint32_t CTERR : 1; /*!< [31..31] Counter read error status. Error is triggered when
software reads the lower word of the counters, and fails
to read the upper counter within 1/100 second. This is
because when the lower counter is read, the upper counter
is held off from incrementing until it is read so that
the full time stamp can be read. */
} CTRUP_b;
} ;
union {
__IOM uint32_t ALMLOW; /*!< (@ 0x00000048) This register is the Alarm settings for hours,
minutes, second and 1/100th seconds settings. */
struct {
__IOM uint32_t ALM100 : 8; /*!< [7..0] 100ths of a second Alarm */
__IOM uint32_t ALMSEC : 7; /*!< [14..8] Seconds Alarm */
__IM uint32_t : 1;
__IOM uint32_t ALMMIN : 7; /*!< [22..16] Minutes Alarm */
__IM uint32_t : 1;
__IOM uint32_t ALMHR : 6; /*!< [29..24] Hours Alarm */
} ALMLOW_b;
} ;
union {
__IOM uint32_t ALMUP; /*!< (@ 0x0000004C) This register is the alarm settings for week,
month and day. */
struct {
__IOM uint32_t ALMDATE : 6; /*!< [5..0] Date Alarm */
__IM uint32_t : 2;
__IOM uint32_t ALMMO : 5; /*!< [12..8] Months Alarm */
__IM uint32_t : 3;
__IOM uint32_t ALMWKDY : 3; /*!< [18..16] Weekdays Alarm */
} ALMUP_b;
} ;
union {
__IOM uint32_t RTCCTL; /*!< (@ 0x00000050) This is the register control for the RTC module.
It sets the 12 or 24 hours mode, enables
counter writes and sets the alarm repeat
interval. */
struct {
__IOM uint32_t WRTC : 1; /*!< [0..0] Counter write control */
__IOM uint32_t RPT : 3; /*!< [3..1] Alarm repeat interval */
__IOM uint32_t RSTOP : 1; /*!< [4..4] RTC input clock control */
__IOM uint32_t HR1224 : 1; /*!< [5..5] Hours Counter mode */
} RTCCTL_b;
} ;
__IM uint32_t RESERVED1[43];
union {
__IOM uint32_t INTEN; /*!< (@ 0x00000100) Set bits in this register to allow this module
to generate the corresponding interrupt. */
struct {
__IOM uint32_t ALM : 1; /*!< [0..0] RTC Alarm interrupt */
} INTEN_b;
} ;
union {
__IOM uint32_t INTSTAT; /*!< (@ 0x00000104) Read bits from this register to discover the
cause of a recent interrupt. */
struct {
__IOM uint32_t ALM : 1; /*!< [0..0] RTC Alarm interrupt */
} INTSTAT_b;
} ;
union {
__IOM uint32_t INTCLR; /*!< (@ 0x00000108) Write a 1 to a bit in this register to clear
the interrupt status associated with that
bit. */
struct {
__IOM uint32_t ALM : 1; /*!< [0..0] RTC Alarm interrupt */
} INTCLR_b;
} ;
union {
__IOM uint32_t INTSET; /*!< (@ 0x0000010C) Write a 1 to a bit in this register to instantly
generate an interrupt from this module.
(Generally used for testing purposes). */
struct {
__IOM uint32_t ALM : 1; /*!< [0..0] RTC Alarm interrupt */
} INTSET_b;
} ;
} RTC_Type; /*!< Size = 272 (0x110) */
/* =========================================================================================================================== */
/* ================ SCARD ================ */
/* =========================================================================================================================== */
/**
* @brief Serial ISO7816 (SCARD)
*/
typedef struct { /*!< (@ 0x40080000) SCARD Structure */
union {
__IOM uint32_t SR; /*!< (@ 0x00000000) ISO7816 interrupt status */
struct {
__IOM uint32_t FNE : 1; /*!< [0..0] RX FIFO not empty. */
__IOM uint32_t TBERBF : 1; /*!< [1..1] FIFO empty (transmit) or full (receive). */
__IOM uint32_t FER : 1; /*!< [2..2] Framing error. */
__IOM uint32_t OVR : 1; /*!< [3..3] RX FIFO overflow. */
__IOM uint32_t PE : 1; /*!< [4..4] Parity Error. */
__IOM uint32_t FT2REND : 1; /*!< [5..5] TX to RX finished. */
__IOM uint32_t FHF : 1; /*!< [6..6] FIFO Half Full. */
} SR_b;
} ;
union {
__IOM uint32_t IER; /*!< (@ 0x00000004) ISO7816 interrupt enable */
struct {
__IOM uint32_t FNEEN : 1; /*!< [0..0] RX FIFO not empty interrupt enable. */
__IOM uint32_t TBERBFEN : 1; /*!< [1..1] FIFO empty (transmit) or full (receive) interrupt enable. */
__IOM uint32_t FEREN : 1; /*!< [2..2] Framing error interrupt enable. */
__IOM uint32_t OVREN : 1; /*!< [3..3] RX FIFOI overflow interrupt enable. */
__IOM uint32_t PEEN : 1; /*!< [4..4] Parity Error interrupt enable. */
__IOM uint32_t FT2RENDEN : 1; /*!< [5..5] TX to RX finished interrupt enable. */
__IOM uint32_t FHFEN : 1; /*!< [6..6] FIFO Half Full interrupt enable. */
} IER_b;
} ;
union {
__IOM uint32_t TCR; /*!< (@ 0x00000008) ISO7816 transmit control */
struct {
__IOM uint32_t CONV : 1; /*!< [0..0] Conversion inversion control. */
__IOM uint32_t SS : 1; /*!< [1..1] Use first byte to configure conversion. */
__IOM uint32_t LCT : 1; /*!< [2..2] Fast TX to RX. */
__IOM uint32_t TR : 1; /*!< [3..3] Transmit/receive mode. */
__IOM uint32_t PROT : 1; /*!< [4..4] PROT control. */
__IOM uint32_t AUTOCONV : 1; /*!< [5..5] Automatic conversion. */
__IOM uint32_t FIP : 1; /*!< [6..6] Parity select. */
__IOM uint32_t DMAMD : 1; /*!< [7..7] DMA direction. */
} TCR_b;
} ;
union {
__IOM uint32_t UCR; /*!< (@ 0x0000000C) ISO7816 user control */
struct {
__IOM uint32_t CST : 1; /*!< [0..0] Clock control. */
__IOM uint32_t RIU : 1; /*!< [1..1] ISO7816 reset. This bit is write-only. */
__IOM uint32_t RSTIN : 1; /*!< [2..2] Reset polarity. */
__IOM uint32_t RETXEN : 1; /*!< [3..3] Enable TX/RX time configuration. */
} UCR_b;
} ;
union {
__IOM uint32_t DR; /*!< (@ 0x00000010) ISO7816 data */
struct {
__IOM uint32_t DR : 8; /*!< [7..0] Data register. */
} DR_b;
} ;
union {
__IOM uint32_t BPRL; /*!< (@ 0x00000014) ISO7816 baud rate low */
struct {
__IOM uint32_t BPRL : 8; /*!< [7..0] Baud rate low */
} BPRL_b;
} ;
union {
__IOM uint32_t BPRH; /*!< (@ 0x00000018) ISO7816 baud rate high */
struct {
__IOM uint32_t BPRH : 4; /*!< [3..0] Baud rate high */
} BPRH_b;
} ;
union {
__IOM uint32_t UCR1; /*!< (@ 0x0000001C) ISO7816 user control 1 */
struct {
__IOM uint32_t PR : 1; /*!< [0..0] Query Card Detect. */
__IM uint32_t : 1;
__IOM uint32_t STSP : 1; /*!< [2..2] ETU counter control. This bit is write-only. */
__IOM uint32_t T1PAREN : 1; /*!< [3..3] Parity check control. */
__IOM uint32_t CLKIOV : 1; /*!< [4..4] Output clock level. */
__IOM uint32_t ENLASTB : 1; /*!< [5..5] Enable last byte function. */
} UCR1_b;
} ;
union {
__IOM uint32_t SR1; /*!< (@ 0x00000020) ISO7816 interrupt status 1 */
struct {
__IOM uint32_t ECNTOVER : 1; /*!< [0..0] ETU counter overflow. */
__IOM uint32_t PRL : 1; /*!< [1..1] Card insert/remove. */
__IOM uint32_t SYNCEND : 1; /*!< [2..2] Write complete synchronization. */
__IOM uint32_t IDLE : 1; /*!< [3..3] ISO7816 idle. */
} SR1_b;
} ;
union {
__IOM uint32_t IER1; /*!< (@ 0x00000024) ISO7816 interrupt enable 1 */
struct {
__IOM uint32_t ECNTOVEREN : 1; /*!< [0..0] ETU counter overflow interrupt enable. */
__IOM uint32_t PRLEN : 1; /*!< [1..1] Card insert/remove interrupt enable. */
__IOM uint32_t SYNCENDEN : 1; /*!< [2..2] Write complete synchronization interrupt enable. */
} IER1_b;
} ;
union {
__IOM uint32_t ECNTL; /*!< (@ 0x00000028) ETU counter low */
struct {
__IOM uint32_t ECNTL : 8; /*!< [7..0] ETU counter low register. */
} ECNTL_b;
} ;
union {
__IOM uint32_t ECNTH; /*!< (@ 0x0000002C) ETU counter high */
struct {
__IOM uint32_t ECNTH : 8; /*!< [7..0] ETU counter high register. */
} ECNTH_b;
} ;
union {
__IOM uint32_t GTR; /*!< (@ 0x00000030) ISO7816 guard time configuration */
struct {
__IOM uint32_t GTR : 8; /*!< [7..0] Guard time configuration register. */
} GTR_b;
} ;
union {
__IOM uint32_t RETXCNT; /*!< (@ 0x00000034) ISO7816 resend count */
struct {
__IOM uint32_t RETXCNT : 4; /*!< [3..0] Resend count register. */
} RETXCNT_b;
} ;
union {
__IOM uint32_t RETXCNTRMI; /*!< (@ 0x00000038) ISO7816 resent count inquiry */
struct {
__IOM uint32_t RETXCNTRMI : 4; /*!< [3..0] Resent count inquiry register. */
} RETXCNTRMI_b;
} ;
__IM uint32_t RESERVED[49];
union {
__IOM uint32_t CLKCTRL; /*!< (@ 0x00000100) SCARD external clock control */
struct {
__IOM uint32_t CLKEN : 1; /*!< [0..0] Enable the serial source clock for SCARD. */
__IOM uint32_t APBCLKEN : 1; /*!< [1..1] Enable the SCARD APB clock to run continuously. */
} CLKCTRL_b;
} ;
} SCARD_Type; /*!< Size = 260 (0x104) */
/* =========================================================================================================================== */
/* ================ SECURITY ================ */
/* =========================================================================================================================== */
/**
* @brief Security Interfaces (SECURITY)
*/
typedef struct { /*!< (@ 0x40030000) SECURITY Structure */
union {
__IOM uint32_t CTRL; /*!< (@ 0x00000000) Control Register */
struct {
__IOM uint32_t ENABLE : 1; /*!< [0..0] Function Enable. Software should set the ENABLE bit to
initiate a CRC operation. Hardware will clear the ENABLE
bit upon completion. */
__IM uint32_t : 3;
__IOM uint32_t FUNCTION : 4; /*!< [7..4] Function Select */
__IM uint32_t : 23;
__IOM uint32_t CRCERROR : 1; /*!< [31..31] CRC Error Status - Set to 1 if an error occurs during
a CRC operation. Cleared when CTRL register is written
(with any value). Usually indicates an invalid address
range. */
} CTRL_b;
} ;
__IM uint32_t RESERVED[3];
union {
__IOM uint32_t SRCADDR; /*!< (@ 0x00000010) Source Addresss */
struct {
__IOM uint32_t ADDR : 32; /*!< [31..0] Source Buffer Address. Address may be byte aligned,
but the length must be a multiple of 4 bits. */
} SRCADDR_b;
} ;
__IM uint32_t RESERVED1[3];
union {
__IOM uint32_t LEN; /*!< (@ 0x00000020) Length */
struct {
__IM uint32_t : 2;
__IOM uint32_t LEN : 18; /*!< [19..2] Buffer size (bottom two bits assumed to be zero to ensure
a multiple of 4 bytes) */
} LEN_b;
} ;
__IM uint32_t RESERVED2[3];
union {
__IOM uint32_t RESULT; /*!< (@ 0x00000030) CRC Seed/Result Register */
struct {
__IOM uint32_t CRC : 32; /*!< [31..0] CRC Seed/Result. Software must seed the CRC with 0xFFFFFFFF
before starting a CRC operation (unless the CRC is continued
from a previous operation). */
} RESULT_b;
} ;
__IM uint32_t RESERVED3[17];
union {
__IOM uint32_t LOCKCTRL; /*!< (@ 0x00000078) LOCK Control Register */
struct {
__IOM uint32_t SELECT : 8; /*!< [7..0] LOCK Function Select register. */
} LOCKCTRL_b;
} ;
union {
__IOM uint32_t LOCKSTAT; /*!< (@ 0x0000007C) LOCK Status Register */
struct {
__IOM uint32_t STATUS : 32; /*!< [31..0] LOCK Status register. This register is a bitmask for
which resources are currently unlocked. These bits are
one-hot per resource. */
} LOCKSTAT_b;
} ;
union {
__IOM uint32_t KEY0; /*!< (@ 0x00000080) Key0 Register */
struct {
__IOM uint32_t KEY0 : 32; /*!< [31..0] Bits [31:0] of the 128-bit key should be written to
this register. To protect key values, the register always
returns 0x00000000. */
} KEY0_b;
} ;
union {
__IOM uint32_t KEY1; /*!< (@ 0x00000084) Key1 Register */
struct {
__IOM uint32_t KEY1 : 32; /*!< [31..0] Bits [63:32] of the 128-bit key should be written to
this register. To protect key values, the register always
returns 0x00000000. */
} KEY1_b;
} ;
union {
__IOM uint32_t KEY2; /*!< (@ 0x00000088) Key2 Register */
struct {
__IOM uint32_t KEY2 : 32; /*!< [31..0] Bits [95:64] of the 128-bit key should be written to
this register. To protect key values, the register always
returns 0x00000000. */
} KEY2_b;
} ;
union {
__IOM uint32_t KEY3; /*!< (@ 0x0000008C) Key3 Register */
struct {
__IOM uint32_t KEY3 : 32; /*!< [31..0] Bits [127:96] of the 128-bit key should be written to
this register. To protect key values, the register always
returns 0x00000000. */
} KEY3_b;
} ;
} SECURITY_Type; /*!< Size = 144 (0x90) */
/* =========================================================================================================================== */
/* ================ UART0 ================ */
/* =========================================================================================================================== */
/**
* @brief Serial UART (UART0)
*/
typedef struct { /*!< (@ 0x4001C000) UART0 Structure */
union {
__IOM uint32_t DR; /*!< (@ 0x00000000) UART Data Register */
struct {
__IOM uint32_t DATA : 8; /*!< [7..0] This is the UART data port. */
__IOM uint32_t FEDATA : 1; /*!< [8..8] This is the framing error indicator. */
__IOM uint32_t PEDATA : 1; /*!< [9..9] This is the parity error indicator. */
__IOM uint32_t BEDATA : 1; /*!< [10..10] This is the break error indicator. */
__IOM uint32_t OEDATA : 1; /*!< [11..11] This is the overrun error indicator. */
} DR_b;
} ;
union {
__IOM uint32_t RSR; /*!< (@ 0x00000004) UART Status Register */
struct {
__IOM uint32_t FESTAT : 1; /*!< [0..0] This is the framing error indicator. */
__IOM uint32_t PESTAT : 1; /*!< [1..1] This is the parity error indicator. */
__IOM uint32_t BESTAT : 1; /*!< [2..2] This is the break error indicator. */
__IOM uint32_t OESTAT : 1; /*!< [3..3] This is the overrun error indicator. */
} RSR_b;
} ;
__IM uint32_t RESERVED[4];
union {
__IOM uint32_t FR; /*!< (@ 0x00000018) Flag Register */
struct {
__IOM uint32_t CTS : 1; /*!< [0..0] This bit holds the clear to send indicator. */
__IOM uint32_t DSR : 1; /*!< [1..1] This bit holds the data set ready indicator. */
__IOM uint32_t DCD : 1; /*!< [2..2] This bit holds the data carrier detect indicator. */
__IOM uint32_t BUSY : 1; /*!< [3..3] This bit holds the busy indicator. */
__IOM uint32_t RXFE : 1; /*!< [4..4] This bit holds the receive FIFO empty indicator. */
__IOM uint32_t TXFF : 1; /*!< [5..5] This bit holds the transmit FIFO full indicator. */
__IOM uint32_t RXFF : 1; /*!< [6..6] This bit holds the receive FIFO full indicator. */
__IOM uint32_t TXFE : 1; /*!< [7..7] This bit holds the transmit FIFO empty indicator. */
__IOM uint32_t TXBUSY : 1; /*!< [8..8] This bit holds the transmit BUSY indicator. */
} FR_b;
} ;
__IM uint32_t RESERVED1;
union {
__IOM uint32_t ILPR; /*!< (@ 0x00000020) IrDA Counter */
struct {
__IOM uint32_t ILPDVSR : 8; /*!< [7..0] These bits hold the IrDA counter divisor. */
} ILPR_b;
} ;
union {
__IOM uint32_t IBRD; /*!< (@ 0x00000024) Integer Baud Rate Divisor */
struct {
__IOM uint32_t DIVINT : 16; /*!< [15..0] These bits hold the baud integer divisor. */
} IBRD_b;
} ;
union {
__IOM uint32_t FBRD; /*!< (@ 0x00000028) Fractional Baud Rate Divisor */
struct {
__IOM uint32_t DIVFRAC : 6; /*!< [5..0] These bits hold the baud fractional divisor. */
} FBRD_b;
} ;
union {
__IOM uint32_t LCRH; /*!< (@ 0x0000002C) Line Control High */
struct {
__IOM uint32_t BRK : 1; /*!< [0..0] This bit holds the break set. */
__IOM uint32_t PEN : 1; /*!< [1..1] This bit holds the parity enable. */
__IOM uint32_t EPS : 1; /*!< [2..2] This bit holds the even parity select. */
__IOM uint32_t STP2 : 1; /*!< [3..3] This bit holds the two stop bits select. */
__IOM uint32_t FEN : 1; /*!< [4..4] This bit holds the FIFO enable. */
__IOM uint32_t WLEN : 2; /*!< [6..5] These bits hold the write length. */
__IOM uint32_t SPS : 1; /*!< [7..7] This bit holds the stick parity select. */
} LCRH_b;
} ;
union {
__IOM uint32_t CR; /*!< (@ 0x00000030) Control Register */
struct {
__IOM uint32_t UARTEN : 1; /*!< [0..0] This bit is the UART enable. */
__IOM uint32_t SIREN : 1; /*!< [1..1] This bit is the SIR ENDEC enable. */
__IOM uint32_t SIRLP : 1; /*!< [2..2] This bit is the SIR low power select. */
__IOM uint32_t CLKEN : 1; /*!< [3..3] This bit is the UART clock enable. */
__IOM uint32_t CLKSEL : 3; /*!< [6..4] This bitfield is the UART clock select. */
__IOM uint32_t LBE : 1; /*!< [7..7] This bit is the loopback enable. */
__IOM uint32_t TXE : 1; /*!< [8..8] This bit is the transmit enable. */
__IOM uint32_t RXE : 1; /*!< [9..9] This bit is the receive enable. */
__IOM uint32_t DTR : 1; /*!< [10..10] This bit enables data transmit ready. */
__IOM uint32_t RTS : 1; /*!< [11..11] This bit enables request to send. */
__IOM uint32_t OUT1 : 1; /*!< [12..12] This bit holds modem Out1. */
__IOM uint32_t OUT2 : 1; /*!< [13..13] This bit holds modem Out2. */
__IOM uint32_t RTSEN : 1; /*!< [14..14] This bit enables RTS hardware flow control. */
__IOM uint32_t CTSEN : 1; /*!< [15..15] This bit enables CTS hardware flow control. */
} CR_b;
} ;
union {
__IOM uint32_t IFLS; /*!< (@ 0x00000034) FIFO Interrupt Level Select */
struct {
__IOM uint32_t TXIFLSEL : 3; /*!< [2..0] These bits hold the transmit FIFO interrupt level. */
__IOM uint32_t RXIFLSEL : 3; /*!< [5..3] These bits hold the receive FIFO interrupt level. */
} IFLS_b;
} ;
union {
__IOM uint32_t IER; /*!< (@ 0x00000038) Interrupt Enable */
struct {
__IOM uint32_t TXCMPMIM : 1; /*!< [0..0] This bit holds the modem TXCMP interrupt enable. */
__IOM uint32_t CTSMIM : 1; /*!< [1..1] This bit holds the modem CTS interrupt enable. */
__IOM uint32_t DCDMIM : 1; /*!< [2..2] This bit holds the modem DCD interrupt enable. */
__IOM uint32_t DSRMIM : 1; /*!< [3..3] This bit holds the modem DSR interrupt enable. */
__IOM uint32_t RXIM : 1; /*!< [4..4] This bit holds the receive interrupt enable. */
__IOM uint32_t TXIM : 1; /*!< [5..5] This bit holds the transmit interrupt enable. */
__IOM uint32_t RTIM : 1; /*!< [6..6] This bit holds the receive timeout interrupt enable. */
__IOM uint32_t FEIM : 1; /*!< [7..7] This bit holds the framing error interrupt enable. */
__IOM uint32_t PEIM : 1; /*!< [8..8] This bit holds the parity error interrupt enable. */
__IOM uint32_t BEIM : 1; /*!< [9..9] This bit holds the break error interrupt enable. */
__IOM uint32_t OEIM : 1; /*!< [10..10] This bit holds the overflow interrupt enable. */
} IER_b;
} ;
union {
__IOM uint32_t IES; /*!< (@ 0x0000003C) Interrupt Status */
struct {
__IOM uint32_t TXCMPMRIS : 1; /*!< [0..0] This bit holds the modem TXCMP interrupt status. */
__IOM uint32_t CTSMRIS : 1; /*!< [1..1] This bit holds the modem CTS interrupt status. */
__IOM uint32_t DCDMRIS : 1; /*!< [2..2] This bit holds the modem DCD interrupt status. */
__IOM uint32_t DSRMRIS : 1; /*!< [3..3] This bit holds the modem DSR interrupt status. */
__IOM uint32_t RXRIS : 1; /*!< [4..4] This bit holds the receive interrupt status. */
__IOM uint32_t TXRIS : 1; /*!< [5..5] This bit holds the transmit interrupt status. */
__IOM uint32_t RTRIS : 1; /*!< [6..6] This bit holds the receive timeout interrupt status. */
__IOM uint32_t FERIS : 1; /*!< [7..7] This bit holds the framing error interrupt status. */
__IOM uint32_t PERIS : 1; /*!< [8..8] This bit holds the parity error interrupt status. */
__IOM uint32_t BERIS : 1; /*!< [9..9] This bit holds the break error interrupt status. */
__IOM uint32_t OERIS : 1; /*!< [10..10] This bit holds the overflow interrupt status. */
} IES_b;
} ;
union {
__IOM uint32_t MIS; /*!< (@ 0x00000040) Masked Interrupt Status */
struct {
__IOM uint32_t TXCMPMMIS : 1; /*!< [0..0] This bit holds the modem TXCMP interrupt status masked. */
__IOM uint32_t CTSMMIS : 1; /*!< [1..1] This bit holds the modem CTS interrupt status masked. */
__IOM uint32_t DCDMMIS : 1; /*!< [2..2] This bit holds the modem DCD interrupt status masked. */
__IOM uint32_t DSRMMIS : 1; /*!< [3..3] This bit holds the modem DSR interrupt status masked. */
__IOM uint32_t RXMIS : 1; /*!< [4..4] This bit holds the receive interrupt status masked. */
__IOM uint32_t TXMIS : 1; /*!< [5..5] This bit holds the transmit interrupt status masked. */
__IOM uint32_t RTMIS : 1; /*!< [6..6] This bit holds the receive timeout interrupt status masked. */
__IOM uint32_t FEMIS : 1; /*!< [7..7] This bit holds the framing error interrupt status masked. */
__IOM uint32_t PEMIS : 1; /*!< [8..8] This bit holds the parity error interrupt status masked. */
__IOM uint32_t BEMIS : 1; /*!< [9..9] This bit holds the break error interrupt status masked. */
__IOM uint32_t OEMIS : 1; /*!< [10..10] This bit holds the overflow interrupt status masked. */
} MIS_b;
} ;
union {
__IOM uint32_t IEC; /*!< (@ 0x00000044) Interrupt Clear */
struct {
__IOM uint32_t TXCMPMIC : 1; /*!< [0..0] This bit holds the modem TXCMP interrupt clear. */
__IOM uint32_t CTSMIC : 1; /*!< [1..1] This bit holds the modem CTS interrupt clear. */
__IOM uint32_t DCDMIC : 1; /*!< [2..2] This bit holds the modem DCD interrupt clear. */
__IOM uint32_t DSRMIC : 1; /*!< [3..3] This bit holds the modem DSR interrupt clear. */
__IOM uint32_t RXIC : 1; /*!< [4..4] This bit holds the receive interrupt clear. */
__IOM uint32_t TXIC : 1; /*!< [5..5] This bit holds the transmit interrupt clear. */
__IOM uint32_t RTIC : 1; /*!< [6..6] This bit holds the receive timeout interrupt clear. */
__IOM uint32_t FEIC : 1; /*!< [7..7] This bit holds the framing error interrupt clear. */
__IOM uint32_t PEIC : 1; /*!< [8..8] This bit holds the parity error interrupt clear. */
__IOM uint32_t BEIC : 1; /*!< [9..9] This bit holds the break error interrupt clear. */
__IOM uint32_t OEIC : 1; /*!< [10..10] This bit holds the overflow interrupt clear. */
} IEC_b;
} ;
} UART0_Type; /*!< Size = 72 (0x48) */
/* =========================================================================================================================== */
/* ================ VCOMP ================ */
/* =========================================================================================================================== */
/**
* @brief Voltage Comparator (VCOMP)
*/
typedef struct { /*!< (@ 0x4000C000) VCOMP Structure */
union {
__IOM uint32_t CFG; /*!< (@ 0x00000000) The Voltage Comparator Configuration Register
contains the software control for selecting
beween the 4 options for the positive input
as well as the multiple options for the
reference input. */
struct {
__IOM uint32_t PSEL : 2; /*!< [1..0] This bitfield selects the positive input to the comparator. */
__IM uint32_t : 6;
__IOM uint32_t NSEL : 2; /*!< [9..8] This bitfield selects the negative input to the comparator. */
__IM uint32_t : 6;
__IOM uint32_t LVLSEL : 4; /*!< [19..16] When the reference input NSEL is set to NSEL_DAC, this
bitfield selects the voltage level for the negative input
to the comparator. */
} CFG_b;
} ;
union {
__IOM uint32_t STAT; /*!< (@ 0x00000004) Status Register */
struct {
__IOM uint32_t CMPOUT : 1; /*!< [0..0] This bit is 1 if the positive input of the comparator
is greater than the negative input. */
__IOM uint32_t PWDSTAT : 1; /*!< [1..1] This bit indicates the power down state of the voltage
comparator. */
} STAT_b;
} ;
union {
__IOM uint32_t PWDKEY; /*!< (@ 0x00000008) Write a value of 0x37 to unlock, write any other
value to lock. This register also indicates
lock status when read. When in the unlccked
state (i.e. 0x37 has been written), it reads
as 1. When in the locked state, it reads
as 0. */
struct {
__IOM uint32_t PWDKEY : 32; /*!< [31..0] Key register value. */
} PWDKEY_b;
} ;
__IM uint32_t RESERVED[125];
union {
__IOM uint32_t INTEN; /*!< (@ 0x00000200) Set bits in this register to allow this module
to generate the corresponding interrupt. */
struct {
__IOM uint32_t OUTLOW : 1; /*!< [0..0] This bit is the vcompout low interrupt. */
__IOM uint32_t OUTHI : 1; /*!< [1..1] This bit is the vcompout high interrupt. */
} INTEN_b;
} ;
union {
__IOM uint32_t INTSTAT; /*!< (@ 0x00000204) Read bits from this register to discover the
cause of a recent interrupt. */
struct {
__IOM uint32_t OUTLOW : 1; /*!< [0..0] This bit is the vcompout low interrupt. */
__IOM uint32_t OUTHI : 1; /*!< [1..1] This bit is the vcompout high interrupt. */
} INTSTAT_b;
} ;
union {
__IOM uint32_t INTCLR; /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
the interrupt status associated with that
bit. */
struct {
__IOM uint32_t OUTLOW : 1; /*!< [0..0] This bit is the vcompout low interrupt. */
__IOM uint32_t OUTHI : 1; /*!< [1..1] This bit is the vcompout high interrupt. */
} INTCLR_b;
} ;
union {
__IOM uint32_t INTSET; /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
generate an interrupt from this module.
(Generally used for testing purposes). */
struct {
__IOM uint32_t OUTLOW : 1; /*!< [0..0] This bit is the vcompout low interrupt. */
__IOM uint32_t OUTHI : 1; /*!< [1..1] This bit is the vcompout high interrupt. */
} INTSET_b;
} ;
} VCOMP_Type; /*!< Size = 528 (0x210) */
/* =========================================================================================================================== */
/* ================ WDT ================ */
/* =========================================================================================================================== */
/**
* @brief Watchdog Timer (WDT)
*/
typedef struct { /*!< (@ 0x40024000) WDT Structure */
union {
__IOM uint32_t CFG; /*!< (@ 0x00000000) This is the configuration register for the watch
dog timer. It controls the enable, interrupt
set, clocks for the timer, the compare values
for the counters to trigger a reset or interrupt.
This register can only be written to if
the watch dog timer is unlocked (WDTLOCK
is not set). */
struct {
__IOM uint32_t WDTEN : 1; /*!< [0..0] This bitfield enables the WDT. */
__IOM uint32_t INTEN : 1; /*!< [1..1] This bitfield enables the WDT interrupt. Note : This
bit must be set before the interrupt status bit will reflect
a watchdog timer expiration. The IER interrupt register
must also be enabled for a WDT interrupt to be sent to
the NVIC. */
__IOM uint32_t RESEN : 1; /*!< [2..2] This bitfield enables the WDT reset. This needs to be
set together with the WDREN bit in REG_RSTGEN_CFG register
(in reset gen) to trigger the reset. */
__IM uint32_t : 5;
__IOM uint32_t RESVAL : 8; /*!< [15..8] This bitfield is the compare value for counter bits
7:0 to generate a watchdog reset. This will cause a software
reset. */
__IOM uint32_t INTVAL : 8; /*!< [23..16] This bitfield is the compare value for counter bits
7:0 to generate a watchdog interrupt. */
__IOM uint32_t CLKSEL : 3; /*!< [26..24] Select the frequency for the WDT. All values not enumerated
below are undefined. */
} CFG_b;
} ;
union {
__IOM uint32_t RSTRT; /*!< (@ 0x00000004) This register will Restart the watchdog timer.
Writing a special key value into this register
will result in the watch dog timer being
reset, so that the count will start again.
It is expected that the software will periodically
write to this register to indicate that
the system is functional. The watch dog
timer can continue running when the system
is in deep sleep, and the interrupt will
trigger the wake. After the wake, the core
can reset the watch dog timer. */
struct {
__IOM uint32_t RSTRT : 8; /*!< [7..0] Writing 0xB2 to WDTRSTRT restarts the watchdog timer.
This is a write only register. Reading this register will
only provide all 0. */
} RSTRT_b;
} ;
union {
__IOM uint32_t LOCK; /*!< (@ 0x00000008) This register locks the watch dog timer. Once
it is locked, the configuration register
(WDTCFG) for watch dog timer cannot be written
to. */
struct {
__IOM uint32_t LOCK : 8; /*!< [7..0] Writing 0x3A locks the watchdog timer. Once locked, the
WDTCFG reg cannot be written and WDTEN is set. */
} LOCK_b;
} ;
union {
__IOM uint32_t COUNT; /*!< (@ 0x0000000C) This register holds the current count for the
watch dog timer. This is a read only register.
SW cannot set the value in the counter,
but can reset it. */
struct {
__IOM uint32_t COUNT : 8; /*!< [7..0] Read-Only current value of the WDT counter */
} COUNT_b;
} ;
__IM uint32_t RESERVED[124];
union {
__IOM uint32_t INTEN; /*!< (@ 0x00000200) Set bits in this register to allow this module
to generate the corresponding interrupt. */
struct {
__IOM uint32_t WDTINT : 1; /*!< [0..0] Watchdog Timer Interrupt. */
} INTEN_b;
} ;
union {
__IOM uint32_t INTSTAT; /*!< (@ 0x00000204) Read bits from this register to discover the
cause of a recent interrupt. */
struct {
__IOM uint32_t WDTINT : 1; /*!< [0..0] Watchdog Timer Interrupt. */
} INTSTAT_b;
} ;
union {
__IOM uint32_t INTCLR; /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
the interrupt status associated with that
bit. */
struct {
__IOM uint32_t WDTINT : 1; /*!< [0..0] Watchdog Timer Interrupt. */
} INTCLR_b;
} ;
union {
__IOM uint32_t INTSET; /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
generate an interrupt from this module.
(Generally used for testing purposes). */
struct {
__IOM uint32_t WDTINT : 1; /*!< [0..0] Watchdog Timer Interrupt. */
} INTSET_b;
} ;
} WDT_Type; /*!< Size = 528 (0x210) */
/** @} */ /* End of group Device_Peripheral_peripherals */
/* =========================================================================================================================== */
/* ================ Device Specific Peripheral Address Map ================ */
/* =========================================================================================================================== */
/** @addtogroup Device_Peripheral_peripheralAddr
* @{
*/
#define ADC_BASE 0x50010000UL
#define APBDMA_BASE 0x40011000UL
#define BLEIF_BASE 0x5000C000UL
#define CACHECTRL_BASE 0x40018000UL
#define CLKGEN_BASE 0x40004000UL
#define CTIMER_BASE 0x40008000UL
#define GPIO_BASE 0x40010000UL
#define IOM0_BASE 0x50004000UL
#define IOM1_BASE 0x50005000UL
#define IOM2_BASE 0x50006000UL
#define IOM3_BASE 0x50007000UL
#define IOM4_BASE 0x50008000UL
#define IOM5_BASE 0x50009000UL
#define IOSLAVE_BASE 0x50000000UL
#define MCUCTRL_BASE 0x40020000UL
#define MSPI_BASE 0x50014000UL
#define PDM_BASE 0x50011000UL
#define PWRCTRL_BASE 0x40021000UL
#define RSTGEN_BASE 0x40000000UL
#define RTC_BASE 0x40004200UL
#define SCARD_BASE 0x40080000UL
#define SECURITY_BASE 0x40030000UL
#define UART0_BASE 0x4001C000UL
#define UART1_BASE 0x4001D000UL
#define VCOMP_BASE 0x4000C000UL
#define WDT_BASE 0x40024000UL
/** @} */ /* End of group Device_Peripheral_peripheralAddr */
/* =========================================================================================================================== */
/* ================ Peripheral declaration ================ */
/* =========================================================================================================================== */
/** @addtogroup Device_Peripheral_declaration
* @{
*/
#define ADC ((ADC_Type*) ADC_BASE)
#define APBDMA ((APBDMA_Type*) APBDMA_BASE)
#define BLEIF ((BLEIF_Type*) BLEIF_BASE)
#define CACHECTRL ((CACHECTRL_Type*) CACHECTRL_BASE)
#define CLKGEN ((CLKGEN_Type*) CLKGEN_BASE)
#define CTIMER ((CTIMER_Type*) CTIMER_BASE)
#define GPIO ((GPIO_Type*) GPIO_BASE)
#define IOM0 ((IOM0_Type*) IOM0_BASE)
#define IOM1 ((IOM0_Type*) IOM1_BASE)
#define IOM2 ((IOM0_Type*) IOM2_BASE)
#define IOM3 ((IOM0_Type*) IOM3_BASE)
#define IOM4 ((IOM0_Type*) IOM4_BASE)
#define IOM5 ((IOM0_Type*) IOM5_BASE)
#define IOSLAVE ((IOSLAVE_Type*) IOSLAVE_BASE)
#define MCUCTRL ((MCUCTRL_Type*) MCUCTRL_BASE)
#define MSPI ((MSPI_Type*) MSPI_BASE)
#define PDM ((PDM_Type*) PDM_BASE)
#define PWRCTRL ((PWRCTRL_Type*) PWRCTRL_BASE)
#define RSTGEN ((RSTGEN_Type*) RSTGEN_BASE)
#define RTC ((RTC_Type*) RTC_BASE)
#define SCARD ((SCARD_Type*) SCARD_BASE)
#define SECURITY ((SECURITY_Type*) SECURITY_BASE)
#define UART0 ((UART0_Type*) UART0_BASE)
#define UART1 ((UART0_Type*) UART1_BASE)
#define VCOMP ((VCOMP_Type*) VCOMP_BASE)
#define WDT ((WDT_Type*) WDT_BASE)
/** @} */ /* End of group Device_Peripheral_declaration */
/* ========================================= End of section using anonymous unions ========================================= */
#if defined (__CC_ARM)
#pragma pop
#elif defined (__ICCARM__)
/* leave anonymous unions enabled */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning restore
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#endif
/* =========================================================================================================================== */
/* ================ Pos/Mask Peripheral Section ================ */
/* =========================================================================================================================== */
/** @addtogroup PosMask_peripherals
* @{
*/
/* =========================================================================================================================== */
/* ================ ADC ================ */
/* =========================================================================================================================== */
/* ========================================================== CFG ========================================================== */
#define ADC_CFG_CLKSEL_Pos (24UL) /*!< CLKSEL (Bit 24) */
#define ADC_CFG_CLKSEL_Msk (0x3000000UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */
#define ADC_CFG_TRIGPOL_Pos (19UL) /*!< TRIGPOL (Bit 19) */
#define ADC_CFG_TRIGPOL_Msk (0x80000UL) /*!< TRIGPOL (Bitfield-Mask: 0x01) */
#define ADC_CFG_TRIGSEL_Pos (16UL) /*!< TRIGSEL (Bit 16) */
#define ADC_CFG_TRIGSEL_Msk (0x70000UL) /*!< TRIGSEL (Bitfield-Mask: 0x07) */
#define ADC_CFG_DFIFORDEN_Pos (12UL) /*!< DFIFORDEN (Bit 12) */
#define ADC_CFG_DFIFORDEN_Msk (0x1000UL) /*!< DFIFORDEN (Bitfield-Mask: 0x01) */
#define ADC_CFG_REFSEL_Pos (8UL) /*!< REFSEL (Bit 8) */
#define ADC_CFG_REFSEL_Msk (0x300UL) /*!< REFSEL (Bitfield-Mask: 0x03) */
#define ADC_CFG_CKMODE_Pos (4UL) /*!< CKMODE (Bit 4) */
#define ADC_CFG_CKMODE_Msk (0x10UL) /*!< CKMODE (Bitfield-Mask: 0x01) */
#define ADC_CFG_LPMODE_Pos (3UL) /*!< LPMODE (Bit 3) */
#define ADC_CFG_LPMODE_Msk (0x8UL) /*!< LPMODE (Bitfield-Mask: 0x01) */
#define ADC_CFG_RPTEN_Pos (2UL) /*!< RPTEN (Bit 2) */
#define ADC_CFG_RPTEN_Msk (0x4UL) /*!< RPTEN (Bitfield-Mask: 0x01) */
#define ADC_CFG_ADCEN_Pos (0UL) /*!< ADCEN (Bit 0) */
#define ADC_CFG_ADCEN_Msk (0x1UL) /*!< ADCEN (Bitfield-Mask: 0x01) */
/* ========================================================= STAT ========================================================== */
#define ADC_STAT_PWDSTAT_Pos (0UL) /*!< PWDSTAT (Bit 0) */
#define ADC_STAT_PWDSTAT_Msk (0x1UL) /*!< PWDSTAT (Bitfield-Mask: 0x01) */
/* ========================================================== SWT ========================================================== */
#define ADC_SWT_SWT_Pos (0UL) /*!< SWT (Bit 0) */
#define ADC_SWT_SWT_Msk (0xffUL) /*!< SWT (Bitfield-Mask: 0xff) */
/* ======================================================== SL0CFG ========================================================= */
#define ADC_SL0CFG_ADSEL0_Pos (24UL) /*!< ADSEL0 (Bit 24) */
#define ADC_SL0CFG_ADSEL0_Msk (0x7000000UL) /*!< ADSEL0 (Bitfield-Mask: 0x07) */
#define ADC_SL0CFG_PRMODE0_Pos (16UL) /*!< PRMODE0 (Bit 16) */
#define ADC_SL0CFG_PRMODE0_Msk (0x30000UL) /*!< PRMODE0 (Bitfield-Mask: 0x03) */
#define ADC_SL0CFG_CHSEL0_Pos (8UL) /*!< CHSEL0 (Bit 8) */
#define ADC_SL0CFG_CHSEL0_Msk (0xf00UL) /*!< CHSEL0 (Bitfield-Mask: 0x0f) */
#define ADC_SL0CFG_WCEN0_Pos (1UL) /*!< WCEN0 (Bit 1) */
#define ADC_SL0CFG_WCEN0_Msk (0x2UL) /*!< WCEN0 (Bitfield-Mask: 0x01) */
#define ADC_SL0CFG_SLEN0_Pos (0UL) /*!< SLEN0 (Bit 0) */
#define ADC_SL0CFG_SLEN0_Msk (0x1UL) /*!< SLEN0 (Bitfield-Mask: 0x01) */
/* ======================================================== SL1CFG ========================================================= */
#define ADC_SL1CFG_ADSEL1_Pos (24UL) /*!< ADSEL1 (Bit 24) */
#define ADC_SL1CFG_ADSEL1_Msk (0x7000000UL) /*!< ADSEL1 (Bitfield-Mask: 0x07) */
#define ADC_SL1CFG_PRMODE1_Pos (16UL) /*!< PRMODE1 (Bit 16) */
#define ADC_SL1CFG_PRMODE1_Msk (0x30000UL) /*!< PRMODE1 (Bitfield-Mask: 0x03) */
#define ADC_SL1CFG_CHSEL1_Pos (8UL) /*!< CHSEL1 (Bit 8) */
#define ADC_SL1CFG_CHSEL1_Msk (0xf00UL) /*!< CHSEL1 (Bitfield-Mask: 0x0f) */
#define ADC_SL1CFG_WCEN1_Pos (1UL) /*!< WCEN1 (Bit 1) */
#define ADC_SL1CFG_WCEN1_Msk (0x2UL) /*!< WCEN1 (Bitfield-Mask: 0x01) */
#define ADC_SL1CFG_SLEN1_Pos (0UL) /*!< SLEN1 (Bit 0) */
#define ADC_SL1CFG_SLEN1_Msk (0x1UL) /*!< SLEN1 (Bitfield-Mask: 0x01) */
/* ======================================================== SL2CFG ========================================================= */
#define ADC_SL2CFG_ADSEL2_Pos (24UL) /*!< ADSEL2 (Bit 24) */
#define ADC_SL2CFG_ADSEL2_Msk (0x7000000UL) /*!< ADSEL2 (Bitfield-Mask: 0x07) */
#define ADC_SL2CFG_PRMODE2_Pos (16UL) /*!< PRMODE2 (Bit 16) */
#define ADC_SL2CFG_PRMODE2_Msk (0x30000UL) /*!< PRMODE2 (Bitfield-Mask: 0x03) */
#define ADC_SL2CFG_CHSEL2_Pos (8UL) /*!< CHSEL2 (Bit 8) */
#define ADC_SL2CFG_CHSEL2_Msk (0xf00UL) /*!< CHSEL2 (Bitfield-Mask: 0x0f) */
#define ADC_SL2CFG_WCEN2_Pos (1UL) /*!< WCEN2 (Bit 1) */
#define ADC_SL2CFG_WCEN2_Msk (0x2UL) /*!< WCEN2 (Bitfield-Mask: 0x01) */
#define ADC_SL2CFG_SLEN2_Pos (0UL) /*!< SLEN2 (Bit 0) */
#define ADC_SL2CFG_SLEN2_Msk (0x1UL) /*!< SLEN2 (Bitfield-Mask: 0x01) */
/* ======================================================== SL3CFG ========================================================= */
#define ADC_SL3CFG_ADSEL3_Pos (24UL) /*!< ADSEL3 (Bit 24) */
#define ADC_SL3CFG_ADSEL3_Msk (0x7000000UL) /*!< ADSEL3 (Bitfield-Mask: 0x07) */
#define ADC_SL3CFG_PRMODE3_Pos (16UL) /*!< PRMODE3 (Bit 16) */
#define ADC_SL3CFG_PRMODE3_Msk (0x30000UL) /*!< PRMODE3 (Bitfield-Mask: 0x03) */
#define ADC_SL3CFG_CHSEL3_Pos (8UL) /*!< CHSEL3 (Bit 8) */
#define ADC_SL3CFG_CHSEL3_Msk (0xf00UL) /*!< CHSEL3 (Bitfield-Mask: 0x0f) */
#define ADC_SL3CFG_WCEN3_Pos (1UL) /*!< WCEN3 (Bit 1) */
#define ADC_SL3CFG_WCEN3_Msk (0x2UL) /*!< WCEN3 (Bitfield-Mask: 0x01) */
#define ADC_SL3CFG_SLEN3_Pos (0UL) /*!< SLEN3 (Bit 0) */
#define ADC_SL3CFG_SLEN3_Msk (0x1UL) /*!< SLEN3 (Bitfield-Mask: 0x01) */
/* ======================================================== SL4CFG ========================================================= */
#define ADC_SL4CFG_ADSEL4_Pos (24UL) /*!< ADSEL4 (Bit 24) */
#define ADC_SL4CFG_ADSEL4_Msk (0x7000000UL) /*!< ADSEL4 (Bitfield-Mask: 0x07) */
#define ADC_SL4CFG_PRMODE4_Pos (16UL) /*!< PRMODE4 (Bit 16) */
#define ADC_SL4CFG_PRMODE4_Msk (0x30000UL) /*!< PRMODE4 (Bitfield-Mask: 0x03) */
#define ADC_SL4CFG_CHSEL4_Pos (8UL) /*!< CHSEL4 (Bit 8) */
#define ADC_SL4CFG_CHSEL4_Msk (0xf00UL) /*!< CHSEL4 (Bitfield-Mask: 0x0f) */
#define ADC_SL4CFG_WCEN4_Pos (1UL) /*!< WCEN4 (Bit 1) */
#define ADC_SL4CFG_WCEN4_Msk (0x2UL) /*!< WCEN4 (Bitfield-Mask: 0x01) */
#define ADC_SL4CFG_SLEN4_Pos (0UL) /*!< SLEN4 (Bit 0) */
#define ADC_SL4CFG_SLEN4_Msk (0x1UL) /*!< SLEN4 (Bitfield-Mask: 0x01) */
/* ======================================================== SL5CFG ========================================================= */
#define ADC_SL5CFG_ADSEL5_Pos (24UL) /*!< ADSEL5 (Bit 24) */
#define ADC_SL5CFG_ADSEL5_Msk (0x7000000UL) /*!< ADSEL5 (Bitfield-Mask: 0x07) */
#define ADC_SL5CFG_PRMODE5_Pos (16UL) /*!< PRMODE5 (Bit 16) */
#define ADC_SL5CFG_PRMODE5_Msk (0x30000UL) /*!< PRMODE5 (Bitfield-Mask: 0x03) */
#define ADC_SL5CFG_CHSEL5_Pos (8UL) /*!< CHSEL5 (Bit 8) */
#define ADC_SL5CFG_CHSEL5_Msk (0xf00UL) /*!< CHSEL5 (Bitfield-Mask: 0x0f) */
#define ADC_SL5CFG_WCEN5_Pos (1UL) /*!< WCEN5 (Bit 1) */
#define ADC_SL5CFG_WCEN5_Msk (0x2UL) /*!< WCEN5 (Bitfield-Mask: 0x01) */
#define ADC_SL5CFG_SLEN5_Pos (0UL) /*!< SLEN5 (Bit 0) */
#define ADC_SL5CFG_SLEN5_Msk (0x1UL) /*!< SLEN5 (Bitfield-Mask: 0x01) */
/* ======================================================== SL6CFG ========================================================= */
#define ADC_SL6CFG_ADSEL6_Pos (24UL) /*!< ADSEL6 (Bit 24) */
#define ADC_SL6CFG_ADSEL6_Msk (0x7000000UL) /*!< ADSEL6 (Bitfield-Mask: 0x07) */
#define ADC_SL6CFG_PRMODE6_Pos (16UL) /*!< PRMODE6 (Bit 16) */
#define ADC_SL6CFG_PRMODE6_Msk (0x30000UL) /*!< PRMODE6 (Bitfield-Mask: 0x03) */
#define ADC_SL6CFG_CHSEL6_Pos (8UL) /*!< CHSEL6 (Bit 8) */
#define ADC_SL6CFG_CHSEL6_Msk (0xf00UL) /*!< CHSEL6 (Bitfield-Mask: 0x0f) */
#define ADC_SL6CFG_WCEN6_Pos (1UL) /*!< WCEN6 (Bit 1) */
#define ADC_SL6CFG_WCEN6_Msk (0x2UL) /*!< WCEN6 (Bitfield-Mask: 0x01) */
#define ADC_SL6CFG_SLEN6_Pos (0UL) /*!< SLEN6 (Bit 0) */
#define ADC_SL6CFG_SLEN6_Msk (0x1UL) /*!< SLEN6 (Bitfield-Mask: 0x01) */
/* ======================================================== SL7CFG ========================================================= */
#define ADC_SL7CFG_ADSEL7_Pos (24UL) /*!< ADSEL7 (Bit 24) */
#define ADC_SL7CFG_ADSEL7_Msk (0x7000000UL) /*!< ADSEL7 (Bitfield-Mask: 0x07) */
#define ADC_SL7CFG_PRMODE7_Pos (16UL) /*!< PRMODE7 (Bit 16) */
#define ADC_SL7CFG_PRMODE7_Msk (0x30000UL) /*!< PRMODE7 (Bitfield-Mask: 0x03) */
#define ADC_SL7CFG_CHSEL7_Pos (8UL) /*!< CHSEL7 (Bit 8) */
#define ADC_SL7CFG_CHSEL7_Msk (0xf00UL) /*!< CHSEL7 (Bitfield-Mask: 0x0f) */
#define ADC_SL7CFG_WCEN7_Pos (1UL) /*!< WCEN7 (Bit 1) */
#define ADC_SL7CFG_WCEN7_Msk (0x2UL) /*!< WCEN7 (Bitfield-Mask: 0x01) */
#define ADC_SL7CFG_SLEN7_Pos (0UL) /*!< SLEN7 (Bit 0) */
#define ADC_SL7CFG_SLEN7_Msk (0x1UL) /*!< SLEN7 (Bitfield-Mask: 0x01) */
/* ========================================================= WULIM ========================================================= */
#define ADC_WULIM_ULIM_Pos (0UL) /*!< ULIM (Bit 0) */
#define ADC_WULIM_ULIM_Msk (0xfffffUL) /*!< ULIM (Bitfield-Mask: 0xfffff) */
/* ========================================================= WLLIM ========================================================= */
#define ADC_WLLIM_LLIM_Pos (0UL) /*!< LLIM (Bit 0) */
#define ADC_WLLIM_LLIM_Msk (0xfffffUL) /*!< LLIM (Bitfield-Mask: 0xfffff) */
/* ======================================================== SCWLIM ========================================================= */
#define ADC_SCWLIM_SCWLIMEN_Pos (0UL) /*!< SCWLIMEN (Bit 0) */
#define ADC_SCWLIM_SCWLIMEN_Msk (0x1UL) /*!< SCWLIMEN (Bitfield-Mask: 0x01) */
/* ========================================================= FIFO ========================================================== */
#define ADC_FIFO_RSVD_Pos (31UL) /*!< RSVD (Bit 31) */
#define ADC_FIFO_RSVD_Msk (0x80000000UL) /*!< RSVD (Bitfield-Mask: 0x01) */
#define ADC_FIFO_SLOTNUM_Pos (28UL) /*!< SLOTNUM (Bit 28) */
#define ADC_FIFO_SLOTNUM_Msk (0x70000000UL) /*!< SLOTNUM (Bitfield-Mask: 0x07) */
#define ADC_FIFO_COUNT_Pos (20UL) /*!< COUNT (Bit 20) */
#define ADC_FIFO_COUNT_Msk (0xff00000UL) /*!< COUNT (Bitfield-Mask: 0xff) */
#define ADC_FIFO_DATA_Pos (0UL) /*!< DATA (Bit 0) */
#define ADC_FIFO_DATA_Msk (0xfffffUL) /*!< DATA (Bitfield-Mask: 0xfffff) */
/* ======================================================== FIFOPR ========================================================= */
#define ADC_FIFOPR_RSVDPR_Pos (31UL) /*!< RSVDPR (Bit 31) */
#define ADC_FIFOPR_RSVDPR_Msk (0x80000000UL) /*!< RSVDPR (Bitfield-Mask: 0x01) */
#define ADC_FIFOPR_SLOTNUMPR_Pos (28UL) /*!< SLOTNUMPR (Bit 28) */
#define ADC_FIFOPR_SLOTNUMPR_Msk (0x70000000UL) /*!< SLOTNUMPR (Bitfield-Mask: 0x07) */
#define ADC_FIFOPR_COUNT_Pos (20UL) /*!< COUNT (Bit 20) */
#define ADC_FIFOPR_COUNT_Msk (0xff00000UL) /*!< COUNT (Bitfield-Mask: 0xff) */
#define ADC_FIFOPR_DATA_Pos (0UL) /*!< DATA (Bit 0) */
#define ADC_FIFOPR_DATA_Msk (0xfffffUL) /*!< DATA (Bitfield-Mask: 0xfffff) */
/* ========================================================= INTEN ========================================================= */
#define ADC_INTEN_DERR_Pos (7UL) /*!< DERR (Bit 7) */
#define ADC_INTEN_DERR_Msk (0x80UL) /*!< DERR (Bitfield-Mask: 0x01) */
#define ADC_INTEN_DCMP_Pos (6UL) /*!< DCMP (Bit 6) */
#define ADC_INTEN_DCMP_Msk (0x40UL) /*!< DCMP (Bitfield-Mask: 0x01) */
#define ADC_INTEN_WCINC_Pos (5UL) /*!< WCINC (Bit 5) */
#define ADC_INTEN_WCINC_Msk (0x20UL) /*!< WCINC (Bitfield-Mask: 0x01) */
#define ADC_INTEN_WCEXC_Pos (4UL) /*!< WCEXC (Bit 4) */
#define ADC_INTEN_WCEXC_Msk (0x10UL) /*!< WCEXC (Bitfield-Mask: 0x01) */
#define ADC_INTEN_FIFOOVR2_Pos (3UL) /*!< FIFOOVR2 (Bit 3) */
#define ADC_INTEN_FIFOOVR2_Msk (0x8UL) /*!< FIFOOVR2 (Bitfield-Mask: 0x01) */
#define ADC_INTEN_FIFOOVR1_Pos (2UL) /*!< FIFOOVR1 (Bit 2) */
#define ADC_INTEN_FIFOOVR1_Msk (0x4UL) /*!< FIFOOVR1 (Bitfield-Mask: 0x01) */
#define ADC_INTEN_SCNCMP_Pos (1UL) /*!< SCNCMP (Bit 1) */
#define ADC_INTEN_SCNCMP_Msk (0x2UL) /*!< SCNCMP (Bitfield-Mask: 0x01) */
#define ADC_INTEN_CNVCMP_Pos (0UL) /*!< CNVCMP (Bit 0) */
#define ADC_INTEN_CNVCMP_Msk (0x1UL) /*!< CNVCMP (Bitfield-Mask: 0x01) */
/* ======================================================== INTSTAT ======================================================== */
#define ADC_INTSTAT_DERR_Pos (7UL) /*!< DERR (Bit 7) */
#define ADC_INTSTAT_DERR_Msk (0x80UL) /*!< DERR (Bitfield-Mask: 0x01) */
#define ADC_INTSTAT_DCMP_Pos (6UL) /*!< DCMP (Bit 6) */
#define ADC_INTSTAT_DCMP_Msk (0x40UL) /*!< DCMP (Bitfield-Mask: 0x01) */
#define ADC_INTSTAT_WCINC_Pos (5UL) /*!< WCINC (Bit 5) */
#define ADC_INTSTAT_WCINC_Msk (0x20UL) /*!< WCINC (Bitfield-Mask: 0x01) */
#define ADC_INTSTAT_WCEXC_Pos (4UL) /*!< WCEXC (Bit 4) */
#define ADC_INTSTAT_WCEXC_Msk (0x10UL) /*!< WCEXC (Bitfield-Mask: 0x01) */
#define ADC_INTSTAT_FIFOOVR2_Pos (3UL) /*!< FIFOOVR2 (Bit 3) */
#define ADC_INTSTAT_FIFOOVR2_Msk (0x8UL) /*!< FIFOOVR2 (Bitfield-Mask: 0x01) */
#define ADC_INTSTAT_FIFOOVR1_Pos (2UL) /*!< FIFOOVR1 (Bit 2) */
#define ADC_INTSTAT_FIFOOVR1_Msk (0x4UL) /*!< FIFOOVR1 (Bitfield-Mask: 0x01) */
#define ADC_INTSTAT_SCNCMP_Pos (1UL) /*!< SCNCMP (Bit 1) */
#define ADC_INTSTAT_SCNCMP_Msk (0x2UL) /*!< SCNCMP (Bitfield-Mask: 0x01) */
#define ADC_INTSTAT_CNVCMP_Pos (0UL) /*!< CNVCMP (Bit 0) */
#define ADC_INTSTAT_CNVCMP_Msk (0x1UL) /*!< CNVCMP (Bitfield-Mask: 0x01) */
/* ======================================================== INTCLR ========================================================= */
#define ADC_INTCLR_DERR_Pos (7UL) /*!< DERR (Bit 7) */
#define ADC_INTCLR_DERR_Msk (0x80UL) /*!< DERR (Bitfield-Mask: 0x01) */
#define ADC_INTCLR_DCMP_Pos (6UL) /*!< DCMP (Bit 6) */
#define ADC_INTCLR_DCMP_Msk (0x40UL) /*!< DCMP (Bitfield-Mask: 0x01) */
#define ADC_INTCLR_WCINC_Pos (5UL) /*!< WCINC (Bit 5) */
#define ADC_INTCLR_WCINC_Msk (0x20UL) /*!< WCINC (Bitfield-Mask: 0x01) */
#define ADC_INTCLR_WCEXC_Pos (4UL) /*!< WCEXC (Bit 4) */
#define ADC_INTCLR_WCEXC_Msk (0x10UL) /*!< WCEXC (Bitfield-Mask: 0x01) */
#define ADC_INTCLR_FIFOOVR2_Pos (3UL) /*!< FIFOOVR2 (Bit 3) */
#define ADC_INTCLR_FIFOOVR2_Msk (0x8UL) /*!< FIFOOVR2 (Bitfield-Mask: 0x01) */
#define ADC_INTCLR_FIFOOVR1_Pos (2UL) /*!< FIFOOVR1 (Bit 2) */
#define ADC_INTCLR_FIFOOVR1_Msk (0x4UL) /*!< FIFOOVR1 (Bitfield-Mask: 0x01) */
#define ADC_INTCLR_SCNCMP_Pos (1UL) /*!< SCNCMP (Bit 1) */
#define ADC_INTCLR_SCNCMP_Msk (0x2UL) /*!< SCNCMP (Bitfield-Mask: 0x01) */
#define ADC_INTCLR_CNVCMP_Pos (0UL) /*!< CNVCMP (Bit 0) */
#define ADC_INTCLR_CNVCMP_Msk (0x1UL) /*!< CNVCMP (Bitfield-Mask: 0x01) */
/* ======================================================== INTSET ========================================================= */
#define ADC_INTSET_DERR_Pos (7UL) /*!< DERR (Bit 7) */
#define ADC_INTSET_DERR_Msk (0x80UL) /*!< DERR (Bitfield-Mask: 0x01) */
#define ADC_INTSET_DCMP_Pos (6UL) /*!< DCMP (Bit 6) */
#define ADC_INTSET_DCMP_Msk (0x40UL) /*!< DCMP (Bitfield-Mask: 0x01) */
#define ADC_INTSET_WCINC_Pos (5UL) /*!< WCINC (Bit 5) */
#define ADC_INTSET_WCINC_Msk (0x20UL) /*!< WCINC (Bitfield-Mask: 0x01) */
#define ADC_INTSET_WCEXC_Pos (4UL) /*!< WCEXC (Bit 4) */
#define ADC_INTSET_WCEXC_Msk (0x10UL) /*!< WCEXC (Bitfield-Mask: 0x01) */
#define ADC_INTSET_FIFOOVR2_Pos (3UL) /*!< FIFOOVR2 (Bit 3) */
#define ADC_INTSET_FIFOOVR2_Msk (0x8UL) /*!< FIFOOVR2 (Bitfield-Mask: 0x01) */
#define ADC_INTSET_FIFOOVR1_Pos (2UL) /*!< FIFOOVR1 (Bit 2) */
#define ADC_INTSET_FIFOOVR1_Msk (0x4UL) /*!< FIFOOVR1 (Bitfield-Mask: 0x01) */
#define ADC_INTSET_SCNCMP_Pos (1UL) /*!< SCNCMP (Bit 1) */
#define ADC_INTSET_SCNCMP_Msk (0x2UL) /*!< SCNCMP (Bitfield-Mask: 0x01) */
#define ADC_INTSET_CNVCMP_Pos (0UL) /*!< CNVCMP (Bit 0) */
#define ADC_INTSET_CNVCMP_Msk (0x1UL) /*!< CNVCMP (Bitfield-Mask: 0x01) */
/* ======================================================= DMATRIGEN ======================================================= */
#define ADC_DMATRIGEN_DFIFOFULL_Pos (1UL) /*!< DFIFOFULL (Bit 1) */
#define ADC_DMATRIGEN_DFIFOFULL_Msk (0x2UL) /*!< DFIFOFULL (Bitfield-Mask: 0x01) */
#define ADC_DMATRIGEN_DFIFO75_Pos (0UL) /*!< DFIFO75 (Bit 0) */
#define ADC_DMATRIGEN_DFIFO75_Msk (0x1UL) /*!< DFIFO75 (Bitfield-Mask: 0x01) */
/* ====================================================== DMATRIGSTAT ====================================================== */
#define ADC_DMATRIGSTAT_DFULLSTAT_Pos (1UL) /*!< DFULLSTAT (Bit 1) */
#define ADC_DMATRIGSTAT_DFULLSTAT_Msk (0x2UL) /*!< DFULLSTAT (Bitfield-Mask: 0x01) */
#define ADC_DMATRIGSTAT_D75STAT_Pos (0UL) /*!< D75STAT (Bit 0) */
#define ADC_DMATRIGSTAT_D75STAT_Msk (0x1UL) /*!< D75STAT (Bitfield-Mask: 0x01) */
/* ======================================================== DMACFG ========================================================= */
#define ADC_DMACFG_DPWROFF_Pos (18UL) /*!< DPWROFF (Bit 18) */
#define ADC_DMACFG_DPWROFF_Msk (0x40000UL) /*!< DPWROFF (Bitfield-Mask: 0x01) */
#define ADC_DMACFG_DMAMSK_Pos (17UL) /*!< DMAMSK (Bit 17) */
#define ADC_DMACFG_DMAMSK_Msk (0x20000UL) /*!< DMAMSK (Bitfield-Mask: 0x01) */
#define ADC_DMACFG_DMAHONSTAT_Pos (16UL) /*!< DMAHONSTAT (Bit 16) */
#define ADC_DMACFG_DMAHONSTAT_Msk (0x10000UL) /*!< DMAHONSTAT (Bitfield-Mask: 0x01) */
#define ADC_DMACFG_DMADYNPRI_Pos (9UL) /*!< DMADYNPRI (Bit 9) */
#define ADC_DMACFG_DMADYNPRI_Msk (0x200UL) /*!< DMADYNPRI (Bitfield-Mask: 0x01) */
#define ADC_DMACFG_DMAPRI_Pos (8UL) /*!< DMAPRI (Bit 8) */
#define ADC_DMACFG_DMAPRI_Msk (0x100UL) /*!< DMAPRI (Bitfield-Mask: 0x01) */
#define ADC_DMACFG_DMADIR_Pos (2UL) /*!< DMADIR (Bit 2) */
#define ADC_DMACFG_DMADIR_Msk (0x4UL) /*!< DMADIR (Bitfield-Mask: 0x01) */
#define ADC_DMACFG_DMAEN_Pos (0UL) /*!< DMAEN (Bit 0) */
#define ADC_DMACFG_DMAEN_Msk (0x1UL) /*!< DMAEN (Bitfield-Mask: 0x01) */
/* ====================================================== DMATOTCOUNT ====================================================== */
#define ADC_DMATOTCOUNT_TOTCOUNT_Pos (2UL) /*!< TOTCOUNT (Bit 2) */
#define ADC_DMATOTCOUNT_TOTCOUNT_Msk (0x3fffcUL) /*!< TOTCOUNT (Bitfield-Mask: 0xffff) */
/* ====================================================== DMATARGADDR ====================================================== */
#define ADC_DMATARGADDR_UTARGADDR_Pos (19UL) /*!< UTARGADDR (Bit 19) */
#define ADC_DMATARGADDR_UTARGADDR_Msk (0xfff80000UL) /*!< UTARGADDR (Bitfield-Mask: 0x1fff) */
#define ADC_DMATARGADDR_LTARGADDR_Pos (0UL) /*!< LTARGADDR (Bit 0) */
#define ADC_DMATARGADDR_LTARGADDR_Msk (0x7ffffUL) /*!< LTARGADDR (Bitfield-Mask: 0x7ffff) */
/* ======================================================== DMASTAT ======================================================== */
#define ADC_DMASTAT_DMAERR_Pos (2UL) /*!< DMAERR (Bit 2) */
#define ADC_DMASTAT_DMAERR_Msk (0x4UL) /*!< DMAERR (Bitfield-Mask: 0x01) */
#define ADC_DMASTAT_DMACPL_Pos (1UL) /*!< DMACPL (Bit 1) */
#define ADC_DMASTAT_DMACPL_Msk (0x2UL) /*!< DMACPL (Bitfield-Mask: 0x01) */
#define ADC_DMASTAT_DMATIP_Pos (0UL) /*!< DMATIP (Bit 0) */
#define ADC_DMASTAT_DMATIP_Msk (0x1UL) /*!< DMATIP (Bitfield-Mask: 0x01) */
/* =========================================================================================================================== */
/* ================ APBDMA ================ */
/* =========================================================================================================================== */
/* ======================================================== BBVALUE ======================================================== */
#define APBDMA_BBVALUE_PIN_Pos (16UL) /*!< PIN (Bit 16) */
#define APBDMA_BBVALUE_PIN_Msk (0xff0000UL) /*!< PIN (Bitfield-Mask: 0xff) */
#define APBDMA_BBVALUE_DATAOUT_Pos (0UL) /*!< DATAOUT (Bit 0) */
#define APBDMA_BBVALUE_DATAOUT_Msk (0xffUL) /*!< DATAOUT (Bitfield-Mask: 0xff) */
/* ====================================================== BBSETCLEAR ======================================================= */
#define APBDMA_BBSETCLEAR_CLEAR_Pos (16UL) /*!< CLEAR (Bit 16) */
#define APBDMA_BBSETCLEAR_CLEAR_Msk (0xff0000UL) /*!< CLEAR (Bitfield-Mask: 0xff) */
#define APBDMA_BBSETCLEAR_SET_Pos (0UL) /*!< SET (Bit 0) */
#define APBDMA_BBSETCLEAR_SET_Msk (0xffUL) /*!< SET (Bitfield-Mask: 0xff) */
/* ======================================================== BBINPUT ======================================================== */
#define APBDMA_BBINPUT_DATAIN_Pos (0UL) /*!< DATAIN (Bit 0) */
#define APBDMA_BBINPUT_DATAIN_Msk (0xffUL) /*!< DATAIN (Bitfield-Mask: 0xff) */
/* ======================================================= DEBUGDATA ======================================================= */
#define APBDMA_DEBUGDATA_DEBUGDATA_Pos (0UL) /*!< DEBUGDATA (Bit 0) */
#define APBDMA_DEBUGDATA_DEBUGDATA_Msk (0xffffffffUL) /*!< DEBUGDATA (Bitfield-Mask: 0xffffffff) */
/* ========================================================= DEBUG ========================================================= */
#define APBDMA_DEBUG_DEBUGEN_Pos (0UL) /*!< DEBUGEN (Bit 0) */
#define APBDMA_DEBUG_DEBUGEN_Msk (0xfUL) /*!< DEBUGEN (Bitfield-Mask: 0x0f) */
/* =========================================================================================================================== */
/* ================ BLEIF ================ */
/* =========================================================================================================================== */
/* ========================================================= FIFO ========================================================== */
#define BLEIF_FIFO_FIFO_Pos (0UL) /*!< FIFO (Bit 0) */
#define BLEIF_FIFO_FIFO_Msk (0xffffffffUL) /*!< FIFO (Bitfield-Mask: 0xffffffff) */
/* ======================================================== FIFOPTR ======================================================== */
#define BLEIF_FIFOPTR_FIFO1REM_Pos (24UL) /*!< FIFO1REM (Bit 24) */
#define BLEIF_FIFOPTR_FIFO1REM_Msk (0xff000000UL) /*!< FIFO1REM (Bitfield-Mask: 0xff) */
#define BLEIF_FIFOPTR_FIFO1SIZ_Pos (16UL) /*!< FIFO1SIZ (Bit 16) */
#define BLEIF_FIFOPTR_FIFO1SIZ_Msk (0xff0000UL) /*!< FIFO1SIZ (Bitfield-Mask: 0xff) */
#define BLEIF_FIFOPTR_FIFO0REM_Pos (8UL) /*!< FIFO0REM (Bit 8) */
#define BLEIF_FIFOPTR_FIFO0REM_Msk (0xff00UL) /*!< FIFO0REM (Bitfield-Mask: 0xff) */
#define BLEIF_FIFOPTR_FIFO0SIZ_Pos (0UL) /*!< FIFO0SIZ (Bit 0) */
#define BLEIF_FIFOPTR_FIFO0SIZ_Msk (0xffUL) /*!< FIFO0SIZ (Bitfield-Mask: 0xff) */
/* ======================================================== FIFOTHR ======================================================== */
#define BLEIF_FIFOTHR_FIFOWTHR_Pos (8UL) /*!< FIFOWTHR (Bit 8) */
#define BLEIF_FIFOTHR_FIFOWTHR_Msk (0x3f00UL) /*!< FIFOWTHR (Bitfield-Mask: 0x3f) */
#define BLEIF_FIFOTHR_FIFORTHR_Pos (0UL) /*!< FIFORTHR (Bit 0) */
#define BLEIF_FIFOTHR_FIFORTHR_Msk (0x3fUL) /*!< FIFORTHR (Bitfield-Mask: 0x3f) */
/* ======================================================== FIFOPOP ======================================================== */
#define BLEIF_FIFOPOP_FIFODOUT_Pos (0UL) /*!< FIFODOUT (Bit 0) */
#define BLEIF_FIFOPOP_FIFODOUT_Msk (0xffffffffUL) /*!< FIFODOUT (Bitfield-Mask: 0xffffffff) */
/* ======================================================= FIFOPUSH ======================================================== */
#define BLEIF_FIFOPUSH_FIFODIN_Pos (0UL) /*!< FIFODIN (Bit 0) */
#define BLEIF_FIFOPUSH_FIFODIN_Msk (0xffffffffUL) /*!< FIFODIN (Bitfield-Mask: 0xffffffff) */
/* ======================================================= FIFOCTRL ======================================================== */
#define BLEIF_FIFOCTRL_FIFORSTN_Pos (1UL) /*!< FIFORSTN (Bit 1) */
#define BLEIF_FIFOCTRL_FIFORSTN_Msk (0x2UL) /*!< FIFORSTN (Bitfield-Mask: 0x01) */
#define BLEIF_FIFOCTRL_POPWR_Pos (0UL) /*!< POPWR (Bit 0) */
#define BLEIF_FIFOCTRL_POPWR_Msk (0x1UL) /*!< POPWR (Bitfield-Mask: 0x01) */
/* ======================================================== FIFOLOC ======================================================== */
#define BLEIF_FIFOLOC_FIFORPTR_Pos (8UL) /*!< FIFORPTR (Bit 8) */
#define BLEIF_FIFOLOC_FIFORPTR_Msk (0xf00UL) /*!< FIFORPTR (Bitfield-Mask: 0x0f) */
#define BLEIF_FIFOLOC_FIFOWPTR_Pos (0UL) /*!< FIFOWPTR (Bit 0) */
#define BLEIF_FIFOLOC_FIFOWPTR_Msk (0xfUL) /*!< FIFOWPTR (Bitfield-Mask: 0x0f) */
/* ======================================================== CLKCFG ========================================================= */
#define BLEIF_CLKCFG_DIV3_Pos (12UL) /*!< DIV3 (Bit 12) */
#define BLEIF_CLKCFG_DIV3_Msk (0x1000UL) /*!< DIV3 (Bitfield-Mask: 0x01) */
#define BLEIF_CLKCFG_CLK32KEN_Pos (11UL) /*!< CLK32KEN (Bit 11) */
#define BLEIF_CLKCFG_CLK32KEN_Msk (0x800UL) /*!< CLK32KEN (Bitfield-Mask: 0x01) */
#define BLEIF_CLKCFG_FSEL_Pos (8UL) /*!< FSEL (Bit 8) */
#define BLEIF_CLKCFG_FSEL_Msk (0x700UL) /*!< FSEL (Bitfield-Mask: 0x07) */
#define BLEIF_CLKCFG_IOCLKEN_Pos (0UL) /*!< IOCLKEN (Bit 0) */
#define BLEIF_CLKCFG_IOCLKEN_Msk (0x1UL) /*!< IOCLKEN (Bitfield-Mask: 0x01) */
/* ========================================================== CMD ========================================================== */
#define BLEIF_CMD_OFFSETLO_Pos (24UL) /*!< OFFSETLO (Bit 24) */
#define BLEIF_CMD_OFFSETLO_Msk (0xff000000UL) /*!< OFFSETLO (Bitfield-Mask: 0xff) */
#define BLEIF_CMD_CMDSEL_Pos (20UL) /*!< CMDSEL (Bit 20) */
#define BLEIF_CMD_CMDSEL_Msk (0x300000UL) /*!< CMDSEL (Bitfield-Mask: 0x03) */
#define BLEIF_CMD_TSIZE_Pos (8UL) /*!< TSIZE (Bit 8) */
#define BLEIF_CMD_TSIZE_Msk (0xfff00UL) /*!< TSIZE (Bitfield-Mask: 0xfff) */
#define BLEIF_CMD_CONT_Pos (7UL) /*!< CONT (Bit 7) */
#define BLEIF_CMD_CONT_Msk (0x80UL) /*!< CONT (Bitfield-Mask: 0x01) */
#define BLEIF_CMD_OFFSETCNT_Pos (5UL) /*!< OFFSETCNT (Bit 5) */
#define BLEIF_CMD_OFFSETCNT_Msk (0x60UL) /*!< OFFSETCNT (Bitfield-Mask: 0x03) */
#define BLEIF_CMD_CMD_Pos (0UL) /*!< CMD (Bit 0) */
#define BLEIF_CMD_CMD_Msk (0x1fUL) /*!< CMD (Bitfield-Mask: 0x1f) */
/* ======================================================== CMDRPT ========================================================= */
#define BLEIF_CMDRPT_CMDRPT_Pos (0UL) /*!< CMDRPT (Bit 0) */
#define BLEIF_CMDRPT_CMDRPT_Msk (0x1fUL) /*!< CMDRPT (Bitfield-Mask: 0x1f) */
/* ======================================================= OFFSETHI ======================================================== */
#define BLEIF_OFFSETHI_OFFSETHI_Pos (0UL) /*!< OFFSETHI (Bit 0) */
#define BLEIF_OFFSETHI_OFFSETHI_Msk (0xffffUL) /*!< OFFSETHI (Bitfield-Mask: 0xffff) */
/* ======================================================== CMDSTAT ======================================================== */
#define BLEIF_CMDSTAT_CTSIZE_Pos (8UL) /*!< CTSIZE (Bit 8) */
#define BLEIF_CMDSTAT_CTSIZE_Msk (0xfff00UL) /*!< CTSIZE (Bitfield-Mask: 0xfff) */
#define BLEIF_CMDSTAT_CMDSTAT_Pos (5UL) /*!< CMDSTAT (Bit 5) */
#define BLEIF_CMDSTAT_CMDSTAT_Msk (0xe0UL) /*!< CMDSTAT (Bitfield-Mask: 0x07) */
#define BLEIF_CMDSTAT_CCMD_Pos (0UL) /*!< CCMD (Bit 0) */
#define BLEIF_CMDSTAT_CCMD_Msk (0x1fUL) /*!< CCMD (Bitfield-Mask: 0x1f) */
/* ========================================================= INTEN ========================================================= */
#define BLEIF_INTEN_B2MSHUTDN_Pos (16UL) /*!< B2MSHUTDN (Bit 16) */
#define BLEIF_INTEN_B2MSHUTDN_Msk (0x10000UL) /*!< B2MSHUTDN (Bitfield-Mask: 0x01) */
#define BLEIF_INTEN_B2MACTIVE_Pos (15UL) /*!< B2MACTIVE (Bit 15) */
#define BLEIF_INTEN_B2MACTIVE_Msk (0x8000UL) /*!< B2MACTIVE (Bitfield-Mask: 0x01) */
#define BLEIF_INTEN_B2MSLEEP_Pos (14UL) /*!< B2MSLEEP (Bit 14) */
#define BLEIF_INTEN_B2MSLEEP_Msk (0x4000UL) /*!< B2MSLEEP (Bitfield-Mask: 0x01) */
#define BLEIF_INTEN_CQERR_Pos (13UL) /*!< CQERR (Bit 13) */
#define BLEIF_INTEN_CQERR_Msk (0x2000UL) /*!< CQERR (Bitfield-Mask: 0x01) */
#define BLEIF_INTEN_CQUPD_Pos (12UL) /*!< CQUPD (Bit 12) */
#define BLEIF_INTEN_CQUPD_Msk (0x1000UL) /*!< CQUPD (Bitfield-Mask: 0x01) */
#define BLEIF_INTEN_CQPAUSED_Pos (11UL) /*!< CQPAUSED (Bit 11) */
#define BLEIF_INTEN_CQPAUSED_Msk (0x800UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */
#define BLEIF_INTEN_DERR_Pos (10UL) /*!< DERR (Bit 10) */
#define BLEIF_INTEN_DERR_Msk (0x400UL) /*!< DERR (Bitfield-Mask: 0x01) */
#define BLEIF_INTEN_DCMP_Pos (9UL) /*!< DCMP (Bit 9) */
#define BLEIF_INTEN_DCMP_Msk (0x200UL) /*!< DCMP (Bitfield-Mask: 0x01) */
#define BLEIF_INTEN_BLECSSTAT_Pos (8UL) /*!< BLECSSTAT (Bit 8) */
#define BLEIF_INTEN_BLECSSTAT_Msk (0x100UL) /*!< BLECSSTAT (Bitfield-Mask: 0x01) */
#define BLEIF_INTEN_BLECIRQ_Pos (7UL) /*!< BLECIRQ (Bit 7) */
#define BLEIF_INTEN_BLECIRQ_Msk (0x80UL) /*!< BLECIRQ (Bitfield-Mask: 0x01) */
#define BLEIF_INTEN_ICMD_Pos (6UL) /*!< ICMD (Bit 6) */
#define BLEIF_INTEN_ICMD_Msk (0x40UL) /*!< ICMD (Bitfield-Mask: 0x01) */
#define BLEIF_INTEN_IACC_Pos (5UL) /*!< IACC (Bit 5) */
#define BLEIF_INTEN_IACC_Msk (0x20UL) /*!< IACC (Bitfield-Mask: 0x01) */
#define BLEIF_INTEN_B2MST_Pos (4UL) /*!< B2MST (Bit 4) */
#define BLEIF_INTEN_B2MST_Msk (0x10UL) /*!< B2MST (Bitfield-Mask: 0x01) */
#define BLEIF_INTEN_FOVFL_Pos (3UL) /*!< FOVFL (Bit 3) */
#define BLEIF_INTEN_FOVFL_Msk (0x8UL) /*!< FOVFL (Bitfield-Mask: 0x01) */
#define BLEIF_INTEN_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */
#define BLEIF_INTEN_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */
#define BLEIF_INTEN_THR_Pos (1UL) /*!< THR (Bit 1) */
#define BLEIF_INTEN_THR_Msk (0x2UL) /*!< THR (Bitfield-Mask: 0x01) */
#define BLEIF_INTEN_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */
#define BLEIF_INTEN_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */
/* ======================================================== INTSTAT ======================================================== */
#define BLEIF_INTSTAT_B2MSHUTDN_Pos (16UL) /*!< B2MSHUTDN (Bit 16) */
#define BLEIF_INTSTAT_B2MSHUTDN_Msk (0x10000UL) /*!< B2MSHUTDN (Bitfield-Mask: 0x01) */
#define BLEIF_INTSTAT_B2MACTIVE_Pos (15UL) /*!< B2MACTIVE (Bit 15) */
#define BLEIF_INTSTAT_B2MACTIVE_Msk (0x8000UL) /*!< B2MACTIVE (Bitfield-Mask: 0x01) */
#define BLEIF_INTSTAT_B2MSLEEP_Pos (14UL) /*!< B2MSLEEP (Bit 14) */
#define BLEIF_INTSTAT_B2MSLEEP_Msk (0x4000UL) /*!< B2MSLEEP (Bitfield-Mask: 0x01) */
#define BLEIF_INTSTAT_CQERR_Pos (13UL) /*!< CQERR (Bit 13) */
#define BLEIF_INTSTAT_CQERR_Msk (0x2000UL) /*!< CQERR (Bitfield-Mask: 0x01) */
#define BLEIF_INTSTAT_CQUPD_Pos (12UL) /*!< CQUPD (Bit 12) */
#define BLEIF_INTSTAT_CQUPD_Msk (0x1000UL) /*!< CQUPD (Bitfield-Mask: 0x01) */
#define BLEIF_INTSTAT_CQPAUSED_Pos (11UL) /*!< CQPAUSED (Bit 11) */
#define BLEIF_INTSTAT_CQPAUSED_Msk (0x800UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */
#define BLEIF_INTSTAT_DERR_Pos (10UL) /*!< DERR (Bit 10) */
#define BLEIF_INTSTAT_DERR_Msk (0x400UL) /*!< DERR (Bitfield-Mask: 0x01) */
#define BLEIF_INTSTAT_DCMP_Pos (9UL) /*!< DCMP (Bit 9) */
#define BLEIF_INTSTAT_DCMP_Msk (0x200UL) /*!< DCMP (Bitfield-Mask: 0x01) */
#define BLEIF_INTSTAT_BLECSSTAT_Pos (8UL) /*!< BLECSSTAT (Bit 8) */
#define BLEIF_INTSTAT_BLECSSTAT_Msk (0x100UL) /*!< BLECSSTAT (Bitfield-Mask: 0x01) */
#define BLEIF_INTSTAT_BLECIRQ_Pos (7UL) /*!< BLECIRQ (Bit 7) */
#define BLEIF_INTSTAT_BLECIRQ_Msk (0x80UL) /*!< BLECIRQ (Bitfield-Mask: 0x01) */
#define BLEIF_INTSTAT_ICMD_Pos (6UL) /*!< ICMD (Bit 6) */
#define BLEIF_INTSTAT_ICMD_Msk (0x40UL) /*!< ICMD (Bitfield-Mask: 0x01) */
#define BLEIF_INTSTAT_IACC_Pos (5UL) /*!< IACC (Bit 5) */
#define BLEIF_INTSTAT_IACC_Msk (0x20UL) /*!< IACC (Bitfield-Mask: 0x01) */
#define BLEIF_INTSTAT_B2MST_Pos (4UL) /*!< B2MST (Bit 4) */
#define BLEIF_INTSTAT_B2MST_Msk (0x10UL) /*!< B2MST (Bitfield-Mask: 0x01) */
#define BLEIF_INTSTAT_FOVFL_Pos (3UL) /*!< FOVFL (Bit 3) */
#define BLEIF_INTSTAT_FOVFL_Msk (0x8UL) /*!< FOVFL (Bitfield-Mask: 0x01) */
#define BLEIF_INTSTAT_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */
#define BLEIF_INTSTAT_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */
#define BLEIF_INTSTAT_THR_Pos (1UL) /*!< THR (Bit 1) */
#define BLEIF_INTSTAT_THR_Msk (0x2UL) /*!< THR (Bitfield-Mask: 0x01) */
#define BLEIF_INTSTAT_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */
#define BLEIF_INTSTAT_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */
/* ======================================================== INTCLR ========================================================= */
#define BLEIF_INTCLR_B2MSHUTDN_Pos (16UL) /*!< B2MSHUTDN (Bit 16) */
#define BLEIF_INTCLR_B2MSHUTDN_Msk (0x10000UL) /*!< B2MSHUTDN (Bitfield-Mask: 0x01) */
#define BLEIF_INTCLR_B2MACTIVE_Pos (15UL) /*!< B2MACTIVE (Bit 15) */
#define BLEIF_INTCLR_B2MACTIVE_Msk (0x8000UL) /*!< B2MACTIVE (Bitfield-Mask: 0x01) */
#define BLEIF_INTCLR_B2MSLEEP_Pos (14UL) /*!< B2MSLEEP (Bit 14) */
#define BLEIF_INTCLR_B2MSLEEP_Msk (0x4000UL) /*!< B2MSLEEP (Bitfield-Mask: 0x01) */
#define BLEIF_INTCLR_CQERR_Pos (13UL) /*!< CQERR (Bit 13) */
#define BLEIF_INTCLR_CQERR_Msk (0x2000UL) /*!< CQERR (Bitfield-Mask: 0x01) */
#define BLEIF_INTCLR_CQUPD_Pos (12UL) /*!< CQUPD (Bit 12) */
#define BLEIF_INTCLR_CQUPD_Msk (0x1000UL) /*!< CQUPD (Bitfield-Mask: 0x01) */
#define BLEIF_INTCLR_CQPAUSED_Pos (11UL) /*!< CQPAUSED (Bit 11) */
#define BLEIF_INTCLR_CQPAUSED_Msk (0x800UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */
#define BLEIF_INTCLR_DERR_Pos (10UL) /*!< DERR (Bit 10) */
#define BLEIF_INTCLR_DERR_Msk (0x400UL) /*!< DERR (Bitfield-Mask: 0x01) */
#define BLEIF_INTCLR_DCMP_Pos (9UL) /*!< DCMP (Bit 9) */
#define BLEIF_INTCLR_DCMP_Msk (0x200UL) /*!< DCMP (Bitfield-Mask: 0x01) */
#define BLEIF_INTCLR_BLECSSTAT_Pos (8UL) /*!< BLECSSTAT (Bit 8) */
#define BLEIF_INTCLR_BLECSSTAT_Msk (0x100UL) /*!< BLECSSTAT (Bitfield-Mask: 0x01) */
#define BLEIF_INTCLR_BLECIRQ_Pos (7UL) /*!< BLECIRQ (Bit 7) */
#define BLEIF_INTCLR_BLECIRQ_Msk (0x80UL) /*!< BLECIRQ (Bitfield-Mask: 0x01) */
#define BLEIF_INTCLR_ICMD_Pos (6UL) /*!< ICMD (Bit 6) */
#define BLEIF_INTCLR_ICMD_Msk (0x40UL) /*!< ICMD (Bitfield-Mask: 0x01) */
#define BLEIF_INTCLR_IACC_Pos (5UL) /*!< IACC (Bit 5) */
#define BLEIF_INTCLR_IACC_Msk (0x20UL) /*!< IACC (Bitfield-Mask: 0x01) */
#define BLEIF_INTCLR_B2MST_Pos (4UL) /*!< B2MST (Bit 4) */
#define BLEIF_INTCLR_B2MST_Msk (0x10UL) /*!< B2MST (Bitfield-Mask: 0x01) */
#define BLEIF_INTCLR_FOVFL_Pos (3UL) /*!< FOVFL (Bit 3) */
#define BLEIF_INTCLR_FOVFL_Msk (0x8UL) /*!< FOVFL (Bitfield-Mask: 0x01) */
#define BLEIF_INTCLR_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */
#define BLEIF_INTCLR_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */
#define BLEIF_INTCLR_THR_Pos (1UL) /*!< THR (Bit 1) */
#define BLEIF_INTCLR_THR_Msk (0x2UL) /*!< THR (Bitfield-Mask: 0x01) */
#define BLEIF_INTCLR_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */
#define BLEIF_INTCLR_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */
/* ======================================================== INTSET ========================================================= */
#define BLEIF_INTSET_B2MSHUTDN_Pos (16UL) /*!< B2MSHUTDN (Bit 16) */
#define BLEIF_INTSET_B2MSHUTDN_Msk (0x10000UL) /*!< B2MSHUTDN (Bitfield-Mask: 0x01) */
#define BLEIF_INTSET_B2MACTIVE_Pos (15UL) /*!< B2MACTIVE (Bit 15) */
#define BLEIF_INTSET_B2MACTIVE_Msk (0x8000UL) /*!< B2MACTIVE (Bitfield-Mask: 0x01) */
#define BLEIF_INTSET_B2MSLEEP_Pos (14UL) /*!< B2MSLEEP (Bit 14) */
#define BLEIF_INTSET_B2MSLEEP_Msk (0x4000UL) /*!< B2MSLEEP (Bitfield-Mask: 0x01) */
#define BLEIF_INTSET_CQERR_Pos (13UL) /*!< CQERR (Bit 13) */
#define BLEIF_INTSET_CQERR_Msk (0x2000UL) /*!< CQERR (Bitfield-Mask: 0x01) */
#define BLEIF_INTSET_CQUPD_Pos (12UL) /*!< CQUPD (Bit 12) */
#define BLEIF_INTSET_CQUPD_Msk (0x1000UL) /*!< CQUPD (Bitfield-Mask: 0x01) */
#define BLEIF_INTSET_CQPAUSED_Pos (11UL) /*!< CQPAUSED (Bit 11) */
#define BLEIF_INTSET_CQPAUSED_Msk (0x800UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */
#define BLEIF_INTSET_DERR_Pos (10UL) /*!< DERR (Bit 10) */
#define BLEIF_INTSET_DERR_Msk (0x400UL) /*!< DERR (Bitfield-Mask: 0x01) */
#define BLEIF_INTSET_DCMP_Pos (9UL) /*!< DCMP (Bit 9) */
#define BLEIF_INTSET_DCMP_Msk (0x200UL) /*!< DCMP (Bitfield-Mask: 0x01) */
#define BLEIF_INTSET_BLECSSTAT_Pos (8UL) /*!< BLECSSTAT (Bit 8) */
#define BLEIF_INTSET_BLECSSTAT_Msk (0x100UL) /*!< BLECSSTAT (Bitfield-Mask: 0x01) */
#define BLEIF_INTSET_BLECIRQ_Pos (7UL) /*!< BLECIRQ (Bit 7) */
#define BLEIF_INTSET_BLECIRQ_Msk (0x80UL) /*!< BLECIRQ (Bitfield-Mask: 0x01) */
#define BLEIF_INTSET_ICMD_Pos (6UL) /*!< ICMD (Bit 6) */
#define BLEIF_INTSET_ICMD_Msk (0x40UL) /*!< ICMD (Bitfield-Mask: 0x01) */
#define BLEIF_INTSET_IACC_Pos (5UL) /*!< IACC (Bit 5) */
#define BLEIF_INTSET_IACC_Msk (0x20UL) /*!< IACC (Bitfield-Mask: 0x01) */
#define BLEIF_INTSET_B2MST_Pos (4UL) /*!< B2MST (Bit 4) */
#define BLEIF_INTSET_B2MST_Msk (0x10UL) /*!< B2MST (Bitfield-Mask: 0x01) */
#define BLEIF_INTSET_FOVFL_Pos (3UL) /*!< FOVFL (Bit 3) */
#define BLEIF_INTSET_FOVFL_Msk (0x8UL) /*!< FOVFL (Bitfield-Mask: 0x01) */
#define BLEIF_INTSET_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */
#define BLEIF_INTSET_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */
#define BLEIF_INTSET_THR_Pos (1UL) /*!< THR (Bit 1) */
#define BLEIF_INTSET_THR_Msk (0x2UL) /*!< THR (Bitfield-Mask: 0x01) */
#define BLEIF_INTSET_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */
#define BLEIF_INTSET_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */
/* ======================================================= DMATRIGEN ======================================================= */
#define BLEIF_DMATRIGEN_DTHREN_Pos (1UL) /*!< DTHREN (Bit 1) */
#define BLEIF_DMATRIGEN_DTHREN_Msk (0x2UL) /*!< DTHREN (Bitfield-Mask: 0x01) */
#define BLEIF_DMATRIGEN_DCMDCMPEN_Pos (0UL) /*!< DCMDCMPEN (Bit 0) */
#define BLEIF_DMATRIGEN_DCMDCMPEN_Msk (0x1UL) /*!< DCMDCMPEN (Bitfield-Mask: 0x01) */
/* ====================================================== DMATRIGSTAT ====================================================== */
#define BLEIF_DMATRIGSTAT_DTOTCMP_Pos (2UL) /*!< DTOTCMP (Bit 2) */
#define BLEIF_DMATRIGSTAT_DTOTCMP_Msk (0x4UL) /*!< DTOTCMP (Bitfield-Mask: 0x01) */
#define BLEIF_DMATRIGSTAT_DTHR_Pos (1UL) /*!< DTHR (Bit 1) */
#define BLEIF_DMATRIGSTAT_DTHR_Msk (0x2UL) /*!< DTHR (Bitfield-Mask: 0x01) */
#define BLEIF_DMATRIGSTAT_DCMDCMP_Pos (0UL) /*!< DCMDCMP (Bit 0) */
#define BLEIF_DMATRIGSTAT_DCMDCMP_Msk (0x1UL) /*!< DCMDCMP (Bitfield-Mask: 0x01) */
/* ======================================================== DMACFG ========================================================= */
#define BLEIF_DMACFG_DPWROFF_Pos (9UL) /*!< DPWROFF (Bit 9) */
#define BLEIF_DMACFG_DPWROFF_Msk (0x200UL) /*!< DPWROFF (Bitfield-Mask: 0x01) */
#define BLEIF_DMACFG_DMAPRI_Pos (8UL) /*!< DMAPRI (Bit 8) */
#define BLEIF_DMACFG_DMAPRI_Msk (0x100UL) /*!< DMAPRI (Bitfield-Mask: 0x01) */
#define BLEIF_DMACFG_DMADIR_Pos (1UL) /*!< DMADIR (Bit 1) */
#define BLEIF_DMACFG_DMADIR_Msk (0x2UL) /*!< DMADIR (Bitfield-Mask: 0x01) */
#define BLEIF_DMACFG_DMAEN_Pos (0UL) /*!< DMAEN (Bit 0) */
#define BLEIF_DMACFG_DMAEN_Msk (0x1UL) /*!< DMAEN (Bitfield-Mask: 0x01) */
/* ====================================================== DMATOTCOUNT ====================================================== */
#define BLEIF_DMATOTCOUNT_TOTCOUNT_Pos (0UL) /*!< TOTCOUNT (Bit 0) */
#define BLEIF_DMATOTCOUNT_TOTCOUNT_Msk (0xfffUL) /*!< TOTCOUNT (Bitfield-Mask: 0xfff) */
/* ====================================================== DMATARGADDR ====================================================== */
#define BLEIF_DMATARGADDR_TARGADDR28_Pos (28UL) /*!< TARGADDR28 (Bit 28) */
#define BLEIF_DMATARGADDR_TARGADDR28_Msk (0x10000000UL) /*!< TARGADDR28 (Bitfield-Mask: 0x01) */
#define BLEIF_DMATARGADDR_TARGADDR_Pos (0UL) /*!< TARGADDR (Bit 0) */
#define BLEIF_DMATARGADDR_TARGADDR_Msk (0xfffffUL) /*!< TARGADDR (Bitfield-Mask: 0xfffff) */
/* ======================================================== DMASTAT ======================================================== */
#define BLEIF_DMASTAT_DMAERR_Pos (2UL) /*!< DMAERR (Bit 2) */
#define BLEIF_DMASTAT_DMAERR_Msk (0x4UL) /*!< DMAERR (Bitfield-Mask: 0x01) */
#define BLEIF_DMASTAT_DMACPL_Pos (1UL) /*!< DMACPL (Bit 1) */
#define BLEIF_DMASTAT_DMACPL_Msk (0x2UL) /*!< DMACPL (Bitfield-Mask: 0x01) */
#define BLEIF_DMASTAT_DMATIP_Pos (0UL) /*!< DMATIP (Bit 0) */
#define BLEIF_DMASTAT_DMATIP_Msk (0x1UL) /*!< DMATIP (Bitfield-Mask: 0x01) */
/* ========================================================= CQCFG ========================================================= */
#define BLEIF_CQCFG_CQPRI_Pos (1UL) /*!< CQPRI (Bit 1) */
#define BLEIF_CQCFG_CQPRI_Msk (0x2UL) /*!< CQPRI (Bitfield-Mask: 0x01) */
#define BLEIF_CQCFG_CQEN_Pos (0UL) /*!< CQEN (Bit 0) */
#define BLEIF_CQCFG_CQEN_Msk (0x1UL) /*!< CQEN (Bitfield-Mask: 0x01) */
/* ======================================================== CQADDR ========================================================= */
#define BLEIF_CQADDR_CQADDR28_Pos (28UL) /*!< CQADDR28 (Bit 28) */
#define BLEIF_CQADDR_CQADDR28_Msk (0x10000000UL) /*!< CQADDR28 (Bitfield-Mask: 0x01) */
#define BLEIF_CQADDR_CQADDR_Pos (2UL) /*!< CQADDR (Bit 2) */
#define BLEIF_CQADDR_CQADDR_Msk (0xffffcUL) /*!< CQADDR (Bitfield-Mask: 0x3ffff) */
/* ======================================================== CQSTAT ========================================================= */
#define BLEIF_CQSTAT_CQERR_Pos (2UL) /*!< CQERR (Bit 2) */
#define BLEIF_CQSTAT_CQERR_Msk (0x4UL) /*!< CQERR (Bitfield-Mask: 0x01) */
#define BLEIF_CQSTAT_CQPAUSED_Pos (1UL) /*!< CQPAUSED (Bit 1) */
#define BLEIF_CQSTAT_CQPAUSED_Msk (0x2UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */
#define BLEIF_CQSTAT_CQTIP_Pos (0UL) /*!< CQTIP (Bit 0) */
#define BLEIF_CQSTAT_CQTIP_Msk (0x1UL) /*!< CQTIP (Bitfield-Mask: 0x01) */
/* ======================================================== CQFLAGS ======================================================== */
#define BLEIF_CQFLAGS_CQIRQMASK_Pos (16UL) /*!< CQIRQMASK (Bit 16) */
#define BLEIF_CQFLAGS_CQIRQMASK_Msk (0xffff0000UL) /*!< CQIRQMASK (Bitfield-Mask: 0xffff) */
#define BLEIF_CQFLAGS_CQFLAGS_Pos (0UL) /*!< CQFLAGS (Bit 0) */
#define BLEIF_CQFLAGS_CQFLAGS_Msk (0xffffUL) /*!< CQFLAGS (Bitfield-Mask: 0xffff) */
/* ====================================================== CQSETCLEAR ======================================================= */
#define BLEIF_CQSETCLEAR_CQFCLR_Pos (16UL) /*!< CQFCLR (Bit 16) */
#define BLEIF_CQSETCLEAR_CQFCLR_Msk (0xff0000UL) /*!< CQFCLR (Bitfield-Mask: 0xff) */
#define BLEIF_CQSETCLEAR_CQFTGL_Pos (8UL) /*!< CQFTGL (Bit 8) */
#define BLEIF_CQSETCLEAR_CQFTGL_Msk (0xff00UL) /*!< CQFTGL (Bitfield-Mask: 0xff) */
#define BLEIF_CQSETCLEAR_CQFSET_Pos (0UL) /*!< CQFSET (Bit 0) */
#define BLEIF_CQSETCLEAR_CQFSET_Msk (0xffUL) /*!< CQFSET (Bitfield-Mask: 0xff) */
/* ======================================================= CQPAUSEEN ======================================================= */
#define BLEIF_CQPAUSEEN_CQPEN_Pos (0UL) /*!< CQPEN (Bit 0) */
#define BLEIF_CQPAUSEEN_CQPEN_Msk (0xffffUL) /*!< CQPEN (Bitfield-Mask: 0xffff) */
/* ======================================================= CQCURIDX ======================================================== */
#define BLEIF_CQCURIDX_CQCURIDX_Pos (0UL) /*!< CQCURIDX (Bit 0) */
#define BLEIF_CQCURIDX_CQCURIDX_Msk (0xffUL) /*!< CQCURIDX (Bitfield-Mask: 0xff) */
/* ======================================================= CQENDIDX ======================================================== */
#define BLEIF_CQENDIDX_CQENDIDX_Pos (0UL) /*!< CQENDIDX (Bit 0) */
#define BLEIF_CQENDIDX_CQENDIDX_Msk (0xffUL) /*!< CQENDIDX (Bitfield-Mask: 0xff) */
/* ======================================================== STATUS ========================================================= */
#define BLEIF_STATUS_IDLEST_Pos (2UL) /*!< IDLEST (Bit 2) */
#define BLEIF_STATUS_IDLEST_Msk (0x4UL) /*!< IDLEST (Bitfield-Mask: 0x01) */
#define BLEIF_STATUS_CMDACT_Pos (1UL) /*!< CMDACT (Bit 1) */
#define BLEIF_STATUS_CMDACT_Msk (0x2UL) /*!< CMDACT (Bitfield-Mask: 0x01) */
#define BLEIF_STATUS_ERR_Pos (0UL) /*!< ERR (Bit 0) */
#define BLEIF_STATUS_ERR_Msk (0x1UL) /*!< ERR (Bitfield-Mask: 0x01) */
/* ======================================================== MSPICFG ======================================================== */
#define BLEIF_MSPICFG_MSPIRST_Pos (30UL) /*!< MSPIRST (Bit 30) */
#define BLEIF_MSPICFG_MSPIRST_Msk (0x40000000UL) /*!< MSPIRST (Bitfield-Mask: 0x01) */
#define BLEIF_MSPICFG_DOUTDLY_Pos (27UL) /*!< DOUTDLY (Bit 27) */
#define BLEIF_MSPICFG_DOUTDLY_Msk (0x38000000UL) /*!< DOUTDLY (Bitfield-Mask: 0x07) */
#define BLEIF_MSPICFG_DINDLY_Pos (24UL) /*!< DINDLY (Bit 24) */
#define BLEIF_MSPICFG_DINDLY_Msk (0x7000000UL) /*!< DINDLY (Bitfield-Mask: 0x07) */
#define BLEIF_MSPICFG_SPILSB_Pos (23UL) /*!< SPILSB (Bit 23) */
#define BLEIF_MSPICFG_SPILSB_Msk (0x800000UL) /*!< SPILSB (Bitfield-Mask: 0x01) */
#define BLEIF_MSPICFG_RDFCPOL_Pos (22UL) /*!< RDFCPOL (Bit 22) */
#define BLEIF_MSPICFG_RDFCPOL_Msk (0x400000UL) /*!< RDFCPOL (Bitfield-Mask: 0x01) */
#define BLEIF_MSPICFG_WTFCPOL_Pos (21UL) /*!< WTFCPOL (Bit 21) */
#define BLEIF_MSPICFG_WTFCPOL_Msk (0x200000UL) /*!< WTFCPOL (Bitfield-Mask: 0x01) */
#define BLEIF_MSPICFG_RDFC_Pos (17UL) /*!< RDFC (Bit 17) */
#define BLEIF_MSPICFG_RDFC_Msk (0x20000UL) /*!< RDFC (Bitfield-Mask: 0x01) */
#define BLEIF_MSPICFG_WTFC_Pos (16UL) /*!< WTFC (Bit 16) */
#define BLEIF_MSPICFG_WTFC_Msk (0x10000UL) /*!< WTFC (Bitfield-Mask: 0x01) */
#define BLEIF_MSPICFG_FULLDUP_Pos (2UL) /*!< FULLDUP (Bit 2) */
#define BLEIF_MSPICFG_FULLDUP_Msk (0x4UL) /*!< FULLDUP (Bitfield-Mask: 0x01) */
#define BLEIF_MSPICFG_SPHA_Pos (1UL) /*!< SPHA (Bit 1) */
#define BLEIF_MSPICFG_SPHA_Msk (0x2UL) /*!< SPHA (Bitfield-Mask: 0x01) */
#define BLEIF_MSPICFG_SPOL_Pos (0UL) /*!< SPOL (Bit 0) */
#define BLEIF_MSPICFG_SPOL_Msk (0x1UL) /*!< SPOL (Bitfield-Mask: 0x01) */
/* ======================================================== BLECFG ========================================================= */
#define BLEIF_BLECFG_SPIISOCTL_Pos (14UL) /*!< SPIISOCTL (Bit 14) */
#define BLEIF_BLECFG_SPIISOCTL_Msk (0xc000UL) /*!< SPIISOCTL (Bitfield-Mask: 0x03) */
#define BLEIF_BLECFG_PWRISOCTL_Pos (12UL) /*!< PWRISOCTL (Bit 12) */
#define BLEIF_BLECFG_PWRISOCTL_Msk (0x3000UL) /*!< PWRISOCTL (Bitfield-Mask: 0x03) */
#define BLEIF_BLECFG_STAYASLEEP_Pos (11UL) /*!< STAYASLEEP (Bit 11) */
#define BLEIF_BLECFG_STAYASLEEP_Msk (0x800UL) /*!< STAYASLEEP (Bitfield-Mask: 0x01) */
#define BLEIF_BLECFG_FRCCLK_Pos (10UL) /*!< FRCCLK (Bit 10) */
#define BLEIF_BLECFG_FRCCLK_Msk (0x400UL) /*!< FRCCLK (Bitfield-Mask: 0x01) */
#define BLEIF_BLECFG_MCUFRCSLP_Pos (9UL) /*!< MCUFRCSLP (Bit 9) */
#define BLEIF_BLECFG_MCUFRCSLP_Msk (0x200UL) /*!< MCUFRCSLP (Bitfield-Mask: 0x01) */
#define BLEIF_BLECFG_WT4ACTOFF_Pos (8UL) /*!< WT4ACTOFF (Bit 8) */
#define BLEIF_BLECFG_WT4ACTOFF_Msk (0x100UL) /*!< WT4ACTOFF (Bitfield-Mask: 0x01) */
#define BLEIF_BLECFG_BLEHREQCTL_Pos (6UL) /*!< BLEHREQCTL (Bit 6) */
#define BLEIF_BLECFG_BLEHREQCTL_Msk (0xc0UL) /*!< BLEHREQCTL (Bitfield-Mask: 0x03) */
#define BLEIF_BLECFG_DCDCFLGCTL_Pos (4UL) /*!< DCDCFLGCTL (Bit 4) */
#define BLEIF_BLECFG_DCDCFLGCTL_Msk (0x30UL) /*!< DCDCFLGCTL (Bitfield-Mask: 0x03) */
#define BLEIF_BLECFG_WAKEUPCTL_Pos (2UL) /*!< WAKEUPCTL (Bit 2) */
#define BLEIF_BLECFG_WAKEUPCTL_Msk (0xcUL) /*!< WAKEUPCTL (Bitfield-Mask: 0x03) */
#define BLEIF_BLECFG_BLERSTN_Pos (1UL) /*!< BLERSTN (Bit 1) */
#define BLEIF_BLECFG_BLERSTN_Msk (0x2UL) /*!< BLERSTN (Bitfield-Mask: 0x01) */
#define BLEIF_BLECFG_PWRSMEN_Pos (0UL) /*!< PWRSMEN (Bit 0) */
#define BLEIF_BLECFG_PWRSMEN_Msk (0x1UL) /*!< PWRSMEN (Bitfield-Mask: 0x01) */
/* ======================================================== PWRCMD ========================================================= */
#define BLEIF_PWRCMD_RESTART_Pos (1UL) /*!< RESTART (Bit 1) */
#define BLEIF_PWRCMD_RESTART_Msk (0x2UL) /*!< RESTART (Bitfield-Mask: 0x01) */
#define BLEIF_PWRCMD_WAKEREQ_Pos (0UL) /*!< WAKEREQ (Bit 0) */
#define BLEIF_PWRCMD_WAKEREQ_Msk (0x1UL) /*!< WAKEREQ (Bitfield-Mask: 0x01) */
/* ======================================================== BSTATUS ======================================================== */
#define BLEIF_BSTATUS_BLEHREQ_Pos (12UL) /*!< BLEHREQ (Bit 12) */
#define BLEIF_BSTATUS_BLEHREQ_Msk (0x1000UL) /*!< BLEHREQ (Bitfield-Mask: 0x01) */
#define BLEIF_BSTATUS_BLEHACK_Pos (11UL) /*!< BLEHACK (Bit 11) */
#define BLEIF_BSTATUS_BLEHACK_Msk (0x800UL) /*!< BLEHACK (Bitfield-Mask: 0x01) */
#define BLEIF_BSTATUS_PWRST_Pos (8UL) /*!< PWRST (Bit 8) */
#define BLEIF_BSTATUS_PWRST_Msk (0x700UL) /*!< PWRST (Bitfield-Mask: 0x07) */
#define BLEIF_BSTATUS_BLEIRQ_Pos (7UL) /*!< BLEIRQ (Bit 7) */
#define BLEIF_BSTATUS_BLEIRQ_Msk (0x80UL) /*!< BLEIRQ (Bitfield-Mask: 0x01) */
#define BLEIF_BSTATUS_WAKEUP_Pos (6UL) /*!< WAKEUP (Bit 6) */
#define BLEIF_BSTATUS_WAKEUP_Msk (0x40UL) /*!< WAKEUP (Bitfield-Mask: 0x01) */
#define BLEIF_BSTATUS_DCDCFLAG_Pos (5UL) /*!< DCDCFLAG (Bit 5) */
#define BLEIF_BSTATUS_DCDCFLAG_Msk (0x20UL) /*!< DCDCFLAG (Bitfield-Mask: 0x01) */
#define BLEIF_BSTATUS_DCDCREQ_Pos (4UL) /*!< DCDCREQ (Bit 4) */
#define BLEIF_BSTATUS_DCDCREQ_Msk (0x10UL) /*!< DCDCREQ (Bitfield-Mask: 0x01) */
#define BLEIF_BSTATUS_SPISTATUS_Pos (3UL) /*!< SPISTATUS (Bit 3) */
#define BLEIF_BSTATUS_SPISTATUS_Msk (0x8UL) /*!< SPISTATUS (Bitfield-Mask: 0x01) */
#define BLEIF_BSTATUS_B2MSTATE_Pos (0UL) /*!< B2MSTATE (Bit 0) */
#define BLEIF_BSTATUS_B2MSTATE_Msk (0x7UL) /*!< B2MSTATE (Bitfield-Mask: 0x07) */
/* ======================================================== BLEDBG ========================================================= */
#define BLEIF_BLEDBG_DBGDATA_Pos (3UL) /*!< DBGDATA (Bit 3) */
#define BLEIF_BLEDBG_DBGDATA_Msk (0xfffffff8UL) /*!< DBGDATA (Bitfield-Mask: 0x1fffffff) */
#define BLEIF_BLEDBG_APBCLKON_Pos (2UL) /*!< APBCLKON (Bit 2) */
#define BLEIF_BLEDBG_APBCLKON_Msk (0x4UL) /*!< APBCLKON (Bitfield-Mask: 0x01) */
#define BLEIF_BLEDBG_IOCLKON_Pos (1UL) /*!< IOCLKON (Bit 1) */
#define BLEIF_BLEDBG_IOCLKON_Msk (0x2UL) /*!< IOCLKON (Bitfield-Mask: 0x01) */
#define BLEIF_BLEDBG_DBGEN_Pos (0UL) /*!< DBGEN (Bit 0) */
#define BLEIF_BLEDBG_DBGEN_Msk (0x1UL) /*!< DBGEN (Bitfield-Mask: 0x01) */
/* =========================================================================================================================== */
/* ================ CACHECTRL ================ */
/* =========================================================================================================================== */
/* ======================================================= CACHECFG ======================================================== */
#define CACHECTRL_CACHECFG_ENABLE_MONITOR_Pos (24UL) /*!< ENABLE_MONITOR (Bit 24) */
#define CACHECTRL_CACHECFG_ENABLE_MONITOR_Msk (0x1000000UL) /*!< ENABLE_MONITOR (Bitfield-Mask: 0x01) */
#define CACHECTRL_CACHECFG_DATA_CLKGATE_Pos (20UL) /*!< DATA_CLKGATE (Bit 20) */
#define CACHECTRL_CACHECFG_DATA_CLKGATE_Msk (0x100000UL) /*!< DATA_CLKGATE (Bitfield-Mask: 0x01) */
#define CACHECTRL_CACHECFG_CACHE_LS_Pos (11UL) /*!< CACHE_LS (Bit 11) */
#define CACHECTRL_CACHECFG_CACHE_LS_Msk (0x800UL) /*!< CACHE_LS (Bitfield-Mask: 0x01) */
#define CACHECTRL_CACHECFG_CACHE_CLKGATE_Pos (10UL) /*!< CACHE_CLKGATE (Bit 10) */
#define CACHECTRL_CACHECFG_CACHE_CLKGATE_Msk (0x400UL) /*!< CACHE_CLKGATE (Bitfield-Mask: 0x01) */
#define CACHECTRL_CACHECFG_DCACHE_ENABLE_Pos (9UL) /*!< DCACHE_ENABLE (Bit 9) */
#define CACHECTRL_CACHECFG_DCACHE_ENABLE_Msk (0x200UL) /*!< DCACHE_ENABLE (Bitfield-Mask: 0x01) */
#define CACHECTRL_CACHECFG_ICACHE_ENABLE_Pos (8UL) /*!< ICACHE_ENABLE (Bit 8) */
#define CACHECTRL_CACHECFG_ICACHE_ENABLE_Msk (0x100UL) /*!< ICACHE_ENABLE (Bitfield-Mask: 0x01) */
#define CACHECTRL_CACHECFG_CONFIG_Pos (4UL) /*!< CONFIG (Bit 4) */
#define CACHECTRL_CACHECFG_CONFIG_Msk (0xf0UL) /*!< CONFIG (Bitfield-Mask: 0x0f) */
#define CACHECTRL_CACHECFG_ENABLE_NC1_Pos (3UL) /*!< ENABLE_NC1 (Bit 3) */
#define CACHECTRL_CACHECFG_ENABLE_NC1_Msk (0x8UL) /*!< ENABLE_NC1 (Bitfield-Mask: 0x01) */
#define CACHECTRL_CACHECFG_ENABLE_NC0_Pos (2UL) /*!< ENABLE_NC0 (Bit 2) */
#define CACHECTRL_CACHECFG_ENABLE_NC0_Msk (0x4UL) /*!< ENABLE_NC0 (Bitfield-Mask: 0x01) */
#define CACHECTRL_CACHECFG_LRU_Pos (1UL) /*!< LRU (Bit 1) */
#define CACHECTRL_CACHECFG_LRU_Msk (0x2UL) /*!< LRU (Bitfield-Mask: 0x01) */
#define CACHECTRL_CACHECFG_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */
#define CACHECTRL_CACHECFG_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
/* ======================================================= FLASHCFG ======================================================== */
#define CACHECTRL_FLASHCFG_LPMMODE_Pos (12UL) /*!< LPMMODE (Bit 12) */
#define CACHECTRL_FLASHCFG_LPMMODE_Msk (0x3000UL) /*!< LPMMODE (Bitfield-Mask: 0x03) */
#define CACHECTRL_FLASHCFG_LPM_RD_WAIT_Pos (8UL) /*!< LPM_RD_WAIT (Bit 8) */
#define CACHECTRL_FLASHCFG_LPM_RD_WAIT_Msk (0xf00UL) /*!< LPM_RD_WAIT (Bitfield-Mask: 0x0f) */
#define CACHECTRL_FLASHCFG_SEDELAY_Pos (4UL) /*!< SEDELAY (Bit 4) */
#define CACHECTRL_FLASHCFG_SEDELAY_Msk (0x70UL) /*!< SEDELAY (Bitfield-Mask: 0x07) */
#define CACHECTRL_FLASHCFG_RD_WAIT_Pos (0UL) /*!< RD_WAIT (Bit 0) */
#define CACHECTRL_FLASHCFG_RD_WAIT_Msk (0xfUL) /*!< RD_WAIT (Bitfield-Mask: 0x0f) */
/* ========================================================= CTRL ========================================================== */
#define CACHECTRL_CTRL_FLASH1_SLM_ENABLE_Pos (10UL) /*!< FLASH1_SLM_ENABLE (Bit 10) */
#define CACHECTRL_CTRL_FLASH1_SLM_ENABLE_Msk (0x400UL) /*!< FLASH1_SLM_ENABLE (Bitfield-Mask: 0x01) */
#define CACHECTRL_CTRL_FLASH1_SLM_DISABLE_Pos (9UL) /*!< FLASH1_SLM_DISABLE (Bit 9) */
#define CACHECTRL_CTRL_FLASH1_SLM_DISABLE_Msk (0x200UL) /*!< FLASH1_SLM_DISABLE (Bitfield-Mask: 0x01) */
#define CACHECTRL_CTRL_FLASH1_SLM_STATUS_Pos (8UL) /*!< FLASH1_SLM_STATUS (Bit 8) */
#define CACHECTRL_CTRL_FLASH1_SLM_STATUS_Msk (0x100UL) /*!< FLASH1_SLM_STATUS (Bitfield-Mask: 0x01) */
#define CACHECTRL_CTRL_FLASH0_SLM_ENABLE_Pos (6UL) /*!< FLASH0_SLM_ENABLE (Bit 6) */
#define CACHECTRL_CTRL_FLASH0_SLM_ENABLE_Msk (0x40UL) /*!< FLASH0_SLM_ENABLE (Bitfield-Mask: 0x01) */
#define CACHECTRL_CTRL_FLASH0_SLM_DISABLE_Pos (5UL) /*!< FLASH0_SLM_DISABLE (Bit 5) */
#define CACHECTRL_CTRL_FLASH0_SLM_DISABLE_Msk (0x20UL) /*!< FLASH0_SLM_DISABLE (Bitfield-Mask: 0x01) */
#define CACHECTRL_CTRL_FLASH0_SLM_STATUS_Pos (4UL) /*!< FLASH0_SLM_STATUS (Bit 4) */
#define CACHECTRL_CTRL_FLASH0_SLM_STATUS_Msk (0x10UL) /*!< FLASH0_SLM_STATUS (Bitfield-Mask: 0x01) */
#define CACHECTRL_CTRL_CACHE_READY_Pos (2UL) /*!< CACHE_READY (Bit 2) */
#define CACHECTRL_CTRL_CACHE_READY_Msk (0x4UL) /*!< CACHE_READY (Bitfield-Mask: 0x01) */
#define CACHECTRL_CTRL_RESET_STAT_Pos (1UL) /*!< RESET_STAT (Bit 1) */
#define CACHECTRL_CTRL_RESET_STAT_Msk (0x2UL) /*!< RESET_STAT (Bitfield-Mask: 0x01) */
#define CACHECTRL_CTRL_INVALIDATE_Pos (0UL) /*!< INVALIDATE (Bit 0) */
#define CACHECTRL_CTRL_INVALIDATE_Msk (0x1UL) /*!< INVALIDATE (Bitfield-Mask: 0x01) */
/* ======================================================= NCR0START ======================================================= */
#define CACHECTRL_NCR0START_ADDR_Pos (4UL) /*!< ADDR (Bit 4) */
#define CACHECTRL_NCR0START_ADDR_Msk (0x7fffff0UL) /*!< ADDR (Bitfield-Mask: 0x7fffff) */
/* ======================================================== NCR0END ======================================================== */
#define CACHECTRL_NCR0END_ADDR_Pos (4UL) /*!< ADDR (Bit 4) */
#define CACHECTRL_NCR0END_ADDR_Msk (0x7fffff0UL) /*!< ADDR (Bitfield-Mask: 0x7fffff) */
/* ======================================================= NCR1START ======================================================= */
#define CACHECTRL_NCR1START_ADDR_Pos (4UL) /*!< ADDR (Bit 4) */
#define CACHECTRL_NCR1START_ADDR_Msk (0x7fffff0UL) /*!< ADDR (Bitfield-Mask: 0x7fffff) */
/* ======================================================== NCR1END ======================================================== */
#define CACHECTRL_NCR1END_ADDR_Pos (4UL) /*!< ADDR (Bit 4) */
#define CACHECTRL_NCR1END_ADDR_Msk (0x7fffff0UL) /*!< ADDR (Bitfield-Mask: 0x7fffff) */
/* ========================================================= DMON0 ========================================================= */
#define CACHECTRL_DMON0_DACCESS_COUNT_Pos (0UL) /*!< DACCESS_COUNT (Bit 0) */
#define CACHECTRL_DMON0_DACCESS_COUNT_Msk (0xffffffffUL) /*!< DACCESS_COUNT (Bitfield-Mask: 0xffffffff) */
/* ========================================================= DMON1 ========================================================= */
#define CACHECTRL_DMON1_DLOOKUP_COUNT_Pos (0UL) /*!< DLOOKUP_COUNT (Bit 0) */
#define CACHECTRL_DMON1_DLOOKUP_COUNT_Msk (0xffffffffUL) /*!< DLOOKUP_COUNT (Bitfield-Mask: 0xffffffff) */
/* ========================================================= DMON2 ========================================================= */
#define CACHECTRL_DMON2_DHIT_COUNT_Pos (0UL) /*!< DHIT_COUNT (Bit 0) */
#define CACHECTRL_DMON2_DHIT_COUNT_Msk (0xffffffffUL) /*!< DHIT_COUNT (Bitfield-Mask: 0xffffffff) */
/* ========================================================= DMON3 ========================================================= */
#define CACHECTRL_DMON3_DLINE_COUNT_Pos (0UL) /*!< DLINE_COUNT (Bit 0) */
#define CACHECTRL_DMON3_DLINE_COUNT_Msk (0xffffffffUL) /*!< DLINE_COUNT (Bitfield-Mask: 0xffffffff) */
/* ========================================================= IMON0 ========================================================= */
#define CACHECTRL_IMON0_IACCESS_COUNT_Pos (0UL) /*!< IACCESS_COUNT (Bit 0) */
#define CACHECTRL_IMON0_IACCESS_COUNT_Msk (0xffffffffUL) /*!< IACCESS_COUNT (Bitfield-Mask: 0xffffffff) */
/* ========================================================= IMON1 ========================================================= */
#define CACHECTRL_IMON1_ILOOKUP_COUNT_Pos (0UL) /*!< ILOOKUP_COUNT (Bit 0) */
#define CACHECTRL_IMON1_ILOOKUP_COUNT_Msk (0xffffffffUL) /*!< ILOOKUP_COUNT (Bitfield-Mask: 0xffffffff) */
/* ========================================================= IMON2 ========================================================= */
#define CACHECTRL_IMON2_IHIT_COUNT_Pos (0UL) /*!< IHIT_COUNT (Bit 0) */
#define CACHECTRL_IMON2_IHIT_COUNT_Msk (0xffffffffUL) /*!< IHIT_COUNT (Bitfield-Mask: 0xffffffff) */
/* ========================================================= IMON3 ========================================================= */
#define CACHECTRL_IMON3_ILINE_COUNT_Pos (0UL) /*!< ILINE_COUNT (Bit 0) */
#define CACHECTRL_IMON3_ILINE_COUNT_Msk (0xffffffffUL) /*!< ILINE_COUNT (Bitfield-Mask: 0xffffffff) */
/* =========================================================================================================================== */
/* ================ CLKGEN ================ */
/* =========================================================================================================================== */
/* ========================================================= CALXT ========================================================= */
#define CLKGEN_CALXT_CALXT_Pos (0UL) /*!< CALXT (Bit 0) */
#define CLKGEN_CALXT_CALXT_Msk (0x7ffUL) /*!< CALXT (Bitfield-Mask: 0x7ff) */
/* ========================================================= CALRC ========================================================= */
#define CLKGEN_CALRC_CALRC_Pos (0UL) /*!< CALRC (Bit 0) */
#define CLKGEN_CALRC_CALRC_Msk (0x3ffffUL) /*!< CALRC (Bitfield-Mask: 0x3ffff) */
/* ======================================================== ACALCTR ======================================================== */
#define CLKGEN_ACALCTR_ACALCTR_Pos (0UL) /*!< ACALCTR (Bit 0) */
#define CLKGEN_ACALCTR_ACALCTR_Msk (0xffffffUL) /*!< ACALCTR (Bitfield-Mask: 0xffffff) */
/* ========================================================= OCTRL ========================================================= */
#define CLKGEN_OCTRL_ACAL_Pos (8UL) /*!< ACAL (Bit 8) */
#define CLKGEN_OCTRL_ACAL_Msk (0x700UL) /*!< ACAL (Bitfield-Mask: 0x07) */
#define CLKGEN_OCTRL_OSEL_Pos (7UL) /*!< OSEL (Bit 7) */
#define CLKGEN_OCTRL_OSEL_Msk (0x80UL) /*!< OSEL (Bitfield-Mask: 0x01) */
#define CLKGEN_OCTRL_FOS_Pos (6UL) /*!< FOS (Bit 6) */
#define CLKGEN_OCTRL_FOS_Msk (0x40UL) /*!< FOS (Bitfield-Mask: 0x01) */
#define CLKGEN_OCTRL_STOPRC_Pos (1UL) /*!< STOPRC (Bit 1) */
#define CLKGEN_OCTRL_STOPRC_Msk (0x2UL) /*!< STOPRC (Bitfield-Mask: 0x01) */
#define CLKGEN_OCTRL_STOPXT_Pos (0UL) /*!< STOPXT (Bit 0) */
#define CLKGEN_OCTRL_STOPXT_Msk (0x1UL) /*!< STOPXT (Bitfield-Mask: 0x01) */
/* ======================================================== CLKOUT ========================================================= */
#define CLKGEN_CLKOUT_CKEN_Pos (7UL) /*!< CKEN (Bit 7) */
#define CLKGEN_CLKOUT_CKEN_Msk (0x80UL) /*!< CKEN (Bitfield-Mask: 0x01) */
#define CLKGEN_CLKOUT_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */
#define CLKGEN_CLKOUT_CKSEL_Msk (0x3fUL) /*!< CKSEL (Bitfield-Mask: 0x3f) */
/* ======================================================== CLKKEY ========================================================= */
#define CLKGEN_CLKKEY_CLKKEY_Pos (0UL) /*!< CLKKEY (Bit 0) */
#define CLKGEN_CLKKEY_CLKKEY_Msk (0xffffffffUL) /*!< CLKKEY (Bitfield-Mask: 0xffffffff) */
/* ========================================================= CCTRL ========================================================= */
#define CLKGEN_CCTRL_CORESEL_Pos (0UL) /*!< CORESEL (Bit 0) */
#define CLKGEN_CCTRL_CORESEL_Msk (0x1UL) /*!< CORESEL (Bitfield-Mask: 0x01) */
/* ======================================================== STATUS ========================================================= */
#define CLKGEN_STATUS_OSCF_Pos (1UL) /*!< OSCF (Bit 1) */
#define CLKGEN_STATUS_OSCF_Msk (0x2UL) /*!< OSCF (Bitfield-Mask: 0x01) */
#define CLKGEN_STATUS_OMODE_Pos (0UL) /*!< OMODE (Bit 0) */
#define CLKGEN_STATUS_OMODE_Msk (0x1UL) /*!< OMODE (Bitfield-Mask: 0x01) */
/* ========================================================= HFADJ ========================================================= */
#define CLKGEN_HFADJ_HFADJGAIN_Pos (21UL) /*!< HFADJGAIN (Bit 21) */
#define CLKGEN_HFADJ_HFADJGAIN_Msk (0xe00000UL) /*!< HFADJGAIN (Bitfield-Mask: 0x07) */
#define CLKGEN_HFADJ_HFWARMUP_Pos (20UL) /*!< HFWARMUP (Bit 20) */
#define CLKGEN_HFADJ_HFWARMUP_Msk (0x100000UL) /*!< HFWARMUP (Bitfield-Mask: 0x01) */
#define CLKGEN_HFADJ_HFXTADJ_Pos (8UL) /*!< HFXTADJ (Bit 8) */
#define CLKGEN_HFADJ_HFXTADJ_Msk (0xfff00UL) /*!< HFXTADJ (Bitfield-Mask: 0xfff) */
#define CLKGEN_HFADJ_HFADJCK_Pos (1UL) /*!< HFADJCK (Bit 1) */
#define CLKGEN_HFADJ_HFADJCK_Msk (0xeUL) /*!< HFADJCK (Bitfield-Mask: 0x07) */
#define CLKGEN_HFADJ_HFADJEN_Pos (0UL) /*!< HFADJEN (Bit 0) */
#define CLKGEN_HFADJ_HFADJEN_Msk (0x1UL) /*!< HFADJEN (Bitfield-Mask: 0x01) */
/* ====================================================== CLOCKENSTAT ====================================================== */
#define CLKGEN_CLOCKENSTAT_CLOCKENSTAT_Pos (0UL) /*!< CLOCKENSTAT (Bit 0) */
#define CLKGEN_CLOCKENSTAT_CLOCKENSTAT_Msk (0xffffffffUL) /*!< CLOCKENSTAT (Bitfield-Mask: 0xffffffff) */
/* ===================================================== CLOCKEN2STAT ====================================================== */
#define CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_Pos (0UL) /*!< CLOCKEN2STAT (Bit 0) */
#define CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_Msk (0xffffffffUL) /*!< CLOCKEN2STAT (Bitfield-Mask: 0xffffffff) */
/* ===================================================== CLOCKEN3STAT ====================================================== */
#define CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_Pos (0UL) /*!< CLOCKEN3STAT (Bit 0) */
#define CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_Msk (0xffffffffUL) /*!< CLOCKEN3STAT (Bitfield-Mask: 0xffffffff) */
/* ======================================================= FREQCTRL ======================================================== */
#define CLKGEN_FREQCTRL_BURSTSTATUS_Pos (2UL) /*!< BURSTSTATUS (Bit 2) */
#define CLKGEN_FREQCTRL_BURSTSTATUS_Msk (0x4UL) /*!< BURSTSTATUS (Bitfield-Mask: 0x01) */
#define CLKGEN_FREQCTRL_BURSTACK_Pos (1UL) /*!< BURSTACK (Bit 1) */
#define CLKGEN_FREQCTRL_BURSTACK_Msk (0x2UL) /*!< BURSTACK (Bitfield-Mask: 0x01) */
#define CLKGEN_FREQCTRL_BURSTREQ_Pos (0UL) /*!< BURSTREQ (Bit 0) */
#define CLKGEN_FREQCTRL_BURSTREQ_Msk (0x1UL) /*!< BURSTREQ (Bitfield-Mask: 0x01) */
/* ===================================================== BLEBUCKTONADJ ===================================================== */
#define CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTEN_Pos (27UL) /*!< ZEROLENDETECTEN (Bit 27) */
#define CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTEN_Msk (0x8000000UL) /*!< ZEROLENDETECTEN (Bitfield-Mask: 0x01) */
#define CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Pos (23UL) /*!< ZEROLENDETECTTRIM (Bit 23) */
#define CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Msk (0x7800000UL) /*!< ZEROLENDETECTTRIM (Bitfield-Mask: 0x0f) */
#define CLKGEN_BLEBUCKTONADJ_TONADJUSTEN_Pos (22UL) /*!< TONADJUSTEN (Bit 22) */
#define CLKGEN_BLEBUCKTONADJ_TONADJUSTEN_Msk (0x400000UL) /*!< TONADJUSTEN (Bitfield-Mask: 0x01) */
#define CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_Pos (20UL) /*!< TONADJUSTPERIOD (Bit 20) */
#define CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_Msk (0x300000UL) /*!< TONADJUSTPERIOD (Bitfield-Mask: 0x03) */
#define CLKGEN_BLEBUCKTONADJ_TONHIGHTHRESHOLD_Pos (10UL) /*!< TONHIGHTHRESHOLD (Bit 10) */
#define CLKGEN_BLEBUCKTONADJ_TONHIGHTHRESHOLD_Msk (0xffc00UL) /*!< TONHIGHTHRESHOLD (Bitfield-Mask: 0x3ff) */
#define CLKGEN_BLEBUCKTONADJ_TONLOWTHRESHOLD_Pos (0UL) /*!< TONLOWTHRESHOLD (Bit 0) */
#define CLKGEN_BLEBUCKTONADJ_TONLOWTHRESHOLD_Msk (0x3ffUL) /*!< TONLOWTHRESHOLD (Bitfield-Mask: 0x3ff) */
/* ======================================================= INTRPTEN ======================================================== */
#define CLKGEN_INTRPTEN_OF_Pos (2UL) /*!< OF (Bit 2) */
#define CLKGEN_INTRPTEN_OF_Msk (0x4UL) /*!< OF (Bitfield-Mask: 0x01) */
#define CLKGEN_INTRPTEN_ACC_Pos (1UL) /*!< ACC (Bit 1) */
#define CLKGEN_INTRPTEN_ACC_Msk (0x2UL) /*!< ACC (Bitfield-Mask: 0x01) */
#define CLKGEN_INTRPTEN_ACF_Pos (0UL) /*!< ACF (Bit 0) */
#define CLKGEN_INTRPTEN_ACF_Msk (0x1UL) /*!< ACF (Bitfield-Mask: 0x01) */
/* ====================================================== INTRPTSTAT ======================================================= */
#define CLKGEN_INTRPTSTAT_OF_Pos (2UL) /*!< OF (Bit 2) */
#define CLKGEN_INTRPTSTAT_OF_Msk (0x4UL) /*!< OF (Bitfield-Mask: 0x01) */
#define CLKGEN_INTRPTSTAT_ACC_Pos (1UL) /*!< ACC (Bit 1) */
#define CLKGEN_INTRPTSTAT_ACC_Msk (0x2UL) /*!< ACC (Bitfield-Mask: 0x01) */
#define CLKGEN_INTRPTSTAT_ACF_Pos (0UL) /*!< ACF (Bit 0) */
#define CLKGEN_INTRPTSTAT_ACF_Msk (0x1UL) /*!< ACF (Bitfield-Mask: 0x01) */
/* ======================================================= INTRPTCLR ======================================================= */
#define CLKGEN_INTRPTCLR_OF_Pos (2UL) /*!< OF (Bit 2) */
#define CLKGEN_INTRPTCLR_OF_Msk (0x4UL) /*!< OF (Bitfield-Mask: 0x01) */
#define CLKGEN_INTRPTCLR_ACC_Pos (1UL) /*!< ACC (Bit 1) */
#define CLKGEN_INTRPTCLR_ACC_Msk (0x2UL) /*!< ACC (Bitfield-Mask: 0x01) */
#define CLKGEN_INTRPTCLR_ACF_Pos (0UL) /*!< ACF (Bit 0) */
#define CLKGEN_INTRPTCLR_ACF_Msk (0x1UL) /*!< ACF (Bitfield-Mask: 0x01) */
/* ======================================================= INTRPTSET ======================================================= */
#define CLKGEN_INTRPTSET_OF_Pos (2UL) /*!< OF (Bit 2) */
#define CLKGEN_INTRPTSET_OF_Msk (0x4UL) /*!< OF (Bitfield-Mask: 0x01) */
#define CLKGEN_INTRPTSET_ACC_Pos (1UL) /*!< ACC (Bit 1) */
#define CLKGEN_INTRPTSET_ACC_Msk (0x2UL) /*!< ACC (Bitfield-Mask: 0x01) */
#define CLKGEN_INTRPTSET_ACF_Pos (0UL) /*!< ACF (Bit 0) */
#define CLKGEN_INTRPTSET_ACF_Msk (0x1UL) /*!< ACF (Bitfield-Mask: 0x01) */
/* =========================================================================================================================== */
/* ================ CTIMER ================ */
/* =========================================================================================================================== */
/* ========================================================= TMR0 ========================================================== */
#define CTIMER_TMR0_CTTMRB0_Pos (16UL) /*!< CTTMRB0 (Bit 16) */
#define CTIMER_TMR0_CTTMRB0_Msk (0xffff0000UL) /*!< CTTMRB0 (Bitfield-Mask: 0xffff) */
#define CTIMER_TMR0_CTTMRA0_Pos (0UL) /*!< CTTMRA0 (Bit 0) */
#define CTIMER_TMR0_CTTMRA0_Msk (0xffffUL) /*!< CTTMRA0 (Bitfield-Mask: 0xffff) */
/* ======================================================== CMPRA0 ========================================================= */
#define CTIMER_CMPRA0_CMPR1A0_Pos (16UL) /*!< CMPR1A0 (Bit 16) */
#define CTIMER_CMPRA0_CMPR1A0_Msk (0xffff0000UL) /*!< CMPR1A0 (Bitfield-Mask: 0xffff) */
#define CTIMER_CMPRA0_CMPR0A0_Pos (0UL) /*!< CMPR0A0 (Bit 0) */
#define CTIMER_CMPRA0_CMPR0A0_Msk (0xffffUL) /*!< CMPR0A0 (Bitfield-Mask: 0xffff) */
/* ======================================================== CMPRB0 ========================================================= */
#define CTIMER_CMPRB0_CMPR1B0_Pos (16UL) /*!< CMPR1B0 (Bit 16) */
#define CTIMER_CMPRB0_CMPR1B0_Msk (0xffff0000UL) /*!< CMPR1B0 (Bitfield-Mask: 0xffff) */
#define CTIMER_CMPRB0_CMPR0B0_Pos (0UL) /*!< CMPR0B0 (Bit 0) */
#define CTIMER_CMPRB0_CMPR0B0_Msk (0xffffUL) /*!< CMPR0B0 (Bitfield-Mask: 0xffff) */
/* ========================================================= CTRL0 ========================================================= */
#define CTIMER_CTRL0_CTLINK0_Pos (31UL) /*!< CTLINK0 (Bit 31) */
#define CTIMER_CTRL0_CTLINK0_Msk (0x80000000UL) /*!< CTLINK0 (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL0_TMRB0POL_Pos (28UL) /*!< TMRB0POL (Bit 28) */
#define CTIMER_CTRL0_TMRB0POL_Msk (0x10000000UL) /*!< TMRB0POL (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL0_TMRB0CLR_Pos (27UL) /*!< TMRB0CLR (Bit 27) */
#define CTIMER_CTRL0_TMRB0CLR_Msk (0x8000000UL) /*!< TMRB0CLR (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL0_TMRB0IE1_Pos (26UL) /*!< TMRB0IE1 (Bit 26) */
#define CTIMER_CTRL0_TMRB0IE1_Msk (0x4000000UL) /*!< TMRB0IE1 (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL0_TMRB0IE0_Pos (25UL) /*!< TMRB0IE0 (Bit 25) */
#define CTIMER_CTRL0_TMRB0IE0_Msk (0x2000000UL) /*!< TMRB0IE0 (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL0_TMRB0FN_Pos (22UL) /*!< TMRB0FN (Bit 22) */
#define CTIMER_CTRL0_TMRB0FN_Msk (0x1c00000UL) /*!< TMRB0FN (Bitfield-Mask: 0x07) */
#define CTIMER_CTRL0_TMRB0CLK_Pos (17UL) /*!< TMRB0CLK (Bit 17) */
#define CTIMER_CTRL0_TMRB0CLK_Msk (0x3e0000UL) /*!< TMRB0CLK (Bitfield-Mask: 0x1f) */
#define CTIMER_CTRL0_TMRB0EN_Pos (16UL) /*!< TMRB0EN (Bit 16) */
#define CTIMER_CTRL0_TMRB0EN_Msk (0x10000UL) /*!< TMRB0EN (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL0_TMRA0POL_Pos (12UL) /*!< TMRA0POL (Bit 12) */
#define CTIMER_CTRL0_TMRA0POL_Msk (0x1000UL) /*!< TMRA0POL (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL0_TMRA0CLR_Pos (11UL) /*!< TMRA0CLR (Bit 11) */
#define CTIMER_CTRL0_TMRA0CLR_Msk (0x800UL) /*!< TMRA0CLR (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL0_TMRA0IE1_Pos (10UL) /*!< TMRA0IE1 (Bit 10) */
#define CTIMER_CTRL0_TMRA0IE1_Msk (0x400UL) /*!< TMRA0IE1 (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL0_TMRA0IE0_Pos (9UL) /*!< TMRA0IE0 (Bit 9) */
#define CTIMER_CTRL0_TMRA0IE0_Msk (0x200UL) /*!< TMRA0IE0 (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL0_TMRA0FN_Pos (6UL) /*!< TMRA0FN (Bit 6) */
#define CTIMER_CTRL0_TMRA0FN_Msk (0x1c0UL) /*!< TMRA0FN (Bitfield-Mask: 0x07) */
#define CTIMER_CTRL0_TMRA0CLK_Pos (1UL) /*!< TMRA0CLK (Bit 1) */
#define CTIMER_CTRL0_TMRA0CLK_Msk (0x3eUL) /*!< TMRA0CLK (Bitfield-Mask: 0x1f) */
#define CTIMER_CTRL0_TMRA0EN_Pos (0UL) /*!< TMRA0EN (Bit 0) */
#define CTIMER_CTRL0_TMRA0EN_Msk (0x1UL) /*!< TMRA0EN (Bitfield-Mask: 0x01) */
/* ======================================================= CMPRAUXA0 ======================================================= */
#define CTIMER_CMPRAUXA0_CMPR3A0_Pos (16UL) /*!< CMPR3A0 (Bit 16) */
#define CTIMER_CMPRAUXA0_CMPR3A0_Msk (0xffff0000UL) /*!< CMPR3A0 (Bitfield-Mask: 0xffff) */
#define CTIMER_CMPRAUXA0_CMPR2A0_Pos (0UL) /*!< CMPR2A0 (Bit 0) */
#define CTIMER_CMPRAUXA0_CMPR2A0_Msk (0xffffUL) /*!< CMPR2A0 (Bitfield-Mask: 0xffff) */
/* ======================================================= CMPRAUXB0 ======================================================= */
#define CTIMER_CMPRAUXB0_CMPR3B0_Pos (16UL) /*!< CMPR3B0 (Bit 16) */
#define CTIMER_CMPRAUXB0_CMPR3B0_Msk (0xffff0000UL) /*!< CMPR3B0 (Bitfield-Mask: 0xffff) */
#define CTIMER_CMPRAUXB0_CMPR2B0_Pos (0UL) /*!< CMPR2B0 (Bit 0) */
#define CTIMER_CMPRAUXB0_CMPR2B0_Msk (0xffffUL) /*!< CMPR2B0 (Bitfield-Mask: 0xffff) */
/* ========================================================= AUX0 ========================================================== */
#define CTIMER_AUX0_TMRB0EN23_Pos (30UL) /*!< TMRB0EN23 (Bit 30) */
#define CTIMER_AUX0_TMRB0EN23_Msk (0x40000000UL) /*!< TMRB0EN23 (Bitfield-Mask: 0x01) */
#define CTIMER_AUX0_TMRB0POL23_Pos (29UL) /*!< TMRB0POL23 (Bit 29) */
#define CTIMER_AUX0_TMRB0POL23_Msk (0x20000000UL) /*!< TMRB0POL23 (Bitfield-Mask: 0x01) */
#define CTIMER_AUX0_TMRB0TINV_Pos (28UL) /*!< TMRB0TINV (Bit 28) */
#define CTIMER_AUX0_TMRB0TINV_Msk (0x10000000UL) /*!< TMRB0TINV (Bitfield-Mask: 0x01) */
#define CTIMER_AUX0_TMRB0NOSYNC_Pos (27UL) /*!< TMRB0NOSYNC (Bit 27) */
#define CTIMER_AUX0_TMRB0NOSYNC_Msk (0x8000000UL) /*!< TMRB0NOSYNC (Bitfield-Mask: 0x01) */
#define CTIMER_AUX0_TMRB0TRIG_Pos (23UL) /*!< TMRB0TRIG (Bit 23) */
#define CTIMER_AUX0_TMRB0TRIG_Msk (0x7800000UL) /*!< TMRB0TRIG (Bitfield-Mask: 0x0f) */
#define CTIMER_AUX0_TMRB0LMT_Pos (16UL) /*!< TMRB0LMT (Bit 16) */
#define CTIMER_AUX0_TMRB0LMT_Msk (0x3f0000UL) /*!< TMRB0LMT (Bitfield-Mask: 0x3f) */
#define CTIMER_AUX0_TMRA0EN23_Pos (14UL) /*!< TMRA0EN23 (Bit 14) */
#define CTIMER_AUX0_TMRA0EN23_Msk (0x4000UL) /*!< TMRA0EN23 (Bitfield-Mask: 0x01) */
#define CTIMER_AUX0_TMRA0POL23_Pos (13UL) /*!< TMRA0POL23 (Bit 13) */
#define CTIMER_AUX0_TMRA0POL23_Msk (0x2000UL) /*!< TMRA0POL23 (Bitfield-Mask: 0x01) */
#define CTIMER_AUX0_TMRA0TINV_Pos (12UL) /*!< TMRA0TINV (Bit 12) */
#define CTIMER_AUX0_TMRA0TINV_Msk (0x1000UL) /*!< TMRA0TINV (Bitfield-Mask: 0x01) */
#define CTIMER_AUX0_TMRA0NOSYNC_Pos (11UL) /*!< TMRA0NOSYNC (Bit 11) */
#define CTIMER_AUX0_TMRA0NOSYNC_Msk (0x800UL) /*!< TMRA0NOSYNC (Bitfield-Mask: 0x01) */
#define CTIMER_AUX0_TMRA0TRIG_Pos (7UL) /*!< TMRA0TRIG (Bit 7) */
#define CTIMER_AUX0_TMRA0TRIG_Msk (0x780UL) /*!< TMRA0TRIG (Bitfield-Mask: 0x0f) */
#define CTIMER_AUX0_TMRA0LMT_Pos (0UL) /*!< TMRA0LMT (Bit 0) */
#define CTIMER_AUX0_TMRA0LMT_Msk (0x7fUL) /*!< TMRA0LMT (Bitfield-Mask: 0x7f) */
/* ========================================================= TMR1 ========================================================== */
#define CTIMER_TMR1_CTTMRB1_Pos (16UL) /*!< CTTMRB1 (Bit 16) */
#define CTIMER_TMR1_CTTMRB1_Msk (0xffff0000UL) /*!< CTTMRB1 (Bitfield-Mask: 0xffff) */
#define CTIMER_TMR1_CTTMRA1_Pos (0UL) /*!< CTTMRA1 (Bit 0) */
#define CTIMER_TMR1_CTTMRA1_Msk (0xffffUL) /*!< CTTMRA1 (Bitfield-Mask: 0xffff) */
/* ======================================================== CMPRA1 ========================================================= */
#define CTIMER_CMPRA1_CMPR1A1_Pos (16UL) /*!< CMPR1A1 (Bit 16) */
#define CTIMER_CMPRA1_CMPR1A1_Msk (0xffff0000UL) /*!< CMPR1A1 (Bitfield-Mask: 0xffff) */
#define CTIMER_CMPRA1_CMPR0A1_Pos (0UL) /*!< CMPR0A1 (Bit 0) */
#define CTIMER_CMPRA1_CMPR0A1_Msk (0xffffUL) /*!< CMPR0A1 (Bitfield-Mask: 0xffff) */
/* ======================================================== CMPRB1 ========================================================= */
#define CTIMER_CMPRB1_CMPR1B1_Pos (16UL) /*!< CMPR1B1 (Bit 16) */
#define CTIMER_CMPRB1_CMPR1B1_Msk (0xffff0000UL) /*!< CMPR1B1 (Bitfield-Mask: 0xffff) */
#define CTIMER_CMPRB1_CMPR0B1_Pos (0UL) /*!< CMPR0B1 (Bit 0) */
#define CTIMER_CMPRB1_CMPR0B1_Msk (0xffffUL) /*!< CMPR0B1 (Bitfield-Mask: 0xffff) */
/* ========================================================= CTRL1 ========================================================= */
#define CTIMER_CTRL1_CTLINK1_Pos (31UL) /*!< CTLINK1 (Bit 31) */
#define CTIMER_CTRL1_CTLINK1_Msk (0x80000000UL) /*!< CTLINK1 (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL1_TMRB1POL_Pos (28UL) /*!< TMRB1POL (Bit 28) */
#define CTIMER_CTRL1_TMRB1POL_Msk (0x10000000UL) /*!< TMRB1POL (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL1_TMRB1CLR_Pos (27UL) /*!< TMRB1CLR (Bit 27) */
#define CTIMER_CTRL1_TMRB1CLR_Msk (0x8000000UL) /*!< TMRB1CLR (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL1_TMRB1IE1_Pos (26UL) /*!< TMRB1IE1 (Bit 26) */
#define CTIMER_CTRL1_TMRB1IE1_Msk (0x4000000UL) /*!< TMRB1IE1 (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL1_TMRB1IE0_Pos (25UL) /*!< TMRB1IE0 (Bit 25) */
#define CTIMER_CTRL1_TMRB1IE0_Msk (0x2000000UL) /*!< TMRB1IE0 (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL1_TMRB1FN_Pos (22UL) /*!< TMRB1FN (Bit 22) */
#define CTIMER_CTRL1_TMRB1FN_Msk (0x1c00000UL) /*!< TMRB1FN (Bitfield-Mask: 0x07) */
#define CTIMER_CTRL1_TMRB1CLK_Pos (17UL) /*!< TMRB1CLK (Bit 17) */
#define CTIMER_CTRL1_TMRB1CLK_Msk (0x3e0000UL) /*!< TMRB1CLK (Bitfield-Mask: 0x1f) */
#define CTIMER_CTRL1_TMRB1EN_Pos (16UL) /*!< TMRB1EN (Bit 16) */
#define CTIMER_CTRL1_TMRB1EN_Msk (0x10000UL) /*!< TMRB1EN (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL1_TMRA1POL_Pos (12UL) /*!< TMRA1POL (Bit 12) */
#define CTIMER_CTRL1_TMRA1POL_Msk (0x1000UL) /*!< TMRA1POL (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL1_TMRA1CLR_Pos (11UL) /*!< TMRA1CLR (Bit 11) */
#define CTIMER_CTRL1_TMRA1CLR_Msk (0x800UL) /*!< TMRA1CLR (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL1_TMRA1IE1_Pos (10UL) /*!< TMRA1IE1 (Bit 10) */
#define CTIMER_CTRL1_TMRA1IE1_Msk (0x400UL) /*!< TMRA1IE1 (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL1_TMRA1IE0_Pos (9UL) /*!< TMRA1IE0 (Bit 9) */
#define CTIMER_CTRL1_TMRA1IE0_Msk (0x200UL) /*!< TMRA1IE0 (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL1_TMRA1FN_Pos (6UL) /*!< TMRA1FN (Bit 6) */
#define CTIMER_CTRL1_TMRA1FN_Msk (0x1c0UL) /*!< TMRA1FN (Bitfield-Mask: 0x07) */
#define CTIMER_CTRL1_TMRA1CLK_Pos (1UL) /*!< TMRA1CLK (Bit 1) */
#define CTIMER_CTRL1_TMRA1CLK_Msk (0x3eUL) /*!< TMRA1CLK (Bitfield-Mask: 0x1f) */
#define CTIMER_CTRL1_TMRA1EN_Pos (0UL) /*!< TMRA1EN (Bit 0) */
#define CTIMER_CTRL1_TMRA1EN_Msk (0x1UL) /*!< TMRA1EN (Bitfield-Mask: 0x01) */
/* ======================================================= CMPRAUXA1 ======================================================= */
#define CTIMER_CMPRAUXA1_CMPR3A1_Pos (16UL) /*!< CMPR3A1 (Bit 16) */
#define CTIMER_CMPRAUXA1_CMPR3A1_Msk (0xffff0000UL) /*!< CMPR3A1 (Bitfield-Mask: 0xffff) */
#define CTIMER_CMPRAUXA1_CMPR2A1_Pos (0UL) /*!< CMPR2A1 (Bit 0) */
#define CTIMER_CMPRAUXA1_CMPR2A1_Msk (0xffffUL) /*!< CMPR2A1 (Bitfield-Mask: 0xffff) */
/* ======================================================= CMPRAUXB1 ======================================================= */
#define CTIMER_CMPRAUXB1_CMPR3B1_Pos (16UL) /*!< CMPR3B1 (Bit 16) */
#define CTIMER_CMPRAUXB1_CMPR3B1_Msk (0xffff0000UL) /*!< CMPR3B1 (Bitfield-Mask: 0xffff) */
#define CTIMER_CMPRAUXB1_CMPR2B1_Pos (0UL) /*!< CMPR2B1 (Bit 0) */
#define CTIMER_CMPRAUXB1_CMPR2B1_Msk (0xffffUL) /*!< CMPR2B1 (Bitfield-Mask: 0xffff) */
/* ========================================================= AUX1 ========================================================== */
#define CTIMER_AUX1_TMRB1EN23_Pos (30UL) /*!< TMRB1EN23 (Bit 30) */
#define CTIMER_AUX1_TMRB1EN23_Msk (0x40000000UL) /*!< TMRB1EN23 (Bitfield-Mask: 0x01) */
#define CTIMER_AUX1_TMRB1POL23_Pos (29UL) /*!< TMRB1POL23 (Bit 29) */
#define CTIMER_AUX1_TMRB1POL23_Msk (0x20000000UL) /*!< TMRB1POL23 (Bitfield-Mask: 0x01) */
#define CTIMER_AUX1_TMRB1TINV_Pos (28UL) /*!< TMRB1TINV (Bit 28) */
#define CTIMER_AUX1_TMRB1TINV_Msk (0x10000000UL) /*!< TMRB1TINV (Bitfield-Mask: 0x01) */
#define CTIMER_AUX1_TMRB1NOSYNC_Pos (27UL) /*!< TMRB1NOSYNC (Bit 27) */
#define CTIMER_AUX1_TMRB1NOSYNC_Msk (0x8000000UL) /*!< TMRB1NOSYNC (Bitfield-Mask: 0x01) */
#define CTIMER_AUX1_TMRB1TRIG_Pos (23UL) /*!< TMRB1TRIG (Bit 23) */
#define CTIMER_AUX1_TMRB1TRIG_Msk (0x7800000UL) /*!< TMRB1TRIG (Bitfield-Mask: 0x0f) */
#define CTIMER_AUX1_TMRB1LMT_Pos (16UL) /*!< TMRB1LMT (Bit 16) */
#define CTIMER_AUX1_TMRB1LMT_Msk (0x3f0000UL) /*!< TMRB1LMT (Bitfield-Mask: 0x3f) */
#define CTIMER_AUX1_TMRA1EN23_Pos (14UL) /*!< TMRA1EN23 (Bit 14) */
#define CTIMER_AUX1_TMRA1EN23_Msk (0x4000UL) /*!< TMRA1EN23 (Bitfield-Mask: 0x01) */
#define CTIMER_AUX1_TMRA1POL23_Pos (13UL) /*!< TMRA1POL23 (Bit 13) */
#define CTIMER_AUX1_TMRA1POL23_Msk (0x2000UL) /*!< TMRA1POL23 (Bitfield-Mask: 0x01) */
#define CTIMER_AUX1_TMRA1TINV_Pos (12UL) /*!< TMRA1TINV (Bit 12) */
#define CTIMER_AUX1_TMRA1TINV_Msk (0x1000UL) /*!< TMRA1TINV (Bitfield-Mask: 0x01) */
#define CTIMER_AUX1_TMRA1NOSYNC_Pos (11UL) /*!< TMRA1NOSYNC (Bit 11) */
#define CTIMER_AUX1_TMRA1NOSYNC_Msk (0x800UL) /*!< TMRA1NOSYNC (Bitfield-Mask: 0x01) */
#define CTIMER_AUX1_TMRA1TRIG_Pos (7UL) /*!< TMRA1TRIG (Bit 7) */
#define CTIMER_AUX1_TMRA1TRIG_Msk (0x780UL) /*!< TMRA1TRIG (Bitfield-Mask: 0x0f) */
#define CTIMER_AUX1_TMRA1LMT_Pos (0UL) /*!< TMRA1LMT (Bit 0) */
#define CTIMER_AUX1_TMRA1LMT_Msk (0x7fUL) /*!< TMRA1LMT (Bitfield-Mask: 0x7f) */
/* ========================================================= TMR2 ========================================================== */
#define CTIMER_TMR2_CTTMRB2_Pos (16UL) /*!< CTTMRB2 (Bit 16) */
#define CTIMER_TMR2_CTTMRB2_Msk (0xffff0000UL) /*!< CTTMRB2 (Bitfield-Mask: 0xffff) */
#define CTIMER_TMR2_CTTMRA2_Pos (0UL) /*!< CTTMRA2 (Bit 0) */
#define CTIMER_TMR2_CTTMRA2_Msk (0xffffUL) /*!< CTTMRA2 (Bitfield-Mask: 0xffff) */
/* ======================================================== CMPRA2 ========================================================= */
#define CTIMER_CMPRA2_CMPR1A2_Pos (16UL) /*!< CMPR1A2 (Bit 16) */
#define CTIMER_CMPRA2_CMPR1A2_Msk (0xffff0000UL) /*!< CMPR1A2 (Bitfield-Mask: 0xffff) */
#define CTIMER_CMPRA2_CMPR0A2_Pos (0UL) /*!< CMPR0A2 (Bit 0) */
#define CTIMER_CMPRA2_CMPR0A2_Msk (0xffffUL) /*!< CMPR0A2 (Bitfield-Mask: 0xffff) */
/* ======================================================== CMPRB2 ========================================================= */
#define CTIMER_CMPRB2_CMPR1B2_Pos (16UL) /*!< CMPR1B2 (Bit 16) */
#define CTIMER_CMPRB2_CMPR1B2_Msk (0xffff0000UL) /*!< CMPR1B2 (Bitfield-Mask: 0xffff) */
#define CTIMER_CMPRB2_CMPR0B2_Pos (0UL) /*!< CMPR0B2 (Bit 0) */
#define CTIMER_CMPRB2_CMPR0B2_Msk (0xffffUL) /*!< CMPR0B2 (Bitfield-Mask: 0xffff) */
/* ========================================================= CTRL2 ========================================================= */
#define CTIMER_CTRL2_CTLINK2_Pos (31UL) /*!< CTLINK2 (Bit 31) */
#define CTIMER_CTRL2_CTLINK2_Msk (0x80000000UL) /*!< CTLINK2 (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL2_TMRB2POL_Pos (28UL) /*!< TMRB2POL (Bit 28) */
#define CTIMER_CTRL2_TMRB2POL_Msk (0x10000000UL) /*!< TMRB2POL (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL2_TMRB2CLR_Pos (27UL) /*!< TMRB2CLR (Bit 27) */
#define CTIMER_CTRL2_TMRB2CLR_Msk (0x8000000UL) /*!< TMRB2CLR (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL2_TMRB2IE1_Pos (26UL) /*!< TMRB2IE1 (Bit 26) */
#define CTIMER_CTRL2_TMRB2IE1_Msk (0x4000000UL) /*!< TMRB2IE1 (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL2_TMRB2IE0_Pos (25UL) /*!< TMRB2IE0 (Bit 25) */
#define CTIMER_CTRL2_TMRB2IE0_Msk (0x2000000UL) /*!< TMRB2IE0 (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL2_TMRB2FN_Pos (22UL) /*!< TMRB2FN (Bit 22) */
#define CTIMER_CTRL2_TMRB2FN_Msk (0x1c00000UL) /*!< TMRB2FN (Bitfield-Mask: 0x07) */
#define CTIMER_CTRL2_TMRB2CLK_Pos (17UL) /*!< TMRB2CLK (Bit 17) */
#define CTIMER_CTRL2_TMRB2CLK_Msk (0x3e0000UL) /*!< TMRB2CLK (Bitfield-Mask: 0x1f) */
#define CTIMER_CTRL2_TMRB2EN_Pos (16UL) /*!< TMRB2EN (Bit 16) */
#define CTIMER_CTRL2_TMRB2EN_Msk (0x10000UL) /*!< TMRB2EN (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL2_TMRA2POL_Pos (12UL) /*!< TMRA2POL (Bit 12) */
#define CTIMER_CTRL2_TMRA2POL_Msk (0x1000UL) /*!< TMRA2POL (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL2_TMRA2CLR_Pos (11UL) /*!< TMRA2CLR (Bit 11) */
#define CTIMER_CTRL2_TMRA2CLR_Msk (0x800UL) /*!< TMRA2CLR (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL2_TMRA2IE1_Pos (10UL) /*!< TMRA2IE1 (Bit 10) */
#define CTIMER_CTRL2_TMRA2IE1_Msk (0x400UL) /*!< TMRA2IE1 (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL2_TMRA2IE0_Pos (9UL) /*!< TMRA2IE0 (Bit 9) */
#define CTIMER_CTRL2_TMRA2IE0_Msk (0x200UL) /*!< TMRA2IE0 (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL2_TMRA2FN_Pos (6UL) /*!< TMRA2FN (Bit 6) */
#define CTIMER_CTRL2_TMRA2FN_Msk (0x1c0UL) /*!< TMRA2FN (Bitfield-Mask: 0x07) */
#define CTIMER_CTRL2_TMRA2CLK_Pos (1UL) /*!< TMRA2CLK (Bit 1) */
#define CTIMER_CTRL2_TMRA2CLK_Msk (0x3eUL) /*!< TMRA2CLK (Bitfield-Mask: 0x1f) */
#define CTIMER_CTRL2_TMRA2EN_Pos (0UL) /*!< TMRA2EN (Bit 0) */
#define CTIMER_CTRL2_TMRA2EN_Msk (0x1UL) /*!< TMRA2EN (Bitfield-Mask: 0x01) */
/* ======================================================= CMPRAUXA2 ======================================================= */
#define CTIMER_CMPRAUXA2_CMPR3A2_Pos (16UL) /*!< CMPR3A2 (Bit 16) */
#define CTIMER_CMPRAUXA2_CMPR3A2_Msk (0xffff0000UL) /*!< CMPR3A2 (Bitfield-Mask: 0xffff) */
#define CTIMER_CMPRAUXA2_CMPR2A2_Pos (0UL) /*!< CMPR2A2 (Bit 0) */
#define CTIMER_CMPRAUXA2_CMPR2A2_Msk (0xffffUL) /*!< CMPR2A2 (Bitfield-Mask: 0xffff) */
/* ======================================================= CMPRAUXB2 ======================================================= */
#define CTIMER_CMPRAUXB2_CMPR3B2_Pos (16UL) /*!< CMPR3B2 (Bit 16) */
#define CTIMER_CMPRAUXB2_CMPR3B2_Msk (0xffff0000UL) /*!< CMPR3B2 (Bitfield-Mask: 0xffff) */
#define CTIMER_CMPRAUXB2_CMPR2B2_Pos (0UL) /*!< CMPR2B2 (Bit 0) */
#define CTIMER_CMPRAUXB2_CMPR2B2_Msk (0xffffUL) /*!< CMPR2B2 (Bitfield-Mask: 0xffff) */
/* ========================================================= AUX2 ========================================================== */
#define CTIMER_AUX2_TMRB2EN23_Pos (30UL) /*!< TMRB2EN23 (Bit 30) */
#define CTIMER_AUX2_TMRB2EN23_Msk (0x40000000UL) /*!< TMRB2EN23 (Bitfield-Mask: 0x01) */
#define CTIMER_AUX2_TMRB2POL23_Pos (29UL) /*!< TMRB2POL23 (Bit 29) */
#define CTIMER_AUX2_TMRB2POL23_Msk (0x20000000UL) /*!< TMRB2POL23 (Bitfield-Mask: 0x01) */
#define CTIMER_AUX2_TMRB2TINV_Pos (28UL) /*!< TMRB2TINV (Bit 28) */
#define CTIMER_AUX2_TMRB2TINV_Msk (0x10000000UL) /*!< TMRB2TINV (Bitfield-Mask: 0x01) */
#define CTIMER_AUX2_TMRB2NOSYNC_Pos (27UL) /*!< TMRB2NOSYNC (Bit 27) */
#define CTIMER_AUX2_TMRB2NOSYNC_Msk (0x8000000UL) /*!< TMRB2NOSYNC (Bitfield-Mask: 0x01) */
#define CTIMER_AUX2_TMRB2TRIG_Pos (23UL) /*!< TMRB2TRIG (Bit 23) */
#define CTIMER_AUX2_TMRB2TRIG_Msk (0x7800000UL) /*!< TMRB2TRIG (Bitfield-Mask: 0x0f) */
#define CTIMER_AUX2_TMRB2LMT_Pos (16UL) /*!< TMRB2LMT (Bit 16) */
#define CTIMER_AUX2_TMRB2LMT_Msk (0x3f0000UL) /*!< TMRB2LMT (Bitfield-Mask: 0x3f) */
#define CTIMER_AUX2_TMRA2EN23_Pos (14UL) /*!< TMRA2EN23 (Bit 14) */
#define CTIMER_AUX2_TMRA2EN23_Msk (0x4000UL) /*!< TMRA2EN23 (Bitfield-Mask: 0x01) */
#define CTIMER_AUX2_TMRA2POL23_Pos (13UL) /*!< TMRA2POL23 (Bit 13) */
#define CTIMER_AUX2_TMRA2POL23_Msk (0x2000UL) /*!< TMRA2POL23 (Bitfield-Mask: 0x01) */
#define CTIMER_AUX2_TMRA2TINV_Pos (12UL) /*!< TMRA2TINV (Bit 12) */
#define CTIMER_AUX2_TMRA2TINV_Msk (0x1000UL) /*!< TMRA2TINV (Bitfield-Mask: 0x01) */
#define CTIMER_AUX2_TMRA2NOSYNC_Pos (11UL) /*!< TMRA2NOSYNC (Bit 11) */
#define CTIMER_AUX2_TMRA2NOSYNC_Msk (0x800UL) /*!< TMRA2NOSYNC (Bitfield-Mask: 0x01) */
#define CTIMER_AUX2_TMRA2TRIG_Pos (7UL) /*!< TMRA2TRIG (Bit 7) */
#define CTIMER_AUX2_TMRA2TRIG_Msk (0x780UL) /*!< TMRA2TRIG (Bitfield-Mask: 0x0f) */
#define CTIMER_AUX2_TMRA2LMT_Pos (0UL) /*!< TMRA2LMT (Bit 0) */
#define CTIMER_AUX2_TMRA2LMT_Msk (0x7fUL) /*!< TMRA2LMT (Bitfield-Mask: 0x7f) */
/* ========================================================= TMR3 ========================================================== */
#define CTIMER_TMR3_CTTMRB3_Pos (16UL) /*!< CTTMRB3 (Bit 16) */
#define CTIMER_TMR3_CTTMRB3_Msk (0xffff0000UL) /*!< CTTMRB3 (Bitfield-Mask: 0xffff) */
#define CTIMER_TMR3_CTTMRA3_Pos (0UL) /*!< CTTMRA3 (Bit 0) */
#define CTIMER_TMR3_CTTMRA3_Msk (0xffffUL) /*!< CTTMRA3 (Bitfield-Mask: 0xffff) */
/* ======================================================== CMPRA3 ========================================================= */
#define CTIMER_CMPRA3_CMPR1A3_Pos (16UL) /*!< CMPR1A3 (Bit 16) */
#define CTIMER_CMPRA3_CMPR1A3_Msk (0xffff0000UL) /*!< CMPR1A3 (Bitfield-Mask: 0xffff) */
#define CTIMER_CMPRA3_CMPR0A3_Pos (0UL) /*!< CMPR0A3 (Bit 0) */
#define CTIMER_CMPRA3_CMPR0A3_Msk (0xffffUL) /*!< CMPR0A3 (Bitfield-Mask: 0xffff) */
/* ======================================================== CMPRB3 ========================================================= */
#define CTIMER_CMPRB3_CMPR1B3_Pos (16UL) /*!< CMPR1B3 (Bit 16) */
#define CTIMER_CMPRB3_CMPR1B3_Msk (0xffff0000UL) /*!< CMPR1B3 (Bitfield-Mask: 0xffff) */
#define CTIMER_CMPRB3_CMPR0B3_Pos (0UL) /*!< CMPR0B3 (Bit 0) */
#define CTIMER_CMPRB3_CMPR0B3_Msk (0xffffUL) /*!< CMPR0B3 (Bitfield-Mask: 0xffff) */
/* ========================================================= CTRL3 ========================================================= */
#define CTIMER_CTRL3_CTLINK3_Pos (31UL) /*!< CTLINK3 (Bit 31) */
#define CTIMER_CTRL3_CTLINK3_Msk (0x80000000UL) /*!< CTLINK3 (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL3_TMRB3POL_Pos (28UL) /*!< TMRB3POL (Bit 28) */
#define CTIMER_CTRL3_TMRB3POL_Msk (0x10000000UL) /*!< TMRB3POL (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL3_TMRB3CLR_Pos (27UL) /*!< TMRB3CLR (Bit 27) */
#define CTIMER_CTRL3_TMRB3CLR_Msk (0x8000000UL) /*!< TMRB3CLR (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL3_TMRB3IE1_Pos (26UL) /*!< TMRB3IE1 (Bit 26) */
#define CTIMER_CTRL3_TMRB3IE1_Msk (0x4000000UL) /*!< TMRB3IE1 (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL3_TMRB3IE0_Pos (25UL) /*!< TMRB3IE0 (Bit 25) */
#define CTIMER_CTRL3_TMRB3IE0_Msk (0x2000000UL) /*!< TMRB3IE0 (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL3_TMRB3FN_Pos (22UL) /*!< TMRB3FN (Bit 22) */
#define CTIMER_CTRL3_TMRB3FN_Msk (0x1c00000UL) /*!< TMRB3FN (Bitfield-Mask: 0x07) */
#define CTIMER_CTRL3_TMRB3CLK_Pos (17UL) /*!< TMRB3CLK (Bit 17) */
#define CTIMER_CTRL3_TMRB3CLK_Msk (0x3e0000UL) /*!< TMRB3CLK (Bitfield-Mask: 0x1f) */
#define CTIMER_CTRL3_TMRB3EN_Pos (16UL) /*!< TMRB3EN (Bit 16) */
#define CTIMER_CTRL3_TMRB3EN_Msk (0x10000UL) /*!< TMRB3EN (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL3_ADCEN_Pos (15UL) /*!< ADCEN (Bit 15) */
#define CTIMER_CTRL3_ADCEN_Msk (0x8000UL) /*!< ADCEN (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL3_TMRA3POL_Pos (12UL) /*!< TMRA3POL (Bit 12) */
#define CTIMER_CTRL3_TMRA3POL_Msk (0x1000UL) /*!< TMRA3POL (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL3_TMRA3CLR_Pos (11UL) /*!< TMRA3CLR (Bit 11) */
#define CTIMER_CTRL3_TMRA3CLR_Msk (0x800UL) /*!< TMRA3CLR (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL3_TMRA3IE1_Pos (10UL) /*!< TMRA3IE1 (Bit 10) */
#define CTIMER_CTRL3_TMRA3IE1_Msk (0x400UL) /*!< TMRA3IE1 (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL3_TMRA3IE0_Pos (9UL) /*!< TMRA3IE0 (Bit 9) */
#define CTIMER_CTRL3_TMRA3IE0_Msk (0x200UL) /*!< TMRA3IE0 (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL3_TMRA3FN_Pos (6UL) /*!< TMRA3FN (Bit 6) */
#define CTIMER_CTRL3_TMRA3FN_Msk (0x1c0UL) /*!< TMRA3FN (Bitfield-Mask: 0x07) */
#define CTIMER_CTRL3_TMRA3CLK_Pos (1UL) /*!< TMRA3CLK (Bit 1) */
#define CTIMER_CTRL3_TMRA3CLK_Msk (0x3eUL) /*!< TMRA3CLK (Bitfield-Mask: 0x1f) */
#define CTIMER_CTRL3_TMRA3EN_Pos (0UL) /*!< TMRA3EN (Bit 0) */
#define CTIMER_CTRL3_TMRA3EN_Msk (0x1UL) /*!< TMRA3EN (Bitfield-Mask: 0x01) */
/* ======================================================= CMPRAUXA3 ======================================================= */
#define CTIMER_CMPRAUXA3_CMPR3A3_Pos (16UL) /*!< CMPR3A3 (Bit 16) */
#define CTIMER_CMPRAUXA3_CMPR3A3_Msk (0xffff0000UL) /*!< CMPR3A3 (Bitfield-Mask: 0xffff) */
#define CTIMER_CMPRAUXA3_CMPR2A3_Pos (0UL) /*!< CMPR2A3 (Bit 0) */
#define CTIMER_CMPRAUXA3_CMPR2A3_Msk (0xffffUL) /*!< CMPR2A3 (Bitfield-Mask: 0xffff) */
/* ======================================================= CMPRAUXB3 ======================================================= */
#define CTIMER_CMPRAUXB3_CMPR3B3_Pos (16UL) /*!< CMPR3B3 (Bit 16) */
#define CTIMER_CMPRAUXB3_CMPR3B3_Msk (0xffff0000UL) /*!< CMPR3B3 (Bitfield-Mask: 0xffff) */
#define CTIMER_CMPRAUXB3_CMPR2B3_Pos (0UL) /*!< CMPR2B3 (Bit 0) */
#define CTIMER_CMPRAUXB3_CMPR2B3_Msk (0xffffUL) /*!< CMPR2B3 (Bitfield-Mask: 0xffff) */
/* ========================================================= AUX3 ========================================================== */
#define CTIMER_AUX3_TMRB3EN23_Pos (30UL) /*!< TMRB3EN23 (Bit 30) */
#define CTIMER_AUX3_TMRB3EN23_Msk (0x40000000UL) /*!< TMRB3EN23 (Bitfield-Mask: 0x01) */
#define CTIMER_AUX3_TMRB3POL23_Pos (29UL) /*!< TMRB3POL23 (Bit 29) */
#define CTIMER_AUX3_TMRB3POL23_Msk (0x20000000UL) /*!< TMRB3POL23 (Bitfield-Mask: 0x01) */
#define CTIMER_AUX3_TMRB3TINV_Pos (28UL) /*!< TMRB3TINV (Bit 28) */
#define CTIMER_AUX3_TMRB3TINV_Msk (0x10000000UL) /*!< TMRB3TINV (Bitfield-Mask: 0x01) */
#define CTIMER_AUX3_TMRB3NOSYNC_Pos (27UL) /*!< TMRB3NOSYNC (Bit 27) */
#define CTIMER_AUX3_TMRB3NOSYNC_Msk (0x8000000UL) /*!< TMRB3NOSYNC (Bitfield-Mask: 0x01) */
#define CTIMER_AUX3_TMRB3TRIG_Pos (23UL) /*!< TMRB3TRIG (Bit 23) */
#define CTIMER_AUX3_TMRB3TRIG_Msk (0x7800000UL) /*!< TMRB3TRIG (Bitfield-Mask: 0x0f) */
#define CTIMER_AUX3_TMRB3LMT_Pos (16UL) /*!< TMRB3LMT (Bit 16) */
#define CTIMER_AUX3_TMRB3LMT_Msk (0x3f0000UL) /*!< TMRB3LMT (Bitfield-Mask: 0x3f) */
#define CTIMER_AUX3_TMRA3EN23_Pos (14UL) /*!< TMRA3EN23 (Bit 14) */
#define CTIMER_AUX3_TMRA3EN23_Msk (0x4000UL) /*!< TMRA3EN23 (Bitfield-Mask: 0x01) */
#define CTIMER_AUX3_TMRA3POL23_Pos (13UL) /*!< TMRA3POL23 (Bit 13) */
#define CTIMER_AUX3_TMRA3POL23_Msk (0x2000UL) /*!< TMRA3POL23 (Bitfield-Mask: 0x01) */
#define CTIMER_AUX3_TMRA3TINV_Pos (12UL) /*!< TMRA3TINV (Bit 12) */
#define CTIMER_AUX3_TMRA3TINV_Msk (0x1000UL) /*!< TMRA3TINV (Bitfield-Mask: 0x01) */
#define CTIMER_AUX3_TMRA3NOSYNC_Pos (11UL) /*!< TMRA3NOSYNC (Bit 11) */
#define CTIMER_AUX3_TMRA3NOSYNC_Msk (0x800UL) /*!< TMRA3NOSYNC (Bitfield-Mask: 0x01) */
#define CTIMER_AUX3_TMRA3TRIG_Pos (7UL) /*!< TMRA3TRIG (Bit 7) */
#define CTIMER_AUX3_TMRA3TRIG_Msk (0x780UL) /*!< TMRA3TRIG (Bitfield-Mask: 0x0f) */
#define CTIMER_AUX3_TMRA3LMT_Pos (0UL) /*!< TMRA3LMT (Bit 0) */
#define CTIMER_AUX3_TMRA3LMT_Msk (0x7fUL) /*!< TMRA3LMT (Bitfield-Mask: 0x7f) */
/* ========================================================= TMR4 ========================================================== */
#define CTIMER_TMR4_CTTMRB4_Pos (16UL) /*!< CTTMRB4 (Bit 16) */
#define CTIMER_TMR4_CTTMRB4_Msk (0xffff0000UL) /*!< CTTMRB4 (Bitfield-Mask: 0xffff) */
#define CTIMER_TMR4_CTTMRA4_Pos (0UL) /*!< CTTMRA4 (Bit 0) */
#define CTIMER_TMR4_CTTMRA4_Msk (0xffffUL) /*!< CTTMRA4 (Bitfield-Mask: 0xffff) */
/* ======================================================== CMPRA4 ========================================================= */
#define CTIMER_CMPRA4_CMPR1A4_Pos (16UL) /*!< CMPR1A4 (Bit 16) */
#define CTIMER_CMPRA4_CMPR1A4_Msk (0xffff0000UL) /*!< CMPR1A4 (Bitfield-Mask: 0xffff) */
#define CTIMER_CMPRA4_CMPR0A4_Pos (0UL) /*!< CMPR0A4 (Bit 0) */
#define CTIMER_CMPRA4_CMPR0A4_Msk (0xffffUL) /*!< CMPR0A4 (Bitfield-Mask: 0xffff) */
/* ======================================================== CMPRB4 ========================================================= */
#define CTIMER_CMPRB4_CMPR1B4_Pos (16UL) /*!< CMPR1B4 (Bit 16) */
#define CTIMER_CMPRB4_CMPR1B4_Msk (0xffff0000UL) /*!< CMPR1B4 (Bitfield-Mask: 0xffff) */
#define CTIMER_CMPRB4_CMPR0B4_Pos (0UL) /*!< CMPR0B4 (Bit 0) */
#define CTIMER_CMPRB4_CMPR0B4_Msk (0xffffUL) /*!< CMPR0B4 (Bitfield-Mask: 0xffff) */
/* ========================================================= CTRL4 ========================================================= */
#define CTIMER_CTRL4_CTLINK4_Pos (31UL) /*!< CTLINK4 (Bit 31) */
#define CTIMER_CTRL4_CTLINK4_Msk (0x80000000UL) /*!< CTLINK4 (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL4_TMRB4POL_Pos (28UL) /*!< TMRB4POL (Bit 28) */
#define CTIMER_CTRL4_TMRB4POL_Msk (0x10000000UL) /*!< TMRB4POL (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL4_TMRB4CLR_Pos (27UL) /*!< TMRB4CLR (Bit 27) */
#define CTIMER_CTRL4_TMRB4CLR_Msk (0x8000000UL) /*!< TMRB4CLR (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL4_TMRB4IE1_Pos (26UL) /*!< TMRB4IE1 (Bit 26) */
#define CTIMER_CTRL4_TMRB4IE1_Msk (0x4000000UL) /*!< TMRB4IE1 (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL4_TMRB4IE0_Pos (25UL) /*!< TMRB4IE0 (Bit 25) */
#define CTIMER_CTRL4_TMRB4IE0_Msk (0x2000000UL) /*!< TMRB4IE0 (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL4_TMRB4FN_Pos (22UL) /*!< TMRB4FN (Bit 22) */
#define CTIMER_CTRL4_TMRB4FN_Msk (0x1c00000UL) /*!< TMRB4FN (Bitfield-Mask: 0x07) */
#define CTIMER_CTRL4_TMRB4CLK_Pos (17UL) /*!< TMRB4CLK (Bit 17) */
#define CTIMER_CTRL4_TMRB4CLK_Msk (0x3e0000UL) /*!< TMRB4CLK (Bitfield-Mask: 0x1f) */
#define CTIMER_CTRL4_TMRB4EN_Pos (16UL) /*!< TMRB4EN (Bit 16) */
#define CTIMER_CTRL4_TMRB4EN_Msk (0x10000UL) /*!< TMRB4EN (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL4_TMRA4POL_Pos (12UL) /*!< TMRA4POL (Bit 12) */
#define CTIMER_CTRL4_TMRA4POL_Msk (0x1000UL) /*!< TMRA4POL (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL4_TMRA4CLR_Pos (11UL) /*!< TMRA4CLR (Bit 11) */
#define CTIMER_CTRL4_TMRA4CLR_Msk (0x800UL) /*!< TMRA4CLR (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL4_TMRA4IE1_Pos (10UL) /*!< TMRA4IE1 (Bit 10) */
#define CTIMER_CTRL4_TMRA4IE1_Msk (0x400UL) /*!< TMRA4IE1 (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL4_TMRA4IE0_Pos (9UL) /*!< TMRA4IE0 (Bit 9) */
#define CTIMER_CTRL4_TMRA4IE0_Msk (0x200UL) /*!< TMRA4IE0 (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL4_TMRA4FN_Pos (6UL) /*!< TMRA4FN (Bit 6) */
#define CTIMER_CTRL4_TMRA4FN_Msk (0x1c0UL) /*!< TMRA4FN (Bitfield-Mask: 0x07) */
#define CTIMER_CTRL4_TMRA4CLK_Pos (1UL) /*!< TMRA4CLK (Bit 1) */
#define CTIMER_CTRL4_TMRA4CLK_Msk (0x3eUL) /*!< TMRA4CLK (Bitfield-Mask: 0x1f) */
#define CTIMER_CTRL4_TMRA4EN_Pos (0UL) /*!< TMRA4EN (Bit 0) */
#define CTIMER_CTRL4_TMRA4EN_Msk (0x1UL) /*!< TMRA4EN (Bitfield-Mask: 0x01) */
/* ======================================================= CMPRAUXA4 ======================================================= */
#define CTIMER_CMPRAUXA4_CMPR3A4_Pos (16UL) /*!< CMPR3A4 (Bit 16) */
#define CTIMER_CMPRAUXA4_CMPR3A4_Msk (0xffff0000UL) /*!< CMPR3A4 (Bitfield-Mask: 0xffff) */
#define CTIMER_CMPRAUXA4_CMPR2A4_Pos (0UL) /*!< CMPR2A4 (Bit 0) */
#define CTIMER_CMPRAUXA4_CMPR2A4_Msk (0xffffUL) /*!< CMPR2A4 (Bitfield-Mask: 0xffff) */
/* ======================================================= CMPRAUXB4 ======================================================= */
#define CTIMER_CMPRAUXB4_CMPR3B4_Pos (16UL) /*!< CMPR3B4 (Bit 16) */
#define CTIMER_CMPRAUXB4_CMPR3B4_Msk (0xffff0000UL) /*!< CMPR3B4 (Bitfield-Mask: 0xffff) */
#define CTIMER_CMPRAUXB4_CMPR2B4_Pos (0UL) /*!< CMPR2B4 (Bit 0) */
#define CTIMER_CMPRAUXB4_CMPR2B4_Msk (0xffffUL) /*!< CMPR2B4 (Bitfield-Mask: 0xffff) */
/* ========================================================= AUX4 ========================================================== */
#define CTIMER_AUX4_TMRB4EN23_Pos (30UL) /*!< TMRB4EN23 (Bit 30) */
#define CTIMER_AUX4_TMRB4EN23_Msk (0x40000000UL) /*!< TMRB4EN23 (Bitfield-Mask: 0x01) */
#define CTIMER_AUX4_TMRB4POL23_Pos (29UL) /*!< TMRB4POL23 (Bit 29) */
#define CTIMER_AUX4_TMRB4POL23_Msk (0x20000000UL) /*!< TMRB4POL23 (Bitfield-Mask: 0x01) */
#define CTIMER_AUX4_TMRB4TINV_Pos (28UL) /*!< TMRB4TINV (Bit 28) */
#define CTIMER_AUX4_TMRB4TINV_Msk (0x10000000UL) /*!< TMRB4TINV (Bitfield-Mask: 0x01) */
#define CTIMER_AUX4_TMRB4NOSYNC_Pos (27UL) /*!< TMRB4NOSYNC (Bit 27) */
#define CTIMER_AUX4_TMRB4NOSYNC_Msk (0x8000000UL) /*!< TMRB4NOSYNC (Bitfield-Mask: 0x01) */
#define CTIMER_AUX4_TMRB4TRIG_Pos (23UL) /*!< TMRB4TRIG (Bit 23) */
#define CTIMER_AUX4_TMRB4TRIG_Msk (0x7800000UL) /*!< TMRB4TRIG (Bitfield-Mask: 0x0f) */
#define CTIMER_AUX4_TMRB4LMT_Pos (16UL) /*!< TMRB4LMT (Bit 16) */
#define CTIMER_AUX4_TMRB4LMT_Msk (0x3f0000UL) /*!< TMRB4LMT (Bitfield-Mask: 0x3f) */
#define CTIMER_AUX4_TMRA4EN23_Pos (14UL) /*!< TMRA4EN23 (Bit 14) */
#define CTIMER_AUX4_TMRA4EN23_Msk (0x4000UL) /*!< TMRA4EN23 (Bitfield-Mask: 0x01) */
#define CTIMER_AUX4_TMRA4POL23_Pos (13UL) /*!< TMRA4POL23 (Bit 13) */
#define CTIMER_AUX4_TMRA4POL23_Msk (0x2000UL) /*!< TMRA4POL23 (Bitfield-Mask: 0x01) */
#define CTIMER_AUX4_TMRA4TINV_Pos (12UL) /*!< TMRA4TINV (Bit 12) */
#define CTIMER_AUX4_TMRA4TINV_Msk (0x1000UL) /*!< TMRA4TINV (Bitfield-Mask: 0x01) */
#define CTIMER_AUX4_TMRA4NOSYNC_Pos (11UL) /*!< TMRA4NOSYNC (Bit 11) */
#define CTIMER_AUX4_TMRA4NOSYNC_Msk (0x800UL) /*!< TMRA4NOSYNC (Bitfield-Mask: 0x01) */
#define CTIMER_AUX4_TMRA4TRIG_Pos (7UL) /*!< TMRA4TRIG (Bit 7) */
#define CTIMER_AUX4_TMRA4TRIG_Msk (0x780UL) /*!< TMRA4TRIG (Bitfield-Mask: 0x0f) */
#define CTIMER_AUX4_TMRA4LMT_Pos (0UL) /*!< TMRA4LMT (Bit 0) */
#define CTIMER_AUX4_TMRA4LMT_Msk (0x7fUL) /*!< TMRA4LMT (Bitfield-Mask: 0x7f) */
/* ========================================================= TMR5 ========================================================== */
#define CTIMER_TMR5_CTTMRB5_Pos (16UL) /*!< CTTMRB5 (Bit 16) */
#define CTIMER_TMR5_CTTMRB5_Msk (0xffff0000UL) /*!< CTTMRB5 (Bitfield-Mask: 0xffff) */
#define CTIMER_TMR5_CTTMRA5_Pos (0UL) /*!< CTTMRA5 (Bit 0) */
#define CTIMER_TMR5_CTTMRA5_Msk (0xffffUL) /*!< CTTMRA5 (Bitfield-Mask: 0xffff) */
/* ======================================================== CMPRA5 ========================================================= */
#define CTIMER_CMPRA5_CMPR1A5_Pos (16UL) /*!< CMPR1A5 (Bit 16) */
#define CTIMER_CMPRA5_CMPR1A5_Msk (0xffff0000UL) /*!< CMPR1A5 (Bitfield-Mask: 0xffff) */
#define CTIMER_CMPRA5_CMPR0A5_Pos (0UL) /*!< CMPR0A5 (Bit 0) */
#define CTIMER_CMPRA5_CMPR0A5_Msk (0xffffUL) /*!< CMPR0A5 (Bitfield-Mask: 0xffff) */
/* ======================================================== CMPRB5 ========================================================= */
#define CTIMER_CMPRB5_CMPR1B5_Pos (16UL) /*!< CMPR1B5 (Bit 16) */
#define CTIMER_CMPRB5_CMPR1B5_Msk (0xffff0000UL) /*!< CMPR1B5 (Bitfield-Mask: 0xffff) */
#define CTIMER_CMPRB5_CMPR0B5_Pos (0UL) /*!< CMPR0B5 (Bit 0) */
#define CTIMER_CMPRB5_CMPR0B5_Msk (0xffffUL) /*!< CMPR0B5 (Bitfield-Mask: 0xffff) */
/* ========================================================= CTRL5 ========================================================= */
#define CTIMER_CTRL5_CTLINK5_Pos (31UL) /*!< CTLINK5 (Bit 31) */
#define CTIMER_CTRL5_CTLINK5_Msk (0x80000000UL) /*!< CTLINK5 (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL5_TMRB5POL_Pos (28UL) /*!< TMRB5POL (Bit 28) */
#define CTIMER_CTRL5_TMRB5POL_Msk (0x10000000UL) /*!< TMRB5POL (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL5_TMRB5CLR_Pos (27UL) /*!< TMRB5CLR (Bit 27) */
#define CTIMER_CTRL5_TMRB5CLR_Msk (0x8000000UL) /*!< TMRB5CLR (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL5_TMRB5IE1_Pos (26UL) /*!< TMRB5IE1 (Bit 26) */
#define CTIMER_CTRL5_TMRB5IE1_Msk (0x4000000UL) /*!< TMRB5IE1 (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL5_TMRB5IE0_Pos (25UL) /*!< TMRB5IE0 (Bit 25) */
#define CTIMER_CTRL5_TMRB5IE0_Msk (0x2000000UL) /*!< TMRB5IE0 (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL5_TMRB5FN_Pos (22UL) /*!< TMRB5FN (Bit 22) */
#define CTIMER_CTRL5_TMRB5FN_Msk (0x1c00000UL) /*!< TMRB5FN (Bitfield-Mask: 0x07) */
#define CTIMER_CTRL5_TMRB5CLK_Pos (17UL) /*!< TMRB5CLK (Bit 17) */
#define CTIMER_CTRL5_TMRB5CLK_Msk (0x3e0000UL) /*!< TMRB5CLK (Bitfield-Mask: 0x1f) */
#define CTIMER_CTRL5_TMRB5EN_Pos (16UL) /*!< TMRB5EN (Bit 16) */
#define CTIMER_CTRL5_TMRB5EN_Msk (0x10000UL) /*!< TMRB5EN (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL5_TMRA5POL_Pos (12UL) /*!< TMRA5POL (Bit 12) */
#define CTIMER_CTRL5_TMRA5POL_Msk (0x1000UL) /*!< TMRA5POL (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL5_TMRA5CLR_Pos (11UL) /*!< TMRA5CLR (Bit 11) */
#define CTIMER_CTRL5_TMRA5CLR_Msk (0x800UL) /*!< TMRA5CLR (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL5_TMRA5IE1_Pos (10UL) /*!< TMRA5IE1 (Bit 10) */
#define CTIMER_CTRL5_TMRA5IE1_Msk (0x400UL) /*!< TMRA5IE1 (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL5_TMRA5IE0_Pos (9UL) /*!< TMRA5IE0 (Bit 9) */
#define CTIMER_CTRL5_TMRA5IE0_Msk (0x200UL) /*!< TMRA5IE0 (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL5_TMRA5FN_Pos (6UL) /*!< TMRA5FN (Bit 6) */
#define CTIMER_CTRL5_TMRA5FN_Msk (0x1c0UL) /*!< TMRA5FN (Bitfield-Mask: 0x07) */
#define CTIMER_CTRL5_TMRA5CLK_Pos (1UL) /*!< TMRA5CLK (Bit 1) */
#define CTIMER_CTRL5_TMRA5CLK_Msk (0x3eUL) /*!< TMRA5CLK (Bitfield-Mask: 0x1f) */
#define CTIMER_CTRL5_TMRA5EN_Pos (0UL) /*!< TMRA5EN (Bit 0) */
#define CTIMER_CTRL5_TMRA5EN_Msk (0x1UL) /*!< TMRA5EN (Bitfield-Mask: 0x01) */
/* ======================================================= CMPRAUXA5 ======================================================= */
#define CTIMER_CMPRAUXA5_CMPR3A5_Pos (16UL) /*!< CMPR3A5 (Bit 16) */
#define CTIMER_CMPRAUXA5_CMPR3A5_Msk (0xffff0000UL) /*!< CMPR3A5 (Bitfield-Mask: 0xffff) */
#define CTIMER_CMPRAUXA5_CMPR2A5_Pos (0UL) /*!< CMPR2A5 (Bit 0) */
#define CTIMER_CMPRAUXA5_CMPR2A5_Msk (0xffffUL) /*!< CMPR2A5 (Bitfield-Mask: 0xffff) */
/* ======================================================= CMPRAUXB5 ======================================================= */
#define CTIMER_CMPRAUXB5_CMPR3B5_Pos (16UL) /*!< CMPR3B5 (Bit 16) */
#define CTIMER_CMPRAUXB5_CMPR3B5_Msk (0xffff0000UL) /*!< CMPR3B5 (Bitfield-Mask: 0xffff) */
#define CTIMER_CMPRAUXB5_CMPR2B5_Pos (0UL) /*!< CMPR2B5 (Bit 0) */
#define CTIMER_CMPRAUXB5_CMPR2B5_Msk (0xffffUL) /*!< CMPR2B5 (Bitfield-Mask: 0xffff) */
/* ========================================================= AUX5 ========================================================== */
#define CTIMER_AUX5_TMRB5EN23_Pos (30UL) /*!< TMRB5EN23 (Bit 30) */
#define CTIMER_AUX5_TMRB5EN23_Msk (0x40000000UL) /*!< TMRB5EN23 (Bitfield-Mask: 0x01) */
#define CTIMER_AUX5_TMRB5POL23_Pos (29UL) /*!< TMRB5POL23 (Bit 29) */
#define CTIMER_AUX5_TMRB5POL23_Msk (0x20000000UL) /*!< TMRB5POL23 (Bitfield-Mask: 0x01) */
#define CTIMER_AUX5_TMRB5TINV_Pos (28UL) /*!< TMRB5TINV (Bit 28) */
#define CTIMER_AUX5_TMRB5TINV_Msk (0x10000000UL) /*!< TMRB5TINV (Bitfield-Mask: 0x01) */
#define CTIMER_AUX5_TMRB5NOSYNC_Pos (27UL) /*!< TMRB5NOSYNC (Bit 27) */
#define CTIMER_AUX5_TMRB5NOSYNC_Msk (0x8000000UL) /*!< TMRB5NOSYNC (Bitfield-Mask: 0x01) */
#define CTIMER_AUX5_TMRB5TRIG_Pos (23UL) /*!< TMRB5TRIG (Bit 23) */
#define CTIMER_AUX5_TMRB5TRIG_Msk (0x7800000UL) /*!< TMRB5TRIG (Bitfield-Mask: 0x0f) */
#define CTIMER_AUX5_TMRB5LMT_Pos (16UL) /*!< TMRB5LMT (Bit 16) */
#define CTIMER_AUX5_TMRB5LMT_Msk (0x3f0000UL) /*!< TMRB5LMT (Bitfield-Mask: 0x3f) */
#define CTIMER_AUX5_TMRA5EN23_Pos (14UL) /*!< TMRA5EN23 (Bit 14) */
#define CTIMER_AUX5_TMRA5EN23_Msk (0x4000UL) /*!< TMRA5EN23 (Bitfield-Mask: 0x01) */
#define CTIMER_AUX5_TMRA5POL23_Pos (13UL) /*!< TMRA5POL23 (Bit 13) */
#define CTIMER_AUX5_TMRA5POL23_Msk (0x2000UL) /*!< TMRA5POL23 (Bitfield-Mask: 0x01) */
#define CTIMER_AUX5_TMRA5TINV_Pos (12UL) /*!< TMRA5TINV (Bit 12) */
#define CTIMER_AUX5_TMRA5TINV_Msk (0x1000UL) /*!< TMRA5TINV (Bitfield-Mask: 0x01) */
#define CTIMER_AUX5_TMRA5NOSYNC_Pos (11UL) /*!< TMRA5NOSYNC (Bit 11) */
#define CTIMER_AUX5_TMRA5NOSYNC_Msk (0x800UL) /*!< TMRA5NOSYNC (Bitfield-Mask: 0x01) */
#define CTIMER_AUX5_TMRA5TRIG_Pos (7UL) /*!< TMRA5TRIG (Bit 7) */
#define CTIMER_AUX5_TMRA5TRIG_Msk (0x780UL) /*!< TMRA5TRIG (Bitfield-Mask: 0x0f) */
#define CTIMER_AUX5_TMRA5LMT_Pos (0UL) /*!< TMRA5LMT (Bit 0) */
#define CTIMER_AUX5_TMRA5LMT_Msk (0x7fUL) /*!< TMRA5LMT (Bitfield-Mask: 0x7f) */
/* ========================================================= TMR6 ========================================================== */
#define CTIMER_TMR6_CTTMRB6_Pos (16UL) /*!< CTTMRB6 (Bit 16) */
#define CTIMER_TMR6_CTTMRB6_Msk (0xffff0000UL) /*!< CTTMRB6 (Bitfield-Mask: 0xffff) */
#define CTIMER_TMR6_CTTMRA6_Pos (0UL) /*!< CTTMRA6 (Bit 0) */
#define CTIMER_TMR6_CTTMRA6_Msk (0xffffUL) /*!< CTTMRA6 (Bitfield-Mask: 0xffff) */
/* ======================================================== CMPRA6 ========================================================= */
#define CTIMER_CMPRA6_CMPR1A6_Pos (16UL) /*!< CMPR1A6 (Bit 16) */
#define CTIMER_CMPRA6_CMPR1A6_Msk (0xffff0000UL) /*!< CMPR1A6 (Bitfield-Mask: 0xffff) */
#define CTIMER_CMPRA6_CMPR0A6_Pos (0UL) /*!< CMPR0A6 (Bit 0) */
#define CTIMER_CMPRA6_CMPR0A6_Msk (0xffffUL) /*!< CMPR0A6 (Bitfield-Mask: 0xffff) */
/* ======================================================== CMPRB6 ========================================================= */
#define CTIMER_CMPRB6_CMPR1B6_Pos (16UL) /*!< CMPR1B6 (Bit 16) */
#define CTIMER_CMPRB6_CMPR1B6_Msk (0xffff0000UL) /*!< CMPR1B6 (Bitfield-Mask: 0xffff) */
#define CTIMER_CMPRB6_CMPR0B6_Pos (0UL) /*!< CMPR0B6 (Bit 0) */
#define CTIMER_CMPRB6_CMPR0B6_Msk (0xffffUL) /*!< CMPR0B6 (Bitfield-Mask: 0xffff) */
/* ========================================================= CTRL6 ========================================================= */
#define CTIMER_CTRL6_CTLINK6_Pos (31UL) /*!< CTLINK6 (Bit 31) */
#define CTIMER_CTRL6_CTLINK6_Msk (0x80000000UL) /*!< CTLINK6 (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL6_TMRB6POL_Pos (28UL) /*!< TMRB6POL (Bit 28) */
#define CTIMER_CTRL6_TMRB6POL_Msk (0x10000000UL) /*!< TMRB6POL (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL6_TMRB6CLR_Pos (27UL) /*!< TMRB6CLR (Bit 27) */
#define CTIMER_CTRL6_TMRB6CLR_Msk (0x8000000UL) /*!< TMRB6CLR (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL6_TMRB6IE1_Pos (26UL) /*!< TMRB6IE1 (Bit 26) */
#define CTIMER_CTRL6_TMRB6IE1_Msk (0x4000000UL) /*!< TMRB6IE1 (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL6_TMRB6IE0_Pos (25UL) /*!< TMRB6IE0 (Bit 25) */
#define CTIMER_CTRL6_TMRB6IE0_Msk (0x2000000UL) /*!< TMRB6IE0 (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL6_TMRB6FN_Pos (22UL) /*!< TMRB6FN (Bit 22) */
#define CTIMER_CTRL6_TMRB6FN_Msk (0x1c00000UL) /*!< TMRB6FN (Bitfield-Mask: 0x07) */
#define CTIMER_CTRL6_TMRB6CLK_Pos (17UL) /*!< TMRB6CLK (Bit 17) */
#define CTIMER_CTRL6_TMRB6CLK_Msk (0x3e0000UL) /*!< TMRB6CLK (Bitfield-Mask: 0x1f) */
#define CTIMER_CTRL6_TMRB6EN_Pos (16UL) /*!< TMRB6EN (Bit 16) */
#define CTIMER_CTRL6_TMRB6EN_Msk (0x10000UL) /*!< TMRB6EN (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL6_TMRA6POL_Pos (12UL) /*!< TMRA6POL (Bit 12) */
#define CTIMER_CTRL6_TMRA6POL_Msk (0x1000UL) /*!< TMRA6POL (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL6_TMRA6CLR_Pos (11UL) /*!< TMRA6CLR (Bit 11) */
#define CTIMER_CTRL6_TMRA6CLR_Msk (0x800UL) /*!< TMRA6CLR (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL6_TMRA6IE1_Pos (10UL) /*!< TMRA6IE1 (Bit 10) */
#define CTIMER_CTRL6_TMRA6IE1_Msk (0x400UL) /*!< TMRA6IE1 (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL6_TMRA6IE0_Pos (9UL) /*!< TMRA6IE0 (Bit 9) */
#define CTIMER_CTRL6_TMRA6IE0_Msk (0x200UL) /*!< TMRA6IE0 (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL6_TMRA6FN_Pos (6UL) /*!< TMRA6FN (Bit 6) */
#define CTIMER_CTRL6_TMRA6FN_Msk (0x1c0UL) /*!< TMRA6FN (Bitfield-Mask: 0x07) */
#define CTIMER_CTRL6_TMRA6CLK_Pos (1UL) /*!< TMRA6CLK (Bit 1) */
#define CTIMER_CTRL6_TMRA6CLK_Msk (0x3eUL) /*!< TMRA6CLK (Bitfield-Mask: 0x1f) */
#define CTIMER_CTRL6_TMRA6EN_Pos (0UL) /*!< TMRA6EN (Bit 0) */
#define CTIMER_CTRL6_TMRA6EN_Msk (0x1UL) /*!< TMRA6EN (Bitfield-Mask: 0x01) */
/* ======================================================= CMPRAUXA6 ======================================================= */
#define CTIMER_CMPRAUXA6_CMPR3A6_Pos (16UL) /*!< CMPR3A6 (Bit 16) */
#define CTIMER_CMPRAUXA6_CMPR3A6_Msk (0xffff0000UL) /*!< CMPR3A6 (Bitfield-Mask: 0xffff) */
#define CTIMER_CMPRAUXA6_CMPR2A6_Pos (0UL) /*!< CMPR2A6 (Bit 0) */
#define CTIMER_CMPRAUXA6_CMPR2A6_Msk (0xffffUL) /*!< CMPR2A6 (Bitfield-Mask: 0xffff) */
/* ======================================================= CMPRAUXB6 ======================================================= */
#define CTIMER_CMPRAUXB6_CMPR3B6_Pos (16UL) /*!< CMPR3B6 (Bit 16) */
#define CTIMER_CMPRAUXB6_CMPR3B6_Msk (0xffff0000UL) /*!< CMPR3B6 (Bitfield-Mask: 0xffff) */
#define CTIMER_CMPRAUXB6_CMPR2B6_Pos (0UL) /*!< CMPR2B6 (Bit 0) */
#define CTIMER_CMPRAUXB6_CMPR2B6_Msk (0xffffUL) /*!< CMPR2B6 (Bitfield-Mask: 0xffff) */
/* ========================================================= AUX6 ========================================================== */
#define CTIMER_AUX6_TMRB6EN23_Pos (30UL) /*!< TMRB6EN23 (Bit 30) */
#define CTIMER_AUX6_TMRB6EN23_Msk (0x40000000UL) /*!< TMRB6EN23 (Bitfield-Mask: 0x01) */
#define CTIMER_AUX6_TMRB6POL23_Pos (29UL) /*!< TMRB6POL23 (Bit 29) */
#define CTIMER_AUX6_TMRB6POL23_Msk (0x20000000UL) /*!< TMRB6POL23 (Bitfield-Mask: 0x01) */
#define CTIMER_AUX6_TMRB6TINV_Pos (28UL) /*!< TMRB6TINV (Bit 28) */
#define CTIMER_AUX6_TMRB6TINV_Msk (0x10000000UL) /*!< TMRB6TINV (Bitfield-Mask: 0x01) */
#define CTIMER_AUX6_TMRB6NOSYNC_Pos (27UL) /*!< TMRB6NOSYNC (Bit 27) */
#define CTIMER_AUX6_TMRB6NOSYNC_Msk (0x8000000UL) /*!< TMRB6NOSYNC (Bitfield-Mask: 0x01) */
#define CTIMER_AUX6_TMRB6TRIG_Pos (23UL) /*!< TMRB6TRIG (Bit 23) */
#define CTIMER_AUX6_TMRB6TRIG_Msk (0x7800000UL) /*!< TMRB6TRIG (Bitfield-Mask: 0x0f) */
#define CTIMER_AUX6_TMRB6LMT_Pos (16UL) /*!< TMRB6LMT (Bit 16) */
#define CTIMER_AUX6_TMRB6LMT_Msk (0x3f0000UL) /*!< TMRB6LMT (Bitfield-Mask: 0x3f) */
#define CTIMER_AUX6_TMRA6EN23_Pos (14UL) /*!< TMRA6EN23 (Bit 14) */
#define CTIMER_AUX6_TMRA6EN23_Msk (0x4000UL) /*!< TMRA6EN23 (Bitfield-Mask: 0x01) */
#define CTIMER_AUX6_TMRA6POL23_Pos (13UL) /*!< TMRA6POL23 (Bit 13) */
#define CTIMER_AUX6_TMRA6POL23_Msk (0x2000UL) /*!< TMRA6POL23 (Bitfield-Mask: 0x01) */
#define CTIMER_AUX6_TMRA6TINV_Pos (12UL) /*!< TMRA6TINV (Bit 12) */
#define CTIMER_AUX6_TMRA6TINV_Msk (0x1000UL) /*!< TMRA6TINV (Bitfield-Mask: 0x01) */
#define CTIMER_AUX6_TMRA6NOSYNC_Pos (11UL) /*!< TMRA6NOSYNC (Bit 11) */
#define CTIMER_AUX6_TMRA6NOSYNC_Msk (0x800UL) /*!< TMRA6NOSYNC (Bitfield-Mask: 0x01) */
#define CTIMER_AUX6_TMRA6TRIG_Pos (7UL) /*!< TMRA6TRIG (Bit 7) */
#define CTIMER_AUX6_TMRA6TRIG_Msk (0x780UL) /*!< TMRA6TRIG (Bitfield-Mask: 0x0f) */
#define CTIMER_AUX6_TMRA6LMT_Pos (0UL) /*!< TMRA6LMT (Bit 0) */
#define CTIMER_AUX6_TMRA6LMT_Msk (0x7fUL) /*!< TMRA6LMT (Bitfield-Mask: 0x7f) */
/* ========================================================= TMR7 ========================================================== */
#define CTIMER_TMR7_CTTMRB7_Pos (16UL) /*!< CTTMRB7 (Bit 16) */
#define CTIMER_TMR7_CTTMRB7_Msk (0xffff0000UL) /*!< CTTMRB7 (Bitfield-Mask: 0xffff) */
#define CTIMER_TMR7_CTTMRA7_Pos (0UL) /*!< CTTMRA7 (Bit 0) */
#define CTIMER_TMR7_CTTMRA7_Msk (0xffffUL) /*!< CTTMRA7 (Bitfield-Mask: 0xffff) */
/* ======================================================== CMPRA7 ========================================================= */
#define CTIMER_CMPRA7_CMPR1A7_Pos (16UL) /*!< CMPR1A7 (Bit 16) */
#define CTIMER_CMPRA7_CMPR1A7_Msk (0xffff0000UL) /*!< CMPR1A7 (Bitfield-Mask: 0xffff) */
#define CTIMER_CMPRA7_CMPR0A7_Pos (0UL) /*!< CMPR0A7 (Bit 0) */
#define CTIMER_CMPRA7_CMPR0A7_Msk (0xffffUL) /*!< CMPR0A7 (Bitfield-Mask: 0xffff) */
/* ======================================================== CMPRB7 ========================================================= */
#define CTIMER_CMPRB7_CMPR1B7_Pos (16UL) /*!< CMPR1B7 (Bit 16) */
#define CTIMER_CMPRB7_CMPR1B7_Msk (0xffff0000UL) /*!< CMPR1B7 (Bitfield-Mask: 0xffff) */
#define CTIMER_CMPRB7_CMPR0B7_Pos (0UL) /*!< CMPR0B7 (Bit 0) */
#define CTIMER_CMPRB7_CMPR0B7_Msk (0xffffUL) /*!< CMPR0B7 (Bitfield-Mask: 0xffff) */
/* ========================================================= CTRL7 ========================================================= */
#define CTIMER_CTRL7_CTLINK7_Pos (31UL) /*!< CTLINK7 (Bit 31) */
#define CTIMER_CTRL7_CTLINK7_Msk (0x80000000UL) /*!< CTLINK7 (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL7_TMRB7POL_Pos (28UL) /*!< TMRB7POL (Bit 28) */
#define CTIMER_CTRL7_TMRB7POL_Msk (0x10000000UL) /*!< TMRB7POL (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL7_TMRB7CLR_Pos (27UL) /*!< TMRB7CLR (Bit 27) */
#define CTIMER_CTRL7_TMRB7CLR_Msk (0x8000000UL) /*!< TMRB7CLR (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL7_TMRB7IE1_Pos (26UL) /*!< TMRB7IE1 (Bit 26) */
#define CTIMER_CTRL7_TMRB7IE1_Msk (0x4000000UL) /*!< TMRB7IE1 (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL7_TMRB7IE0_Pos (25UL) /*!< TMRB7IE0 (Bit 25) */
#define CTIMER_CTRL7_TMRB7IE0_Msk (0x2000000UL) /*!< TMRB7IE0 (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL7_TMRB7FN_Pos (22UL) /*!< TMRB7FN (Bit 22) */
#define CTIMER_CTRL7_TMRB7FN_Msk (0x1c00000UL) /*!< TMRB7FN (Bitfield-Mask: 0x07) */
#define CTIMER_CTRL7_TMRB7CLK_Pos (17UL) /*!< TMRB7CLK (Bit 17) */
#define CTIMER_CTRL7_TMRB7CLK_Msk (0x3e0000UL) /*!< TMRB7CLK (Bitfield-Mask: 0x1f) */
#define CTIMER_CTRL7_TMRB7EN_Pos (16UL) /*!< TMRB7EN (Bit 16) */
#define CTIMER_CTRL7_TMRB7EN_Msk (0x10000UL) /*!< TMRB7EN (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL7_TMRA7POL_Pos (12UL) /*!< TMRA7POL (Bit 12) */
#define CTIMER_CTRL7_TMRA7POL_Msk (0x1000UL) /*!< TMRA7POL (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL7_TMRA7CLR_Pos (11UL) /*!< TMRA7CLR (Bit 11) */
#define CTIMER_CTRL7_TMRA7CLR_Msk (0x800UL) /*!< TMRA7CLR (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL7_TMRA7IE1_Pos (10UL) /*!< TMRA7IE1 (Bit 10) */
#define CTIMER_CTRL7_TMRA7IE1_Msk (0x400UL) /*!< TMRA7IE1 (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL7_TMRA7IE0_Pos (9UL) /*!< TMRA7IE0 (Bit 9) */
#define CTIMER_CTRL7_TMRA7IE0_Msk (0x200UL) /*!< TMRA7IE0 (Bitfield-Mask: 0x01) */
#define CTIMER_CTRL7_TMRA7FN_Pos (6UL) /*!< TMRA7FN (Bit 6) */
#define CTIMER_CTRL7_TMRA7FN_Msk (0x1c0UL) /*!< TMRA7FN (Bitfield-Mask: 0x07) */
#define CTIMER_CTRL7_TMRA7CLK_Pos (1UL) /*!< TMRA7CLK (Bit 1) */
#define CTIMER_CTRL7_TMRA7CLK_Msk (0x3eUL) /*!< TMRA7CLK (Bitfield-Mask: 0x1f) */
#define CTIMER_CTRL7_TMRA7EN_Pos (0UL) /*!< TMRA7EN (Bit 0) */
#define CTIMER_CTRL7_TMRA7EN_Msk (0x1UL) /*!< TMRA7EN (Bitfield-Mask: 0x01) */
/* ======================================================= CMPRAUXA7 ======================================================= */
#define CTIMER_CMPRAUXA7_CMPR3A7_Pos (16UL) /*!< CMPR3A7 (Bit 16) */
#define CTIMER_CMPRAUXA7_CMPR3A7_Msk (0xffff0000UL) /*!< CMPR3A7 (Bitfield-Mask: 0xffff) */
#define CTIMER_CMPRAUXA7_CMPR2A7_Pos (0UL) /*!< CMPR2A7 (Bit 0) */
#define CTIMER_CMPRAUXA7_CMPR2A7_Msk (0xffffUL) /*!< CMPR2A7 (Bitfield-Mask: 0xffff) */
/* ======================================================= CMPRAUXB7 ======================================================= */
#define CTIMER_CMPRAUXB7_CMPR3B7_Pos (16UL) /*!< CMPR3B7 (Bit 16) */
#define CTIMER_CMPRAUXB7_CMPR3B7_Msk (0xffff0000UL) /*!< CMPR3B7 (Bitfield-Mask: 0xffff) */
#define CTIMER_CMPRAUXB7_CMPR2B7_Pos (0UL) /*!< CMPR2B7 (Bit 0) */
#define CTIMER_CMPRAUXB7_CMPR2B7_Msk (0xffffUL) /*!< CMPR2B7 (Bitfield-Mask: 0xffff) */
/* ========================================================= AUX7 ========================================================== */
#define CTIMER_AUX7_TMRB7EN23_Pos (30UL) /*!< TMRB7EN23 (Bit 30) */
#define CTIMER_AUX7_TMRB7EN23_Msk (0x40000000UL) /*!< TMRB7EN23 (Bitfield-Mask: 0x01) */
#define CTIMER_AUX7_TMRB7POL23_Pos (29UL) /*!< TMRB7POL23 (Bit 29) */
#define CTIMER_AUX7_TMRB7POL23_Msk (0x20000000UL) /*!< TMRB7POL23 (Bitfield-Mask: 0x01) */
#define CTIMER_AUX7_TMRB7TINV_Pos (28UL) /*!< TMRB7TINV (Bit 28) */
#define CTIMER_AUX7_TMRB7TINV_Msk (0x10000000UL) /*!< TMRB7TINV (Bitfield-Mask: 0x01) */
#define CTIMER_AUX7_TMRB7NOSYNC_Pos (27UL) /*!< TMRB7NOSYNC (Bit 27) */
#define CTIMER_AUX7_TMRB7NOSYNC_Msk (0x8000000UL) /*!< TMRB7NOSYNC (Bitfield-Mask: 0x01) */
#define CTIMER_AUX7_TMRB7TRIG_Pos (23UL) /*!< TMRB7TRIG (Bit 23) */
#define CTIMER_AUX7_TMRB7TRIG_Msk (0x7800000UL) /*!< TMRB7TRIG (Bitfield-Mask: 0x0f) */
#define CTIMER_AUX7_TMRB7LMT_Pos (16UL) /*!< TMRB7LMT (Bit 16) */
#define CTIMER_AUX7_TMRB7LMT_Msk (0x3f0000UL) /*!< TMRB7LMT (Bitfield-Mask: 0x3f) */
#define CTIMER_AUX7_TMRA7EN23_Pos (14UL) /*!< TMRA7EN23 (Bit 14) */
#define CTIMER_AUX7_TMRA7EN23_Msk (0x4000UL) /*!< TMRA7EN23 (Bitfield-Mask: 0x01) */
#define CTIMER_AUX7_TMRA7POL23_Pos (13UL) /*!< TMRA7POL23 (Bit 13) */
#define CTIMER_AUX7_TMRA7POL23_Msk (0x2000UL) /*!< TMRA7POL23 (Bitfield-Mask: 0x01) */
#define CTIMER_AUX7_TMRA7TINV_Pos (12UL) /*!< TMRA7TINV (Bit 12) */
#define CTIMER_AUX7_TMRA7TINV_Msk (0x1000UL) /*!< TMRA7TINV (Bitfield-Mask: 0x01) */
#define CTIMER_AUX7_TMRA7NOSYNC_Pos (11UL) /*!< TMRA7NOSYNC (Bit 11) */
#define CTIMER_AUX7_TMRA7NOSYNC_Msk (0x800UL) /*!< TMRA7NOSYNC (Bitfield-Mask: 0x01) */
#define CTIMER_AUX7_TMRA7TRIG_Pos (7UL) /*!< TMRA7TRIG (Bit 7) */
#define CTIMER_AUX7_TMRA7TRIG_Msk (0x780UL) /*!< TMRA7TRIG (Bitfield-Mask: 0x0f) */
#define CTIMER_AUX7_TMRA7LMT_Pos (0UL) /*!< TMRA7LMT (Bit 0) */
#define CTIMER_AUX7_TMRA7LMT_Msk (0x7fUL) /*!< TMRA7LMT (Bitfield-Mask: 0x7f) */
/* ======================================================== GLOBEN ========================================================= */
#define CTIMER_GLOBEN_ENB7_Pos (15UL) /*!< ENB7 (Bit 15) */
#define CTIMER_GLOBEN_ENB7_Msk (0x8000UL) /*!< ENB7 (Bitfield-Mask: 0x01) */
#define CTIMER_GLOBEN_ENA7_Pos (14UL) /*!< ENA7 (Bit 14) */
#define CTIMER_GLOBEN_ENA7_Msk (0x4000UL) /*!< ENA7 (Bitfield-Mask: 0x01) */
#define CTIMER_GLOBEN_ENB6_Pos (13UL) /*!< ENB6 (Bit 13) */
#define CTIMER_GLOBEN_ENB6_Msk (0x2000UL) /*!< ENB6 (Bitfield-Mask: 0x01) */
#define CTIMER_GLOBEN_ENA6_Pos (12UL) /*!< ENA6 (Bit 12) */
#define CTIMER_GLOBEN_ENA6_Msk (0x1000UL) /*!< ENA6 (Bitfield-Mask: 0x01) */
#define CTIMER_GLOBEN_ENB5_Pos (11UL) /*!< ENB5 (Bit 11) */
#define CTIMER_GLOBEN_ENB5_Msk (0x800UL) /*!< ENB5 (Bitfield-Mask: 0x01) */
#define CTIMER_GLOBEN_ENA5_Pos (10UL) /*!< ENA5 (Bit 10) */
#define CTIMER_GLOBEN_ENA5_Msk (0x400UL) /*!< ENA5 (Bitfield-Mask: 0x01) */
#define CTIMER_GLOBEN_ENB4_Pos (9UL) /*!< ENB4 (Bit 9) */
#define CTIMER_GLOBEN_ENB4_Msk (0x200UL) /*!< ENB4 (Bitfield-Mask: 0x01) */
#define CTIMER_GLOBEN_ENA4_Pos (8UL) /*!< ENA4 (Bit 8) */
#define CTIMER_GLOBEN_ENA4_Msk (0x100UL) /*!< ENA4 (Bitfield-Mask: 0x01) */
#define CTIMER_GLOBEN_ENB3_Pos (7UL) /*!< ENB3 (Bit 7) */
#define CTIMER_GLOBEN_ENB3_Msk (0x80UL) /*!< ENB3 (Bitfield-Mask: 0x01) */
#define CTIMER_GLOBEN_ENA3_Pos (6UL) /*!< ENA3 (Bit 6) */
#define CTIMER_GLOBEN_ENA3_Msk (0x40UL) /*!< ENA3 (Bitfield-Mask: 0x01) */
#define CTIMER_GLOBEN_ENB2_Pos (5UL) /*!< ENB2 (Bit 5) */
#define CTIMER_GLOBEN_ENB2_Msk (0x20UL) /*!< ENB2 (Bitfield-Mask: 0x01) */
#define CTIMER_GLOBEN_ENA2_Pos (4UL) /*!< ENA2 (Bit 4) */
#define CTIMER_GLOBEN_ENA2_Msk (0x10UL) /*!< ENA2 (Bitfield-Mask: 0x01) */
#define CTIMER_GLOBEN_ENB1_Pos (3UL) /*!< ENB1 (Bit 3) */
#define CTIMER_GLOBEN_ENB1_Msk (0x8UL) /*!< ENB1 (Bitfield-Mask: 0x01) */
#define CTIMER_GLOBEN_ENA1_Pos (2UL) /*!< ENA1 (Bit 2) */
#define CTIMER_GLOBEN_ENA1_Msk (0x4UL) /*!< ENA1 (Bitfield-Mask: 0x01) */
#define CTIMER_GLOBEN_ENB0_Pos (1UL) /*!< ENB0 (Bit 1) */
#define CTIMER_GLOBEN_ENB0_Msk (0x2UL) /*!< ENB0 (Bitfield-Mask: 0x01) */
#define CTIMER_GLOBEN_ENA0_Pos (0UL) /*!< ENA0 (Bit 0) */
#define CTIMER_GLOBEN_ENA0_Msk (0x1UL) /*!< ENA0 (Bitfield-Mask: 0x01) */
/* ======================================================== OUTCFG0 ======================================================== */
#define CTIMER_OUTCFG0_CFG9_Pos (28UL) /*!< CFG9 (Bit 28) */
#define CTIMER_OUTCFG0_CFG9_Msk (0x70000000UL) /*!< CFG9 (Bitfield-Mask: 0x07) */
#define CTIMER_OUTCFG0_CFG8_Pos (25UL) /*!< CFG8 (Bit 25) */
#define CTIMER_OUTCFG0_CFG8_Msk (0xe000000UL) /*!< CFG8 (Bitfield-Mask: 0x07) */
#define CTIMER_OUTCFG0_CFG7_Pos (22UL) /*!< CFG7 (Bit 22) */
#define CTIMER_OUTCFG0_CFG7_Msk (0x1c00000UL) /*!< CFG7 (Bitfield-Mask: 0x07) */
#define CTIMER_OUTCFG0_CFG6_Pos (19UL) /*!< CFG6 (Bit 19) */
#define CTIMER_OUTCFG0_CFG6_Msk (0x380000UL) /*!< CFG6 (Bitfield-Mask: 0x07) */
#define CTIMER_OUTCFG0_CFG5_Pos (16UL) /*!< CFG5 (Bit 16) */
#define CTIMER_OUTCFG0_CFG5_Msk (0x70000UL) /*!< CFG5 (Bitfield-Mask: 0x07) */
#define CTIMER_OUTCFG0_CFG4_Pos (12UL) /*!< CFG4 (Bit 12) */
#define CTIMER_OUTCFG0_CFG4_Msk (0x7000UL) /*!< CFG4 (Bitfield-Mask: 0x07) */
#define CTIMER_OUTCFG0_CFG3_Pos (9UL) /*!< CFG3 (Bit 9) */
#define CTIMER_OUTCFG0_CFG3_Msk (0xe00UL) /*!< CFG3 (Bitfield-Mask: 0x07) */
#define CTIMER_OUTCFG0_CFG2_Pos (6UL) /*!< CFG2 (Bit 6) */
#define CTIMER_OUTCFG0_CFG2_Msk (0x1c0UL) /*!< CFG2 (Bitfield-Mask: 0x07) */
#define CTIMER_OUTCFG0_CFG1_Pos (3UL) /*!< CFG1 (Bit 3) */
#define CTIMER_OUTCFG0_CFG1_Msk (0x38UL) /*!< CFG1 (Bitfield-Mask: 0x07) */
#define CTIMER_OUTCFG0_CFG0_Pos (0UL) /*!< CFG0 (Bit 0) */
#define CTIMER_OUTCFG0_CFG0_Msk (0x7UL) /*!< CFG0 (Bitfield-Mask: 0x07) */
/* ======================================================== OUTCFG1 ======================================================== */
#define CTIMER_OUTCFG1_CFG19_Pos (28UL) /*!< CFG19 (Bit 28) */
#define CTIMER_OUTCFG1_CFG19_Msk (0x70000000UL) /*!< CFG19 (Bitfield-Mask: 0x07) */
#define CTIMER_OUTCFG1_CFG18_Pos (25UL) /*!< CFG18 (Bit 25) */
#define CTIMER_OUTCFG1_CFG18_Msk (0xe000000UL) /*!< CFG18 (Bitfield-Mask: 0x07) */
#define CTIMER_OUTCFG1_CFG17_Pos (22UL) /*!< CFG17 (Bit 22) */
#define CTIMER_OUTCFG1_CFG17_Msk (0x1c00000UL) /*!< CFG17 (Bitfield-Mask: 0x07) */
#define CTIMER_OUTCFG1_CFG16_Pos (19UL) /*!< CFG16 (Bit 19) */
#define CTIMER_OUTCFG1_CFG16_Msk (0x380000UL) /*!< CFG16 (Bitfield-Mask: 0x07) */
#define CTIMER_OUTCFG1_CFG15_Pos (16UL) /*!< CFG15 (Bit 16) */
#define CTIMER_OUTCFG1_CFG15_Msk (0x70000UL) /*!< CFG15 (Bitfield-Mask: 0x07) */
#define CTIMER_OUTCFG1_CFG14_Pos (12UL) /*!< CFG14 (Bit 12) */
#define CTIMER_OUTCFG1_CFG14_Msk (0x7000UL) /*!< CFG14 (Bitfield-Mask: 0x07) */
#define CTIMER_OUTCFG1_CFG13_Pos (9UL) /*!< CFG13 (Bit 9) */
#define CTIMER_OUTCFG1_CFG13_Msk (0xe00UL) /*!< CFG13 (Bitfield-Mask: 0x07) */
#define CTIMER_OUTCFG1_CFG12_Pos (6UL) /*!< CFG12 (Bit 6) */
#define CTIMER_OUTCFG1_CFG12_Msk (0x1c0UL) /*!< CFG12 (Bitfield-Mask: 0x07) */
#define CTIMER_OUTCFG1_CFG11_Pos (3UL) /*!< CFG11 (Bit 3) */
#define CTIMER_OUTCFG1_CFG11_Msk (0x38UL) /*!< CFG11 (Bitfield-Mask: 0x07) */
#define CTIMER_OUTCFG1_CFG10_Pos (0UL) /*!< CFG10 (Bit 0) */
#define CTIMER_OUTCFG1_CFG10_Msk (0x7UL) /*!< CFG10 (Bitfield-Mask: 0x07) */
/* ======================================================== OUTCFG2 ======================================================== */
#define CTIMER_OUTCFG2_CFG29_Pos (28UL) /*!< CFG29 (Bit 28) */
#define CTIMER_OUTCFG2_CFG29_Msk (0x70000000UL) /*!< CFG29 (Bitfield-Mask: 0x07) */
#define CTIMER_OUTCFG2_CFG28_Pos (25UL) /*!< CFG28 (Bit 25) */
#define CTIMER_OUTCFG2_CFG28_Msk (0xe000000UL) /*!< CFG28 (Bitfield-Mask: 0x07) */
#define CTIMER_OUTCFG2_CFG27_Pos (22UL) /*!< CFG27 (Bit 22) */
#define CTIMER_OUTCFG2_CFG27_Msk (0x1c00000UL) /*!< CFG27 (Bitfield-Mask: 0x07) */
#define CTIMER_OUTCFG2_CFG26_Pos (19UL) /*!< CFG26 (Bit 19) */
#define CTIMER_OUTCFG2_CFG26_Msk (0x380000UL) /*!< CFG26 (Bitfield-Mask: 0x07) */
#define CTIMER_OUTCFG2_CFG25_Pos (16UL) /*!< CFG25 (Bit 16) */
#define CTIMER_OUTCFG2_CFG25_Msk (0x70000UL) /*!< CFG25 (Bitfield-Mask: 0x07) */
#define CTIMER_OUTCFG2_CFG24_Pos (12UL) /*!< CFG24 (Bit 12) */
#define CTIMER_OUTCFG2_CFG24_Msk (0x7000UL) /*!< CFG24 (Bitfield-Mask: 0x07) */
#define CTIMER_OUTCFG2_CFG23_Pos (9UL) /*!< CFG23 (Bit 9) */
#define CTIMER_OUTCFG2_CFG23_Msk (0xe00UL) /*!< CFG23 (Bitfield-Mask: 0x07) */
#define CTIMER_OUTCFG2_CFG22_Pos (6UL) /*!< CFG22 (Bit 6) */
#define CTIMER_OUTCFG2_CFG22_Msk (0x1c0UL) /*!< CFG22 (Bitfield-Mask: 0x07) */
#define CTIMER_OUTCFG2_CFG21_Pos (3UL) /*!< CFG21 (Bit 3) */
#define CTIMER_OUTCFG2_CFG21_Msk (0x38UL) /*!< CFG21 (Bitfield-Mask: 0x07) */
#define CTIMER_OUTCFG2_CFG20_Pos (0UL) /*!< CFG20 (Bit 0) */
#define CTIMER_OUTCFG2_CFG20_Msk (0x7UL) /*!< CFG20 (Bitfield-Mask: 0x07) */
/* ======================================================== OUTCFG3 ======================================================== */
#define CTIMER_OUTCFG3_CFG31_Pos (3UL) /*!< CFG31 (Bit 3) */
#define CTIMER_OUTCFG3_CFG31_Msk (0x38UL) /*!< CFG31 (Bitfield-Mask: 0x07) */
#define CTIMER_OUTCFG3_CFG30_Pos (0UL) /*!< CFG30 (Bit 0) */
#define CTIMER_OUTCFG3_CFG30_Msk (0x7UL) /*!< CFG30 (Bitfield-Mask: 0x07) */
/* ========================================================= INCFG ========================================================= */
#define CTIMER_INCFG_CFGB7_Pos (15UL) /*!< CFGB7 (Bit 15) */
#define CTIMER_INCFG_CFGB7_Msk (0x8000UL) /*!< CFGB7 (Bitfield-Mask: 0x01) */
#define CTIMER_INCFG_CFGA7_Pos (14UL) /*!< CFGA7 (Bit 14) */
#define CTIMER_INCFG_CFGA7_Msk (0x4000UL) /*!< CFGA7 (Bitfield-Mask: 0x01) */
#define CTIMER_INCFG_CFGB6_Pos (13UL) /*!< CFGB6 (Bit 13) */
#define CTIMER_INCFG_CFGB6_Msk (0x2000UL) /*!< CFGB6 (Bitfield-Mask: 0x01) */
#define CTIMER_INCFG_CFGA6_Pos (12UL) /*!< CFGA6 (Bit 12) */
#define CTIMER_INCFG_CFGA6_Msk (0x1000UL) /*!< CFGA6 (Bitfield-Mask: 0x01) */
#define CTIMER_INCFG_CFGB5_Pos (11UL) /*!< CFGB5 (Bit 11) */
#define CTIMER_INCFG_CFGB5_Msk (0x800UL) /*!< CFGB5 (Bitfield-Mask: 0x01) */
#define CTIMER_INCFG_CFGA5_Pos (10UL) /*!< CFGA5 (Bit 10) */
#define CTIMER_INCFG_CFGA5_Msk (0x400UL) /*!< CFGA5 (Bitfield-Mask: 0x01) */
#define CTIMER_INCFG_CFGB4_Pos (9UL) /*!< CFGB4 (Bit 9) */
#define CTIMER_INCFG_CFGB4_Msk (0x200UL) /*!< CFGB4 (Bitfield-Mask: 0x01) */
#define CTIMER_INCFG_CFGA4_Pos (8UL) /*!< CFGA4 (Bit 8) */
#define CTIMER_INCFG_CFGA4_Msk (0x100UL) /*!< CFGA4 (Bitfield-Mask: 0x01) */
#define CTIMER_INCFG_CFGB3_Pos (7UL) /*!< CFGB3 (Bit 7) */
#define CTIMER_INCFG_CFGB3_Msk (0x80UL) /*!< CFGB3 (Bitfield-Mask: 0x01) */
#define CTIMER_INCFG_CFGA3_Pos (6UL) /*!< CFGA3 (Bit 6) */
#define CTIMER_INCFG_CFGA3_Msk (0x40UL) /*!< CFGA3 (Bitfield-Mask: 0x01) */
#define CTIMER_INCFG_CFGB2_Pos (5UL) /*!< CFGB2 (Bit 5) */
#define CTIMER_INCFG_CFGB2_Msk (0x20UL) /*!< CFGB2 (Bitfield-Mask: 0x01) */
#define CTIMER_INCFG_CFGA2_Pos (4UL) /*!< CFGA2 (Bit 4) */
#define CTIMER_INCFG_CFGA2_Msk (0x10UL) /*!< CFGA2 (Bitfield-Mask: 0x01) */
#define CTIMER_INCFG_CFGB1_Pos (3UL) /*!< CFGB1 (Bit 3) */
#define CTIMER_INCFG_CFGB1_Msk (0x8UL) /*!< CFGB1 (Bitfield-Mask: 0x01) */
#define CTIMER_INCFG_CFGA1_Pos (2UL) /*!< CFGA1 (Bit 2) */
#define CTIMER_INCFG_CFGA1_Msk (0x4UL) /*!< CFGA1 (Bitfield-Mask: 0x01) */
#define CTIMER_INCFG_CFGB0_Pos (1UL) /*!< CFGB0 (Bit 1) */
#define CTIMER_INCFG_CFGB0_Msk (0x2UL) /*!< CFGB0 (Bitfield-Mask: 0x01) */
#define CTIMER_INCFG_CFGA0_Pos (0UL) /*!< CFGA0 (Bit 0) */
#define CTIMER_INCFG_CFGA0_Msk (0x1UL) /*!< CFGA0 (Bitfield-Mask: 0x01) */
/* ========================================================= STCFG ========================================================= */
#define CTIMER_STCFG_FREEZE_Pos (31UL) /*!< FREEZE (Bit 31) */
#define CTIMER_STCFG_FREEZE_Msk (0x80000000UL) /*!< FREEZE (Bitfield-Mask: 0x01) */
#define CTIMER_STCFG_CLEAR_Pos (30UL) /*!< CLEAR (Bit 30) */
#define CTIMER_STCFG_CLEAR_Msk (0x40000000UL) /*!< CLEAR (Bitfield-Mask: 0x01) */
#define CTIMER_STCFG_COMPARE_H_EN_Pos (15UL) /*!< COMPARE_H_EN (Bit 15) */
#define CTIMER_STCFG_COMPARE_H_EN_Msk (0x8000UL) /*!< COMPARE_H_EN (Bitfield-Mask: 0x01) */
#define CTIMER_STCFG_COMPARE_G_EN_Pos (14UL) /*!< COMPARE_G_EN (Bit 14) */
#define CTIMER_STCFG_COMPARE_G_EN_Msk (0x4000UL) /*!< COMPARE_G_EN (Bitfield-Mask: 0x01) */
#define CTIMER_STCFG_COMPARE_F_EN_Pos (13UL) /*!< COMPARE_F_EN (Bit 13) */
#define CTIMER_STCFG_COMPARE_F_EN_Msk (0x2000UL) /*!< COMPARE_F_EN (Bitfield-Mask: 0x01) */
#define CTIMER_STCFG_COMPARE_E_EN_Pos (12UL) /*!< COMPARE_E_EN (Bit 12) */
#define CTIMER_STCFG_COMPARE_E_EN_Msk (0x1000UL) /*!< COMPARE_E_EN (Bitfield-Mask: 0x01) */
#define CTIMER_STCFG_COMPARE_D_EN_Pos (11UL) /*!< COMPARE_D_EN (Bit 11) */
#define CTIMER_STCFG_COMPARE_D_EN_Msk (0x800UL) /*!< COMPARE_D_EN (Bitfield-Mask: 0x01) */
#define CTIMER_STCFG_COMPARE_C_EN_Pos (10UL) /*!< COMPARE_C_EN (Bit 10) */
#define CTIMER_STCFG_COMPARE_C_EN_Msk (0x400UL) /*!< COMPARE_C_EN (Bitfield-Mask: 0x01) */
#define CTIMER_STCFG_COMPARE_B_EN_Pos (9UL) /*!< COMPARE_B_EN (Bit 9) */
#define CTIMER_STCFG_COMPARE_B_EN_Msk (0x200UL) /*!< COMPARE_B_EN (Bitfield-Mask: 0x01) */
#define CTIMER_STCFG_COMPARE_A_EN_Pos (8UL) /*!< COMPARE_A_EN (Bit 8) */
#define CTIMER_STCFG_COMPARE_A_EN_Msk (0x100UL) /*!< COMPARE_A_EN (Bitfield-Mask: 0x01) */
#define CTIMER_STCFG_CLKSEL_Pos (0UL) /*!< CLKSEL (Bit 0) */
#define CTIMER_STCFG_CLKSEL_Msk (0xfUL) /*!< CLKSEL (Bitfield-Mask: 0x0f) */
/* ========================================================= STTMR ========================================================= */
#define CTIMER_STTMR_STTMR_Pos (0UL) /*!< STTMR (Bit 0) */
#define CTIMER_STTMR_STTMR_Msk (0xffffffffUL) /*!< STTMR (Bitfield-Mask: 0xffffffff) */
/* ==================================================== CAPTURECONTROL ===================================================== */
#define CTIMER_CAPTURECONTROL_CAPTURE3_Pos (3UL) /*!< CAPTURE3 (Bit 3) */
#define CTIMER_CAPTURECONTROL_CAPTURE3_Msk (0x8UL) /*!< CAPTURE3 (Bitfield-Mask: 0x01) */
#define CTIMER_CAPTURECONTROL_CAPTURE2_Pos (2UL) /*!< CAPTURE2 (Bit 2) */
#define CTIMER_CAPTURECONTROL_CAPTURE2_Msk (0x4UL) /*!< CAPTURE2 (Bitfield-Mask: 0x01) */
#define CTIMER_CAPTURECONTROL_CAPTURE1_Pos (1UL) /*!< CAPTURE1 (Bit 1) */
#define CTIMER_CAPTURECONTROL_CAPTURE1_Msk (0x2UL) /*!< CAPTURE1 (Bitfield-Mask: 0x01) */
#define CTIMER_CAPTURECONTROL_CAPTURE0_Pos (0UL) /*!< CAPTURE0 (Bit 0) */
#define CTIMER_CAPTURECONTROL_CAPTURE0_Msk (0x1UL) /*!< CAPTURE0 (Bitfield-Mask: 0x01) */
/* ======================================================== SCMPR0 ========================================================= */
#define CTIMER_SCMPR0_SCMPR0_Pos (0UL) /*!< SCMPR0 (Bit 0) */
#define CTIMER_SCMPR0_SCMPR0_Msk (0xffffffffUL) /*!< SCMPR0 (Bitfield-Mask: 0xffffffff) */
/* ======================================================== SCMPR1 ========================================================= */
#define CTIMER_SCMPR1_SCMPR1_Pos (0UL) /*!< SCMPR1 (Bit 0) */
#define CTIMER_SCMPR1_SCMPR1_Msk (0xffffffffUL) /*!< SCMPR1 (Bitfield-Mask: 0xffffffff) */
/* ======================================================== SCMPR2 ========================================================= */
#define CTIMER_SCMPR2_SCMPR2_Pos (0UL) /*!< SCMPR2 (Bit 0) */
#define CTIMER_SCMPR2_SCMPR2_Msk (0xffffffffUL) /*!< SCMPR2 (Bitfield-Mask: 0xffffffff) */
/* ======================================================== SCMPR3 ========================================================= */
#define CTIMER_SCMPR3_SCMPR3_Pos (0UL) /*!< SCMPR3 (Bit 0) */
#define CTIMER_SCMPR3_SCMPR3_Msk (0xffffffffUL) /*!< SCMPR3 (Bitfield-Mask: 0xffffffff) */
/* ======================================================== SCMPR4 ========================================================= */
#define CTIMER_SCMPR4_SCMPR4_Pos (0UL) /*!< SCMPR4 (Bit 0) */
#define CTIMER_SCMPR4_SCMPR4_Msk (0xffffffffUL) /*!< SCMPR4 (Bitfield-Mask: 0xffffffff) */
/* ======================================================== SCMPR5 ========================================================= */
#define CTIMER_SCMPR5_SCMPR5_Pos (0UL) /*!< SCMPR5 (Bit 0) */
#define CTIMER_SCMPR5_SCMPR5_Msk (0xffffffffUL) /*!< SCMPR5 (Bitfield-Mask: 0xffffffff) */
/* ======================================================== SCMPR6 ========================================================= */
#define CTIMER_SCMPR6_SCMPR6_Pos (0UL) /*!< SCMPR6 (Bit 0) */
#define CTIMER_SCMPR6_SCMPR6_Msk (0xffffffffUL) /*!< SCMPR6 (Bitfield-Mask: 0xffffffff) */
/* ======================================================== SCMPR7 ========================================================= */
#define CTIMER_SCMPR7_SCMPR7_Pos (0UL) /*!< SCMPR7 (Bit 0) */
#define CTIMER_SCMPR7_SCMPR7_Msk (0xffffffffUL) /*!< SCMPR7 (Bitfield-Mask: 0xffffffff) */
/* ======================================================== SCAPT0 ========================================================= */
#define CTIMER_SCAPT0_SCAPT0_Pos (0UL) /*!< SCAPT0 (Bit 0) */
#define CTIMER_SCAPT0_SCAPT0_Msk (0xffffffffUL) /*!< SCAPT0 (Bitfield-Mask: 0xffffffff) */
/* ======================================================== SCAPT1 ========================================================= */
#define CTIMER_SCAPT1_SCAPT1_Pos (0UL) /*!< SCAPT1 (Bit 0) */
#define CTIMER_SCAPT1_SCAPT1_Msk (0xffffffffUL) /*!< SCAPT1 (Bitfield-Mask: 0xffffffff) */
/* ======================================================== SCAPT2 ========================================================= */
#define CTIMER_SCAPT2_SCAPT2_Pos (0UL) /*!< SCAPT2 (Bit 0) */
#define CTIMER_SCAPT2_SCAPT2_Msk (0xffffffffUL) /*!< SCAPT2 (Bitfield-Mask: 0xffffffff) */
/* ======================================================== SCAPT3 ========================================================= */
#define CTIMER_SCAPT3_SCAPT3_Pos (0UL) /*!< SCAPT3 (Bit 0) */
#define CTIMER_SCAPT3_SCAPT3_Msk (0xffffffffUL) /*!< SCAPT3 (Bitfield-Mask: 0xffffffff) */
/* ========================================================= SNVR0 ========================================================= */
#define CTIMER_SNVR0_SNVR0_Pos (0UL) /*!< SNVR0 (Bit 0) */
#define CTIMER_SNVR0_SNVR0_Msk (0xffffffffUL) /*!< SNVR0 (Bitfield-Mask: 0xffffffff) */
/* ========================================================= SNVR1 ========================================================= */
#define CTIMER_SNVR1_SNVR1_Pos (0UL) /*!< SNVR1 (Bit 0) */
#define CTIMER_SNVR1_SNVR1_Msk (0xffffffffUL) /*!< SNVR1 (Bitfield-Mask: 0xffffffff) */
/* ========================================================= SNVR2 ========================================================= */
#define CTIMER_SNVR2_SNVR2_Pos (0UL) /*!< SNVR2 (Bit 0) */
#define CTIMER_SNVR2_SNVR2_Msk (0xffffffffUL) /*!< SNVR2 (Bitfield-Mask: 0xffffffff) */
/* ========================================================= SNVR3 ========================================================= */
#define CTIMER_SNVR3_SNVR3_Pos (0UL) /*!< SNVR3 (Bit 0) */
#define CTIMER_SNVR3_SNVR3_Msk (0xffffffffUL) /*!< SNVR3 (Bitfield-Mask: 0xffffffff) */
/* ========================================================= INTEN ========================================================= */
#define CTIMER_INTEN_CTMRB7C1INT_Pos (31UL) /*!< CTMRB7C1INT (Bit 31) */
#define CTIMER_INTEN_CTMRB7C1INT_Msk (0x80000000UL) /*!< CTMRB7C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTEN_CTMRA7C1INT_Pos (30UL) /*!< CTMRA7C1INT (Bit 30) */
#define CTIMER_INTEN_CTMRA7C1INT_Msk (0x40000000UL) /*!< CTMRA7C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTEN_CTMRB6C1INT_Pos (29UL) /*!< CTMRB6C1INT (Bit 29) */
#define CTIMER_INTEN_CTMRB6C1INT_Msk (0x20000000UL) /*!< CTMRB6C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTEN_CTMRA6C1INT_Pos (28UL) /*!< CTMRA6C1INT (Bit 28) */
#define CTIMER_INTEN_CTMRA6C1INT_Msk (0x10000000UL) /*!< CTMRA6C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTEN_CTMRB5C1INT_Pos (27UL) /*!< CTMRB5C1INT (Bit 27) */
#define CTIMER_INTEN_CTMRB5C1INT_Msk (0x8000000UL) /*!< CTMRB5C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTEN_CTMRA5C1INT_Pos (26UL) /*!< CTMRA5C1INT (Bit 26) */
#define CTIMER_INTEN_CTMRA5C1INT_Msk (0x4000000UL) /*!< CTMRA5C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTEN_CTMRB4C1INT_Pos (25UL) /*!< CTMRB4C1INT (Bit 25) */
#define CTIMER_INTEN_CTMRB4C1INT_Msk (0x2000000UL) /*!< CTMRB4C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTEN_CTMRA4C1INT_Pos (24UL) /*!< CTMRA4C1INT (Bit 24) */
#define CTIMER_INTEN_CTMRA4C1INT_Msk (0x1000000UL) /*!< CTMRA4C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTEN_CTMRB3C1INT_Pos (23UL) /*!< CTMRB3C1INT (Bit 23) */
#define CTIMER_INTEN_CTMRB3C1INT_Msk (0x800000UL) /*!< CTMRB3C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTEN_CTMRA3C1INT_Pos (22UL) /*!< CTMRA3C1INT (Bit 22) */
#define CTIMER_INTEN_CTMRA3C1INT_Msk (0x400000UL) /*!< CTMRA3C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTEN_CTMRB2C1INT_Pos (21UL) /*!< CTMRB2C1INT (Bit 21) */
#define CTIMER_INTEN_CTMRB2C1INT_Msk (0x200000UL) /*!< CTMRB2C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTEN_CTMRA2C1INT_Pos (20UL) /*!< CTMRA2C1INT (Bit 20) */
#define CTIMER_INTEN_CTMRA2C1INT_Msk (0x100000UL) /*!< CTMRA2C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTEN_CTMRB1C1INT_Pos (19UL) /*!< CTMRB1C1INT (Bit 19) */
#define CTIMER_INTEN_CTMRB1C1INT_Msk (0x80000UL) /*!< CTMRB1C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTEN_CTMRA1C1INT_Pos (18UL) /*!< CTMRA1C1INT (Bit 18) */
#define CTIMER_INTEN_CTMRA1C1INT_Msk (0x40000UL) /*!< CTMRA1C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTEN_CTMRB0C1INT_Pos (17UL) /*!< CTMRB0C1INT (Bit 17) */
#define CTIMER_INTEN_CTMRB0C1INT_Msk (0x20000UL) /*!< CTMRB0C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTEN_CTMRA0C1INT_Pos (16UL) /*!< CTMRA0C1INT (Bit 16) */
#define CTIMER_INTEN_CTMRA0C1INT_Msk (0x10000UL) /*!< CTMRA0C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTEN_CTMRB7C0INT_Pos (15UL) /*!< CTMRB7C0INT (Bit 15) */
#define CTIMER_INTEN_CTMRB7C0INT_Msk (0x8000UL) /*!< CTMRB7C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTEN_CTMRA7C0INT_Pos (14UL) /*!< CTMRA7C0INT (Bit 14) */
#define CTIMER_INTEN_CTMRA7C0INT_Msk (0x4000UL) /*!< CTMRA7C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTEN_CTMRB6C0INT_Pos (13UL) /*!< CTMRB6C0INT (Bit 13) */
#define CTIMER_INTEN_CTMRB6C0INT_Msk (0x2000UL) /*!< CTMRB6C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTEN_CTMRA6C0INT_Pos (12UL) /*!< CTMRA6C0INT (Bit 12) */
#define CTIMER_INTEN_CTMRA6C0INT_Msk (0x1000UL) /*!< CTMRA6C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTEN_CTMRB5C0INT_Pos (11UL) /*!< CTMRB5C0INT (Bit 11) */
#define CTIMER_INTEN_CTMRB5C0INT_Msk (0x800UL) /*!< CTMRB5C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTEN_CTMRA5C0INT_Pos (10UL) /*!< CTMRA5C0INT (Bit 10) */
#define CTIMER_INTEN_CTMRA5C0INT_Msk (0x400UL) /*!< CTMRA5C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTEN_CTMRB4C0INT_Pos (9UL) /*!< CTMRB4C0INT (Bit 9) */
#define CTIMER_INTEN_CTMRB4C0INT_Msk (0x200UL) /*!< CTMRB4C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTEN_CTMRA4C0INT_Pos (8UL) /*!< CTMRA4C0INT (Bit 8) */
#define CTIMER_INTEN_CTMRA4C0INT_Msk (0x100UL) /*!< CTMRA4C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTEN_CTMRB3C0INT_Pos (7UL) /*!< CTMRB3C0INT (Bit 7) */
#define CTIMER_INTEN_CTMRB3C0INT_Msk (0x80UL) /*!< CTMRB3C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTEN_CTMRA3C0INT_Pos (6UL) /*!< CTMRA3C0INT (Bit 6) */
#define CTIMER_INTEN_CTMRA3C0INT_Msk (0x40UL) /*!< CTMRA3C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTEN_CTMRB2C0INT_Pos (5UL) /*!< CTMRB2C0INT (Bit 5) */
#define CTIMER_INTEN_CTMRB2C0INT_Msk (0x20UL) /*!< CTMRB2C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTEN_CTMRA2C0INT_Pos (4UL) /*!< CTMRA2C0INT (Bit 4) */
#define CTIMER_INTEN_CTMRA2C0INT_Msk (0x10UL) /*!< CTMRA2C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTEN_CTMRB1C0INT_Pos (3UL) /*!< CTMRB1C0INT (Bit 3) */
#define CTIMER_INTEN_CTMRB1C0INT_Msk (0x8UL) /*!< CTMRB1C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTEN_CTMRA1C0INT_Pos (2UL) /*!< CTMRA1C0INT (Bit 2) */
#define CTIMER_INTEN_CTMRA1C0INT_Msk (0x4UL) /*!< CTMRA1C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTEN_CTMRB0C0INT_Pos (1UL) /*!< CTMRB0C0INT (Bit 1) */
#define CTIMER_INTEN_CTMRB0C0INT_Msk (0x2UL) /*!< CTMRB0C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTEN_CTMRA0C0INT_Pos (0UL) /*!< CTMRA0C0INT (Bit 0) */
#define CTIMER_INTEN_CTMRA0C0INT_Msk (0x1UL) /*!< CTMRA0C0INT (Bitfield-Mask: 0x01) */
/* ======================================================== INTSTAT ======================================================== */
#define CTIMER_INTSTAT_CTMRB7C1INT_Pos (31UL) /*!< CTMRB7C1INT (Bit 31) */
#define CTIMER_INTSTAT_CTMRB7C1INT_Msk (0x80000000UL) /*!< CTMRB7C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSTAT_CTMRA7C1INT_Pos (30UL) /*!< CTMRA7C1INT (Bit 30) */
#define CTIMER_INTSTAT_CTMRA7C1INT_Msk (0x40000000UL) /*!< CTMRA7C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSTAT_CTMRB6C1INT_Pos (29UL) /*!< CTMRB6C1INT (Bit 29) */
#define CTIMER_INTSTAT_CTMRB6C1INT_Msk (0x20000000UL) /*!< CTMRB6C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSTAT_CTMRA6C1INT_Pos (28UL) /*!< CTMRA6C1INT (Bit 28) */
#define CTIMER_INTSTAT_CTMRA6C1INT_Msk (0x10000000UL) /*!< CTMRA6C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSTAT_CTMRB5C1INT_Pos (27UL) /*!< CTMRB5C1INT (Bit 27) */
#define CTIMER_INTSTAT_CTMRB5C1INT_Msk (0x8000000UL) /*!< CTMRB5C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSTAT_CTMRA5C1INT_Pos (26UL) /*!< CTMRA5C1INT (Bit 26) */
#define CTIMER_INTSTAT_CTMRA5C1INT_Msk (0x4000000UL) /*!< CTMRA5C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSTAT_CTMRB4C1INT_Pos (25UL) /*!< CTMRB4C1INT (Bit 25) */
#define CTIMER_INTSTAT_CTMRB4C1INT_Msk (0x2000000UL) /*!< CTMRB4C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSTAT_CTMRA4C1INT_Pos (24UL) /*!< CTMRA4C1INT (Bit 24) */
#define CTIMER_INTSTAT_CTMRA4C1INT_Msk (0x1000000UL) /*!< CTMRA4C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSTAT_CTMRB3C1INT_Pos (23UL) /*!< CTMRB3C1INT (Bit 23) */
#define CTIMER_INTSTAT_CTMRB3C1INT_Msk (0x800000UL) /*!< CTMRB3C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSTAT_CTMRA3C1INT_Pos (22UL) /*!< CTMRA3C1INT (Bit 22) */
#define CTIMER_INTSTAT_CTMRA3C1INT_Msk (0x400000UL) /*!< CTMRA3C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSTAT_CTMRB2C1INT_Pos (21UL) /*!< CTMRB2C1INT (Bit 21) */
#define CTIMER_INTSTAT_CTMRB2C1INT_Msk (0x200000UL) /*!< CTMRB2C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSTAT_CTMRA2C1INT_Pos (20UL) /*!< CTMRA2C1INT (Bit 20) */
#define CTIMER_INTSTAT_CTMRA2C1INT_Msk (0x100000UL) /*!< CTMRA2C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSTAT_CTMRB1C1INT_Pos (19UL) /*!< CTMRB1C1INT (Bit 19) */
#define CTIMER_INTSTAT_CTMRB1C1INT_Msk (0x80000UL) /*!< CTMRB1C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSTAT_CTMRA1C1INT_Pos (18UL) /*!< CTMRA1C1INT (Bit 18) */
#define CTIMER_INTSTAT_CTMRA1C1INT_Msk (0x40000UL) /*!< CTMRA1C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSTAT_CTMRB0C1INT_Pos (17UL) /*!< CTMRB0C1INT (Bit 17) */
#define CTIMER_INTSTAT_CTMRB0C1INT_Msk (0x20000UL) /*!< CTMRB0C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSTAT_CTMRA0C1INT_Pos (16UL) /*!< CTMRA0C1INT (Bit 16) */
#define CTIMER_INTSTAT_CTMRA0C1INT_Msk (0x10000UL) /*!< CTMRA0C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSTAT_CTMRB7C0INT_Pos (15UL) /*!< CTMRB7C0INT (Bit 15) */
#define CTIMER_INTSTAT_CTMRB7C0INT_Msk (0x8000UL) /*!< CTMRB7C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSTAT_CTMRA7C0INT_Pos (14UL) /*!< CTMRA7C0INT (Bit 14) */
#define CTIMER_INTSTAT_CTMRA7C0INT_Msk (0x4000UL) /*!< CTMRA7C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSTAT_CTMRB6C0INT_Pos (13UL) /*!< CTMRB6C0INT (Bit 13) */
#define CTIMER_INTSTAT_CTMRB6C0INT_Msk (0x2000UL) /*!< CTMRB6C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSTAT_CTMRA6C0INT_Pos (12UL) /*!< CTMRA6C0INT (Bit 12) */
#define CTIMER_INTSTAT_CTMRA6C0INT_Msk (0x1000UL) /*!< CTMRA6C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSTAT_CTMRB5C0INT_Pos (11UL) /*!< CTMRB5C0INT (Bit 11) */
#define CTIMER_INTSTAT_CTMRB5C0INT_Msk (0x800UL) /*!< CTMRB5C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSTAT_CTMRA5C0INT_Pos (10UL) /*!< CTMRA5C0INT (Bit 10) */
#define CTIMER_INTSTAT_CTMRA5C0INT_Msk (0x400UL) /*!< CTMRA5C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSTAT_CTMRB4C0INT_Pos (9UL) /*!< CTMRB4C0INT (Bit 9) */
#define CTIMER_INTSTAT_CTMRB4C0INT_Msk (0x200UL) /*!< CTMRB4C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSTAT_CTMRA4C0INT_Pos (8UL) /*!< CTMRA4C0INT (Bit 8) */
#define CTIMER_INTSTAT_CTMRA4C0INT_Msk (0x100UL) /*!< CTMRA4C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSTAT_CTMRB3C0INT_Pos (7UL) /*!< CTMRB3C0INT (Bit 7) */
#define CTIMER_INTSTAT_CTMRB3C0INT_Msk (0x80UL) /*!< CTMRB3C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSTAT_CTMRA3C0INT_Pos (6UL) /*!< CTMRA3C0INT (Bit 6) */
#define CTIMER_INTSTAT_CTMRA3C0INT_Msk (0x40UL) /*!< CTMRA3C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSTAT_CTMRB2C0INT_Pos (5UL) /*!< CTMRB2C0INT (Bit 5) */
#define CTIMER_INTSTAT_CTMRB2C0INT_Msk (0x20UL) /*!< CTMRB2C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSTAT_CTMRA2C0INT_Pos (4UL) /*!< CTMRA2C0INT (Bit 4) */
#define CTIMER_INTSTAT_CTMRA2C0INT_Msk (0x10UL) /*!< CTMRA2C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSTAT_CTMRB1C0INT_Pos (3UL) /*!< CTMRB1C0INT (Bit 3) */
#define CTIMER_INTSTAT_CTMRB1C0INT_Msk (0x8UL) /*!< CTMRB1C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSTAT_CTMRA1C0INT_Pos (2UL) /*!< CTMRA1C0INT (Bit 2) */
#define CTIMER_INTSTAT_CTMRA1C0INT_Msk (0x4UL) /*!< CTMRA1C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSTAT_CTMRB0C0INT_Pos (1UL) /*!< CTMRB0C0INT (Bit 1) */
#define CTIMER_INTSTAT_CTMRB0C0INT_Msk (0x2UL) /*!< CTMRB0C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSTAT_CTMRA0C0INT_Pos (0UL) /*!< CTMRA0C0INT (Bit 0) */
#define CTIMER_INTSTAT_CTMRA0C0INT_Msk (0x1UL) /*!< CTMRA0C0INT (Bitfield-Mask: 0x01) */
/* ======================================================== INTCLR ========================================================= */
#define CTIMER_INTCLR_CTMRB7C1INT_Pos (31UL) /*!< CTMRB7C1INT (Bit 31) */
#define CTIMER_INTCLR_CTMRB7C1INT_Msk (0x80000000UL) /*!< CTMRB7C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTCLR_CTMRA7C1INT_Pos (30UL) /*!< CTMRA7C1INT (Bit 30) */
#define CTIMER_INTCLR_CTMRA7C1INT_Msk (0x40000000UL) /*!< CTMRA7C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTCLR_CTMRB6C1INT_Pos (29UL) /*!< CTMRB6C1INT (Bit 29) */
#define CTIMER_INTCLR_CTMRB6C1INT_Msk (0x20000000UL) /*!< CTMRB6C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTCLR_CTMRA6C1INT_Pos (28UL) /*!< CTMRA6C1INT (Bit 28) */
#define CTIMER_INTCLR_CTMRA6C1INT_Msk (0x10000000UL) /*!< CTMRA6C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTCLR_CTMRB5C1INT_Pos (27UL) /*!< CTMRB5C1INT (Bit 27) */
#define CTIMER_INTCLR_CTMRB5C1INT_Msk (0x8000000UL) /*!< CTMRB5C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTCLR_CTMRA5C1INT_Pos (26UL) /*!< CTMRA5C1INT (Bit 26) */
#define CTIMER_INTCLR_CTMRA5C1INT_Msk (0x4000000UL) /*!< CTMRA5C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTCLR_CTMRB4C1INT_Pos (25UL) /*!< CTMRB4C1INT (Bit 25) */
#define CTIMER_INTCLR_CTMRB4C1INT_Msk (0x2000000UL) /*!< CTMRB4C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTCLR_CTMRA4C1INT_Pos (24UL) /*!< CTMRA4C1INT (Bit 24) */
#define CTIMER_INTCLR_CTMRA4C1INT_Msk (0x1000000UL) /*!< CTMRA4C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTCLR_CTMRB3C1INT_Pos (23UL) /*!< CTMRB3C1INT (Bit 23) */
#define CTIMER_INTCLR_CTMRB3C1INT_Msk (0x800000UL) /*!< CTMRB3C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTCLR_CTMRA3C1INT_Pos (22UL) /*!< CTMRA3C1INT (Bit 22) */
#define CTIMER_INTCLR_CTMRA3C1INT_Msk (0x400000UL) /*!< CTMRA3C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTCLR_CTMRB2C1INT_Pos (21UL) /*!< CTMRB2C1INT (Bit 21) */
#define CTIMER_INTCLR_CTMRB2C1INT_Msk (0x200000UL) /*!< CTMRB2C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTCLR_CTMRA2C1INT_Pos (20UL) /*!< CTMRA2C1INT (Bit 20) */
#define CTIMER_INTCLR_CTMRA2C1INT_Msk (0x100000UL) /*!< CTMRA2C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTCLR_CTMRB1C1INT_Pos (19UL) /*!< CTMRB1C1INT (Bit 19) */
#define CTIMER_INTCLR_CTMRB1C1INT_Msk (0x80000UL) /*!< CTMRB1C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTCLR_CTMRA1C1INT_Pos (18UL) /*!< CTMRA1C1INT (Bit 18) */
#define CTIMER_INTCLR_CTMRA1C1INT_Msk (0x40000UL) /*!< CTMRA1C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTCLR_CTMRB0C1INT_Pos (17UL) /*!< CTMRB0C1INT (Bit 17) */
#define CTIMER_INTCLR_CTMRB0C1INT_Msk (0x20000UL) /*!< CTMRB0C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTCLR_CTMRA0C1INT_Pos (16UL) /*!< CTMRA0C1INT (Bit 16) */
#define CTIMER_INTCLR_CTMRA0C1INT_Msk (0x10000UL) /*!< CTMRA0C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTCLR_CTMRB7C0INT_Pos (15UL) /*!< CTMRB7C0INT (Bit 15) */
#define CTIMER_INTCLR_CTMRB7C0INT_Msk (0x8000UL) /*!< CTMRB7C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTCLR_CTMRA7C0INT_Pos (14UL) /*!< CTMRA7C0INT (Bit 14) */
#define CTIMER_INTCLR_CTMRA7C0INT_Msk (0x4000UL) /*!< CTMRA7C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTCLR_CTMRB6C0INT_Pos (13UL) /*!< CTMRB6C0INT (Bit 13) */
#define CTIMER_INTCLR_CTMRB6C0INT_Msk (0x2000UL) /*!< CTMRB6C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTCLR_CTMRA6C0INT_Pos (12UL) /*!< CTMRA6C0INT (Bit 12) */
#define CTIMER_INTCLR_CTMRA6C0INT_Msk (0x1000UL) /*!< CTMRA6C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTCLR_CTMRB5C0INT_Pos (11UL) /*!< CTMRB5C0INT (Bit 11) */
#define CTIMER_INTCLR_CTMRB5C0INT_Msk (0x800UL) /*!< CTMRB5C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTCLR_CTMRA5C0INT_Pos (10UL) /*!< CTMRA5C0INT (Bit 10) */
#define CTIMER_INTCLR_CTMRA5C0INT_Msk (0x400UL) /*!< CTMRA5C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTCLR_CTMRB4C0INT_Pos (9UL) /*!< CTMRB4C0INT (Bit 9) */
#define CTIMER_INTCLR_CTMRB4C0INT_Msk (0x200UL) /*!< CTMRB4C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTCLR_CTMRA4C0INT_Pos (8UL) /*!< CTMRA4C0INT (Bit 8) */
#define CTIMER_INTCLR_CTMRA4C0INT_Msk (0x100UL) /*!< CTMRA4C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTCLR_CTMRB3C0INT_Pos (7UL) /*!< CTMRB3C0INT (Bit 7) */
#define CTIMER_INTCLR_CTMRB3C0INT_Msk (0x80UL) /*!< CTMRB3C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTCLR_CTMRA3C0INT_Pos (6UL) /*!< CTMRA3C0INT (Bit 6) */
#define CTIMER_INTCLR_CTMRA3C0INT_Msk (0x40UL) /*!< CTMRA3C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTCLR_CTMRB2C0INT_Pos (5UL) /*!< CTMRB2C0INT (Bit 5) */
#define CTIMER_INTCLR_CTMRB2C0INT_Msk (0x20UL) /*!< CTMRB2C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTCLR_CTMRA2C0INT_Pos (4UL) /*!< CTMRA2C0INT (Bit 4) */
#define CTIMER_INTCLR_CTMRA2C0INT_Msk (0x10UL) /*!< CTMRA2C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTCLR_CTMRB1C0INT_Pos (3UL) /*!< CTMRB1C0INT (Bit 3) */
#define CTIMER_INTCLR_CTMRB1C0INT_Msk (0x8UL) /*!< CTMRB1C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTCLR_CTMRA1C0INT_Pos (2UL) /*!< CTMRA1C0INT (Bit 2) */
#define CTIMER_INTCLR_CTMRA1C0INT_Msk (0x4UL) /*!< CTMRA1C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTCLR_CTMRB0C0INT_Pos (1UL) /*!< CTMRB0C0INT (Bit 1) */
#define CTIMER_INTCLR_CTMRB0C0INT_Msk (0x2UL) /*!< CTMRB0C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTCLR_CTMRA0C0INT_Pos (0UL) /*!< CTMRA0C0INT (Bit 0) */
#define CTIMER_INTCLR_CTMRA0C0INT_Msk (0x1UL) /*!< CTMRA0C0INT (Bitfield-Mask: 0x01) */
/* ======================================================== INTSET ========================================================= */
#define CTIMER_INTSET_CTMRB7C1INT_Pos (31UL) /*!< CTMRB7C1INT (Bit 31) */
#define CTIMER_INTSET_CTMRB7C1INT_Msk (0x80000000UL) /*!< CTMRB7C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSET_CTMRA7C1INT_Pos (30UL) /*!< CTMRA7C1INT (Bit 30) */
#define CTIMER_INTSET_CTMRA7C1INT_Msk (0x40000000UL) /*!< CTMRA7C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSET_CTMRB6C1INT_Pos (29UL) /*!< CTMRB6C1INT (Bit 29) */
#define CTIMER_INTSET_CTMRB6C1INT_Msk (0x20000000UL) /*!< CTMRB6C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSET_CTMRA6C1INT_Pos (28UL) /*!< CTMRA6C1INT (Bit 28) */
#define CTIMER_INTSET_CTMRA6C1INT_Msk (0x10000000UL) /*!< CTMRA6C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSET_CTMRB5C1INT_Pos (27UL) /*!< CTMRB5C1INT (Bit 27) */
#define CTIMER_INTSET_CTMRB5C1INT_Msk (0x8000000UL) /*!< CTMRB5C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSET_CTMRA5C1INT_Pos (26UL) /*!< CTMRA5C1INT (Bit 26) */
#define CTIMER_INTSET_CTMRA5C1INT_Msk (0x4000000UL) /*!< CTMRA5C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSET_CTMRB4C1INT_Pos (25UL) /*!< CTMRB4C1INT (Bit 25) */
#define CTIMER_INTSET_CTMRB4C1INT_Msk (0x2000000UL) /*!< CTMRB4C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSET_CTMRA4C1INT_Pos (24UL) /*!< CTMRA4C1INT (Bit 24) */
#define CTIMER_INTSET_CTMRA4C1INT_Msk (0x1000000UL) /*!< CTMRA4C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSET_CTMRB3C1INT_Pos (23UL) /*!< CTMRB3C1INT (Bit 23) */
#define CTIMER_INTSET_CTMRB3C1INT_Msk (0x800000UL) /*!< CTMRB3C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSET_CTMRA3C1INT_Pos (22UL) /*!< CTMRA3C1INT (Bit 22) */
#define CTIMER_INTSET_CTMRA3C1INT_Msk (0x400000UL) /*!< CTMRA3C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSET_CTMRB2C1INT_Pos (21UL) /*!< CTMRB2C1INT (Bit 21) */
#define CTIMER_INTSET_CTMRB2C1INT_Msk (0x200000UL) /*!< CTMRB2C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSET_CTMRA2C1INT_Pos (20UL) /*!< CTMRA2C1INT (Bit 20) */
#define CTIMER_INTSET_CTMRA2C1INT_Msk (0x100000UL) /*!< CTMRA2C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSET_CTMRB1C1INT_Pos (19UL) /*!< CTMRB1C1INT (Bit 19) */
#define CTIMER_INTSET_CTMRB1C1INT_Msk (0x80000UL) /*!< CTMRB1C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSET_CTMRA1C1INT_Pos (18UL) /*!< CTMRA1C1INT (Bit 18) */
#define CTIMER_INTSET_CTMRA1C1INT_Msk (0x40000UL) /*!< CTMRA1C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSET_CTMRB0C1INT_Pos (17UL) /*!< CTMRB0C1INT (Bit 17) */
#define CTIMER_INTSET_CTMRB0C1INT_Msk (0x20000UL) /*!< CTMRB0C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSET_CTMRA0C1INT_Pos (16UL) /*!< CTMRA0C1INT (Bit 16) */
#define CTIMER_INTSET_CTMRA0C1INT_Msk (0x10000UL) /*!< CTMRA0C1INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSET_CTMRB7C0INT_Pos (15UL) /*!< CTMRB7C0INT (Bit 15) */
#define CTIMER_INTSET_CTMRB7C0INT_Msk (0x8000UL) /*!< CTMRB7C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSET_CTMRA7C0INT_Pos (14UL) /*!< CTMRA7C0INT (Bit 14) */
#define CTIMER_INTSET_CTMRA7C0INT_Msk (0x4000UL) /*!< CTMRA7C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSET_CTMRB6C0INT_Pos (13UL) /*!< CTMRB6C0INT (Bit 13) */
#define CTIMER_INTSET_CTMRB6C0INT_Msk (0x2000UL) /*!< CTMRB6C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSET_CTMRA6C0INT_Pos (12UL) /*!< CTMRA6C0INT (Bit 12) */
#define CTIMER_INTSET_CTMRA6C0INT_Msk (0x1000UL) /*!< CTMRA6C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSET_CTMRB5C0INT_Pos (11UL) /*!< CTMRB5C0INT (Bit 11) */
#define CTIMER_INTSET_CTMRB5C0INT_Msk (0x800UL) /*!< CTMRB5C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSET_CTMRA5C0INT_Pos (10UL) /*!< CTMRA5C0INT (Bit 10) */
#define CTIMER_INTSET_CTMRA5C0INT_Msk (0x400UL) /*!< CTMRA5C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSET_CTMRB4C0INT_Pos (9UL) /*!< CTMRB4C0INT (Bit 9) */
#define CTIMER_INTSET_CTMRB4C0INT_Msk (0x200UL) /*!< CTMRB4C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSET_CTMRA4C0INT_Pos (8UL) /*!< CTMRA4C0INT (Bit 8) */
#define CTIMER_INTSET_CTMRA4C0INT_Msk (0x100UL) /*!< CTMRA4C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSET_CTMRB3C0INT_Pos (7UL) /*!< CTMRB3C0INT (Bit 7) */
#define CTIMER_INTSET_CTMRB3C0INT_Msk (0x80UL) /*!< CTMRB3C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSET_CTMRA3C0INT_Pos (6UL) /*!< CTMRA3C0INT (Bit 6) */
#define CTIMER_INTSET_CTMRA3C0INT_Msk (0x40UL) /*!< CTMRA3C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSET_CTMRB2C0INT_Pos (5UL) /*!< CTMRB2C0INT (Bit 5) */
#define CTIMER_INTSET_CTMRB2C0INT_Msk (0x20UL) /*!< CTMRB2C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSET_CTMRA2C0INT_Pos (4UL) /*!< CTMRA2C0INT (Bit 4) */
#define CTIMER_INTSET_CTMRA2C0INT_Msk (0x10UL) /*!< CTMRA2C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSET_CTMRB1C0INT_Pos (3UL) /*!< CTMRB1C0INT (Bit 3) */
#define CTIMER_INTSET_CTMRB1C0INT_Msk (0x8UL) /*!< CTMRB1C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSET_CTMRA1C0INT_Pos (2UL) /*!< CTMRA1C0INT (Bit 2) */
#define CTIMER_INTSET_CTMRA1C0INT_Msk (0x4UL) /*!< CTMRA1C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSET_CTMRB0C0INT_Pos (1UL) /*!< CTMRB0C0INT (Bit 1) */
#define CTIMER_INTSET_CTMRB0C0INT_Msk (0x2UL) /*!< CTMRB0C0INT (Bitfield-Mask: 0x01) */
#define CTIMER_INTSET_CTMRA0C0INT_Pos (0UL) /*!< CTMRA0C0INT (Bit 0) */
#define CTIMER_INTSET_CTMRA0C0INT_Msk (0x1UL) /*!< CTMRA0C0INT (Bitfield-Mask: 0x01) */
/* ======================================================= STMINTEN ======================================================== */
#define CTIMER_STMINTEN_CAPTURED_Pos (12UL) /*!< CAPTURED (Bit 12) */
#define CTIMER_STMINTEN_CAPTURED_Msk (0x1000UL) /*!< CAPTURED (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTEN_CAPTUREC_Pos (11UL) /*!< CAPTUREC (Bit 11) */
#define CTIMER_STMINTEN_CAPTUREC_Msk (0x800UL) /*!< CAPTUREC (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTEN_CAPTUREB_Pos (10UL) /*!< CAPTUREB (Bit 10) */
#define CTIMER_STMINTEN_CAPTUREB_Msk (0x400UL) /*!< CAPTUREB (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTEN_CAPTUREA_Pos (9UL) /*!< CAPTUREA (Bit 9) */
#define CTIMER_STMINTEN_CAPTUREA_Msk (0x200UL) /*!< CAPTUREA (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTEN_OVERFLOW_Pos (8UL) /*!< OVERFLOW (Bit 8) */
#define CTIMER_STMINTEN_OVERFLOW_Msk (0x100UL) /*!< OVERFLOW (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTEN_COMPAREH_Pos (7UL) /*!< COMPAREH (Bit 7) */
#define CTIMER_STMINTEN_COMPAREH_Msk (0x80UL) /*!< COMPAREH (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTEN_COMPAREG_Pos (6UL) /*!< COMPAREG (Bit 6) */
#define CTIMER_STMINTEN_COMPAREG_Msk (0x40UL) /*!< COMPAREG (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTEN_COMPAREF_Pos (5UL) /*!< COMPAREF (Bit 5) */
#define CTIMER_STMINTEN_COMPAREF_Msk (0x20UL) /*!< COMPAREF (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTEN_COMPAREE_Pos (4UL) /*!< COMPAREE (Bit 4) */
#define CTIMER_STMINTEN_COMPAREE_Msk (0x10UL) /*!< COMPAREE (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTEN_COMPARED_Pos (3UL) /*!< COMPARED (Bit 3) */
#define CTIMER_STMINTEN_COMPARED_Msk (0x8UL) /*!< COMPARED (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTEN_COMPAREC_Pos (2UL) /*!< COMPAREC (Bit 2) */
#define CTIMER_STMINTEN_COMPAREC_Msk (0x4UL) /*!< COMPAREC (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTEN_COMPAREB_Pos (1UL) /*!< COMPAREB (Bit 1) */
#define CTIMER_STMINTEN_COMPAREB_Msk (0x2UL) /*!< COMPAREB (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTEN_COMPAREA_Pos (0UL) /*!< COMPAREA (Bit 0) */
#define CTIMER_STMINTEN_COMPAREA_Msk (0x1UL) /*!< COMPAREA (Bitfield-Mask: 0x01) */
/* ====================================================== STMINTSTAT ======================================================= */
#define CTIMER_STMINTSTAT_CAPTURED_Pos (12UL) /*!< CAPTURED (Bit 12) */
#define CTIMER_STMINTSTAT_CAPTURED_Msk (0x1000UL) /*!< CAPTURED (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTSTAT_CAPTUREC_Pos (11UL) /*!< CAPTUREC (Bit 11) */
#define CTIMER_STMINTSTAT_CAPTUREC_Msk (0x800UL) /*!< CAPTUREC (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTSTAT_CAPTUREB_Pos (10UL) /*!< CAPTUREB (Bit 10) */
#define CTIMER_STMINTSTAT_CAPTUREB_Msk (0x400UL) /*!< CAPTUREB (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTSTAT_CAPTUREA_Pos (9UL) /*!< CAPTUREA (Bit 9) */
#define CTIMER_STMINTSTAT_CAPTUREA_Msk (0x200UL) /*!< CAPTUREA (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTSTAT_OVERFLOW_Pos (8UL) /*!< OVERFLOW (Bit 8) */
#define CTIMER_STMINTSTAT_OVERFLOW_Msk (0x100UL) /*!< OVERFLOW (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTSTAT_COMPAREH_Pos (7UL) /*!< COMPAREH (Bit 7) */
#define CTIMER_STMINTSTAT_COMPAREH_Msk (0x80UL) /*!< COMPAREH (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTSTAT_COMPAREG_Pos (6UL) /*!< COMPAREG (Bit 6) */
#define CTIMER_STMINTSTAT_COMPAREG_Msk (0x40UL) /*!< COMPAREG (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTSTAT_COMPAREF_Pos (5UL) /*!< COMPAREF (Bit 5) */
#define CTIMER_STMINTSTAT_COMPAREF_Msk (0x20UL) /*!< COMPAREF (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTSTAT_COMPAREE_Pos (4UL) /*!< COMPAREE (Bit 4) */
#define CTIMER_STMINTSTAT_COMPAREE_Msk (0x10UL) /*!< COMPAREE (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTSTAT_COMPARED_Pos (3UL) /*!< COMPARED (Bit 3) */
#define CTIMER_STMINTSTAT_COMPARED_Msk (0x8UL) /*!< COMPARED (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTSTAT_COMPAREC_Pos (2UL) /*!< COMPAREC (Bit 2) */
#define CTIMER_STMINTSTAT_COMPAREC_Msk (0x4UL) /*!< COMPAREC (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTSTAT_COMPAREB_Pos (1UL) /*!< COMPAREB (Bit 1) */
#define CTIMER_STMINTSTAT_COMPAREB_Msk (0x2UL) /*!< COMPAREB (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTSTAT_COMPAREA_Pos (0UL) /*!< COMPAREA (Bit 0) */
#define CTIMER_STMINTSTAT_COMPAREA_Msk (0x1UL) /*!< COMPAREA (Bitfield-Mask: 0x01) */
/* ======================================================= STMINTCLR ======================================================= */
#define CTIMER_STMINTCLR_CAPTURED_Pos (12UL) /*!< CAPTURED (Bit 12) */
#define CTIMER_STMINTCLR_CAPTURED_Msk (0x1000UL) /*!< CAPTURED (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTCLR_CAPTUREC_Pos (11UL) /*!< CAPTUREC (Bit 11) */
#define CTIMER_STMINTCLR_CAPTUREC_Msk (0x800UL) /*!< CAPTUREC (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTCLR_CAPTUREB_Pos (10UL) /*!< CAPTUREB (Bit 10) */
#define CTIMER_STMINTCLR_CAPTUREB_Msk (0x400UL) /*!< CAPTUREB (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTCLR_CAPTUREA_Pos (9UL) /*!< CAPTUREA (Bit 9) */
#define CTIMER_STMINTCLR_CAPTUREA_Msk (0x200UL) /*!< CAPTUREA (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTCLR_OVERFLOW_Pos (8UL) /*!< OVERFLOW (Bit 8) */
#define CTIMER_STMINTCLR_OVERFLOW_Msk (0x100UL) /*!< OVERFLOW (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTCLR_COMPAREH_Pos (7UL) /*!< COMPAREH (Bit 7) */
#define CTIMER_STMINTCLR_COMPAREH_Msk (0x80UL) /*!< COMPAREH (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTCLR_COMPAREG_Pos (6UL) /*!< COMPAREG (Bit 6) */
#define CTIMER_STMINTCLR_COMPAREG_Msk (0x40UL) /*!< COMPAREG (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTCLR_COMPAREF_Pos (5UL) /*!< COMPAREF (Bit 5) */
#define CTIMER_STMINTCLR_COMPAREF_Msk (0x20UL) /*!< COMPAREF (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTCLR_COMPAREE_Pos (4UL) /*!< COMPAREE (Bit 4) */
#define CTIMER_STMINTCLR_COMPAREE_Msk (0x10UL) /*!< COMPAREE (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTCLR_COMPARED_Pos (3UL) /*!< COMPARED (Bit 3) */
#define CTIMER_STMINTCLR_COMPARED_Msk (0x8UL) /*!< COMPARED (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTCLR_COMPAREC_Pos (2UL) /*!< COMPAREC (Bit 2) */
#define CTIMER_STMINTCLR_COMPAREC_Msk (0x4UL) /*!< COMPAREC (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTCLR_COMPAREB_Pos (1UL) /*!< COMPAREB (Bit 1) */
#define CTIMER_STMINTCLR_COMPAREB_Msk (0x2UL) /*!< COMPAREB (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTCLR_COMPAREA_Pos (0UL) /*!< COMPAREA (Bit 0) */
#define CTIMER_STMINTCLR_COMPAREA_Msk (0x1UL) /*!< COMPAREA (Bitfield-Mask: 0x01) */
/* ======================================================= STMINTSET ======================================================= */
#define CTIMER_STMINTSET_CAPTURED_Pos (12UL) /*!< CAPTURED (Bit 12) */
#define CTIMER_STMINTSET_CAPTURED_Msk (0x1000UL) /*!< CAPTURED (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTSET_CAPTUREC_Pos (11UL) /*!< CAPTUREC (Bit 11) */
#define CTIMER_STMINTSET_CAPTUREC_Msk (0x800UL) /*!< CAPTUREC (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTSET_CAPTUREB_Pos (10UL) /*!< CAPTUREB (Bit 10) */
#define CTIMER_STMINTSET_CAPTUREB_Msk (0x400UL) /*!< CAPTUREB (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTSET_CAPTUREA_Pos (9UL) /*!< CAPTUREA (Bit 9) */
#define CTIMER_STMINTSET_CAPTUREA_Msk (0x200UL) /*!< CAPTUREA (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTSET_OVERFLOW_Pos (8UL) /*!< OVERFLOW (Bit 8) */
#define CTIMER_STMINTSET_OVERFLOW_Msk (0x100UL) /*!< OVERFLOW (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTSET_COMPAREH_Pos (7UL) /*!< COMPAREH (Bit 7) */
#define CTIMER_STMINTSET_COMPAREH_Msk (0x80UL) /*!< COMPAREH (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTSET_COMPAREG_Pos (6UL) /*!< COMPAREG (Bit 6) */
#define CTIMER_STMINTSET_COMPAREG_Msk (0x40UL) /*!< COMPAREG (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTSET_COMPAREF_Pos (5UL) /*!< COMPAREF (Bit 5) */
#define CTIMER_STMINTSET_COMPAREF_Msk (0x20UL) /*!< COMPAREF (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTSET_COMPAREE_Pos (4UL) /*!< COMPAREE (Bit 4) */
#define CTIMER_STMINTSET_COMPAREE_Msk (0x10UL) /*!< COMPAREE (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTSET_COMPARED_Pos (3UL) /*!< COMPARED (Bit 3) */
#define CTIMER_STMINTSET_COMPARED_Msk (0x8UL) /*!< COMPARED (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTSET_COMPAREC_Pos (2UL) /*!< COMPAREC (Bit 2) */
#define CTIMER_STMINTSET_COMPAREC_Msk (0x4UL) /*!< COMPAREC (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTSET_COMPAREB_Pos (1UL) /*!< COMPAREB (Bit 1) */
#define CTIMER_STMINTSET_COMPAREB_Msk (0x2UL) /*!< COMPAREB (Bitfield-Mask: 0x01) */
#define CTIMER_STMINTSET_COMPAREA_Pos (0UL) /*!< COMPAREA (Bit 0) */
#define CTIMER_STMINTSET_COMPAREA_Msk (0x1UL) /*!< COMPAREA (Bitfield-Mask: 0x01) */
/* =========================================================================================================================== */
/* ================ GPIO ================ */
/* =========================================================================================================================== */
/* ======================================================== PADREGA ======================================================== */
#define GPIO_PADREGA_PAD3PWRUP_Pos (30UL) /*!< PAD3PWRUP (Bit 30) */
#define GPIO_PADREGA_PAD3PWRUP_Msk (0x40000000UL) /*!< PAD3PWRUP (Bitfield-Mask: 0x01) */
#define GPIO_PADREGA_PAD3FNCSEL_Pos (27UL) /*!< PAD3FNCSEL (Bit 27) */
#define GPIO_PADREGA_PAD3FNCSEL_Msk (0x38000000UL) /*!< PAD3FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGA_PAD3STRNG_Pos (26UL) /*!< PAD3STRNG (Bit 26) */
#define GPIO_PADREGA_PAD3STRNG_Msk (0x4000000UL) /*!< PAD3STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGA_PAD3INPEN_Pos (25UL) /*!< PAD3INPEN (Bit 25) */
#define GPIO_PADREGA_PAD3INPEN_Msk (0x2000000UL) /*!< PAD3INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGA_PAD3PULL_Pos (24UL) /*!< PAD3PULL (Bit 24) */
#define GPIO_PADREGA_PAD3PULL_Msk (0x1000000UL) /*!< PAD3PULL (Bitfield-Mask: 0x01) */
#define GPIO_PADREGA_PAD2FNCSEL_Pos (19UL) /*!< PAD2FNCSEL (Bit 19) */
#define GPIO_PADREGA_PAD2FNCSEL_Msk (0x380000UL) /*!< PAD2FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGA_PAD2STRNG_Pos (18UL) /*!< PAD2STRNG (Bit 18) */
#define GPIO_PADREGA_PAD2STRNG_Msk (0x40000UL) /*!< PAD2STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGA_PAD2INPEN_Pos (17UL) /*!< PAD2INPEN (Bit 17) */
#define GPIO_PADREGA_PAD2INPEN_Msk (0x20000UL) /*!< PAD2INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGA_PAD2PULL_Pos (16UL) /*!< PAD2PULL (Bit 16) */
#define GPIO_PADREGA_PAD2PULL_Msk (0x10000UL) /*!< PAD2PULL (Bitfield-Mask: 0x01) */
#define GPIO_PADREGA_PAD1RSEL_Pos (14UL) /*!< PAD1RSEL (Bit 14) */
#define GPIO_PADREGA_PAD1RSEL_Msk (0xc000UL) /*!< PAD1RSEL (Bitfield-Mask: 0x03) */
#define GPIO_PADREGA_PAD1FNCSEL_Pos (11UL) /*!< PAD1FNCSEL (Bit 11) */
#define GPIO_PADREGA_PAD1FNCSEL_Msk (0x3800UL) /*!< PAD1FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGA_PAD1STRNG_Pos (10UL) /*!< PAD1STRNG (Bit 10) */
#define GPIO_PADREGA_PAD1STRNG_Msk (0x400UL) /*!< PAD1STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGA_PAD1INPEN_Pos (9UL) /*!< PAD1INPEN (Bit 9) */
#define GPIO_PADREGA_PAD1INPEN_Msk (0x200UL) /*!< PAD1INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGA_PAD1PULL_Pos (8UL) /*!< PAD1PULL (Bit 8) */
#define GPIO_PADREGA_PAD1PULL_Msk (0x100UL) /*!< PAD1PULL (Bitfield-Mask: 0x01) */
#define GPIO_PADREGA_PAD0RSEL_Pos (6UL) /*!< PAD0RSEL (Bit 6) */
#define GPIO_PADREGA_PAD0RSEL_Msk (0xc0UL) /*!< PAD0RSEL (Bitfield-Mask: 0x03) */
#define GPIO_PADREGA_PAD0FNCSEL_Pos (3UL) /*!< PAD0FNCSEL (Bit 3) */
#define GPIO_PADREGA_PAD0FNCSEL_Msk (0x38UL) /*!< PAD0FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGA_PAD0STRNG_Pos (2UL) /*!< PAD0STRNG (Bit 2) */
#define GPIO_PADREGA_PAD0STRNG_Msk (0x4UL) /*!< PAD0STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGA_PAD0INPEN_Pos (1UL) /*!< PAD0INPEN (Bit 1) */
#define GPIO_PADREGA_PAD0INPEN_Msk (0x2UL) /*!< PAD0INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGA_PAD0PULL_Pos (0UL) /*!< PAD0PULL (Bit 0) */
#define GPIO_PADREGA_PAD0PULL_Msk (0x1UL) /*!< PAD0PULL (Bitfield-Mask: 0x01) */
/* ======================================================== PADREGB ======================================================== */
#define GPIO_PADREGB_PAD7FNCSEL_Pos (27UL) /*!< PAD7FNCSEL (Bit 27) */
#define GPIO_PADREGB_PAD7FNCSEL_Msk (0x38000000UL) /*!< PAD7FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGB_PAD7STRNG_Pos (26UL) /*!< PAD7STRNG (Bit 26) */
#define GPIO_PADREGB_PAD7STRNG_Msk (0x4000000UL) /*!< PAD7STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGB_PAD7INPEN_Pos (25UL) /*!< PAD7INPEN (Bit 25) */
#define GPIO_PADREGB_PAD7INPEN_Msk (0x2000000UL) /*!< PAD7INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGB_PAD7PULL_Pos (24UL) /*!< PAD7PULL (Bit 24) */
#define GPIO_PADREGB_PAD7PULL_Msk (0x1000000UL) /*!< PAD7PULL (Bitfield-Mask: 0x01) */
#define GPIO_PADREGB_PAD6RSEL_Pos (22UL) /*!< PAD6RSEL (Bit 22) */
#define GPIO_PADREGB_PAD6RSEL_Msk (0xc00000UL) /*!< PAD6RSEL (Bitfield-Mask: 0x03) */
#define GPIO_PADREGB_PAD6FNCSEL_Pos (19UL) /*!< PAD6FNCSEL (Bit 19) */
#define GPIO_PADREGB_PAD6FNCSEL_Msk (0x380000UL) /*!< PAD6FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGB_PAD6STRNG_Pos (18UL) /*!< PAD6STRNG (Bit 18) */
#define GPIO_PADREGB_PAD6STRNG_Msk (0x40000UL) /*!< PAD6STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGB_PAD6INPEN_Pos (17UL) /*!< PAD6INPEN (Bit 17) */
#define GPIO_PADREGB_PAD6INPEN_Msk (0x20000UL) /*!< PAD6INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGB_PAD6PULL_Pos (16UL) /*!< PAD6PULL (Bit 16) */
#define GPIO_PADREGB_PAD6PULL_Msk (0x10000UL) /*!< PAD6PULL (Bitfield-Mask: 0x01) */
#define GPIO_PADREGB_PAD5RSEL_Pos (14UL) /*!< PAD5RSEL (Bit 14) */
#define GPIO_PADREGB_PAD5RSEL_Msk (0xc000UL) /*!< PAD5RSEL (Bitfield-Mask: 0x03) */
#define GPIO_PADREGB_PAD5FNCSEL_Pos (11UL) /*!< PAD5FNCSEL (Bit 11) */
#define GPIO_PADREGB_PAD5FNCSEL_Msk (0x3800UL) /*!< PAD5FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGB_PAD5STRNG_Pos (10UL) /*!< PAD5STRNG (Bit 10) */
#define GPIO_PADREGB_PAD5STRNG_Msk (0x400UL) /*!< PAD5STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGB_PAD5INPEN_Pos (9UL) /*!< PAD5INPEN (Bit 9) */
#define GPIO_PADREGB_PAD5INPEN_Msk (0x200UL) /*!< PAD5INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGB_PAD5PULL_Pos (8UL) /*!< PAD5PULL (Bit 8) */
#define GPIO_PADREGB_PAD5PULL_Msk (0x100UL) /*!< PAD5PULL (Bitfield-Mask: 0x01) */
#define GPIO_PADREGB_PAD4FNCSEL_Pos (3UL) /*!< PAD4FNCSEL (Bit 3) */
#define GPIO_PADREGB_PAD4FNCSEL_Msk (0x38UL) /*!< PAD4FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGB_PAD4STRNG_Pos (2UL) /*!< PAD4STRNG (Bit 2) */
#define GPIO_PADREGB_PAD4STRNG_Msk (0x4UL) /*!< PAD4STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGB_PAD4INPEN_Pos (1UL) /*!< PAD4INPEN (Bit 1) */
#define GPIO_PADREGB_PAD4INPEN_Msk (0x2UL) /*!< PAD4INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGB_PAD4PULL_Pos (0UL) /*!< PAD4PULL (Bit 0) */
#define GPIO_PADREGB_PAD4PULL_Msk (0x1UL) /*!< PAD4PULL (Bitfield-Mask: 0x01) */
/* ======================================================== PADREGC ======================================================== */
#define GPIO_PADREGC_PAD11FNCSEL_Pos (27UL) /*!< PAD11FNCSEL (Bit 27) */
#define GPIO_PADREGC_PAD11FNCSEL_Msk (0x38000000UL) /*!< PAD11FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGC_PAD11STRNG_Pos (26UL) /*!< PAD11STRNG (Bit 26) */
#define GPIO_PADREGC_PAD11STRNG_Msk (0x4000000UL) /*!< PAD11STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGC_PAD11INPEN_Pos (25UL) /*!< PAD11INPEN (Bit 25) */
#define GPIO_PADREGC_PAD11INPEN_Msk (0x2000000UL) /*!< PAD11INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGC_PAD11PULL_Pos (24UL) /*!< PAD11PULL (Bit 24) */
#define GPIO_PADREGC_PAD11PULL_Msk (0x1000000UL) /*!< PAD11PULL (Bitfield-Mask: 0x01) */
#define GPIO_PADREGC_PAD10FNCSEL_Pos (19UL) /*!< PAD10FNCSEL (Bit 19) */
#define GPIO_PADREGC_PAD10FNCSEL_Msk (0x380000UL) /*!< PAD10FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGC_PAD10STRNG_Pos (18UL) /*!< PAD10STRNG (Bit 18) */
#define GPIO_PADREGC_PAD10STRNG_Msk (0x40000UL) /*!< PAD10STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGC_PAD10INPEN_Pos (17UL) /*!< PAD10INPEN (Bit 17) */
#define GPIO_PADREGC_PAD10INPEN_Msk (0x20000UL) /*!< PAD10INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGC_PAD10PULL_Pos (16UL) /*!< PAD10PULL (Bit 16) */
#define GPIO_PADREGC_PAD10PULL_Msk (0x10000UL) /*!< PAD10PULL (Bitfield-Mask: 0x01) */
#define GPIO_PADREGC_PAD9RSEL_Pos (14UL) /*!< PAD9RSEL (Bit 14) */
#define GPIO_PADREGC_PAD9RSEL_Msk (0xc000UL) /*!< PAD9RSEL (Bitfield-Mask: 0x03) */
#define GPIO_PADREGC_PAD9FNCSEL_Pos (11UL) /*!< PAD9FNCSEL (Bit 11) */
#define GPIO_PADREGC_PAD9FNCSEL_Msk (0x3800UL) /*!< PAD9FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGC_PAD9STRNG_Pos (10UL) /*!< PAD9STRNG (Bit 10) */
#define GPIO_PADREGC_PAD9STRNG_Msk (0x400UL) /*!< PAD9STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGC_PAD9INPEN_Pos (9UL) /*!< PAD9INPEN (Bit 9) */
#define GPIO_PADREGC_PAD9INPEN_Msk (0x200UL) /*!< PAD9INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGC_PAD9PULL_Pos (8UL) /*!< PAD9PULL (Bit 8) */
#define GPIO_PADREGC_PAD9PULL_Msk (0x100UL) /*!< PAD9PULL (Bitfield-Mask: 0x01) */
#define GPIO_PADREGC_PAD8RSEL_Pos (6UL) /*!< PAD8RSEL (Bit 6) */
#define GPIO_PADREGC_PAD8RSEL_Msk (0xc0UL) /*!< PAD8RSEL (Bitfield-Mask: 0x03) */
#define GPIO_PADREGC_PAD8FNCSEL_Pos (3UL) /*!< PAD8FNCSEL (Bit 3) */
#define GPIO_PADREGC_PAD8FNCSEL_Msk (0x38UL) /*!< PAD8FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGC_PAD8STRNG_Pos (2UL) /*!< PAD8STRNG (Bit 2) */
#define GPIO_PADREGC_PAD8STRNG_Msk (0x4UL) /*!< PAD8STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGC_PAD8INPEN_Pos (1UL) /*!< PAD8INPEN (Bit 1) */
#define GPIO_PADREGC_PAD8INPEN_Msk (0x2UL) /*!< PAD8INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGC_PAD8PULL_Pos (0UL) /*!< PAD8PULL (Bit 0) */
#define GPIO_PADREGC_PAD8PULL_Msk (0x1UL) /*!< PAD8PULL (Bitfield-Mask: 0x01) */
/* ======================================================== PADREGD ======================================================== */
#define GPIO_PADREGD_PAD15FNCSEL_Pos (27UL) /*!< PAD15FNCSEL (Bit 27) */
#define GPIO_PADREGD_PAD15FNCSEL_Msk (0x38000000UL) /*!< PAD15FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGD_PAD15STRNG_Pos (26UL) /*!< PAD15STRNG (Bit 26) */
#define GPIO_PADREGD_PAD15STRNG_Msk (0x4000000UL) /*!< PAD15STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGD_PAD15INPEN_Pos (25UL) /*!< PAD15INPEN (Bit 25) */
#define GPIO_PADREGD_PAD15INPEN_Msk (0x2000000UL) /*!< PAD15INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGD_PAD15PULL_Pos (24UL) /*!< PAD15PULL (Bit 24) */
#define GPIO_PADREGD_PAD15PULL_Msk (0x1000000UL) /*!< PAD15PULL (Bitfield-Mask: 0x01) */
#define GPIO_PADREGD_PAD14FNCSEL_Pos (19UL) /*!< PAD14FNCSEL (Bit 19) */
#define GPIO_PADREGD_PAD14FNCSEL_Msk (0x380000UL) /*!< PAD14FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGD_PAD14STRNG_Pos (18UL) /*!< PAD14STRNG (Bit 18) */
#define GPIO_PADREGD_PAD14STRNG_Msk (0x40000UL) /*!< PAD14STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGD_PAD14INPEN_Pos (17UL) /*!< PAD14INPEN (Bit 17) */
#define GPIO_PADREGD_PAD14INPEN_Msk (0x20000UL) /*!< PAD14INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGD_PAD14PULL_Pos (16UL) /*!< PAD14PULL (Bit 16) */
#define GPIO_PADREGD_PAD14PULL_Msk (0x10000UL) /*!< PAD14PULL (Bitfield-Mask: 0x01) */
#define GPIO_PADREGD_PAD13FNCSEL_Pos (11UL) /*!< PAD13FNCSEL (Bit 11) */
#define GPIO_PADREGD_PAD13FNCSEL_Msk (0x3800UL) /*!< PAD13FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGD_PAD13STRNG_Pos (10UL) /*!< PAD13STRNG (Bit 10) */
#define GPIO_PADREGD_PAD13STRNG_Msk (0x400UL) /*!< PAD13STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGD_PAD13INPEN_Pos (9UL) /*!< PAD13INPEN (Bit 9) */
#define GPIO_PADREGD_PAD13INPEN_Msk (0x200UL) /*!< PAD13INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGD_PAD13PULL_Pos (8UL) /*!< PAD13PULL (Bit 8) */
#define GPIO_PADREGD_PAD13PULL_Msk (0x100UL) /*!< PAD13PULL (Bitfield-Mask: 0x01) */
#define GPIO_PADREGD_PAD12FNCSEL_Pos (3UL) /*!< PAD12FNCSEL (Bit 3) */
#define GPIO_PADREGD_PAD12FNCSEL_Msk (0x38UL) /*!< PAD12FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGD_PAD12STRNG_Pos (2UL) /*!< PAD12STRNG (Bit 2) */
#define GPIO_PADREGD_PAD12STRNG_Msk (0x4UL) /*!< PAD12STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGD_PAD12INPEN_Pos (1UL) /*!< PAD12INPEN (Bit 1) */
#define GPIO_PADREGD_PAD12INPEN_Msk (0x2UL) /*!< PAD12INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGD_PAD12PULL_Pos (0UL) /*!< PAD12PULL (Bit 0) */
#define GPIO_PADREGD_PAD12PULL_Msk (0x1UL) /*!< PAD12PULL (Bitfield-Mask: 0x01) */
/* ======================================================== PADREGE ======================================================== */
#define GPIO_PADREGE_PAD19FNCSEL_Pos (27UL) /*!< PAD19FNCSEL (Bit 27) */
#define GPIO_PADREGE_PAD19FNCSEL_Msk (0x38000000UL) /*!< PAD19FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGE_PAD19STRNG_Pos (26UL) /*!< PAD19STRNG (Bit 26) */
#define GPIO_PADREGE_PAD19STRNG_Msk (0x4000000UL) /*!< PAD19STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGE_PAD19INPEN_Pos (25UL) /*!< PAD19INPEN (Bit 25) */
#define GPIO_PADREGE_PAD19INPEN_Msk (0x2000000UL) /*!< PAD19INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGE_PAD19PULL_Pos (24UL) /*!< PAD19PULL (Bit 24) */
#define GPIO_PADREGE_PAD19PULL_Msk (0x1000000UL) /*!< PAD19PULL (Bitfield-Mask: 0x01) */
#define GPIO_PADREGE_PAD18FNCSEL_Pos (19UL) /*!< PAD18FNCSEL (Bit 19) */
#define GPIO_PADREGE_PAD18FNCSEL_Msk (0x380000UL) /*!< PAD18FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGE_PAD18STRNG_Pos (18UL) /*!< PAD18STRNG (Bit 18) */
#define GPIO_PADREGE_PAD18STRNG_Msk (0x40000UL) /*!< PAD18STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGE_PAD18INPEN_Pos (17UL) /*!< PAD18INPEN (Bit 17) */
#define GPIO_PADREGE_PAD18INPEN_Msk (0x20000UL) /*!< PAD18INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGE_PAD18PULL_Pos (16UL) /*!< PAD18PULL (Bit 16) */
#define GPIO_PADREGE_PAD18PULL_Msk (0x10000UL) /*!< PAD18PULL (Bitfield-Mask: 0x01) */
#define GPIO_PADREGE_PAD17FNCSEL_Pos (11UL) /*!< PAD17FNCSEL (Bit 11) */
#define GPIO_PADREGE_PAD17FNCSEL_Msk (0x3800UL) /*!< PAD17FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGE_PAD17STRNG_Pos (10UL) /*!< PAD17STRNG (Bit 10) */
#define GPIO_PADREGE_PAD17STRNG_Msk (0x400UL) /*!< PAD17STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGE_PAD17INPEN_Pos (9UL) /*!< PAD17INPEN (Bit 9) */
#define GPIO_PADREGE_PAD17INPEN_Msk (0x200UL) /*!< PAD17INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGE_PAD17PULL_Pos (8UL) /*!< PAD17PULL (Bit 8) */
#define GPIO_PADREGE_PAD17PULL_Msk (0x100UL) /*!< PAD17PULL (Bitfield-Mask: 0x01) */
#define GPIO_PADREGE_PAD16FNCSEL_Pos (3UL) /*!< PAD16FNCSEL (Bit 3) */
#define GPIO_PADREGE_PAD16FNCSEL_Msk (0x38UL) /*!< PAD16FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGE_PAD16STRNG_Pos (2UL) /*!< PAD16STRNG (Bit 2) */
#define GPIO_PADREGE_PAD16STRNG_Msk (0x4UL) /*!< PAD16STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGE_PAD16INPEN_Pos (1UL) /*!< PAD16INPEN (Bit 1) */
#define GPIO_PADREGE_PAD16INPEN_Msk (0x2UL) /*!< PAD16INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGE_PAD16PULL_Pos (0UL) /*!< PAD16PULL (Bit 0) */
#define GPIO_PADREGE_PAD16PULL_Msk (0x1UL) /*!< PAD16PULL (Bitfield-Mask: 0x01) */
/* ======================================================== PADREGF ======================================================== */
#define GPIO_PADREGF_PAD23FNCSEL_Pos (27UL) /*!< PAD23FNCSEL (Bit 27) */
#define GPIO_PADREGF_PAD23FNCSEL_Msk (0x38000000UL) /*!< PAD23FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGF_PAD23STRNG_Pos (26UL) /*!< PAD23STRNG (Bit 26) */
#define GPIO_PADREGF_PAD23STRNG_Msk (0x4000000UL) /*!< PAD23STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGF_PAD23INPEN_Pos (25UL) /*!< PAD23INPEN (Bit 25) */
#define GPIO_PADREGF_PAD23INPEN_Msk (0x2000000UL) /*!< PAD23INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGF_PAD23PULL_Pos (24UL) /*!< PAD23PULL (Bit 24) */
#define GPIO_PADREGF_PAD23PULL_Msk (0x1000000UL) /*!< PAD23PULL (Bitfield-Mask: 0x01) */
#define GPIO_PADREGF_PAD22FNCSEL_Pos (19UL) /*!< PAD22FNCSEL (Bit 19) */
#define GPIO_PADREGF_PAD22FNCSEL_Msk (0x380000UL) /*!< PAD22FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGF_PAD22STRNG_Pos (18UL) /*!< PAD22STRNG (Bit 18) */
#define GPIO_PADREGF_PAD22STRNG_Msk (0x40000UL) /*!< PAD22STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGF_PAD22INPEN_Pos (17UL) /*!< PAD22INPEN (Bit 17) */
#define GPIO_PADREGF_PAD22INPEN_Msk (0x20000UL) /*!< PAD22INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGF_PAD22PULL_Pos (16UL) /*!< PAD22PULL (Bit 16) */
#define GPIO_PADREGF_PAD22PULL_Msk (0x10000UL) /*!< PAD22PULL (Bitfield-Mask: 0x01) */
#define GPIO_PADREGF_PAD21FNCSEL_Pos (11UL) /*!< PAD21FNCSEL (Bit 11) */
#define GPIO_PADREGF_PAD21FNCSEL_Msk (0x3800UL) /*!< PAD21FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGF_PAD21STRNG_Pos (10UL) /*!< PAD21STRNG (Bit 10) */
#define GPIO_PADREGF_PAD21STRNG_Msk (0x400UL) /*!< PAD21STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGF_PAD21INPEN_Pos (9UL) /*!< PAD21INPEN (Bit 9) */
#define GPIO_PADREGF_PAD21INPEN_Msk (0x200UL) /*!< PAD21INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGF_PAD21PULL_Pos (8UL) /*!< PAD21PULL (Bit 8) */
#define GPIO_PADREGF_PAD21PULL_Msk (0x100UL) /*!< PAD21PULL (Bitfield-Mask: 0x01) */
#define GPIO_PADREGF_PAD20FNCSEL_Pos (3UL) /*!< PAD20FNCSEL (Bit 3) */
#define GPIO_PADREGF_PAD20FNCSEL_Msk (0x38UL) /*!< PAD20FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGF_PAD20STRNG_Pos (2UL) /*!< PAD20STRNG (Bit 2) */
#define GPIO_PADREGF_PAD20STRNG_Msk (0x4UL) /*!< PAD20STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGF_PAD20INPEN_Pos (1UL) /*!< PAD20INPEN (Bit 1) */
#define GPIO_PADREGF_PAD20INPEN_Msk (0x2UL) /*!< PAD20INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGF_PAD20PULL_Pos (0UL) /*!< PAD20PULL (Bit 0) */
#define GPIO_PADREGF_PAD20PULL_Msk (0x1UL) /*!< PAD20PULL (Bitfield-Mask: 0x01) */
/* ======================================================== PADREGG ======================================================== */
#define GPIO_PADREGG_PAD27RSEL_Pos (30UL) /*!< PAD27RSEL (Bit 30) */
#define GPIO_PADREGG_PAD27RSEL_Msk (0xc0000000UL) /*!< PAD27RSEL (Bitfield-Mask: 0x03) */
#define GPIO_PADREGG_PAD27FNCSEL_Pos (27UL) /*!< PAD27FNCSEL (Bit 27) */
#define GPIO_PADREGG_PAD27FNCSEL_Msk (0x38000000UL) /*!< PAD27FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGG_PAD27STRNG_Pos (26UL) /*!< PAD27STRNG (Bit 26) */
#define GPIO_PADREGG_PAD27STRNG_Msk (0x4000000UL) /*!< PAD27STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGG_PAD27INPEN_Pos (25UL) /*!< PAD27INPEN (Bit 25) */
#define GPIO_PADREGG_PAD27INPEN_Msk (0x2000000UL) /*!< PAD27INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGG_PAD27PULL_Pos (24UL) /*!< PAD27PULL (Bit 24) */
#define GPIO_PADREGG_PAD27PULL_Msk (0x1000000UL) /*!< PAD27PULL (Bitfield-Mask: 0x01) */
#define GPIO_PADREGG_PAD26FNCSEL_Pos (19UL) /*!< PAD26FNCSEL (Bit 19) */
#define GPIO_PADREGG_PAD26FNCSEL_Msk (0x380000UL) /*!< PAD26FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGG_PAD26STRNG_Pos (18UL) /*!< PAD26STRNG (Bit 18) */
#define GPIO_PADREGG_PAD26STRNG_Msk (0x40000UL) /*!< PAD26STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGG_PAD26INPEN_Pos (17UL) /*!< PAD26INPEN (Bit 17) */
#define GPIO_PADREGG_PAD26INPEN_Msk (0x20000UL) /*!< PAD26INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGG_PAD26PULL_Pos (16UL) /*!< PAD26PULL (Bit 16) */
#define GPIO_PADREGG_PAD26PULL_Msk (0x10000UL) /*!< PAD26PULL (Bitfield-Mask: 0x01) */
#define GPIO_PADREGG_PAD25RSEL_Pos (14UL) /*!< PAD25RSEL (Bit 14) */
#define GPIO_PADREGG_PAD25RSEL_Msk (0xc000UL) /*!< PAD25RSEL (Bitfield-Mask: 0x03) */
#define GPIO_PADREGG_PAD25FNCSEL_Pos (11UL) /*!< PAD25FNCSEL (Bit 11) */
#define GPIO_PADREGG_PAD25FNCSEL_Msk (0x3800UL) /*!< PAD25FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGG_PAD25STRNG_Pos (10UL) /*!< PAD25STRNG (Bit 10) */
#define GPIO_PADREGG_PAD25STRNG_Msk (0x400UL) /*!< PAD25STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGG_PAD25INPEN_Pos (9UL) /*!< PAD25INPEN (Bit 9) */
#define GPIO_PADREGG_PAD25INPEN_Msk (0x200UL) /*!< PAD25INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGG_PAD25PULL_Pos (8UL) /*!< PAD25PULL (Bit 8) */
#define GPIO_PADREGG_PAD25PULL_Msk (0x100UL) /*!< PAD25PULL (Bitfield-Mask: 0x01) */
#define GPIO_PADREGG_PAD24FNCSEL_Pos (3UL) /*!< PAD24FNCSEL (Bit 3) */
#define GPIO_PADREGG_PAD24FNCSEL_Msk (0x38UL) /*!< PAD24FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGG_PAD24STRNG_Pos (2UL) /*!< PAD24STRNG (Bit 2) */
#define GPIO_PADREGG_PAD24STRNG_Msk (0x4UL) /*!< PAD24STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGG_PAD24INPEN_Pos (1UL) /*!< PAD24INPEN (Bit 1) */
#define GPIO_PADREGG_PAD24INPEN_Msk (0x2UL) /*!< PAD24INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGG_PAD24PULL_Pos (0UL) /*!< PAD24PULL (Bit 0) */
#define GPIO_PADREGG_PAD24PULL_Msk (0x1UL) /*!< PAD24PULL (Bitfield-Mask: 0x01) */
/* ======================================================== PADREGH ======================================================== */
#define GPIO_PADREGH_PAD31FNCSEL_Pos (27UL) /*!< PAD31FNCSEL (Bit 27) */
#define GPIO_PADREGH_PAD31FNCSEL_Msk (0x38000000UL) /*!< PAD31FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGH_PAD31STRNG_Pos (26UL) /*!< PAD31STRNG (Bit 26) */
#define GPIO_PADREGH_PAD31STRNG_Msk (0x4000000UL) /*!< PAD31STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGH_PAD31INPEN_Pos (25UL) /*!< PAD31INPEN (Bit 25) */
#define GPIO_PADREGH_PAD31INPEN_Msk (0x2000000UL) /*!< PAD31INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGH_PAD31PULL_Pos (24UL) /*!< PAD31PULL (Bit 24) */
#define GPIO_PADREGH_PAD31PULL_Msk (0x1000000UL) /*!< PAD31PULL (Bitfield-Mask: 0x01) */
#define GPIO_PADREGH_PAD30FNCSEL_Pos (19UL) /*!< PAD30FNCSEL (Bit 19) */
#define GPIO_PADREGH_PAD30FNCSEL_Msk (0x380000UL) /*!< PAD30FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGH_PAD30STRNG_Pos (18UL) /*!< PAD30STRNG (Bit 18) */
#define GPIO_PADREGH_PAD30STRNG_Msk (0x40000UL) /*!< PAD30STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGH_PAD30INPEN_Pos (17UL) /*!< PAD30INPEN (Bit 17) */
#define GPIO_PADREGH_PAD30INPEN_Msk (0x20000UL) /*!< PAD30INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGH_PAD30PULL_Pos (16UL) /*!< PAD30PULL (Bit 16) */
#define GPIO_PADREGH_PAD30PULL_Msk (0x10000UL) /*!< PAD30PULL (Bitfield-Mask: 0x01) */
#define GPIO_PADREGH_PAD29FNCSEL_Pos (11UL) /*!< PAD29FNCSEL (Bit 11) */
#define GPIO_PADREGH_PAD29FNCSEL_Msk (0x3800UL) /*!< PAD29FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGH_PAD29STRNG_Pos (10UL) /*!< PAD29STRNG (Bit 10) */
#define GPIO_PADREGH_PAD29STRNG_Msk (0x400UL) /*!< PAD29STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGH_PAD29INPEN_Pos (9UL) /*!< PAD29INPEN (Bit 9) */
#define GPIO_PADREGH_PAD29INPEN_Msk (0x200UL) /*!< PAD29INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGH_PAD29PULL_Pos (8UL) /*!< PAD29PULL (Bit 8) */
#define GPIO_PADREGH_PAD29PULL_Msk (0x100UL) /*!< PAD29PULL (Bitfield-Mask: 0x01) */
#define GPIO_PADREGH_PAD28FNCSEL_Pos (3UL) /*!< PAD28FNCSEL (Bit 3) */
#define GPIO_PADREGH_PAD28FNCSEL_Msk (0x38UL) /*!< PAD28FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGH_PAD28STRNG_Pos (2UL) /*!< PAD28STRNG (Bit 2) */
#define GPIO_PADREGH_PAD28STRNG_Msk (0x4UL) /*!< PAD28STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGH_PAD28INPEN_Pos (1UL) /*!< PAD28INPEN (Bit 1) */
#define GPIO_PADREGH_PAD28INPEN_Msk (0x2UL) /*!< PAD28INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGH_PAD28PULL_Pos (0UL) /*!< PAD28PULL (Bit 0) */
#define GPIO_PADREGH_PAD28PULL_Msk (0x1UL) /*!< PAD28PULL (Bitfield-Mask: 0x01) */
/* ======================================================== PADREGI ======================================================== */
#define GPIO_PADREGI_PAD35FNCSEL_Pos (27UL) /*!< PAD35FNCSEL (Bit 27) */
#define GPIO_PADREGI_PAD35FNCSEL_Msk (0x38000000UL) /*!< PAD35FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGI_PAD35STRNG_Pos (26UL) /*!< PAD35STRNG (Bit 26) */
#define GPIO_PADREGI_PAD35STRNG_Msk (0x4000000UL) /*!< PAD35STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGI_PAD35INPEN_Pos (25UL) /*!< PAD35INPEN (Bit 25) */
#define GPIO_PADREGI_PAD35INPEN_Msk (0x2000000UL) /*!< PAD35INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGI_PAD35PULL_Pos (24UL) /*!< PAD35PULL (Bit 24) */
#define GPIO_PADREGI_PAD35PULL_Msk (0x1000000UL) /*!< PAD35PULL (Bitfield-Mask: 0x01) */
#define GPIO_PADREGI_PAD34FNCSEL_Pos (19UL) /*!< PAD34FNCSEL (Bit 19) */
#define GPIO_PADREGI_PAD34FNCSEL_Msk (0x380000UL) /*!< PAD34FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGI_PAD34STRNG_Pos (18UL) /*!< PAD34STRNG (Bit 18) */
#define GPIO_PADREGI_PAD34STRNG_Msk (0x40000UL) /*!< PAD34STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGI_PAD34INPEN_Pos (17UL) /*!< PAD34INPEN (Bit 17) */
#define GPIO_PADREGI_PAD34INPEN_Msk (0x20000UL) /*!< PAD34INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGI_PAD34PULL_Pos (16UL) /*!< PAD34PULL (Bit 16) */
#define GPIO_PADREGI_PAD34PULL_Msk (0x10000UL) /*!< PAD34PULL (Bitfield-Mask: 0x01) */
#define GPIO_PADREGI_PAD33FNCSEL_Pos (11UL) /*!< PAD33FNCSEL (Bit 11) */
#define GPIO_PADREGI_PAD33FNCSEL_Msk (0x3800UL) /*!< PAD33FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGI_PAD33STRNG_Pos (10UL) /*!< PAD33STRNG (Bit 10) */
#define GPIO_PADREGI_PAD33STRNG_Msk (0x400UL) /*!< PAD33STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGI_PAD33INPEN_Pos (9UL) /*!< PAD33INPEN (Bit 9) */
#define GPIO_PADREGI_PAD33INPEN_Msk (0x200UL) /*!< PAD33INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGI_PAD33PULL_Pos (8UL) /*!< PAD33PULL (Bit 8) */
#define GPIO_PADREGI_PAD33PULL_Msk (0x100UL) /*!< PAD33PULL (Bitfield-Mask: 0x01) */
#define GPIO_PADREGI_PAD32FNCSEL_Pos (3UL) /*!< PAD32FNCSEL (Bit 3) */
#define GPIO_PADREGI_PAD32FNCSEL_Msk (0x38UL) /*!< PAD32FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGI_PAD32STRNG_Pos (2UL) /*!< PAD32STRNG (Bit 2) */
#define GPIO_PADREGI_PAD32STRNG_Msk (0x4UL) /*!< PAD32STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGI_PAD32INPEN_Pos (1UL) /*!< PAD32INPEN (Bit 1) */
#define GPIO_PADREGI_PAD32INPEN_Msk (0x2UL) /*!< PAD32INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGI_PAD32PULL_Pos (0UL) /*!< PAD32PULL (Bit 0) */
#define GPIO_PADREGI_PAD32PULL_Msk (0x1UL) /*!< PAD32PULL (Bitfield-Mask: 0x01) */
/* ======================================================== PADREGJ ======================================================== */
#define GPIO_PADREGJ_PAD39RSEL_Pos (30UL) /*!< PAD39RSEL (Bit 30) */
#define GPIO_PADREGJ_PAD39RSEL_Msk (0xc0000000UL) /*!< PAD39RSEL (Bitfield-Mask: 0x03) */
#define GPIO_PADREGJ_PAD39FNCSEL_Pos (27UL) /*!< PAD39FNCSEL (Bit 27) */
#define GPIO_PADREGJ_PAD39FNCSEL_Msk (0x38000000UL) /*!< PAD39FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGJ_PAD39STRNG_Pos (26UL) /*!< PAD39STRNG (Bit 26) */
#define GPIO_PADREGJ_PAD39STRNG_Msk (0x4000000UL) /*!< PAD39STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGJ_PAD39INPEN_Pos (25UL) /*!< PAD39INPEN (Bit 25) */
#define GPIO_PADREGJ_PAD39INPEN_Msk (0x2000000UL) /*!< PAD39INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGJ_PAD39PULL_Pos (24UL) /*!< PAD39PULL (Bit 24) */
#define GPIO_PADREGJ_PAD39PULL_Msk (0x1000000UL) /*!< PAD39PULL (Bitfield-Mask: 0x01) */
#define GPIO_PADREGJ_PAD38FNCSEL_Pos (19UL) /*!< PAD38FNCSEL (Bit 19) */
#define GPIO_PADREGJ_PAD38FNCSEL_Msk (0x380000UL) /*!< PAD38FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGJ_PAD38STRNG_Pos (18UL) /*!< PAD38STRNG (Bit 18) */
#define GPIO_PADREGJ_PAD38STRNG_Msk (0x40000UL) /*!< PAD38STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGJ_PAD38INPEN_Pos (17UL) /*!< PAD38INPEN (Bit 17) */
#define GPIO_PADREGJ_PAD38INPEN_Msk (0x20000UL) /*!< PAD38INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGJ_PAD38PULL_Pos (16UL) /*!< PAD38PULL (Bit 16) */
#define GPIO_PADREGJ_PAD38PULL_Msk (0x10000UL) /*!< PAD38PULL (Bitfield-Mask: 0x01) */
#define GPIO_PADREGJ_PAD37PWRDN_Pos (15UL) /*!< PAD37PWRDN (Bit 15) */
#define GPIO_PADREGJ_PAD37PWRDN_Msk (0x8000UL) /*!< PAD37PWRDN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGJ_PAD37FNCSEL_Pos (11UL) /*!< PAD37FNCSEL (Bit 11) */
#define GPIO_PADREGJ_PAD37FNCSEL_Msk (0x3800UL) /*!< PAD37FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGJ_PAD37STRNG_Pos (10UL) /*!< PAD37STRNG (Bit 10) */
#define GPIO_PADREGJ_PAD37STRNG_Msk (0x400UL) /*!< PAD37STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGJ_PAD37INPEN_Pos (9UL) /*!< PAD37INPEN (Bit 9) */
#define GPIO_PADREGJ_PAD37INPEN_Msk (0x200UL) /*!< PAD37INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGJ_PAD37PULL_Pos (8UL) /*!< PAD37PULL (Bit 8) */
#define GPIO_PADREGJ_PAD37PULL_Msk (0x100UL) /*!< PAD37PULL (Bitfield-Mask: 0x01) */
#define GPIO_PADREGJ_PAD36PWRUP_Pos (6UL) /*!< PAD36PWRUP (Bit 6) */
#define GPIO_PADREGJ_PAD36PWRUP_Msk (0x40UL) /*!< PAD36PWRUP (Bitfield-Mask: 0x01) */
#define GPIO_PADREGJ_PAD36FNCSEL_Pos (3UL) /*!< PAD36FNCSEL (Bit 3) */
#define GPIO_PADREGJ_PAD36FNCSEL_Msk (0x38UL) /*!< PAD36FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGJ_PAD36STRNG_Pos (2UL) /*!< PAD36STRNG (Bit 2) */
#define GPIO_PADREGJ_PAD36STRNG_Msk (0x4UL) /*!< PAD36STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGJ_PAD36INPEN_Pos (1UL) /*!< PAD36INPEN (Bit 1) */
#define GPIO_PADREGJ_PAD36INPEN_Msk (0x2UL) /*!< PAD36INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGJ_PAD36PULL_Pos (0UL) /*!< PAD36PULL (Bit 0) */
#define GPIO_PADREGJ_PAD36PULL_Msk (0x1UL) /*!< PAD36PULL (Bitfield-Mask: 0x01) */
/* ======================================================== PADREGK ======================================================== */
#define GPIO_PADREGK_PAD43RSEL_Pos (30UL) /*!< PAD43RSEL (Bit 30) */
#define GPIO_PADREGK_PAD43RSEL_Msk (0xc0000000UL) /*!< PAD43RSEL (Bitfield-Mask: 0x03) */
#define GPIO_PADREGK_PAD43FNCSEL_Pos (27UL) /*!< PAD43FNCSEL (Bit 27) */
#define GPIO_PADREGK_PAD43FNCSEL_Msk (0x38000000UL) /*!< PAD43FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGK_PAD43STRNG_Pos (26UL) /*!< PAD43STRNG (Bit 26) */
#define GPIO_PADREGK_PAD43STRNG_Msk (0x4000000UL) /*!< PAD43STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGK_PAD43INPEN_Pos (25UL) /*!< PAD43INPEN (Bit 25) */
#define GPIO_PADREGK_PAD43INPEN_Msk (0x2000000UL) /*!< PAD43INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGK_PAD43PULL_Pos (24UL) /*!< PAD43PULL (Bit 24) */
#define GPIO_PADREGK_PAD43PULL_Msk (0x1000000UL) /*!< PAD43PULL (Bitfield-Mask: 0x01) */
#define GPIO_PADREGK_PAD42RSEL_Pos (22UL) /*!< PAD42RSEL (Bit 22) */
#define GPIO_PADREGK_PAD42RSEL_Msk (0xc00000UL) /*!< PAD42RSEL (Bitfield-Mask: 0x03) */
#define GPIO_PADREGK_PAD42FNCSEL_Pos (19UL) /*!< PAD42FNCSEL (Bit 19) */
#define GPIO_PADREGK_PAD42FNCSEL_Msk (0x380000UL) /*!< PAD42FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGK_PAD42STRNG_Pos (18UL) /*!< PAD42STRNG (Bit 18) */
#define GPIO_PADREGK_PAD42STRNG_Msk (0x40000UL) /*!< PAD42STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGK_PAD42INPEN_Pos (17UL) /*!< PAD42INPEN (Bit 17) */
#define GPIO_PADREGK_PAD42INPEN_Msk (0x20000UL) /*!< PAD42INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGK_PAD42PULL_Pos (16UL) /*!< PAD42PULL (Bit 16) */
#define GPIO_PADREGK_PAD42PULL_Msk (0x10000UL) /*!< PAD42PULL (Bitfield-Mask: 0x01) */
#define GPIO_PADREGK_PAD41PWRDN_Pos (15UL) /*!< PAD41PWRDN (Bit 15) */
#define GPIO_PADREGK_PAD41PWRDN_Msk (0x8000UL) /*!< PAD41PWRDN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGK_PAD41FNCSEL_Pos (11UL) /*!< PAD41FNCSEL (Bit 11) */
#define GPIO_PADREGK_PAD41FNCSEL_Msk (0x3800UL) /*!< PAD41FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGK_PAD41STRNG_Pos (10UL) /*!< PAD41STRNG (Bit 10) */
#define GPIO_PADREGK_PAD41STRNG_Msk (0x400UL) /*!< PAD41STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGK_PAD41INPEN_Pos (9UL) /*!< PAD41INPEN (Bit 9) */
#define GPIO_PADREGK_PAD41INPEN_Msk (0x200UL) /*!< PAD41INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGK_PAD41PULL_Pos (8UL) /*!< PAD41PULL (Bit 8) */
#define GPIO_PADREGK_PAD41PULL_Msk (0x100UL) /*!< PAD41PULL (Bitfield-Mask: 0x01) */
#define GPIO_PADREGK_PAD40RSEL_Pos (6UL) /*!< PAD40RSEL (Bit 6) */
#define GPIO_PADREGK_PAD40RSEL_Msk (0xc0UL) /*!< PAD40RSEL (Bitfield-Mask: 0x03) */
#define GPIO_PADREGK_PAD40FNCSEL_Pos (3UL) /*!< PAD40FNCSEL (Bit 3) */
#define GPIO_PADREGK_PAD40FNCSEL_Msk (0x38UL) /*!< PAD40FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGK_PAD40STRNG_Pos (2UL) /*!< PAD40STRNG (Bit 2) */
#define GPIO_PADREGK_PAD40STRNG_Msk (0x4UL) /*!< PAD40STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGK_PAD40INPEN_Pos (1UL) /*!< PAD40INPEN (Bit 1) */
#define GPIO_PADREGK_PAD40INPEN_Msk (0x2UL) /*!< PAD40INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGK_PAD40PULL_Pos (0UL) /*!< PAD40PULL (Bit 0) */
#define GPIO_PADREGK_PAD40PULL_Msk (0x1UL) /*!< PAD40PULL (Bitfield-Mask: 0x01) */
/* ======================================================== PADREGL ======================================================== */
#define GPIO_PADREGL_PAD47FNCSEL_Pos (27UL) /*!< PAD47FNCSEL (Bit 27) */
#define GPIO_PADREGL_PAD47FNCSEL_Msk (0x38000000UL) /*!< PAD47FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGL_PAD47STRNG_Pos (26UL) /*!< PAD47STRNG (Bit 26) */
#define GPIO_PADREGL_PAD47STRNG_Msk (0x4000000UL) /*!< PAD47STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGL_PAD47INPEN_Pos (25UL) /*!< PAD47INPEN (Bit 25) */
#define GPIO_PADREGL_PAD47INPEN_Msk (0x2000000UL) /*!< PAD47INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGL_PAD47PULL_Pos (24UL) /*!< PAD47PULL (Bit 24) */
#define GPIO_PADREGL_PAD47PULL_Msk (0x1000000UL) /*!< PAD47PULL (Bitfield-Mask: 0x01) */
#define GPIO_PADREGL_PAD46FNCSEL_Pos (19UL) /*!< PAD46FNCSEL (Bit 19) */
#define GPIO_PADREGL_PAD46FNCSEL_Msk (0x380000UL) /*!< PAD46FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGL_PAD46STRNG_Pos (18UL) /*!< PAD46STRNG (Bit 18) */
#define GPIO_PADREGL_PAD46STRNG_Msk (0x40000UL) /*!< PAD46STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGL_PAD46INPEN_Pos (17UL) /*!< PAD46INPEN (Bit 17) */
#define GPIO_PADREGL_PAD46INPEN_Msk (0x20000UL) /*!< PAD46INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGL_PAD46PULL_Pos (16UL) /*!< PAD46PULL (Bit 16) */
#define GPIO_PADREGL_PAD46PULL_Msk (0x10000UL) /*!< PAD46PULL (Bitfield-Mask: 0x01) */
#define GPIO_PADREGL_PAD45FNCSEL_Pos (11UL) /*!< PAD45FNCSEL (Bit 11) */
#define GPIO_PADREGL_PAD45FNCSEL_Msk (0x3800UL) /*!< PAD45FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGL_PAD45STRNG_Pos (10UL) /*!< PAD45STRNG (Bit 10) */
#define GPIO_PADREGL_PAD45STRNG_Msk (0x400UL) /*!< PAD45STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGL_PAD45INPEN_Pos (9UL) /*!< PAD45INPEN (Bit 9) */
#define GPIO_PADREGL_PAD45INPEN_Msk (0x200UL) /*!< PAD45INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGL_PAD45PULL_Pos (8UL) /*!< PAD45PULL (Bit 8) */
#define GPIO_PADREGL_PAD45PULL_Msk (0x100UL) /*!< PAD45PULL (Bitfield-Mask: 0x01) */
#define GPIO_PADREGL_PAD44FNCSEL_Pos (3UL) /*!< PAD44FNCSEL (Bit 3) */
#define GPIO_PADREGL_PAD44FNCSEL_Msk (0x38UL) /*!< PAD44FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGL_PAD44STRNG_Pos (2UL) /*!< PAD44STRNG (Bit 2) */
#define GPIO_PADREGL_PAD44STRNG_Msk (0x4UL) /*!< PAD44STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGL_PAD44INPEN_Pos (1UL) /*!< PAD44INPEN (Bit 1) */
#define GPIO_PADREGL_PAD44INPEN_Msk (0x2UL) /*!< PAD44INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGL_PAD44PULL_Pos (0UL) /*!< PAD44PULL (Bit 0) */
#define GPIO_PADREGL_PAD44PULL_Msk (0x1UL) /*!< PAD44PULL (Bitfield-Mask: 0x01) */
/* ======================================================== PADREGM ======================================================== */
#define GPIO_PADREGM_PAD49RSEL_Pos (14UL) /*!< PAD49RSEL (Bit 14) */
#define GPIO_PADREGM_PAD49RSEL_Msk (0xc000UL) /*!< PAD49RSEL (Bitfield-Mask: 0x03) */
#define GPIO_PADREGM_PAD49FNCSEL_Pos (11UL) /*!< PAD49FNCSEL (Bit 11) */
#define GPIO_PADREGM_PAD49FNCSEL_Msk (0x3800UL) /*!< PAD49FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGM_PAD49STRNG_Pos (10UL) /*!< PAD49STRNG (Bit 10) */
#define GPIO_PADREGM_PAD49STRNG_Msk (0x400UL) /*!< PAD49STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGM_PAD49INPEN_Pos (9UL) /*!< PAD49INPEN (Bit 9) */
#define GPIO_PADREGM_PAD49INPEN_Msk (0x200UL) /*!< PAD49INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGM_PAD49PULL_Pos (8UL) /*!< PAD49PULL (Bit 8) */
#define GPIO_PADREGM_PAD49PULL_Msk (0x100UL) /*!< PAD49PULL (Bitfield-Mask: 0x01) */
#define GPIO_PADREGM_PAD48RSEL_Pos (6UL) /*!< PAD48RSEL (Bit 6) */
#define GPIO_PADREGM_PAD48RSEL_Msk (0xc0UL) /*!< PAD48RSEL (Bitfield-Mask: 0x03) */
#define GPIO_PADREGM_PAD48FNCSEL_Pos (3UL) /*!< PAD48FNCSEL (Bit 3) */
#define GPIO_PADREGM_PAD48FNCSEL_Msk (0x38UL) /*!< PAD48FNCSEL (Bitfield-Mask: 0x07) */
#define GPIO_PADREGM_PAD48STRNG_Pos (2UL) /*!< PAD48STRNG (Bit 2) */
#define GPIO_PADREGM_PAD48STRNG_Msk (0x4UL) /*!< PAD48STRNG (Bitfield-Mask: 0x01) */
#define GPIO_PADREGM_PAD48INPEN_Pos (1UL) /*!< PAD48INPEN (Bit 1) */
#define GPIO_PADREGM_PAD48INPEN_Msk (0x2UL) /*!< PAD48INPEN (Bitfield-Mask: 0x01) */
#define GPIO_PADREGM_PAD48PULL_Pos (0UL) /*!< PAD48PULL (Bit 0) */
#define GPIO_PADREGM_PAD48PULL_Msk (0x1UL) /*!< PAD48PULL (Bitfield-Mask: 0x01) */
/* ========================================================= CFGA ========================================================== */
#define GPIO_CFGA_GPIO7INTD_Pos (31UL) /*!< GPIO7INTD (Bit 31) */
#define GPIO_CFGA_GPIO7INTD_Msk (0x80000000UL) /*!< GPIO7INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGA_GPIO7OUTCFG_Pos (29UL) /*!< GPIO7OUTCFG (Bit 29) */
#define GPIO_CFGA_GPIO7OUTCFG_Msk (0x60000000UL) /*!< GPIO7OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGA_GPIO7INCFG_Pos (28UL) /*!< GPIO7INCFG (Bit 28) */
#define GPIO_CFGA_GPIO7INCFG_Msk (0x10000000UL) /*!< GPIO7INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGA_GPIO6INTD_Pos (27UL) /*!< GPIO6INTD (Bit 27) */
#define GPIO_CFGA_GPIO6INTD_Msk (0x8000000UL) /*!< GPIO6INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGA_GPIO6OUTCFG_Pos (25UL) /*!< GPIO6OUTCFG (Bit 25) */
#define GPIO_CFGA_GPIO6OUTCFG_Msk (0x6000000UL) /*!< GPIO6OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGA_GPIO6INCFG_Pos (24UL) /*!< GPIO6INCFG (Bit 24) */
#define GPIO_CFGA_GPIO6INCFG_Msk (0x1000000UL) /*!< GPIO6INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGA_GPIO5INTD_Pos (23UL) /*!< GPIO5INTD (Bit 23) */
#define GPIO_CFGA_GPIO5INTD_Msk (0x800000UL) /*!< GPIO5INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGA_GPIO5OUTCFG_Pos (21UL) /*!< GPIO5OUTCFG (Bit 21) */
#define GPIO_CFGA_GPIO5OUTCFG_Msk (0x600000UL) /*!< GPIO5OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGA_GPIO5INCFG_Pos (20UL) /*!< GPIO5INCFG (Bit 20) */
#define GPIO_CFGA_GPIO5INCFG_Msk (0x100000UL) /*!< GPIO5INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGA_GPIO4INTD_Pos (19UL) /*!< GPIO4INTD (Bit 19) */
#define GPIO_CFGA_GPIO4INTD_Msk (0x80000UL) /*!< GPIO4INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGA_GPIO4OUTCFG_Pos (17UL) /*!< GPIO4OUTCFG (Bit 17) */
#define GPIO_CFGA_GPIO4OUTCFG_Msk (0x60000UL) /*!< GPIO4OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGA_GPIO4INCFG_Pos (16UL) /*!< GPIO4INCFG (Bit 16) */
#define GPIO_CFGA_GPIO4INCFG_Msk (0x10000UL) /*!< GPIO4INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGA_GPIO3INTD_Pos (15UL) /*!< GPIO3INTD (Bit 15) */
#define GPIO_CFGA_GPIO3INTD_Msk (0x8000UL) /*!< GPIO3INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGA_GPIO3OUTCFG_Pos (13UL) /*!< GPIO3OUTCFG (Bit 13) */
#define GPIO_CFGA_GPIO3OUTCFG_Msk (0x6000UL) /*!< GPIO3OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGA_GPIO3INCFG_Pos (12UL) /*!< GPIO3INCFG (Bit 12) */
#define GPIO_CFGA_GPIO3INCFG_Msk (0x1000UL) /*!< GPIO3INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGA_GPIO2INTD_Pos (11UL) /*!< GPIO2INTD (Bit 11) */
#define GPIO_CFGA_GPIO2INTD_Msk (0x800UL) /*!< GPIO2INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGA_GPIO2OUTCFG_Pos (9UL) /*!< GPIO2OUTCFG (Bit 9) */
#define GPIO_CFGA_GPIO2OUTCFG_Msk (0x600UL) /*!< GPIO2OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGA_GPIO2INCFG_Pos (8UL) /*!< GPIO2INCFG (Bit 8) */
#define GPIO_CFGA_GPIO2INCFG_Msk (0x100UL) /*!< GPIO2INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGA_GPIO1INTD_Pos (7UL) /*!< GPIO1INTD (Bit 7) */
#define GPIO_CFGA_GPIO1INTD_Msk (0x80UL) /*!< GPIO1INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGA_GPIO1OUTCFG_Pos (5UL) /*!< GPIO1OUTCFG (Bit 5) */
#define GPIO_CFGA_GPIO1OUTCFG_Msk (0x60UL) /*!< GPIO1OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGA_GPIO1INCFG_Pos (4UL) /*!< GPIO1INCFG (Bit 4) */
#define GPIO_CFGA_GPIO1INCFG_Msk (0x10UL) /*!< GPIO1INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGA_GPIO0INTD_Pos (3UL) /*!< GPIO0INTD (Bit 3) */
#define GPIO_CFGA_GPIO0INTD_Msk (0x8UL) /*!< GPIO0INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGA_GPIO0OUTCFG_Pos (1UL) /*!< GPIO0OUTCFG (Bit 1) */
#define GPIO_CFGA_GPIO0OUTCFG_Msk (0x6UL) /*!< GPIO0OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGA_GPIO0INCFG_Pos (0UL) /*!< GPIO0INCFG (Bit 0) */
#define GPIO_CFGA_GPIO0INCFG_Msk (0x1UL) /*!< GPIO0INCFG (Bitfield-Mask: 0x01) */
/* ========================================================= CFGB ========================================================== */
#define GPIO_CFGB_GPIO15INTD_Pos (31UL) /*!< GPIO15INTD (Bit 31) */
#define GPIO_CFGB_GPIO15INTD_Msk (0x80000000UL) /*!< GPIO15INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGB_GPIO15OUTCFG_Pos (29UL) /*!< GPIO15OUTCFG (Bit 29) */
#define GPIO_CFGB_GPIO15OUTCFG_Msk (0x60000000UL) /*!< GPIO15OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGB_GPIO15INCFG_Pos (28UL) /*!< GPIO15INCFG (Bit 28) */
#define GPIO_CFGB_GPIO15INCFG_Msk (0x10000000UL) /*!< GPIO15INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGB_GPIO14INTD_Pos (27UL) /*!< GPIO14INTD (Bit 27) */
#define GPIO_CFGB_GPIO14INTD_Msk (0x8000000UL) /*!< GPIO14INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGB_GPIO14OUTCFG_Pos (25UL) /*!< GPIO14OUTCFG (Bit 25) */
#define GPIO_CFGB_GPIO14OUTCFG_Msk (0x6000000UL) /*!< GPIO14OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGB_GPIO14INCFG_Pos (24UL) /*!< GPIO14INCFG (Bit 24) */
#define GPIO_CFGB_GPIO14INCFG_Msk (0x1000000UL) /*!< GPIO14INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGB_GPIO13INTD_Pos (23UL) /*!< GPIO13INTD (Bit 23) */
#define GPIO_CFGB_GPIO13INTD_Msk (0x800000UL) /*!< GPIO13INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGB_GPIO13OUTCFG_Pos (21UL) /*!< GPIO13OUTCFG (Bit 21) */
#define GPIO_CFGB_GPIO13OUTCFG_Msk (0x600000UL) /*!< GPIO13OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGB_GPIO13INCFG_Pos (20UL) /*!< GPIO13INCFG (Bit 20) */
#define GPIO_CFGB_GPIO13INCFG_Msk (0x100000UL) /*!< GPIO13INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGB_GPIO12INTD_Pos (19UL) /*!< GPIO12INTD (Bit 19) */
#define GPIO_CFGB_GPIO12INTD_Msk (0x80000UL) /*!< GPIO12INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGB_GPIO12OUTCFG_Pos (17UL) /*!< GPIO12OUTCFG (Bit 17) */
#define GPIO_CFGB_GPIO12OUTCFG_Msk (0x60000UL) /*!< GPIO12OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGB_GPIO12INCFG_Pos (16UL) /*!< GPIO12INCFG (Bit 16) */
#define GPIO_CFGB_GPIO12INCFG_Msk (0x10000UL) /*!< GPIO12INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGB_GPIO11INTD_Pos (15UL) /*!< GPIO11INTD (Bit 15) */
#define GPIO_CFGB_GPIO11INTD_Msk (0x8000UL) /*!< GPIO11INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGB_GPIO11OUTCFG_Pos (13UL) /*!< GPIO11OUTCFG (Bit 13) */
#define GPIO_CFGB_GPIO11OUTCFG_Msk (0x6000UL) /*!< GPIO11OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGB_GPIO11INCFG_Pos (12UL) /*!< GPIO11INCFG (Bit 12) */
#define GPIO_CFGB_GPIO11INCFG_Msk (0x1000UL) /*!< GPIO11INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGB_GPIO10INTD_Pos (11UL) /*!< GPIO10INTD (Bit 11) */
#define GPIO_CFGB_GPIO10INTD_Msk (0x800UL) /*!< GPIO10INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGB_GPIO10OUTCFG_Pos (9UL) /*!< GPIO10OUTCFG (Bit 9) */
#define GPIO_CFGB_GPIO10OUTCFG_Msk (0x600UL) /*!< GPIO10OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGB_GPIO10INCFG_Pos (8UL) /*!< GPIO10INCFG (Bit 8) */
#define GPIO_CFGB_GPIO10INCFG_Msk (0x100UL) /*!< GPIO10INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGB_GPIO9INTD_Pos (7UL) /*!< GPIO9INTD (Bit 7) */
#define GPIO_CFGB_GPIO9INTD_Msk (0x80UL) /*!< GPIO9INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGB_GPIO9OUTCFG_Pos (5UL) /*!< GPIO9OUTCFG (Bit 5) */
#define GPIO_CFGB_GPIO9OUTCFG_Msk (0x60UL) /*!< GPIO9OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGB_GPIO9INCFG_Pos (4UL) /*!< GPIO9INCFG (Bit 4) */
#define GPIO_CFGB_GPIO9INCFG_Msk (0x10UL) /*!< GPIO9INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGB_GPIO8INTD_Pos (3UL) /*!< GPIO8INTD (Bit 3) */
#define GPIO_CFGB_GPIO8INTD_Msk (0x8UL) /*!< GPIO8INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGB_GPIO8OUTCFG_Pos (1UL) /*!< GPIO8OUTCFG (Bit 1) */
#define GPIO_CFGB_GPIO8OUTCFG_Msk (0x6UL) /*!< GPIO8OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGB_GPIO8INCFG_Pos (0UL) /*!< GPIO8INCFG (Bit 0) */
#define GPIO_CFGB_GPIO8INCFG_Msk (0x1UL) /*!< GPIO8INCFG (Bitfield-Mask: 0x01) */
/* ========================================================= CFGC ========================================================== */
#define GPIO_CFGC_GPIO23INTD_Pos (31UL) /*!< GPIO23INTD (Bit 31) */
#define GPIO_CFGC_GPIO23INTD_Msk (0x80000000UL) /*!< GPIO23INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGC_GPIO23OUTCFG_Pos (29UL) /*!< GPIO23OUTCFG (Bit 29) */
#define GPIO_CFGC_GPIO23OUTCFG_Msk (0x60000000UL) /*!< GPIO23OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGC_GPIO23INCFG_Pos (28UL) /*!< GPIO23INCFG (Bit 28) */
#define GPIO_CFGC_GPIO23INCFG_Msk (0x10000000UL) /*!< GPIO23INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGC_GPIO22INTD_Pos (27UL) /*!< GPIO22INTD (Bit 27) */
#define GPIO_CFGC_GPIO22INTD_Msk (0x8000000UL) /*!< GPIO22INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGC_GPIO22OUTCFG_Pos (25UL) /*!< GPIO22OUTCFG (Bit 25) */
#define GPIO_CFGC_GPIO22OUTCFG_Msk (0x6000000UL) /*!< GPIO22OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGC_GPIO22INCFG_Pos (24UL) /*!< GPIO22INCFG (Bit 24) */
#define GPIO_CFGC_GPIO22INCFG_Msk (0x1000000UL) /*!< GPIO22INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGC_GPIO21INTD_Pos (23UL) /*!< GPIO21INTD (Bit 23) */
#define GPIO_CFGC_GPIO21INTD_Msk (0x800000UL) /*!< GPIO21INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGC_GPIO21OUTCFG_Pos (21UL) /*!< GPIO21OUTCFG (Bit 21) */
#define GPIO_CFGC_GPIO21OUTCFG_Msk (0x600000UL) /*!< GPIO21OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGC_GPIO21INCFG_Pos (20UL) /*!< GPIO21INCFG (Bit 20) */
#define GPIO_CFGC_GPIO21INCFG_Msk (0x100000UL) /*!< GPIO21INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGC_GPIO20INTD_Pos (19UL) /*!< GPIO20INTD (Bit 19) */
#define GPIO_CFGC_GPIO20INTD_Msk (0x80000UL) /*!< GPIO20INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGC_GPIO20OUTCFG_Pos (17UL) /*!< GPIO20OUTCFG (Bit 17) */
#define GPIO_CFGC_GPIO20OUTCFG_Msk (0x60000UL) /*!< GPIO20OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGC_GPIO20INCFG_Pos (16UL) /*!< GPIO20INCFG (Bit 16) */
#define GPIO_CFGC_GPIO20INCFG_Msk (0x10000UL) /*!< GPIO20INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGC_GPIO19INTD_Pos (15UL) /*!< GPIO19INTD (Bit 15) */
#define GPIO_CFGC_GPIO19INTD_Msk (0x8000UL) /*!< GPIO19INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGC_GPIO19OUTCFG_Pos (13UL) /*!< GPIO19OUTCFG (Bit 13) */
#define GPIO_CFGC_GPIO19OUTCFG_Msk (0x6000UL) /*!< GPIO19OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGC_GPIO19INCFG_Pos (12UL) /*!< GPIO19INCFG (Bit 12) */
#define GPIO_CFGC_GPIO19INCFG_Msk (0x1000UL) /*!< GPIO19INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGC_GPIO18INTD_Pos (11UL) /*!< GPIO18INTD (Bit 11) */
#define GPIO_CFGC_GPIO18INTD_Msk (0x800UL) /*!< GPIO18INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGC_GPIO18OUTCFG_Pos (9UL) /*!< GPIO18OUTCFG (Bit 9) */
#define GPIO_CFGC_GPIO18OUTCFG_Msk (0x600UL) /*!< GPIO18OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGC_GPIO18INCFG_Pos (8UL) /*!< GPIO18INCFG (Bit 8) */
#define GPIO_CFGC_GPIO18INCFG_Msk (0x100UL) /*!< GPIO18INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGC_GPIO17INTD_Pos (7UL) /*!< GPIO17INTD (Bit 7) */
#define GPIO_CFGC_GPIO17INTD_Msk (0x80UL) /*!< GPIO17INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGC_GPIO17OUTCFG_Pos (5UL) /*!< GPIO17OUTCFG (Bit 5) */
#define GPIO_CFGC_GPIO17OUTCFG_Msk (0x60UL) /*!< GPIO17OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGC_GPIO17INCFG_Pos (4UL) /*!< GPIO17INCFG (Bit 4) */
#define GPIO_CFGC_GPIO17INCFG_Msk (0x10UL) /*!< GPIO17INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGC_GPIO16INTD_Pos (3UL) /*!< GPIO16INTD (Bit 3) */
#define GPIO_CFGC_GPIO16INTD_Msk (0x8UL) /*!< GPIO16INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGC_GPIO16OUTCFG_Pos (1UL) /*!< GPIO16OUTCFG (Bit 1) */
#define GPIO_CFGC_GPIO16OUTCFG_Msk (0x6UL) /*!< GPIO16OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGC_GPIO16INCFG_Pos (0UL) /*!< GPIO16INCFG (Bit 0) */
#define GPIO_CFGC_GPIO16INCFG_Msk (0x1UL) /*!< GPIO16INCFG (Bitfield-Mask: 0x01) */
/* ========================================================= CFGD ========================================================== */
#define GPIO_CFGD_GPIO31INTD_Pos (31UL) /*!< GPIO31INTD (Bit 31) */
#define GPIO_CFGD_GPIO31INTD_Msk (0x80000000UL) /*!< GPIO31INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGD_GPIO31OUTCFG_Pos (29UL) /*!< GPIO31OUTCFG (Bit 29) */
#define GPIO_CFGD_GPIO31OUTCFG_Msk (0x60000000UL) /*!< GPIO31OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGD_GPIO31INCFG_Pos (28UL) /*!< GPIO31INCFG (Bit 28) */
#define GPIO_CFGD_GPIO31INCFG_Msk (0x10000000UL) /*!< GPIO31INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGD_GPIO30INTD_Pos (27UL) /*!< GPIO30INTD (Bit 27) */
#define GPIO_CFGD_GPIO30INTD_Msk (0x8000000UL) /*!< GPIO30INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGD_GPIO30OUTCFG_Pos (25UL) /*!< GPIO30OUTCFG (Bit 25) */
#define GPIO_CFGD_GPIO30OUTCFG_Msk (0x6000000UL) /*!< GPIO30OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGD_GPIO30INCFG_Pos (24UL) /*!< GPIO30INCFG (Bit 24) */
#define GPIO_CFGD_GPIO30INCFG_Msk (0x1000000UL) /*!< GPIO30INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGD_GPIO29INTD_Pos (23UL) /*!< GPIO29INTD (Bit 23) */
#define GPIO_CFGD_GPIO29INTD_Msk (0x800000UL) /*!< GPIO29INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGD_GPIO29OUTCFG_Pos (21UL) /*!< GPIO29OUTCFG (Bit 21) */
#define GPIO_CFGD_GPIO29OUTCFG_Msk (0x600000UL) /*!< GPIO29OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGD_GPIO29INCFG_Pos (20UL) /*!< GPIO29INCFG (Bit 20) */
#define GPIO_CFGD_GPIO29INCFG_Msk (0x100000UL) /*!< GPIO29INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGD_GPIO28INTD_Pos (19UL) /*!< GPIO28INTD (Bit 19) */
#define GPIO_CFGD_GPIO28INTD_Msk (0x80000UL) /*!< GPIO28INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGD_GPIO28OUTCFG_Pos (17UL) /*!< GPIO28OUTCFG (Bit 17) */
#define GPIO_CFGD_GPIO28OUTCFG_Msk (0x60000UL) /*!< GPIO28OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGD_GPIO28INCFG_Pos (16UL) /*!< GPIO28INCFG (Bit 16) */
#define GPIO_CFGD_GPIO28INCFG_Msk (0x10000UL) /*!< GPIO28INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGD_GPIO27INTD_Pos (15UL) /*!< GPIO27INTD (Bit 15) */
#define GPIO_CFGD_GPIO27INTD_Msk (0x8000UL) /*!< GPIO27INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGD_GPIO27OUTCFG_Pos (13UL) /*!< GPIO27OUTCFG (Bit 13) */
#define GPIO_CFGD_GPIO27OUTCFG_Msk (0x6000UL) /*!< GPIO27OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGD_GPIO27INCFG_Pos (12UL) /*!< GPIO27INCFG (Bit 12) */
#define GPIO_CFGD_GPIO27INCFG_Msk (0x1000UL) /*!< GPIO27INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGD_GPIO26INTD_Pos (11UL) /*!< GPIO26INTD (Bit 11) */
#define GPIO_CFGD_GPIO26INTD_Msk (0x800UL) /*!< GPIO26INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGD_GPIO26OUTCFG_Pos (9UL) /*!< GPIO26OUTCFG (Bit 9) */
#define GPIO_CFGD_GPIO26OUTCFG_Msk (0x600UL) /*!< GPIO26OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGD_GPIO26INCFG_Pos (8UL) /*!< GPIO26INCFG (Bit 8) */
#define GPIO_CFGD_GPIO26INCFG_Msk (0x100UL) /*!< GPIO26INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGD_GPIO25INTD_Pos (7UL) /*!< GPIO25INTD (Bit 7) */
#define GPIO_CFGD_GPIO25INTD_Msk (0x80UL) /*!< GPIO25INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGD_GPIO25OUTCFG_Pos (5UL) /*!< GPIO25OUTCFG (Bit 5) */
#define GPIO_CFGD_GPIO25OUTCFG_Msk (0x60UL) /*!< GPIO25OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGD_GPIO25INCFG_Pos (4UL) /*!< GPIO25INCFG (Bit 4) */
#define GPIO_CFGD_GPIO25INCFG_Msk (0x10UL) /*!< GPIO25INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGD_GPIO24INTD_Pos (3UL) /*!< GPIO24INTD (Bit 3) */
#define GPIO_CFGD_GPIO24INTD_Msk (0x8UL) /*!< GPIO24INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGD_GPIO24OUTCFG_Pos (1UL) /*!< GPIO24OUTCFG (Bit 1) */
#define GPIO_CFGD_GPIO24OUTCFG_Msk (0x6UL) /*!< GPIO24OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGD_GPIO24INCFG_Pos (0UL) /*!< GPIO24INCFG (Bit 0) */
#define GPIO_CFGD_GPIO24INCFG_Msk (0x1UL) /*!< GPIO24INCFG (Bitfield-Mask: 0x01) */
/* ========================================================= CFGE ========================================================== */
#define GPIO_CFGE_GPIO39INTD_Pos (31UL) /*!< GPIO39INTD (Bit 31) */
#define GPIO_CFGE_GPIO39INTD_Msk (0x80000000UL) /*!< GPIO39INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGE_GPIO39OUTCFG_Pos (29UL) /*!< GPIO39OUTCFG (Bit 29) */
#define GPIO_CFGE_GPIO39OUTCFG_Msk (0x60000000UL) /*!< GPIO39OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGE_GPIO39INCFG_Pos (28UL) /*!< GPIO39INCFG (Bit 28) */
#define GPIO_CFGE_GPIO39INCFG_Msk (0x10000000UL) /*!< GPIO39INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGE_GPIO38INTD_Pos (27UL) /*!< GPIO38INTD (Bit 27) */
#define GPIO_CFGE_GPIO38INTD_Msk (0x8000000UL) /*!< GPIO38INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGE_GPIO38OUTCFG_Pos (25UL) /*!< GPIO38OUTCFG (Bit 25) */
#define GPIO_CFGE_GPIO38OUTCFG_Msk (0x6000000UL) /*!< GPIO38OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGE_GPIO38INCFG_Pos (24UL) /*!< GPIO38INCFG (Bit 24) */
#define GPIO_CFGE_GPIO38INCFG_Msk (0x1000000UL) /*!< GPIO38INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGE_GPIO37INTD_Pos (23UL) /*!< GPIO37INTD (Bit 23) */
#define GPIO_CFGE_GPIO37INTD_Msk (0x800000UL) /*!< GPIO37INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGE_GPIO37OUTCFG_Pos (21UL) /*!< GPIO37OUTCFG (Bit 21) */
#define GPIO_CFGE_GPIO37OUTCFG_Msk (0x600000UL) /*!< GPIO37OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGE_GPIO37INCFG_Pos (20UL) /*!< GPIO37INCFG (Bit 20) */
#define GPIO_CFGE_GPIO37INCFG_Msk (0x100000UL) /*!< GPIO37INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGE_GPIO36INTD_Pos (19UL) /*!< GPIO36INTD (Bit 19) */
#define GPIO_CFGE_GPIO36INTD_Msk (0x80000UL) /*!< GPIO36INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGE_GPIO36OUTCFG_Pos (17UL) /*!< GPIO36OUTCFG (Bit 17) */
#define GPIO_CFGE_GPIO36OUTCFG_Msk (0x60000UL) /*!< GPIO36OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGE_GPIO36INCFG_Pos (16UL) /*!< GPIO36INCFG (Bit 16) */
#define GPIO_CFGE_GPIO36INCFG_Msk (0x10000UL) /*!< GPIO36INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGE_GPIO35INTD_Pos (15UL) /*!< GPIO35INTD (Bit 15) */
#define GPIO_CFGE_GPIO35INTD_Msk (0x8000UL) /*!< GPIO35INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGE_GPIO35OUTCFG_Pos (13UL) /*!< GPIO35OUTCFG (Bit 13) */
#define GPIO_CFGE_GPIO35OUTCFG_Msk (0x6000UL) /*!< GPIO35OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGE_GPIO35INCFG_Pos (12UL) /*!< GPIO35INCFG (Bit 12) */
#define GPIO_CFGE_GPIO35INCFG_Msk (0x1000UL) /*!< GPIO35INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGE_GPIO34INTD_Pos (11UL) /*!< GPIO34INTD (Bit 11) */
#define GPIO_CFGE_GPIO34INTD_Msk (0x800UL) /*!< GPIO34INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGE_GPIO34OUTCFG_Pos (9UL) /*!< GPIO34OUTCFG (Bit 9) */
#define GPIO_CFGE_GPIO34OUTCFG_Msk (0x600UL) /*!< GPIO34OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGE_GPIO34INCFG_Pos (8UL) /*!< GPIO34INCFG (Bit 8) */
#define GPIO_CFGE_GPIO34INCFG_Msk (0x100UL) /*!< GPIO34INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGE_GPIO33INTD_Pos (7UL) /*!< GPIO33INTD (Bit 7) */
#define GPIO_CFGE_GPIO33INTD_Msk (0x80UL) /*!< GPIO33INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGE_GPIO33OUTCFG_Pos (5UL) /*!< GPIO33OUTCFG (Bit 5) */
#define GPIO_CFGE_GPIO33OUTCFG_Msk (0x60UL) /*!< GPIO33OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGE_GPIO33INCFG_Pos (4UL) /*!< GPIO33INCFG (Bit 4) */
#define GPIO_CFGE_GPIO33INCFG_Msk (0x10UL) /*!< GPIO33INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGE_GPIO32INTD_Pos (3UL) /*!< GPIO32INTD (Bit 3) */
#define GPIO_CFGE_GPIO32INTD_Msk (0x8UL) /*!< GPIO32INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGE_GPIO32OUTCFG_Pos (1UL) /*!< GPIO32OUTCFG (Bit 1) */
#define GPIO_CFGE_GPIO32OUTCFG_Msk (0x6UL) /*!< GPIO32OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGE_GPIO32INCFG_Pos (0UL) /*!< GPIO32INCFG (Bit 0) */
#define GPIO_CFGE_GPIO32INCFG_Msk (0x1UL) /*!< GPIO32INCFG (Bitfield-Mask: 0x01) */
/* ========================================================= CFGF ========================================================== */
#define GPIO_CFGF_GPIO47INTD_Pos (31UL) /*!< GPIO47INTD (Bit 31) */
#define GPIO_CFGF_GPIO47INTD_Msk (0x80000000UL) /*!< GPIO47INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGF_GPIO47OUTCFG_Pos (29UL) /*!< GPIO47OUTCFG (Bit 29) */
#define GPIO_CFGF_GPIO47OUTCFG_Msk (0x60000000UL) /*!< GPIO47OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGF_GPIO47INCFG_Pos (28UL) /*!< GPIO47INCFG (Bit 28) */
#define GPIO_CFGF_GPIO47INCFG_Msk (0x10000000UL) /*!< GPIO47INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGF_GPIO46INTD_Pos (27UL) /*!< GPIO46INTD (Bit 27) */
#define GPIO_CFGF_GPIO46INTD_Msk (0x8000000UL) /*!< GPIO46INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGF_GPIO46OUTCFG_Pos (25UL) /*!< GPIO46OUTCFG (Bit 25) */
#define GPIO_CFGF_GPIO46OUTCFG_Msk (0x6000000UL) /*!< GPIO46OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGF_GPIO46INCFG_Pos (24UL) /*!< GPIO46INCFG (Bit 24) */
#define GPIO_CFGF_GPIO46INCFG_Msk (0x1000000UL) /*!< GPIO46INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGF_GPIO45INTD_Pos (23UL) /*!< GPIO45INTD (Bit 23) */
#define GPIO_CFGF_GPIO45INTD_Msk (0x800000UL) /*!< GPIO45INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGF_GPIO45OUTCFG_Pos (21UL) /*!< GPIO45OUTCFG (Bit 21) */
#define GPIO_CFGF_GPIO45OUTCFG_Msk (0x600000UL) /*!< GPIO45OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGF_GPIO45INCFG_Pos (20UL) /*!< GPIO45INCFG (Bit 20) */
#define GPIO_CFGF_GPIO45INCFG_Msk (0x100000UL) /*!< GPIO45INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGF_GPIO44INTD_Pos (19UL) /*!< GPIO44INTD (Bit 19) */
#define GPIO_CFGF_GPIO44INTD_Msk (0x80000UL) /*!< GPIO44INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGF_GPIO44OUTCFG_Pos (17UL) /*!< GPIO44OUTCFG (Bit 17) */
#define GPIO_CFGF_GPIO44OUTCFG_Msk (0x60000UL) /*!< GPIO44OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGF_GPIO44INCFG_Pos (16UL) /*!< GPIO44INCFG (Bit 16) */
#define GPIO_CFGF_GPIO44INCFG_Msk (0x10000UL) /*!< GPIO44INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGF_GPIO43INTD_Pos (15UL) /*!< GPIO43INTD (Bit 15) */
#define GPIO_CFGF_GPIO43INTD_Msk (0x8000UL) /*!< GPIO43INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGF_GPIO43OUTCFG_Pos (13UL) /*!< GPIO43OUTCFG (Bit 13) */
#define GPIO_CFGF_GPIO43OUTCFG_Msk (0x6000UL) /*!< GPIO43OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGF_GPIO43INCFG_Pos (12UL) /*!< GPIO43INCFG (Bit 12) */
#define GPIO_CFGF_GPIO43INCFG_Msk (0x1000UL) /*!< GPIO43INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGF_GPIO42INTD_Pos (11UL) /*!< GPIO42INTD (Bit 11) */
#define GPIO_CFGF_GPIO42INTD_Msk (0x800UL) /*!< GPIO42INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGF_GPIO42OUTCFG_Pos (9UL) /*!< GPIO42OUTCFG (Bit 9) */
#define GPIO_CFGF_GPIO42OUTCFG_Msk (0x600UL) /*!< GPIO42OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGF_GPIO42INCFG_Pos (8UL) /*!< GPIO42INCFG (Bit 8) */
#define GPIO_CFGF_GPIO42INCFG_Msk (0x100UL) /*!< GPIO42INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGF_GPIO41INTD_Pos (7UL) /*!< GPIO41INTD (Bit 7) */
#define GPIO_CFGF_GPIO41INTD_Msk (0x80UL) /*!< GPIO41INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGF_GPIO41OUTCFG_Pos (5UL) /*!< GPIO41OUTCFG (Bit 5) */
#define GPIO_CFGF_GPIO41OUTCFG_Msk (0x60UL) /*!< GPIO41OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGF_GPIO41INCFG_Pos (4UL) /*!< GPIO41INCFG (Bit 4) */
#define GPIO_CFGF_GPIO41INCFG_Msk (0x10UL) /*!< GPIO41INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGF_GPIO40INTD_Pos (3UL) /*!< GPIO40INTD (Bit 3) */
#define GPIO_CFGF_GPIO40INTD_Msk (0x8UL) /*!< GPIO40INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGF_GPIO40OUTCFG_Pos (1UL) /*!< GPIO40OUTCFG (Bit 1) */
#define GPIO_CFGF_GPIO40OUTCFG_Msk (0x6UL) /*!< GPIO40OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGF_GPIO40INCFG_Pos (0UL) /*!< GPIO40INCFG (Bit 0) */
#define GPIO_CFGF_GPIO40INCFG_Msk (0x1UL) /*!< GPIO40INCFG (Bitfield-Mask: 0x01) */
/* ========================================================= CFGG ========================================================== */
#define GPIO_CFGG_GPIO49INTD_Pos (7UL) /*!< GPIO49INTD (Bit 7) */
#define GPIO_CFGG_GPIO49INTD_Msk (0x80UL) /*!< GPIO49INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGG_GPIO49OUTCFG_Pos (5UL) /*!< GPIO49OUTCFG (Bit 5) */
#define GPIO_CFGG_GPIO49OUTCFG_Msk (0x60UL) /*!< GPIO49OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGG_GPIO49INCFG_Pos (4UL) /*!< GPIO49INCFG (Bit 4) */
#define GPIO_CFGG_GPIO49INCFG_Msk (0x10UL) /*!< GPIO49INCFG (Bitfield-Mask: 0x01) */
#define GPIO_CFGG_GPIO48INTD_Pos (3UL) /*!< GPIO48INTD (Bit 3) */
#define GPIO_CFGG_GPIO48INTD_Msk (0x8UL) /*!< GPIO48INTD (Bitfield-Mask: 0x01) */
#define GPIO_CFGG_GPIO48OUTCFG_Pos (1UL) /*!< GPIO48OUTCFG (Bit 1) */
#define GPIO_CFGG_GPIO48OUTCFG_Msk (0x6UL) /*!< GPIO48OUTCFG (Bitfield-Mask: 0x03) */
#define GPIO_CFGG_GPIO48INCFG_Pos (0UL) /*!< GPIO48INCFG (Bit 0) */
#define GPIO_CFGG_GPIO48INCFG_Msk (0x1UL) /*!< GPIO48INCFG (Bitfield-Mask: 0x01) */
/* ======================================================== PADKEY ========================================================= */
#define GPIO_PADKEY_PADKEY_Pos (0UL) /*!< PADKEY (Bit 0) */
#define GPIO_PADKEY_PADKEY_Msk (0xffffffffUL) /*!< PADKEY (Bitfield-Mask: 0xffffffff) */
/* ========================================================== RDA ========================================================== */
#define GPIO_RDA_RDA_Pos (0UL) /*!< RDA (Bit 0) */
#define GPIO_RDA_RDA_Msk (0xffffffffUL) /*!< RDA (Bitfield-Mask: 0xffffffff) */
/* ========================================================== RDB ========================================================== */
#define GPIO_RDB_RDB_Pos (0UL) /*!< RDB (Bit 0) */
#define GPIO_RDB_RDB_Msk (0x3ffffUL) /*!< RDB (Bitfield-Mask: 0x3ffff) */
/* ========================================================== WTA ========================================================== */
#define GPIO_WTA_WTA_Pos (0UL) /*!< WTA (Bit 0) */
#define GPIO_WTA_WTA_Msk (0xffffffffUL) /*!< WTA (Bitfield-Mask: 0xffffffff) */
/* ========================================================== WTB ========================================================== */
#define GPIO_WTB_WTB_Pos (0UL) /*!< WTB (Bit 0) */
#define GPIO_WTB_WTB_Msk (0x3ffffUL) /*!< WTB (Bitfield-Mask: 0x3ffff) */
/* ========================================================= WTSA ========================================================== */
#define GPIO_WTSA_WTSA_Pos (0UL) /*!< WTSA (Bit 0) */
#define GPIO_WTSA_WTSA_Msk (0xffffffffUL) /*!< WTSA (Bitfield-Mask: 0xffffffff) */
/* ========================================================= WTSB ========================================================== */
#define GPIO_WTSB_WTSB_Pos (0UL) /*!< WTSB (Bit 0) */
#define GPIO_WTSB_WTSB_Msk (0x3ffffUL) /*!< WTSB (Bitfield-Mask: 0x3ffff) */
/* ========================================================= WTCA ========================================================== */
#define GPIO_WTCA_WTCA_Pos (0UL) /*!< WTCA (Bit 0) */
#define GPIO_WTCA_WTCA_Msk (0xffffffffUL) /*!< WTCA (Bitfield-Mask: 0xffffffff) */
/* ========================================================= WTCB ========================================================== */
#define GPIO_WTCB_WTCB_Pos (0UL) /*!< WTCB (Bit 0) */
#define GPIO_WTCB_WTCB_Msk (0x3ffffUL) /*!< WTCB (Bitfield-Mask: 0x3ffff) */
/* ========================================================== ENA ========================================================== */
#define GPIO_ENA_ENA_Pos (0UL) /*!< ENA (Bit 0) */
#define GPIO_ENA_ENA_Msk (0xffffffffUL) /*!< ENA (Bitfield-Mask: 0xffffffff) */
/* ========================================================== ENB ========================================================== */
#define GPIO_ENB_ENB_Pos (0UL) /*!< ENB (Bit 0) */
#define GPIO_ENB_ENB_Msk (0x3ffffUL) /*!< ENB (Bitfield-Mask: 0x3ffff) */
/* ========================================================= ENSA ========================================================== */
#define GPIO_ENSA_ENSA_Pos (0UL) /*!< ENSA (Bit 0) */
#define GPIO_ENSA_ENSA_Msk (0xffffffffUL) /*!< ENSA (Bitfield-Mask: 0xffffffff) */
/* ========================================================= ENSB ========================================================== */
#define GPIO_ENSB_ENSB_Pos (0UL) /*!< ENSB (Bit 0) */
#define GPIO_ENSB_ENSB_Msk (0x3ffffUL) /*!< ENSB (Bitfield-Mask: 0x3ffff) */
/* ========================================================= ENCA ========================================================== */
#define GPIO_ENCA_ENCA_Pos (0UL) /*!< ENCA (Bit 0) */
#define GPIO_ENCA_ENCA_Msk (0xffffffffUL) /*!< ENCA (Bitfield-Mask: 0xffffffff) */
/* ========================================================= ENCB ========================================================== */
#define GPIO_ENCB_ENCB_Pos (0UL) /*!< ENCB (Bit 0) */
#define GPIO_ENCB_ENCB_Msk (0x3ffffUL) /*!< ENCB (Bitfield-Mask: 0x3ffff) */
/* ======================================================== STMRCAP ======================================================== */
#define GPIO_STMRCAP_STPOL3_Pos (30UL) /*!< STPOL3 (Bit 30) */
#define GPIO_STMRCAP_STPOL3_Msk (0x40000000UL) /*!< STPOL3 (Bitfield-Mask: 0x01) */
#define GPIO_STMRCAP_STSEL3_Pos (24UL) /*!< STSEL3 (Bit 24) */
#define GPIO_STMRCAP_STSEL3_Msk (0x3f000000UL) /*!< STSEL3 (Bitfield-Mask: 0x3f) */
#define GPIO_STMRCAP_STPOL2_Pos (22UL) /*!< STPOL2 (Bit 22) */
#define GPIO_STMRCAP_STPOL2_Msk (0x400000UL) /*!< STPOL2 (Bitfield-Mask: 0x01) */
#define GPIO_STMRCAP_STSEL2_Pos (16UL) /*!< STSEL2 (Bit 16) */
#define GPIO_STMRCAP_STSEL2_Msk (0x3f0000UL) /*!< STSEL2 (Bitfield-Mask: 0x3f) */
#define GPIO_STMRCAP_STPOL1_Pos (14UL) /*!< STPOL1 (Bit 14) */
#define GPIO_STMRCAP_STPOL1_Msk (0x4000UL) /*!< STPOL1 (Bitfield-Mask: 0x01) */
#define GPIO_STMRCAP_STSEL1_Pos (8UL) /*!< STSEL1 (Bit 8) */
#define GPIO_STMRCAP_STSEL1_Msk (0x3f00UL) /*!< STSEL1 (Bitfield-Mask: 0x3f) */
#define GPIO_STMRCAP_STPOL0_Pos (6UL) /*!< STPOL0 (Bit 6) */
#define GPIO_STMRCAP_STPOL0_Msk (0x40UL) /*!< STPOL0 (Bitfield-Mask: 0x01) */
#define GPIO_STMRCAP_STSEL0_Pos (0UL) /*!< STSEL0 (Bit 0) */
#define GPIO_STMRCAP_STSEL0_Msk (0x3fUL) /*!< STSEL0 (Bitfield-Mask: 0x3f) */
/* ======================================================== IOM0IRQ ======================================================== */
#define GPIO_IOM0IRQ_IOM0IRQ_Pos (0UL) /*!< IOM0IRQ (Bit 0) */
#define GPIO_IOM0IRQ_IOM0IRQ_Msk (0x3fUL) /*!< IOM0IRQ (Bitfield-Mask: 0x3f) */
/* ======================================================== IOM1IRQ ======================================================== */
#define GPIO_IOM1IRQ_IOM1IRQ_Pos (0UL) /*!< IOM1IRQ (Bit 0) */
#define GPIO_IOM1IRQ_IOM1IRQ_Msk (0x3fUL) /*!< IOM1IRQ (Bitfield-Mask: 0x3f) */
/* ======================================================== IOM2IRQ ======================================================== */
#define GPIO_IOM2IRQ_IOM2IRQ_Pos (0UL) /*!< IOM2IRQ (Bit 0) */
#define GPIO_IOM2IRQ_IOM2IRQ_Msk (0x3fUL) /*!< IOM2IRQ (Bitfield-Mask: 0x3f) */
/* ======================================================== IOM3IRQ ======================================================== */
#define GPIO_IOM3IRQ_IOM3IRQ_Pos (0UL) /*!< IOM3IRQ (Bit 0) */
#define GPIO_IOM3IRQ_IOM3IRQ_Msk (0x3fUL) /*!< IOM3IRQ (Bitfield-Mask: 0x3f) */
/* ======================================================== IOM4IRQ ======================================================== */
#define GPIO_IOM4IRQ_IOM4IRQ_Pos (0UL) /*!< IOM4IRQ (Bit 0) */
#define GPIO_IOM4IRQ_IOM4IRQ_Msk (0x3fUL) /*!< IOM4IRQ (Bitfield-Mask: 0x3f) */
/* ======================================================== IOM5IRQ ======================================================== */
#define GPIO_IOM5IRQ_IOM5IRQ_Pos (0UL) /*!< IOM5IRQ (Bit 0) */
#define GPIO_IOM5IRQ_IOM5IRQ_Msk (0x3fUL) /*!< IOM5IRQ (Bitfield-Mask: 0x3f) */
/* ======================================================= BLEIFIRQ ======================================================== */
#define GPIO_BLEIFIRQ_BLEIFIRQ_Pos (0UL) /*!< BLEIFIRQ (Bit 0) */
#define GPIO_BLEIFIRQ_BLEIFIRQ_Msk (0x3fUL) /*!< BLEIFIRQ (Bitfield-Mask: 0x3f) */
/* ======================================================== GPIOOBS ======================================================== */
#define GPIO_GPIOOBS_OBS_DATA_Pos (0UL) /*!< OBS_DATA (Bit 0) */
#define GPIO_GPIOOBS_OBS_DATA_Msk (0xffffUL) /*!< OBS_DATA (Bitfield-Mask: 0xffff) */
/* ====================================================== ALTPADCFGA ======================================================= */
#define GPIO_ALTPADCFGA_PAD3_SR_Pos (28UL) /*!< PAD3_SR (Bit 28) */
#define GPIO_ALTPADCFGA_PAD3_SR_Msk (0x10000000UL) /*!< PAD3_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGA_PAD3_DS1_Pos (24UL) /*!< PAD3_DS1 (Bit 24) */
#define GPIO_ALTPADCFGA_PAD3_DS1_Msk (0x1000000UL) /*!< PAD3_DS1 (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGA_PAD2_SR_Pos (20UL) /*!< PAD2_SR (Bit 20) */
#define GPIO_ALTPADCFGA_PAD2_SR_Msk (0x100000UL) /*!< PAD2_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGA_PAD2_DS1_Pos (16UL) /*!< PAD2_DS1 (Bit 16) */
#define GPIO_ALTPADCFGA_PAD2_DS1_Msk (0x10000UL) /*!< PAD2_DS1 (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGA_PAD1_SR_Pos (12UL) /*!< PAD1_SR (Bit 12) */
#define GPIO_ALTPADCFGA_PAD1_SR_Msk (0x1000UL) /*!< PAD1_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGA_PAD1_DS1_Pos (8UL) /*!< PAD1_DS1 (Bit 8) */
#define GPIO_ALTPADCFGA_PAD1_DS1_Msk (0x100UL) /*!< PAD1_DS1 (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGA_PAD0_SR_Pos (4UL) /*!< PAD0_SR (Bit 4) */
#define GPIO_ALTPADCFGA_PAD0_SR_Msk (0x10UL) /*!< PAD0_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGA_PAD0_DS1_Pos (0UL) /*!< PAD0_DS1 (Bit 0) */
#define GPIO_ALTPADCFGA_PAD0_DS1_Msk (0x1UL) /*!< PAD0_DS1 (Bitfield-Mask: 0x01) */
/* ====================================================== ALTPADCFGB ======================================================= */
#define GPIO_ALTPADCFGB_PAD7_SR_Pos (28UL) /*!< PAD7_SR (Bit 28) */
#define GPIO_ALTPADCFGB_PAD7_SR_Msk (0x10000000UL) /*!< PAD7_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGB_PAD7_DS1_Pos (24UL) /*!< PAD7_DS1 (Bit 24) */
#define GPIO_ALTPADCFGB_PAD7_DS1_Msk (0x1000000UL) /*!< PAD7_DS1 (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGB_PAD6_SR_Pos (20UL) /*!< PAD6_SR (Bit 20) */
#define GPIO_ALTPADCFGB_PAD6_SR_Msk (0x100000UL) /*!< PAD6_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGB_PAD6_DS1_Pos (16UL) /*!< PAD6_DS1 (Bit 16) */
#define GPIO_ALTPADCFGB_PAD6_DS1_Msk (0x10000UL) /*!< PAD6_DS1 (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGB_PAD5_SR_Pos (12UL) /*!< PAD5_SR (Bit 12) */
#define GPIO_ALTPADCFGB_PAD5_SR_Msk (0x1000UL) /*!< PAD5_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGB_PAD5_DS1_Pos (8UL) /*!< PAD5_DS1 (Bit 8) */
#define GPIO_ALTPADCFGB_PAD5_DS1_Msk (0x100UL) /*!< PAD5_DS1 (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGB_PAD4_SR_Pos (4UL) /*!< PAD4_SR (Bit 4) */
#define GPIO_ALTPADCFGB_PAD4_SR_Msk (0x10UL) /*!< PAD4_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGB_PAD4_DS1_Pos (0UL) /*!< PAD4_DS1 (Bit 0) */
#define GPIO_ALTPADCFGB_PAD4_DS1_Msk (0x1UL) /*!< PAD4_DS1 (Bitfield-Mask: 0x01) */
/* ====================================================== ALTPADCFGC ======================================================= */
#define GPIO_ALTPADCFGC_PAD11_SR_Pos (28UL) /*!< PAD11_SR (Bit 28) */
#define GPIO_ALTPADCFGC_PAD11_SR_Msk (0x10000000UL) /*!< PAD11_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGC_PAD11_DS1_Pos (24UL) /*!< PAD11_DS1 (Bit 24) */
#define GPIO_ALTPADCFGC_PAD11_DS1_Msk (0x1000000UL) /*!< PAD11_DS1 (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGC_PAD10_SR_Pos (20UL) /*!< PAD10_SR (Bit 20) */
#define GPIO_ALTPADCFGC_PAD10_SR_Msk (0x100000UL) /*!< PAD10_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGC_PAD10_DS1_Pos (16UL) /*!< PAD10_DS1 (Bit 16) */
#define GPIO_ALTPADCFGC_PAD10_DS1_Msk (0x10000UL) /*!< PAD10_DS1 (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGC_PAD9_SR_Pos (12UL) /*!< PAD9_SR (Bit 12) */
#define GPIO_ALTPADCFGC_PAD9_SR_Msk (0x1000UL) /*!< PAD9_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGC_PAD9_DS1_Pos (8UL) /*!< PAD9_DS1 (Bit 8) */
#define GPIO_ALTPADCFGC_PAD9_DS1_Msk (0x100UL) /*!< PAD9_DS1 (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGC_PAD8_SR_Pos (4UL) /*!< PAD8_SR (Bit 4) */
#define GPIO_ALTPADCFGC_PAD8_SR_Msk (0x10UL) /*!< PAD8_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGC_PAD8_DS1_Pos (0UL) /*!< PAD8_DS1 (Bit 0) */
#define GPIO_ALTPADCFGC_PAD8_DS1_Msk (0x1UL) /*!< PAD8_DS1 (Bitfield-Mask: 0x01) */
/* ====================================================== ALTPADCFGD ======================================================= */
#define GPIO_ALTPADCFGD_PAD15_SR_Pos (28UL) /*!< PAD15_SR (Bit 28) */
#define GPIO_ALTPADCFGD_PAD15_SR_Msk (0x10000000UL) /*!< PAD15_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGD_PAD15_DS1_Pos (24UL) /*!< PAD15_DS1 (Bit 24) */
#define GPIO_ALTPADCFGD_PAD15_DS1_Msk (0x1000000UL) /*!< PAD15_DS1 (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGD_PAD14_SR_Pos (20UL) /*!< PAD14_SR (Bit 20) */
#define GPIO_ALTPADCFGD_PAD14_SR_Msk (0x100000UL) /*!< PAD14_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGD_PAD14_DS1_Pos (16UL) /*!< PAD14_DS1 (Bit 16) */
#define GPIO_ALTPADCFGD_PAD14_DS1_Msk (0x10000UL) /*!< PAD14_DS1 (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGD_PAD13_SR_Pos (12UL) /*!< PAD13_SR (Bit 12) */
#define GPIO_ALTPADCFGD_PAD13_SR_Msk (0x1000UL) /*!< PAD13_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGD_PAD13_DS1_Pos (8UL) /*!< PAD13_DS1 (Bit 8) */
#define GPIO_ALTPADCFGD_PAD13_DS1_Msk (0x100UL) /*!< PAD13_DS1 (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGD_PAD12_SR_Pos (4UL) /*!< PAD12_SR (Bit 4) */
#define GPIO_ALTPADCFGD_PAD12_SR_Msk (0x10UL) /*!< PAD12_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGD_PAD12_DS1_Pos (0UL) /*!< PAD12_DS1 (Bit 0) */
#define GPIO_ALTPADCFGD_PAD12_DS1_Msk (0x1UL) /*!< PAD12_DS1 (Bitfield-Mask: 0x01) */
/* ====================================================== ALTPADCFGE ======================================================= */
#define GPIO_ALTPADCFGE_PAD19_SR_Pos (28UL) /*!< PAD19_SR (Bit 28) */
#define GPIO_ALTPADCFGE_PAD19_SR_Msk (0x10000000UL) /*!< PAD19_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGE_PAD19_DS1_Pos (24UL) /*!< PAD19_DS1 (Bit 24) */
#define GPIO_ALTPADCFGE_PAD19_DS1_Msk (0x1000000UL) /*!< PAD19_DS1 (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGE_PAD18_SR_Pos (20UL) /*!< PAD18_SR (Bit 20) */
#define GPIO_ALTPADCFGE_PAD18_SR_Msk (0x100000UL) /*!< PAD18_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGE_PAD18_DS1_Pos (16UL) /*!< PAD18_DS1 (Bit 16) */
#define GPIO_ALTPADCFGE_PAD18_DS1_Msk (0x10000UL) /*!< PAD18_DS1 (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGE_PAD17_SR_Pos (12UL) /*!< PAD17_SR (Bit 12) */
#define GPIO_ALTPADCFGE_PAD17_SR_Msk (0x1000UL) /*!< PAD17_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGE_PAD17_DS1_Pos (8UL) /*!< PAD17_DS1 (Bit 8) */
#define GPIO_ALTPADCFGE_PAD17_DS1_Msk (0x100UL) /*!< PAD17_DS1 (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGE_PAD16_SR_Pos (4UL) /*!< PAD16_SR (Bit 4) */
#define GPIO_ALTPADCFGE_PAD16_SR_Msk (0x10UL) /*!< PAD16_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGE_PAD16_DS1_Pos (0UL) /*!< PAD16_DS1 (Bit 0) */
#define GPIO_ALTPADCFGE_PAD16_DS1_Msk (0x1UL) /*!< PAD16_DS1 (Bitfield-Mask: 0x01) */
/* ====================================================== ALTPADCFGF ======================================================= */
#define GPIO_ALTPADCFGF_PAD23_SR_Pos (28UL) /*!< PAD23_SR (Bit 28) */
#define GPIO_ALTPADCFGF_PAD23_SR_Msk (0x10000000UL) /*!< PAD23_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGF_PAD23_DS1_Pos (24UL) /*!< PAD23_DS1 (Bit 24) */
#define GPIO_ALTPADCFGF_PAD23_DS1_Msk (0x1000000UL) /*!< PAD23_DS1 (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGF_PAD22_SR_Pos (20UL) /*!< PAD22_SR (Bit 20) */
#define GPIO_ALTPADCFGF_PAD22_SR_Msk (0x100000UL) /*!< PAD22_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGF_PAD22_DS1_Pos (16UL) /*!< PAD22_DS1 (Bit 16) */
#define GPIO_ALTPADCFGF_PAD22_DS1_Msk (0x10000UL) /*!< PAD22_DS1 (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGF_PAD21_SR_Pos (12UL) /*!< PAD21_SR (Bit 12) */
#define GPIO_ALTPADCFGF_PAD21_SR_Msk (0x1000UL) /*!< PAD21_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGF_PAD21_DS1_Pos (8UL) /*!< PAD21_DS1 (Bit 8) */
#define GPIO_ALTPADCFGF_PAD21_DS1_Msk (0x100UL) /*!< PAD21_DS1 (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGF_PAD20_SR_Pos (4UL) /*!< PAD20_SR (Bit 4) */
#define GPIO_ALTPADCFGF_PAD20_SR_Msk (0x10UL) /*!< PAD20_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGF_PAD20_DS1_Pos (0UL) /*!< PAD20_DS1 (Bit 0) */
#define GPIO_ALTPADCFGF_PAD20_DS1_Msk (0x1UL) /*!< PAD20_DS1 (Bitfield-Mask: 0x01) */
/* ====================================================== ALTPADCFGG ======================================================= */
#define GPIO_ALTPADCFGG_PAD27_SR_Pos (28UL) /*!< PAD27_SR (Bit 28) */
#define GPIO_ALTPADCFGG_PAD27_SR_Msk (0x10000000UL) /*!< PAD27_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGG_PAD27_DS1_Pos (24UL) /*!< PAD27_DS1 (Bit 24) */
#define GPIO_ALTPADCFGG_PAD27_DS1_Msk (0x1000000UL) /*!< PAD27_DS1 (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGG_PAD26_SR_Pos (20UL) /*!< PAD26_SR (Bit 20) */
#define GPIO_ALTPADCFGG_PAD26_SR_Msk (0x100000UL) /*!< PAD26_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGG_PAD26_DS1_Pos (16UL) /*!< PAD26_DS1 (Bit 16) */
#define GPIO_ALTPADCFGG_PAD26_DS1_Msk (0x10000UL) /*!< PAD26_DS1 (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGG_PAD25_SR_Pos (12UL) /*!< PAD25_SR (Bit 12) */
#define GPIO_ALTPADCFGG_PAD25_SR_Msk (0x1000UL) /*!< PAD25_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGG_PAD25_DS1_Pos (8UL) /*!< PAD25_DS1 (Bit 8) */
#define GPIO_ALTPADCFGG_PAD25_DS1_Msk (0x100UL) /*!< PAD25_DS1 (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGG_PAD24_SR_Pos (4UL) /*!< PAD24_SR (Bit 4) */
#define GPIO_ALTPADCFGG_PAD24_SR_Msk (0x10UL) /*!< PAD24_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGG_PAD24_DS1_Pos (0UL) /*!< PAD24_DS1 (Bit 0) */
#define GPIO_ALTPADCFGG_PAD24_DS1_Msk (0x1UL) /*!< PAD24_DS1 (Bitfield-Mask: 0x01) */
/* ====================================================== ALTPADCFGH ======================================================= */
#define GPIO_ALTPADCFGH_PAD31_SR_Pos (28UL) /*!< PAD31_SR (Bit 28) */
#define GPIO_ALTPADCFGH_PAD31_SR_Msk (0x10000000UL) /*!< PAD31_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGH_PAD31_DS1_Pos (24UL) /*!< PAD31_DS1 (Bit 24) */
#define GPIO_ALTPADCFGH_PAD31_DS1_Msk (0x1000000UL) /*!< PAD31_DS1 (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGH_PAD30_SR_Pos (20UL) /*!< PAD30_SR (Bit 20) */
#define GPIO_ALTPADCFGH_PAD30_SR_Msk (0x100000UL) /*!< PAD30_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGH_PAD30_DS1_Pos (16UL) /*!< PAD30_DS1 (Bit 16) */
#define GPIO_ALTPADCFGH_PAD30_DS1_Msk (0x10000UL) /*!< PAD30_DS1 (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGH_PAD29_SR_Pos (12UL) /*!< PAD29_SR (Bit 12) */
#define GPIO_ALTPADCFGH_PAD29_SR_Msk (0x1000UL) /*!< PAD29_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGH_PAD29_DS1_Pos (8UL) /*!< PAD29_DS1 (Bit 8) */
#define GPIO_ALTPADCFGH_PAD29_DS1_Msk (0x100UL) /*!< PAD29_DS1 (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGH_PAD28_SR_Pos (4UL) /*!< PAD28_SR (Bit 4) */
#define GPIO_ALTPADCFGH_PAD28_SR_Msk (0x10UL) /*!< PAD28_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGH_PAD28_DS1_Pos (0UL) /*!< PAD28_DS1 (Bit 0) */
#define GPIO_ALTPADCFGH_PAD28_DS1_Msk (0x1UL) /*!< PAD28_DS1 (Bitfield-Mask: 0x01) */
/* ====================================================== ALTPADCFGI ======================================================= */
#define GPIO_ALTPADCFGI_PAD35_SR_Pos (28UL) /*!< PAD35_SR (Bit 28) */
#define GPIO_ALTPADCFGI_PAD35_SR_Msk (0x10000000UL) /*!< PAD35_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGI_PAD35_DS1_Pos (24UL) /*!< PAD35_DS1 (Bit 24) */
#define GPIO_ALTPADCFGI_PAD35_DS1_Msk (0x1000000UL) /*!< PAD35_DS1 (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGI_PAD34_SR_Pos (20UL) /*!< PAD34_SR (Bit 20) */
#define GPIO_ALTPADCFGI_PAD34_SR_Msk (0x100000UL) /*!< PAD34_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGI_PAD34_DS1_Pos (16UL) /*!< PAD34_DS1 (Bit 16) */
#define GPIO_ALTPADCFGI_PAD34_DS1_Msk (0x10000UL) /*!< PAD34_DS1 (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGI_PAD33_SR_Pos (12UL) /*!< PAD33_SR (Bit 12) */
#define GPIO_ALTPADCFGI_PAD33_SR_Msk (0x1000UL) /*!< PAD33_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGI_PAD33_DS1_Pos (8UL) /*!< PAD33_DS1 (Bit 8) */
#define GPIO_ALTPADCFGI_PAD33_DS1_Msk (0x100UL) /*!< PAD33_DS1 (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGI_PAD32_SR_Pos (4UL) /*!< PAD32_SR (Bit 4) */
#define GPIO_ALTPADCFGI_PAD32_SR_Msk (0x10UL) /*!< PAD32_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGI_PAD32_DS1_Pos (0UL) /*!< PAD32_DS1 (Bit 0) */
#define GPIO_ALTPADCFGI_PAD32_DS1_Msk (0x1UL) /*!< PAD32_DS1 (Bitfield-Mask: 0x01) */
/* ====================================================== ALTPADCFGJ ======================================================= */
#define GPIO_ALTPADCFGJ_PAD39_SR_Pos (28UL) /*!< PAD39_SR (Bit 28) */
#define GPIO_ALTPADCFGJ_PAD39_SR_Msk (0x10000000UL) /*!< PAD39_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGJ_PAD39_DS1_Pos (24UL) /*!< PAD39_DS1 (Bit 24) */
#define GPIO_ALTPADCFGJ_PAD39_DS1_Msk (0x1000000UL) /*!< PAD39_DS1 (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGJ_PAD38_SR_Pos (20UL) /*!< PAD38_SR (Bit 20) */
#define GPIO_ALTPADCFGJ_PAD38_SR_Msk (0x100000UL) /*!< PAD38_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGJ_PAD38_DS1_Pos (16UL) /*!< PAD38_DS1 (Bit 16) */
#define GPIO_ALTPADCFGJ_PAD38_DS1_Msk (0x10000UL) /*!< PAD38_DS1 (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGJ_PAD37_SR_Pos (12UL) /*!< PAD37_SR (Bit 12) */
#define GPIO_ALTPADCFGJ_PAD37_SR_Msk (0x1000UL) /*!< PAD37_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGJ_PAD37_DS1_Pos (8UL) /*!< PAD37_DS1 (Bit 8) */
#define GPIO_ALTPADCFGJ_PAD37_DS1_Msk (0x100UL) /*!< PAD37_DS1 (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGJ_PAD36_SR_Pos (4UL) /*!< PAD36_SR (Bit 4) */
#define GPIO_ALTPADCFGJ_PAD36_SR_Msk (0x10UL) /*!< PAD36_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGJ_PAD36_DS1_Pos (0UL) /*!< PAD36_DS1 (Bit 0) */
#define GPIO_ALTPADCFGJ_PAD36_DS1_Msk (0x1UL) /*!< PAD36_DS1 (Bitfield-Mask: 0x01) */
/* ====================================================== ALTPADCFGK ======================================================= */
#define GPIO_ALTPADCFGK_PAD43_SR_Pos (28UL) /*!< PAD43_SR (Bit 28) */
#define GPIO_ALTPADCFGK_PAD43_SR_Msk (0x10000000UL) /*!< PAD43_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGK_PAD43_DS1_Pos (24UL) /*!< PAD43_DS1 (Bit 24) */
#define GPIO_ALTPADCFGK_PAD43_DS1_Msk (0x1000000UL) /*!< PAD43_DS1 (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGK_PAD42_SR_Pos (20UL) /*!< PAD42_SR (Bit 20) */
#define GPIO_ALTPADCFGK_PAD42_SR_Msk (0x100000UL) /*!< PAD42_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGK_PAD42_DS1_Pos (16UL) /*!< PAD42_DS1 (Bit 16) */
#define GPIO_ALTPADCFGK_PAD42_DS1_Msk (0x10000UL) /*!< PAD42_DS1 (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGK_PAD41_SR_Pos (12UL) /*!< PAD41_SR (Bit 12) */
#define GPIO_ALTPADCFGK_PAD41_SR_Msk (0x1000UL) /*!< PAD41_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGK_PAD41_DS1_Pos (8UL) /*!< PAD41_DS1 (Bit 8) */
#define GPIO_ALTPADCFGK_PAD41_DS1_Msk (0x100UL) /*!< PAD41_DS1 (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGK_PAD40_SR_Pos (4UL) /*!< PAD40_SR (Bit 4) */
#define GPIO_ALTPADCFGK_PAD40_SR_Msk (0x10UL) /*!< PAD40_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGK_PAD40_DS1_Pos (0UL) /*!< PAD40_DS1 (Bit 0) */
#define GPIO_ALTPADCFGK_PAD40_DS1_Msk (0x1UL) /*!< PAD40_DS1 (Bitfield-Mask: 0x01) */
/* ====================================================== ALTPADCFGL ======================================================= */
#define GPIO_ALTPADCFGL_PAD47_SR_Pos (28UL) /*!< PAD47_SR (Bit 28) */
#define GPIO_ALTPADCFGL_PAD47_SR_Msk (0x10000000UL) /*!< PAD47_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGL_PAD47_DS1_Pos (24UL) /*!< PAD47_DS1 (Bit 24) */
#define GPIO_ALTPADCFGL_PAD47_DS1_Msk (0x1000000UL) /*!< PAD47_DS1 (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGL_PAD46_SR_Pos (20UL) /*!< PAD46_SR (Bit 20) */
#define GPIO_ALTPADCFGL_PAD46_SR_Msk (0x100000UL) /*!< PAD46_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGL_PAD46_DS1_Pos (16UL) /*!< PAD46_DS1 (Bit 16) */
#define GPIO_ALTPADCFGL_PAD46_DS1_Msk (0x10000UL) /*!< PAD46_DS1 (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGL_PAD45_SR_Pos (12UL) /*!< PAD45_SR (Bit 12) */
#define GPIO_ALTPADCFGL_PAD45_SR_Msk (0x1000UL) /*!< PAD45_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGL_PAD45_DS1_Pos (8UL) /*!< PAD45_DS1 (Bit 8) */
#define GPIO_ALTPADCFGL_PAD45_DS1_Msk (0x100UL) /*!< PAD45_DS1 (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGL_PAD44_SR_Pos (4UL) /*!< PAD44_SR (Bit 4) */
#define GPIO_ALTPADCFGL_PAD44_SR_Msk (0x10UL) /*!< PAD44_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGL_PAD44_DS1_Pos (0UL) /*!< PAD44_DS1 (Bit 0) */
#define GPIO_ALTPADCFGL_PAD44_DS1_Msk (0x1UL) /*!< PAD44_DS1 (Bitfield-Mask: 0x01) */
/* ====================================================== ALTPADCFGM ======================================================= */
#define GPIO_ALTPADCFGM_PAD49_SR_Pos (12UL) /*!< PAD49_SR (Bit 12) */
#define GPIO_ALTPADCFGM_PAD49_SR_Msk (0x1000UL) /*!< PAD49_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGM_PAD49_DS1_Pos (8UL) /*!< PAD49_DS1 (Bit 8) */
#define GPIO_ALTPADCFGM_PAD49_DS1_Msk (0x100UL) /*!< PAD49_DS1 (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGM_PAD48_SR_Pos (4UL) /*!< PAD48_SR (Bit 4) */
#define GPIO_ALTPADCFGM_PAD48_SR_Msk (0x10UL) /*!< PAD48_SR (Bitfield-Mask: 0x01) */
#define GPIO_ALTPADCFGM_PAD48_DS1_Pos (0UL) /*!< PAD48_DS1 (Bit 0) */
#define GPIO_ALTPADCFGM_PAD48_DS1_Msk (0x1UL) /*!< PAD48_DS1 (Bitfield-Mask: 0x01) */
/* ========================================================= SCDET ========================================================= */
#define GPIO_SCDET_SCDET_Pos (0UL) /*!< SCDET (Bit 0) */
#define GPIO_SCDET_SCDET_Msk (0x3fUL) /*!< SCDET (Bitfield-Mask: 0x3f) */
/* ======================================================== CTENCFG ======================================================== */
#define GPIO_CTENCFG_EN31_Pos (31UL) /*!< EN31 (Bit 31) */
#define GPIO_CTENCFG_EN31_Msk (0x80000000UL) /*!< EN31 (Bitfield-Mask: 0x01) */
#define GPIO_CTENCFG_EN30_Pos (30UL) /*!< EN30 (Bit 30) */
#define GPIO_CTENCFG_EN30_Msk (0x40000000UL) /*!< EN30 (Bitfield-Mask: 0x01) */
#define GPIO_CTENCFG_EN29_Pos (29UL) /*!< EN29 (Bit 29) */
#define GPIO_CTENCFG_EN29_Msk (0x20000000UL) /*!< EN29 (Bitfield-Mask: 0x01) */
#define GPIO_CTENCFG_EN28_Pos (28UL) /*!< EN28 (Bit 28) */
#define GPIO_CTENCFG_EN28_Msk (0x10000000UL) /*!< EN28 (Bitfield-Mask: 0x01) */
#define GPIO_CTENCFG_EN27_Pos (27UL) /*!< EN27 (Bit 27) */
#define GPIO_CTENCFG_EN27_Msk (0x8000000UL) /*!< EN27 (Bitfield-Mask: 0x01) */
#define GPIO_CTENCFG_EN26_Pos (26UL) /*!< EN26 (Bit 26) */
#define GPIO_CTENCFG_EN26_Msk (0x4000000UL) /*!< EN26 (Bitfield-Mask: 0x01) */
#define GPIO_CTENCFG_EN25_Pos (25UL) /*!< EN25 (Bit 25) */
#define GPIO_CTENCFG_EN25_Msk (0x2000000UL) /*!< EN25 (Bitfield-Mask: 0x01) */
#define GPIO_CTENCFG_EN24_Pos (24UL) /*!< EN24 (Bit 24) */
#define GPIO_CTENCFG_EN24_Msk (0x1000000UL) /*!< EN24 (Bitfield-Mask: 0x01) */
#define GPIO_CTENCFG_EN23_Pos (23UL) /*!< EN23 (Bit 23) */
#define GPIO_CTENCFG_EN23_Msk (0x800000UL) /*!< EN23 (Bitfield-Mask: 0x01) */
#define GPIO_CTENCFG_EN22_Pos (22UL) /*!< EN22 (Bit 22) */
#define GPIO_CTENCFG_EN22_Msk (0x400000UL) /*!< EN22 (Bitfield-Mask: 0x01) */
#define GPIO_CTENCFG_EN21_Pos (21UL) /*!< EN21 (Bit 21) */
#define GPIO_CTENCFG_EN21_Msk (0x200000UL) /*!< EN21 (Bitfield-Mask: 0x01) */
#define GPIO_CTENCFG_EN20_Pos (20UL) /*!< EN20 (Bit 20) */
#define GPIO_CTENCFG_EN20_Msk (0x100000UL) /*!< EN20 (Bitfield-Mask: 0x01) */
#define GPIO_CTENCFG_EN19_Pos (19UL) /*!< EN19 (Bit 19) */
#define GPIO_CTENCFG_EN19_Msk (0x80000UL) /*!< EN19 (Bitfield-Mask: 0x01) */
#define GPIO_CTENCFG_EN18_Pos (18UL) /*!< EN18 (Bit 18) */
#define GPIO_CTENCFG_EN18_Msk (0x40000UL) /*!< EN18 (Bitfield-Mask: 0x01) */
#define GPIO_CTENCFG_EN17_Pos (17UL) /*!< EN17 (Bit 17) */
#define GPIO_CTENCFG_EN17_Msk (0x20000UL) /*!< EN17 (Bitfield-Mask: 0x01) */
#define GPIO_CTENCFG_EN16_Pos (16UL) /*!< EN16 (Bit 16) */
#define GPIO_CTENCFG_EN16_Msk (0x10000UL) /*!< EN16 (Bitfield-Mask: 0x01) */
#define GPIO_CTENCFG_EN15_Pos (15UL) /*!< EN15 (Bit 15) */
#define GPIO_CTENCFG_EN15_Msk (0x8000UL) /*!< EN15 (Bitfield-Mask: 0x01) */
#define GPIO_CTENCFG_EN14_Pos (14UL) /*!< EN14 (Bit 14) */
#define GPIO_CTENCFG_EN14_Msk (0x4000UL) /*!< EN14 (Bitfield-Mask: 0x01) */
#define GPIO_CTENCFG_EN13_Pos (13UL) /*!< EN13 (Bit 13) */
#define GPIO_CTENCFG_EN13_Msk (0x2000UL) /*!< EN13 (Bitfield-Mask: 0x01) */
#define GPIO_CTENCFG_EN12_Pos (12UL) /*!< EN12 (Bit 12) */
#define GPIO_CTENCFG_EN12_Msk (0x1000UL) /*!< EN12 (Bitfield-Mask: 0x01) */
#define GPIO_CTENCFG_EN11_Pos (11UL) /*!< EN11 (Bit 11) */
#define GPIO_CTENCFG_EN11_Msk (0x800UL) /*!< EN11 (Bitfield-Mask: 0x01) */
#define GPIO_CTENCFG_EN10_Pos (10UL) /*!< EN10 (Bit 10) */
#define GPIO_CTENCFG_EN10_Msk (0x400UL) /*!< EN10 (Bitfield-Mask: 0x01) */
#define GPIO_CTENCFG_EN9_Pos (9UL) /*!< EN9 (Bit 9) */
#define GPIO_CTENCFG_EN9_Msk (0x200UL) /*!< EN9 (Bitfield-Mask: 0x01) */
#define GPIO_CTENCFG_EN8_Pos (8UL) /*!< EN8 (Bit 8) */
#define GPIO_CTENCFG_EN8_Msk (0x100UL) /*!< EN8 (Bitfield-Mask: 0x01) */
#define GPIO_CTENCFG_EN7_Pos (7UL) /*!< EN7 (Bit 7) */
#define GPIO_CTENCFG_EN7_Msk (0x80UL) /*!< EN7 (Bitfield-Mask: 0x01) */
#define GPIO_CTENCFG_EN6_Pos (6UL) /*!< EN6 (Bit 6) */
#define GPIO_CTENCFG_EN6_Msk (0x40UL) /*!< EN6 (Bitfield-Mask: 0x01) */
#define GPIO_CTENCFG_EN5_Pos (5UL) /*!< EN5 (Bit 5) */
#define GPIO_CTENCFG_EN5_Msk (0x20UL) /*!< EN5 (Bitfield-Mask: 0x01) */
#define GPIO_CTENCFG_EN4_Pos (4UL) /*!< EN4 (Bit 4) */
#define GPIO_CTENCFG_EN4_Msk (0x10UL) /*!< EN4 (Bitfield-Mask: 0x01) */
#define GPIO_CTENCFG_EN3_Pos (3UL) /*!< EN3 (Bit 3) */
#define GPIO_CTENCFG_EN3_Msk (0x8UL) /*!< EN3 (Bitfield-Mask: 0x01) */
#define GPIO_CTENCFG_EN2_Pos (2UL) /*!< EN2 (Bit 2) */
#define GPIO_CTENCFG_EN2_Msk (0x4UL) /*!< EN2 (Bitfield-Mask: 0x01) */
#define GPIO_CTENCFG_EN1_Pos (1UL) /*!< EN1 (Bit 1) */
#define GPIO_CTENCFG_EN1_Msk (0x2UL) /*!< EN1 (Bitfield-Mask: 0x01) */
#define GPIO_CTENCFG_EN0_Pos (0UL) /*!< EN0 (Bit 0) */
#define GPIO_CTENCFG_EN0_Msk (0x1UL) /*!< EN0 (Bitfield-Mask: 0x01) */
/* ======================================================== INT0EN ========================================================= */
#define GPIO_INT0EN_GPIO31_Pos (31UL) /*!< GPIO31 (Bit 31) */
#define GPIO_INT0EN_GPIO31_Msk (0x80000000UL) /*!< GPIO31 (Bitfield-Mask: 0x01) */
#define GPIO_INT0EN_GPIO30_Pos (30UL) /*!< GPIO30 (Bit 30) */
#define GPIO_INT0EN_GPIO30_Msk (0x40000000UL) /*!< GPIO30 (Bitfield-Mask: 0x01) */
#define GPIO_INT0EN_GPIO29_Pos (29UL) /*!< GPIO29 (Bit 29) */
#define GPIO_INT0EN_GPIO29_Msk (0x20000000UL) /*!< GPIO29 (Bitfield-Mask: 0x01) */
#define GPIO_INT0EN_GPIO28_Pos (28UL) /*!< GPIO28 (Bit 28) */
#define GPIO_INT0EN_GPIO28_Msk (0x10000000UL) /*!< GPIO28 (Bitfield-Mask: 0x01) */
#define GPIO_INT0EN_GPIO27_Pos (27UL) /*!< GPIO27 (Bit 27) */
#define GPIO_INT0EN_GPIO27_Msk (0x8000000UL) /*!< GPIO27 (Bitfield-Mask: 0x01) */
#define GPIO_INT0EN_GPIO26_Pos (26UL) /*!< GPIO26 (Bit 26) */
#define GPIO_INT0EN_GPIO26_Msk (0x4000000UL) /*!< GPIO26 (Bitfield-Mask: 0x01) */
#define GPIO_INT0EN_GPIO25_Pos (25UL) /*!< GPIO25 (Bit 25) */
#define GPIO_INT0EN_GPIO25_Msk (0x2000000UL) /*!< GPIO25 (Bitfield-Mask: 0x01) */
#define GPIO_INT0EN_GPIO24_Pos (24UL) /*!< GPIO24 (Bit 24) */
#define GPIO_INT0EN_GPIO24_Msk (0x1000000UL) /*!< GPIO24 (Bitfield-Mask: 0x01) */
#define GPIO_INT0EN_GPIO23_Pos (23UL) /*!< GPIO23 (Bit 23) */
#define GPIO_INT0EN_GPIO23_Msk (0x800000UL) /*!< GPIO23 (Bitfield-Mask: 0x01) */
#define GPIO_INT0EN_GPIO22_Pos (22UL) /*!< GPIO22 (Bit 22) */
#define GPIO_INT0EN_GPIO22_Msk (0x400000UL) /*!< GPIO22 (Bitfield-Mask: 0x01) */
#define GPIO_INT0EN_GPIO21_Pos (21UL) /*!< GPIO21 (Bit 21) */
#define GPIO_INT0EN_GPIO21_Msk (0x200000UL) /*!< GPIO21 (Bitfield-Mask: 0x01) */
#define GPIO_INT0EN_GPIO20_Pos (20UL) /*!< GPIO20 (Bit 20) */
#define GPIO_INT0EN_GPIO20_Msk (0x100000UL) /*!< GPIO20 (Bitfield-Mask: 0x01) */
#define GPIO_INT0EN_GPIO19_Pos (19UL) /*!< GPIO19 (Bit 19) */
#define GPIO_INT0EN_GPIO19_Msk (0x80000UL) /*!< GPIO19 (Bitfield-Mask: 0x01) */
#define GPIO_INT0EN_GPIO18_Pos (18UL) /*!< GPIO18 (Bit 18) */
#define GPIO_INT0EN_GPIO18_Msk (0x40000UL) /*!< GPIO18 (Bitfield-Mask: 0x01) */
#define GPIO_INT0EN_GPIO17_Pos (17UL) /*!< GPIO17 (Bit 17) */
#define GPIO_INT0EN_GPIO17_Msk (0x20000UL) /*!< GPIO17 (Bitfield-Mask: 0x01) */
#define GPIO_INT0EN_GPIO16_Pos (16UL) /*!< GPIO16 (Bit 16) */
#define GPIO_INT0EN_GPIO16_Msk (0x10000UL) /*!< GPIO16 (Bitfield-Mask: 0x01) */
#define GPIO_INT0EN_GPIO15_Pos (15UL) /*!< GPIO15 (Bit 15) */
#define GPIO_INT0EN_GPIO15_Msk (0x8000UL) /*!< GPIO15 (Bitfield-Mask: 0x01) */
#define GPIO_INT0EN_GPIO14_Pos (14UL) /*!< GPIO14 (Bit 14) */
#define GPIO_INT0EN_GPIO14_Msk (0x4000UL) /*!< GPIO14 (Bitfield-Mask: 0x01) */
#define GPIO_INT0EN_GPIO13_Pos (13UL) /*!< GPIO13 (Bit 13) */
#define GPIO_INT0EN_GPIO13_Msk (0x2000UL) /*!< GPIO13 (Bitfield-Mask: 0x01) */
#define GPIO_INT0EN_GPIO12_Pos (12UL) /*!< GPIO12 (Bit 12) */
#define GPIO_INT0EN_GPIO12_Msk (0x1000UL) /*!< GPIO12 (Bitfield-Mask: 0x01) */
#define GPIO_INT0EN_GPIO11_Pos (11UL) /*!< GPIO11 (Bit 11) */
#define GPIO_INT0EN_GPIO11_Msk (0x800UL) /*!< GPIO11 (Bitfield-Mask: 0x01) */
#define GPIO_INT0EN_GPIO10_Pos (10UL) /*!< GPIO10 (Bit 10) */
#define GPIO_INT0EN_GPIO10_Msk (0x400UL) /*!< GPIO10 (Bitfield-Mask: 0x01) */
#define GPIO_INT0EN_GPIO9_Pos (9UL) /*!< GPIO9 (Bit 9) */
#define GPIO_INT0EN_GPIO9_Msk (0x200UL) /*!< GPIO9 (Bitfield-Mask: 0x01) */
#define GPIO_INT0EN_GPIO8_Pos (8UL) /*!< GPIO8 (Bit 8) */
#define GPIO_INT0EN_GPIO8_Msk (0x100UL) /*!< GPIO8 (Bitfield-Mask: 0x01) */
#define GPIO_INT0EN_GPIO7_Pos (7UL) /*!< GPIO7 (Bit 7) */
#define GPIO_INT0EN_GPIO7_Msk (0x80UL) /*!< GPIO7 (Bitfield-Mask: 0x01) */
#define GPIO_INT0EN_GPIO6_Pos (6UL) /*!< GPIO6 (Bit 6) */
#define GPIO_INT0EN_GPIO6_Msk (0x40UL) /*!< GPIO6 (Bitfield-Mask: 0x01) */
#define GPIO_INT0EN_GPIO5_Pos (5UL) /*!< GPIO5 (Bit 5) */
#define GPIO_INT0EN_GPIO5_Msk (0x20UL) /*!< GPIO5 (Bitfield-Mask: 0x01) */
#define GPIO_INT0EN_GPIO4_Pos (4UL) /*!< GPIO4 (Bit 4) */
#define GPIO_INT0EN_GPIO4_Msk (0x10UL) /*!< GPIO4 (Bitfield-Mask: 0x01) */
#define GPIO_INT0EN_GPIO3_Pos (3UL) /*!< GPIO3 (Bit 3) */
#define GPIO_INT0EN_GPIO3_Msk (0x8UL) /*!< GPIO3 (Bitfield-Mask: 0x01) */
#define GPIO_INT0EN_GPIO2_Pos (2UL) /*!< GPIO2 (Bit 2) */
#define GPIO_INT0EN_GPIO2_Msk (0x4UL) /*!< GPIO2 (Bitfield-Mask: 0x01) */
#define GPIO_INT0EN_GPIO1_Pos (1UL) /*!< GPIO1 (Bit 1) */
#define GPIO_INT0EN_GPIO1_Msk (0x2UL) /*!< GPIO1 (Bitfield-Mask: 0x01) */
#define GPIO_INT0EN_GPIO0_Pos (0UL) /*!< GPIO0 (Bit 0) */
#define GPIO_INT0EN_GPIO0_Msk (0x1UL) /*!< GPIO0 (Bitfield-Mask: 0x01) */
/* ======================================================= INT0STAT ======================================================== */
#define GPIO_INT0STAT_GPIO31_Pos (31UL) /*!< GPIO31 (Bit 31) */
#define GPIO_INT0STAT_GPIO31_Msk (0x80000000UL) /*!< GPIO31 (Bitfield-Mask: 0x01) */
#define GPIO_INT0STAT_GPIO30_Pos (30UL) /*!< GPIO30 (Bit 30) */
#define GPIO_INT0STAT_GPIO30_Msk (0x40000000UL) /*!< GPIO30 (Bitfield-Mask: 0x01) */
#define GPIO_INT0STAT_GPIO29_Pos (29UL) /*!< GPIO29 (Bit 29) */
#define GPIO_INT0STAT_GPIO29_Msk (0x20000000UL) /*!< GPIO29 (Bitfield-Mask: 0x01) */
#define GPIO_INT0STAT_GPIO28_Pos (28UL) /*!< GPIO28 (Bit 28) */
#define GPIO_INT0STAT_GPIO28_Msk (0x10000000UL) /*!< GPIO28 (Bitfield-Mask: 0x01) */
#define GPIO_INT0STAT_GPIO27_Pos (27UL) /*!< GPIO27 (Bit 27) */
#define GPIO_INT0STAT_GPIO27_Msk (0x8000000UL) /*!< GPIO27 (Bitfield-Mask: 0x01) */
#define GPIO_INT0STAT_GPIO26_Pos (26UL) /*!< GPIO26 (Bit 26) */
#define GPIO_INT0STAT_GPIO26_Msk (0x4000000UL) /*!< GPIO26 (Bitfield-Mask: 0x01) */
#define GPIO_INT0STAT_GPIO25_Pos (25UL) /*!< GPIO25 (Bit 25) */
#define GPIO_INT0STAT_GPIO25_Msk (0x2000000UL) /*!< GPIO25 (Bitfield-Mask: 0x01) */
#define GPIO_INT0STAT_GPIO24_Pos (24UL) /*!< GPIO24 (Bit 24) */
#define GPIO_INT0STAT_GPIO24_Msk (0x1000000UL) /*!< GPIO24 (Bitfield-Mask: 0x01) */
#define GPIO_INT0STAT_GPIO23_Pos (23UL) /*!< GPIO23 (Bit 23) */
#define GPIO_INT0STAT_GPIO23_Msk (0x800000UL) /*!< GPIO23 (Bitfield-Mask: 0x01) */
#define GPIO_INT0STAT_GPIO22_Pos (22UL) /*!< GPIO22 (Bit 22) */
#define GPIO_INT0STAT_GPIO22_Msk (0x400000UL) /*!< GPIO22 (Bitfield-Mask: 0x01) */
#define GPIO_INT0STAT_GPIO21_Pos (21UL) /*!< GPIO21 (Bit 21) */
#define GPIO_INT0STAT_GPIO21_Msk (0x200000UL) /*!< GPIO21 (Bitfield-Mask: 0x01) */
#define GPIO_INT0STAT_GPIO20_Pos (20UL) /*!< GPIO20 (Bit 20) */
#define GPIO_INT0STAT_GPIO20_Msk (0x100000UL) /*!< GPIO20 (Bitfield-Mask: 0x01) */
#define GPIO_INT0STAT_GPIO19_Pos (19UL) /*!< GPIO19 (Bit 19) */
#define GPIO_INT0STAT_GPIO19_Msk (0x80000UL) /*!< GPIO19 (Bitfield-Mask: 0x01) */
#define GPIO_INT0STAT_GPIO18_Pos (18UL) /*!< GPIO18 (Bit 18) */
#define GPIO_INT0STAT_GPIO18_Msk (0x40000UL) /*!< GPIO18 (Bitfield-Mask: 0x01) */
#define GPIO_INT0STAT_GPIO17_Pos (17UL) /*!< GPIO17 (Bit 17) */
#define GPIO_INT0STAT_GPIO17_Msk (0x20000UL) /*!< GPIO17 (Bitfield-Mask: 0x01) */
#define GPIO_INT0STAT_GPIO16_Pos (16UL) /*!< GPIO16 (Bit 16) */
#define GPIO_INT0STAT_GPIO16_Msk (0x10000UL) /*!< GPIO16 (Bitfield-Mask: 0x01) */
#define GPIO_INT0STAT_GPIO15_Pos (15UL) /*!< GPIO15 (Bit 15) */
#define GPIO_INT0STAT_GPIO15_Msk (0x8000UL) /*!< GPIO15 (Bitfield-Mask: 0x01) */
#define GPIO_INT0STAT_GPIO14_Pos (14UL) /*!< GPIO14 (Bit 14) */
#define GPIO_INT0STAT_GPIO14_Msk (0x4000UL) /*!< GPIO14 (Bitfield-Mask: 0x01) */
#define GPIO_INT0STAT_GPIO13_Pos (13UL) /*!< GPIO13 (Bit 13) */
#define GPIO_INT0STAT_GPIO13_Msk (0x2000UL) /*!< GPIO13 (Bitfield-Mask: 0x01) */
#define GPIO_INT0STAT_GPIO12_Pos (12UL) /*!< GPIO12 (Bit 12) */
#define GPIO_INT0STAT_GPIO12_Msk (0x1000UL) /*!< GPIO12 (Bitfield-Mask: 0x01) */
#define GPIO_INT0STAT_GPIO11_Pos (11UL) /*!< GPIO11 (Bit 11) */
#define GPIO_INT0STAT_GPIO11_Msk (0x800UL) /*!< GPIO11 (Bitfield-Mask: 0x01) */
#define GPIO_INT0STAT_GPIO10_Pos (10UL) /*!< GPIO10 (Bit 10) */
#define GPIO_INT0STAT_GPIO10_Msk (0x400UL) /*!< GPIO10 (Bitfield-Mask: 0x01) */
#define GPIO_INT0STAT_GPIO9_Pos (9UL) /*!< GPIO9 (Bit 9) */
#define GPIO_INT0STAT_GPIO9_Msk (0x200UL) /*!< GPIO9 (Bitfield-Mask: 0x01) */
#define GPIO_INT0STAT_GPIO8_Pos (8UL) /*!< GPIO8 (Bit 8) */
#define GPIO_INT0STAT_GPIO8_Msk (0x100UL) /*!< GPIO8 (Bitfield-Mask: 0x01) */
#define GPIO_INT0STAT_GPIO7_Pos (7UL) /*!< GPIO7 (Bit 7) */
#define GPIO_INT0STAT_GPIO7_Msk (0x80UL) /*!< GPIO7 (Bitfield-Mask: 0x01) */
#define GPIO_INT0STAT_GPIO6_Pos (6UL) /*!< GPIO6 (Bit 6) */
#define GPIO_INT0STAT_GPIO6_Msk (0x40UL) /*!< GPIO6 (Bitfield-Mask: 0x01) */
#define GPIO_INT0STAT_GPIO5_Pos (5UL) /*!< GPIO5 (Bit 5) */
#define GPIO_INT0STAT_GPIO5_Msk (0x20UL) /*!< GPIO5 (Bitfield-Mask: 0x01) */
#define GPIO_INT0STAT_GPIO4_Pos (4UL) /*!< GPIO4 (Bit 4) */
#define GPIO_INT0STAT_GPIO4_Msk (0x10UL) /*!< GPIO4 (Bitfield-Mask: 0x01) */
#define GPIO_INT0STAT_GPIO3_Pos (3UL) /*!< GPIO3 (Bit 3) */
#define GPIO_INT0STAT_GPIO3_Msk (0x8UL) /*!< GPIO3 (Bitfield-Mask: 0x01) */
#define GPIO_INT0STAT_GPIO2_Pos (2UL) /*!< GPIO2 (Bit 2) */
#define GPIO_INT0STAT_GPIO2_Msk (0x4UL) /*!< GPIO2 (Bitfield-Mask: 0x01) */
#define GPIO_INT0STAT_GPIO1_Pos (1UL) /*!< GPIO1 (Bit 1) */
#define GPIO_INT0STAT_GPIO1_Msk (0x2UL) /*!< GPIO1 (Bitfield-Mask: 0x01) */
#define GPIO_INT0STAT_GPIO0_Pos (0UL) /*!< GPIO0 (Bit 0) */
#define GPIO_INT0STAT_GPIO0_Msk (0x1UL) /*!< GPIO0 (Bitfield-Mask: 0x01) */
/* ======================================================== INT0CLR ======================================================== */
#define GPIO_INT0CLR_GPIO31_Pos (31UL) /*!< GPIO31 (Bit 31) */
#define GPIO_INT0CLR_GPIO31_Msk (0x80000000UL) /*!< GPIO31 (Bitfield-Mask: 0x01) */
#define GPIO_INT0CLR_GPIO30_Pos (30UL) /*!< GPIO30 (Bit 30) */
#define GPIO_INT0CLR_GPIO30_Msk (0x40000000UL) /*!< GPIO30 (Bitfield-Mask: 0x01) */
#define GPIO_INT0CLR_GPIO29_Pos (29UL) /*!< GPIO29 (Bit 29) */
#define GPIO_INT0CLR_GPIO29_Msk (0x20000000UL) /*!< GPIO29 (Bitfield-Mask: 0x01) */
#define GPIO_INT0CLR_GPIO28_Pos (28UL) /*!< GPIO28 (Bit 28) */
#define GPIO_INT0CLR_GPIO28_Msk (0x10000000UL) /*!< GPIO28 (Bitfield-Mask: 0x01) */
#define GPIO_INT0CLR_GPIO27_Pos (27UL) /*!< GPIO27 (Bit 27) */
#define GPIO_INT0CLR_GPIO27_Msk (0x8000000UL) /*!< GPIO27 (Bitfield-Mask: 0x01) */
#define GPIO_INT0CLR_GPIO26_Pos (26UL) /*!< GPIO26 (Bit 26) */
#define GPIO_INT0CLR_GPIO26_Msk (0x4000000UL) /*!< GPIO26 (Bitfield-Mask: 0x01) */
#define GPIO_INT0CLR_GPIO25_Pos (25UL) /*!< GPIO25 (Bit 25) */
#define GPIO_INT0CLR_GPIO25_Msk (0x2000000UL) /*!< GPIO25 (Bitfield-Mask: 0x01) */
#define GPIO_INT0CLR_GPIO24_Pos (24UL) /*!< GPIO24 (Bit 24) */
#define GPIO_INT0CLR_GPIO24_Msk (0x1000000UL) /*!< GPIO24 (Bitfield-Mask: 0x01) */
#define GPIO_INT0CLR_GPIO23_Pos (23UL) /*!< GPIO23 (Bit 23) */
#define GPIO_INT0CLR_GPIO23_Msk (0x800000UL) /*!< GPIO23 (Bitfield-Mask: 0x01) */
#define GPIO_INT0CLR_GPIO22_Pos (22UL) /*!< GPIO22 (Bit 22) */
#define GPIO_INT0CLR_GPIO22_Msk (0x400000UL) /*!< GPIO22 (Bitfield-Mask: 0x01) */
#define GPIO_INT0CLR_GPIO21_Pos (21UL) /*!< GPIO21 (Bit 21) */
#define GPIO_INT0CLR_GPIO21_Msk (0x200000UL) /*!< GPIO21 (Bitfield-Mask: 0x01) */
#define GPIO_INT0CLR_GPIO20_Pos (20UL) /*!< GPIO20 (Bit 20) */
#define GPIO_INT0CLR_GPIO20_Msk (0x100000UL) /*!< GPIO20 (Bitfield-Mask: 0x01) */
#define GPIO_INT0CLR_GPIO19_Pos (19UL) /*!< GPIO19 (Bit 19) */
#define GPIO_INT0CLR_GPIO19_Msk (0x80000UL) /*!< GPIO19 (Bitfield-Mask: 0x01) */
#define GPIO_INT0CLR_GPIO18_Pos (18UL) /*!< GPIO18 (Bit 18) */
#define GPIO_INT0CLR_GPIO18_Msk (0x40000UL) /*!< GPIO18 (Bitfield-Mask: 0x01) */
#define GPIO_INT0CLR_GPIO17_Pos (17UL) /*!< GPIO17 (Bit 17) */
#define GPIO_INT0CLR_GPIO17_Msk (0x20000UL) /*!< GPIO17 (Bitfield-Mask: 0x01) */
#define GPIO_INT0CLR_GPIO16_Pos (16UL) /*!< GPIO16 (Bit 16) */
#define GPIO_INT0CLR_GPIO16_Msk (0x10000UL) /*!< GPIO16 (Bitfield-Mask: 0x01) */
#define GPIO_INT0CLR_GPIO15_Pos (15UL) /*!< GPIO15 (Bit 15) */
#define GPIO_INT0CLR_GPIO15_Msk (0x8000UL) /*!< GPIO15 (Bitfield-Mask: 0x01) */
#define GPIO_INT0CLR_GPIO14_Pos (14UL) /*!< GPIO14 (Bit 14) */
#define GPIO_INT0CLR_GPIO14_Msk (0x4000UL) /*!< GPIO14 (Bitfield-Mask: 0x01) */
#define GPIO_INT0CLR_GPIO13_Pos (13UL) /*!< GPIO13 (Bit 13) */
#define GPIO_INT0CLR_GPIO13_Msk (0x2000UL) /*!< GPIO13 (Bitfield-Mask: 0x01) */
#define GPIO_INT0CLR_GPIO12_Pos (12UL) /*!< GPIO12 (Bit 12) */
#define GPIO_INT0CLR_GPIO12_Msk (0x1000UL) /*!< GPIO12 (Bitfield-Mask: 0x01) */
#define GPIO_INT0CLR_GPIO11_Pos (11UL) /*!< GPIO11 (Bit 11) */
#define GPIO_INT0CLR_GPIO11_Msk (0x800UL) /*!< GPIO11 (Bitfield-Mask: 0x01) */
#define GPIO_INT0CLR_GPIO10_Pos (10UL) /*!< GPIO10 (Bit 10) */
#define GPIO_INT0CLR_GPIO10_Msk (0x400UL) /*!< GPIO10 (Bitfield-Mask: 0x01) */
#define GPIO_INT0CLR_GPIO9_Pos (9UL) /*!< GPIO9 (Bit 9) */
#define GPIO_INT0CLR_GPIO9_Msk (0x200UL) /*!< GPIO9 (Bitfield-Mask: 0x01) */
#define GPIO_INT0CLR_GPIO8_Pos (8UL) /*!< GPIO8 (Bit 8) */
#define GPIO_INT0CLR_GPIO8_Msk (0x100UL) /*!< GPIO8 (Bitfield-Mask: 0x01) */
#define GPIO_INT0CLR_GPIO7_Pos (7UL) /*!< GPIO7 (Bit 7) */
#define GPIO_INT0CLR_GPIO7_Msk (0x80UL) /*!< GPIO7 (Bitfield-Mask: 0x01) */
#define GPIO_INT0CLR_GPIO6_Pos (6UL) /*!< GPIO6 (Bit 6) */
#define GPIO_INT0CLR_GPIO6_Msk (0x40UL) /*!< GPIO6 (Bitfield-Mask: 0x01) */
#define GPIO_INT0CLR_GPIO5_Pos (5UL) /*!< GPIO5 (Bit 5) */
#define GPIO_INT0CLR_GPIO5_Msk (0x20UL) /*!< GPIO5 (Bitfield-Mask: 0x01) */
#define GPIO_INT0CLR_GPIO4_Pos (4UL) /*!< GPIO4 (Bit 4) */
#define GPIO_INT0CLR_GPIO4_Msk (0x10UL) /*!< GPIO4 (Bitfield-Mask: 0x01) */
#define GPIO_INT0CLR_GPIO3_Pos (3UL) /*!< GPIO3 (Bit 3) */
#define GPIO_INT0CLR_GPIO3_Msk (0x8UL) /*!< GPIO3 (Bitfield-Mask: 0x01) */
#define GPIO_INT0CLR_GPIO2_Pos (2UL) /*!< GPIO2 (Bit 2) */
#define GPIO_INT0CLR_GPIO2_Msk (0x4UL) /*!< GPIO2 (Bitfield-Mask: 0x01) */
#define GPIO_INT0CLR_GPIO1_Pos (1UL) /*!< GPIO1 (Bit 1) */
#define GPIO_INT0CLR_GPIO1_Msk (0x2UL) /*!< GPIO1 (Bitfield-Mask: 0x01) */
#define GPIO_INT0CLR_GPIO0_Pos (0UL) /*!< GPIO0 (Bit 0) */
#define GPIO_INT0CLR_GPIO0_Msk (0x1UL) /*!< GPIO0 (Bitfield-Mask: 0x01) */
/* ======================================================== INT0SET ======================================================== */
#define GPIO_INT0SET_GPIO31_Pos (31UL) /*!< GPIO31 (Bit 31) */
#define GPIO_INT0SET_GPIO31_Msk (0x80000000UL) /*!< GPIO31 (Bitfield-Mask: 0x01) */
#define GPIO_INT0SET_GPIO30_Pos (30UL) /*!< GPIO30 (Bit 30) */
#define GPIO_INT0SET_GPIO30_Msk (0x40000000UL) /*!< GPIO30 (Bitfield-Mask: 0x01) */
#define GPIO_INT0SET_GPIO29_Pos (29UL) /*!< GPIO29 (Bit 29) */
#define GPIO_INT0SET_GPIO29_Msk (0x20000000UL) /*!< GPIO29 (Bitfield-Mask: 0x01) */
#define GPIO_INT0SET_GPIO28_Pos (28UL) /*!< GPIO28 (Bit 28) */
#define GPIO_INT0SET_GPIO28_Msk (0x10000000UL) /*!< GPIO28 (Bitfield-Mask: 0x01) */
#define GPIO_INT0SET_GPIO27_Pos (27UL) /*!< GPIO27 (Bit 27) */
#define GPIO_INT0SET_GPIO27_Msk (0x8000000UL) /*!< GPIO27 (Bitfield-Mask: 0x01) */
#define GPIO_INT0SET_GPIO26_Pos (26UL) /*!< GPIO26 (Bit 26) */
#define GPIO_INT0SET_GPIO26_Msk (0x4000000UL) /*!< GPIO26 (Bitfield-Mask: 0x01) */
#define GPIO_INT0SET_GPIO25_Pos (25UL) /*!< GPIO25 (Bit 25) */
#define GPIO_INT0SET_GPIO25_Msk (0x2000000UL) /*!< GPIO25 (Bitfield-Mask: 0x01) */
#define GPIO_INT0SET_GPIO24_Pos (24UL) /*!< GPIO24 (Bit 24) */
#define GPIO_INT0SET_GPIO24_Msk (0x1000000UL) /*!< GPIO24 (Bitfield-Mask: 0x01) */
#define GPIO_INT0SET_GPIO23_Pos (23UL) /*!< GPIO23 (Bit 23) */
#define GPIO_INT0SET_GPIO23_Msk (0x800000UL) /*!< GPIO23 (Bitfield-Mask: 0x01) */
#define GPIO_INT0SET_GPIO22_Pos (22UL) /*!< GPIO22 (Bit 22) */
#define GPIO_INT0SET_GPIO22_Msk (0x400000UL) /*!< GPIO22 (Bitfield-Mask: 0x01) */
#define GPIO_INT0SET_GPIO21_Pos (21UL) /*!< GPIO21 (Bit 21) */
#define GPIO_INT0SET_GPIO21_Msk (0x200000UL) /*!< GPIO21 (Bitfield-Mask: 0x01) */
#define GPIO_INT0SET_GPIO20_Pos (20UL) /*!< GPIO20 (Bit 20) */
#define GPIO_INT0SET_GPIO20_Msk (0x100000UL) /*!< GPIO20 (Bitfield-Mask: 0x01) */
#define GPIO_INT0SET_GPIO19_Pos (19UL) /*!< GPIO19 (Bit 19) */
#define GPIO_INT0SET_GPIO19_Msk (0x80000UL) /*!< GPIO19 (Bitfield-Mask: 0x01) */
#define GPIO_INT0SET_GPIO18_Pos (18UL) /*!< GPIO18 (Bit 18) */
#define GPIO_INT0SET_GPIO18_Msk (0x40000UL) /*!< GPIO18 (Bitfield-Mask: 0x01) */
#define GPIO_INT0SET_GPIO17_Pos (17UL) /*!< GPIO17 (Bit 17) */
#define GPIO_INT0SET_GPIO17_Msk (0x20000UL) /*!< GPIO17 (Bitfield-Mask: 0x01) */
#define GPIO_INT0SET_GPIO16_Pos (16UL) /*!< GPIO16 (Bit 16) */
#define GPIO_INT0SET_GPIO16_Msk (0x10000UL) /*!< GPIO16 (Bitfield-Mask: 0x01) */
#define GPIO_INT0SET_GPIO15_Pos (15UL) /*!< GPIO15 (Bit 15) */
#define GPIO_INT0SET_GPIO15_Msk (0x8000UL) /*!< GPIO15 (Bitfield-Mask: 0x01) */
#define GPIO_INT0SET_GPIO14_Pos (14UL) /*!< GPIO14 (Bit 14) */
#define GPIO_INT0SET_GPIO14_Msk (0x4000UL) /*!< GPIO14 (Bitfield-Mask: 0x01) */
#define GPIO_INT0SET_GPIO13_Pos (13UL) /*!< GPIO13 (Bit 13) */
#define GPIO_INT0SET_GPIO13_Msk (0x2000UL) /*!< GPIO13 (Bitfield-Mask: 0x01) */
#define GPIO_INT0SET_GPIO12_Pos (12UL) /*!< GPIO12 (Bit 12) */
#define GPIO_INT0SET_GPIO12_Msk (0x1000UL) /*!< GPIO12 (Bitfield-Mask: 0x01) */
#define GPIO_INT0SET_GPIO11_Pos (11UL) /*!< GPIO11 (Bit 11) */
#define GPIO_INT0SET_GPIO11_Msk (0x800UL) /*!< GPIO11 (Bitfield-Mask: 0x01) */
#define GPIO_INT0SET_GPIO10_Pos (10UL) /*!< GPIO10 (Bit 10) */
#define GPIO_INT0SET_GPIO10_Msk (0x400UL) /*!< GPIO10 (Bitfield-Mask: 0x01) */
#define GPIO_INT0SET_GPIO9_Pos (9UL) /*!< GPIO9 (Bit 9) */
#define GPIO_INT0SET_GPIO9_Msk (0x200UL) /*!< GPIO9 (Bitfield-Mask: 0x01) */
#define GPIO_INT0SET_GPIO8_Pos (8UL) /*!< GPIO8 (Bit 8) */
#define GPIO_INT0SET_GPIO8_Msk (0x100UL) /*!< GPIO8 (Bitfield-Mask: 0x01) */
#define GPIO_INT0SET_GPIO7_Pos (7UL) /*!< GPIO7 (Bit 7) */
#define GPIO_INT0SET_GPIO7_Msk (0x80UL) /*!< GPIO7 (Bitfield-Mask: 0x01) */
#define GPIO_INT0SET_GPIO6_Pos (6UL) /*!< GPIO6 (Bit 6) */
#define GPIO_INT0SET_GPIO6_Msk (0x40UL) /*!< GPIO6 (Bitfield-Mask: 0x01) */
#define GPIO_INT0SET_GPIO5_Pos (5UL) /*!< GPIO5 (Bit 5) */
#define GPIO_INT0SET_GPIO5_Msk (0x20UL) /*!< GPIO5 (Bitfield-Mask: 0x01) */
#define GPIO_INT0SET_GPIO4_Pos (4UL) /*!< GPIO4 (Bit 4) */
#define GPIO_INT0SET_GPIO4_Msk (0x10UL) /*!< GPIO4 (Bitfield-Mask: 0x01) */
#define GPIO_INT0SET_GPIO3_Pos (3UL) /*!< GPIO3 (Bit 3) */
#define GPIO_INT0SET_GPIO3_Msk (0x8UL) /*!< GPIO3 (Bitfield-Mask: 0x01) */
#define GPIO_INT0SET_GPIO2_Pos (2UL) /*!< GPIO2 (Bit 2) */
#define GPIO_INT0SET_GPIO2_Msk (0x4UL) /*!< GPIO2 (Bitfield-Mask: 0x01) */
#define GPIO_INT0SET_GPIO1_Pos (1UL) /*!< GPIO1 (Bit 1) */
#define GPIO_INT0SET_GPIO1_Msk (0x2UL) /*!< GPIO1 (Bitfield-Mask: 0x01) */
#define GPIO_INT0SET_GPIO0_Pos (0UL) /*!< GPIO0 (Bit 0) */
#define GPIO_INT0SET_GPIO0_Msk (0x1UL) /*!< GPIO0 (Bitfield-Mask: 0x01) */
/* ======================================================== INT1EN ========================================================= */
#define GPIO_INT1EN_GPIO49_Pos (17UL) /*!< GPIO49 (Bit 17) */
#define GPIO_INT1EN_GPIO49_Msk (0x20000UL) /*!< GPIO49 (Bitfield-Mask: 0x01) */
#define GPIO_INT1EN_GPIO48_Pos (16UL) /*!< GPIO48 (Bit 16) */
#define GPIO_INT1EN_GPIO48_Msk (0x10000UL) /*!< GPIO48 (Bitfield-Mask: 0x01) */
#define GPIO_INT1EN_GPIO47_Pos (15UL) /*!< GPIO47 (Bit 15) */
#define GPIO_INT1EN_GPIO47_Msk (0x8000UL) /*!< GPIO47 (Bitfield-Mask: 0x01) */
#define GPIO_INT1EN_GPIO46_Pos (14UL) /*!< GPIO46 (Bit 14) */
#define GPIO_INT1EN_GPIO46_Msk (0x4000UL) /*!< GPIO46 (Bitfield-Mask: 0x01) */
#define GPIO_INT1EN_GPIO45_Pos (13UL) /*!< GPIO45 (Bit 13) */
#define GPIO_INT1EN_GPIO45_Msk (0x2000UL) /*!< GPIO45 (Bitfield-Mask: 0x01) */
#define GPIO_INT1EN_GPIO44_Pos (12UL) /*!< GPIO44 (Bit 12) */
#define GPIO_INT1EN_GPIO44_Msk (0x1000UL) /*!< GPIO44 (Bitfield-Mask: 0x01) */
#define GPIO_INT1EN_GPIO43_Pos (11UL) /*!< GPIO43 (Bit 11) */
#define GPIO_INT1EN_GPIO43_Msk (0x800UL) /*!< GPIO43 (Bitfield-Mask: 0x01) */
#define GPIO_INT1EN_GPIO42_Pos (10UL) /*!< GPIO42 (Bit 10) */
#define GPIO_INT1EN_GPIO42_Msk (0x400UL) /*!< GPIO42 (Bitfield-Mask: 0x01) */
#define GPIO_INT1EN_GPIO41_Pos (9UL) /*!< GPIO41 (Bit 9) */
#define GPIO_INT1EN_GPIO41_Msk (0x200UL) /*!< GPIO41 (Bitfield-Mask: 0x01) */
#define GPIO_INT1EN_GPIO40_Pos (8UL) /*!< GPIO40 (Bit 8) */
#define GPIO_INT1EN_GPIO40_Msk (0x100UL) /*!< GPIO40 (Bitfield-Mask: 0x01) */
#define GPIO_INT1EN_GPIO39_Pos (7UL) /*!< GPIO39 (Bit 7) */
#define GPIO_INT1EN_GPIO39_Msk (0x80UL) /*!< GPIO39 (Bitfield-Mask: 0x01) */
#define GPIO_INT1EN_GPIO38_Pos (6UL) /*!< GPIO38 (Bit 6) */
#define GPIO_INT1EN_GPIO38_Msk (0x40UL) /*!< GPIO38 (Bitfield-Mask: 0x01) */
#define GPIO_INT1EN_GPIO37_Pos (5UL) /*!< GPIO37 (Bit 5) */
#define GPIO_INT1EN_GPIO37_Msk (0x20UL) /*!< GPIO37 (Bitfield-Mask: 0x01) */
#define GPIO_INT1EN_GPIO36_Pos (4UL) /*!< GPIO36 (Bit 4) */
#define GPIO_INT1EN_GPIO36_Msk (0x10UL) /*!< GPIO36 (Bitfield-Mask: 0x01) */
#define GPIO_INT1EN_GPIO35_Pos (3UL) /*!< GPIO35 (Bit 3) */
#define GPIO_INT1EN_GPIO35_Msk (0x8UL) /*!< GPIO35 (Bitfield-Mask: 0x01) */
#define GPIO_INT1EN_GPIO34_Pos (2UL) /*!< GPIO34 (Bit 2) */
#define GPIO_INT1EN_GPIO34_Msk (0x4UL) /*!< GPIO34 (Bitfield-Mask: 0x01) */
#define GPIO_INT1EN_GPIO33_Pos (1UL) /*!< GPIO33 (Bit 1) */
#define GPIO_INT1EN_GPIO33_Msk (0x2UL) /*!< GPIO33 (Bitfield-Mask: 0x01) */
#define GPIO_INT1EN_GPIO32_Pos (0UL) /*!< GPIO32 (Bit 0) */
#define GPIO_INT1EN_GPIO32_Msk (0x1UL) /*!< GPIO32 (Bitfield-Mask: 0x01) */
/* ======================================================= INT1STAT ======================================================== */
#define GPIO_INT1STAT_GPIO49_Pos (17UL) /*!< GPIO49 (Bit 17) */
#define GPIO_INT1STAT_GPIO49_Msk (0x20000UL) /*!< GPIO49 (Bitfield-Mask: 0x01) */
#define GPIO_INT1STAT_GPIO48_Pos (16UL) /*!< GPIO48 (Bit 16) */
#define GPIO_INT1STAT_GPIO48_Msk (0x10000UL) /*!< GPIO48 (Bitfield-Mask: 0x01) */
#define GPIO_INT1STAT_GPIO47_Pos (15UL) /*!< GPIO47 (Bit 15) */
#define GPIO_INT1STAT_GPIO47_Msk (0x8000UL) /*!< GPIO47 (Bitfield-Mask: 0x01) */
#define GPIO_INT1STAT_GPIO46_Pos (14UL) /*!< GPIO46 (Bit 14) */
#define GPIO_INT1STAT_GPIO46_Msk (0x4000UL) /*!< GPIO46 (Bitfield-Mask: 0x01) */
#define GPIO_INT1STAT_GPIO45_Pos (13UL) /*!< GPIO45 (Bit 13) */
#define GPIO_INT1STAT_GPIO45_Msk (0x2000UL) /*!< GPIO45 (Bitfield-Mask: 0x01) */
#define GPIO_INT1STAT_GPIO44_Pos (12UL) /*!< GPIO44 (Bit 12) */
#define GPIO_INT1STAT_GPIO44_Msk (0x1000UL) /*!< GPIO44 (Bitfield-Mask: 0x01) */
#define GPIO_INT1STAT_GPIO43_Pos (11UL) /*!< GPIO43 (Bit 11) */
#define GPIO_INT1STAT_GPIO43_Msk (0x800UL) /*!< GPIO43 (Bitfield-Mask: 0x01) */
#define GPIO_INT1STAT_GPIO42_Pos (10UL) /*!< GPIO42 (Bit 10) */
#define GPIO_INT1STAT_GPIO42_Msk (0x400UL) /*!< GPIO42 (Bitfield-Mask: 0x01) */
#define GPIO_INT1STAT_GPIO41_Pos (9UL) /*!< GPIO41 (Bit 9) */
#define GPIO_INT1STAT_GPIO41_Msk (0x200UL) /*!< GPIO41 (Bitfield-Mask: 0x01) */
#define GPIO_INT1STAT_GPIO40_Pos (8UL) /*!< GPIO40 (Bit 8) */
#define GPIO_INT1STAT_GPIO40_Msk (0x100UL) /*!< GPIO40 (Bitfield-Mask: 0x01) */
#define GPIO_INT1STAT_GPIO39_Pos (7UL) /*!< GPIO39 (Bit 7) */
#define GPIO_INT1STAT_GPIO39_Msk (0x80UL) /*!< GPIO39 (Bitfield-Mask: 0x01) */
#define GPIO_INT1STAT_GPIO38_Pos (6UL) /*!< GPIO38 (Bit 6) */
#define GPIO_INT1STAT_GPIO38_Msk (0x40UL) /*!< GPIO38 (Bitfield-Mask: 0x01) */
#define GPIO_INT1STAT_GPIO37_Pos (5UL) /*!< GPIO37 (Bit 5) */
#define GPIO_INT1STAT_GPIO37_Msk (0x20UL) /*!< GPIO37 (Bitfield-Mask: 0x01) */
#define GPIO_INT1STAT_GPIO36_Pos (4UL) /*!< GPIO36 (Bit 4) */
#define GPIO_INT1STAT_GPIO36_Msk (0x10UL) /*!< GPIO36 (Bitfield-Mask: 0x01) */
#define GPIO_INT1STAT_GPIO35_Pos (3UL) /*!< GPIO35 (Bit 3) */
#define GPIO_INT1STAT_GPIO35_Msk (0x8UL) /*!< GPIO35 (Bitfield-Mask: 0x01) */
#define GPIO_INT1STAT_GPIO34_Pos (2UL) /*!< GPIO34 (Bit 2) */
#define GPIO_INT1STAT_GPIO34_Msk (0x4UL) /*!< GPIO34 (Bitfield-Mask: 0x01) */
#define GPIO_INT1STAT_GPIO33_Pos (1UL) /*!< GPIO33 (Bit 1) */
#define GPIO_INT1STAT_GPIO33_Msk (0x2UL) /*!< GPIO33 (Bitfield-Mask: 0x01) */
#define GPIO_INT1STAT_GPIO32_Pos (0UL) /*!< GPIO32 (Bit 0) */
#define GPIO_INT1STAT_GPIO32_Msk (0x1UL) /*!< GPIO32 (Bitfield-Mask: 0x01) */
/* ======================================================== INT1CLR ======================================================== */
#define GPIO_INT1CLR_GPIO49_Pos (17UL) /*!< GPIO49 (Bit 17) */
#define GPIO_INT1CLR_GPIO49_Msk (0x20000UL) /*!< GPIO49 (Bitfield-Mask: 0x01) */
#define GPIO_INT1CLR_GPIO48_Pos (16UL) /*!< GPIO48 (Bit 16) */
#define GPIO_INT1CLR_GPIO48_Msk (0x10000UL) /*!< GPIO48 (Bitfield-Mask: 0x01) */
#define GPIO_INT1CLR_GPIO47_Pos (15UL) /*!< GPIO47 (Bit 15) */
#define GPIO_INT1CLR_GPIO47_Msk (0x8000UL) /*!< GPIO47 (Bitfield-Mask: 0x01) */
#define GPIO_INT1CLR_GPIO46_Pos (14UL) /*!< GPIO46 (Bit 14) */
#define GPIO_INT1CLR_GPIO46_Msk (0x4000UL) /*!< GPIO46 (Bitfield-Mask: 0x01) */
#define GPIO_INT1CLR_GPIO45_Pos (13UL) /*!< GPIO45 (Bit 13) */
#define GPIO_INT1CLR_GPIO45_Msk (0x2000UL) /*!< GPIO45 (Bitfield-Mask: 0x01) */
#define GPIO_INT1CLR_GPIO44_Pos (12UL) /*!< GPIO44 (Bit 12) */
#define GPIO_INT1CLR_GPIO44_Msk (0x1000UL) /*!< GPIO44 (Bitfield-Mask: 0x01) */
#define GPIO_INT1CLR_GPIO43_Pos (11UL) /*!< GPIO43 (Bit 11) */
#define GPIO_INT1CLR_GPIO43_Msk (0x800UL) /*!< GPIO43 (Bitfield-Mask: 0x01) */
#define GPIO_INT1CLR_GPIO42_Pos (10UL) /*!< GPIO42 (Bit 10) */
#define GPIO_INT1CLR_GPIO42_Msk (0x400UL) /*!< GPIO42 (Bitfield-Mask: 0x01) */
#define GPIO_INT1CLR_GPIO41_Pos (9UL) /*!< GPIO41 (Bit 9) */
#define GPIO_INT1CLR_GPIO41_Msk (0x200UL) /*!< GPIO41 (Bitfield-Mask: 0x01) */
#define GPIO_INT1CLR_GPIO40_Pos (8UL) /*!< GPIO40 (Bit 8) */
#define GPIO_INT1CLR_GPIO40_Msk (0x100UL) /*!< GPIO40 (Bitfield-Mask: 0x01) */
#define GPIO_INT1CLR_GPIO39_Pos (7UL) /*!< GPIO39 (Bit 7) */
#define GPIO_INT1CLR_GPIO39_Msk (0x80UL) /*!< GPIO39 (Bitfield-Mask: 0x01) */
#define GPIO_INT1CLR_GPIO38_Pos (6UL) /*!< GPIO38 (Bit 6) */
#define GPIO_INT1CLR_GPIO38_Msk (0x40UL) /*!< GPIO38 (Bitfield-Mask: 0x01) */
#define GPIO_INT1CLR_GPIO37_Pos (5UL) /*!< GPIO37 (Bit 5) */
#define GPIO_INT1CLR_GPIO37_Msk (0x20UL) /*!< GPIO37 (Bitfield-Mask: 0x01) */
#define GPIO_INT1CLR_GPIO36_Pos (4UL) /*!< GPIO36 (Bit 4) */
#define GPIO_INT1CLR_GPIO36_Msk (0x10UL) /*!< GPIO36 (Bitfield-Mask: 0x01) */
#define GPIO_INT1CLR_GPIO35_Pos (3UL) /*!< GPIO35 (Bit 3) */
#define GPIO_INT1CLR_GPIO35_Msk (0x8UL) /*!< GPIO35 (Bitfield-Mask: 0x01) */
#define GPIO_INT1CLR_GPIO34_Pos (2UL) /*!< GPIO34 (Bit 2) */
#define GPIO_INT1CLR_GPIO34_Msk (0x4UL) /*!< GPIO34 (Bitfield-Mask: 0x01) */
#define GPIO_INT1CLR_GPIO33_Pos (1UL) /*!< GPIO33 (Bit 1) */
#define GPIO_INT1CLR_GPIO33_Msk (0x2UL) /*!< GPIO33 (Bitfield-Mask: 0x01) */
#define GPIO_INT1CLR_GPIO32_Pos (0UL) /*!< GPIO32 (Bit 0) */
#define GPIO_INT1CLR_GPIO32_Msk (0x1UL) /*!< GPIO32 (Bitfield-Mask: 0x01) */
/* ======================================================== INT1SET ======================================================== */
#define GPIO_INT1SET_GPIO49_Pos (17UL) /*!< GPIO49 (Bit 17) */
#define GPIO_INT1SET_GPIO49_Msk (0x20000UL) /*!< GPIO49 (Bitfield-Mask: 0x01) */
#define GPIO_INT1SET_GPIO48_Pos (16UL) /*!< GPIO48 (Bit 16) */
#define GPIO_INT1SET_GPIO48_Msk (0x10000UL) /*!< GPIO48 (Bitfield-Mask: 0x01) */
#define GPIO_INT1SET_GPIO47_Pos (15UL) /*!< GPIO47 (Bit 15) */
#define GPIO_INT1SET_GPIO47_Msk (0x8000UL) /*!< GPIO47 (Bitfield-Mask: 0x01) */
#define GPIO_INT1SET_GPIO46_Pos (14UL) /*!< GPIO46 (Bit 14) */
#define GPIO_INT1SET_GPIO46_Msk (0x4000UL) /*!< GPIO46 (Bitfield-Mask: 0x01) */
#define GPIO_INT1SET_GPIO45_Pos (13UL) /*!< GPIO45 (Bit 13) */
#define GPIO_INT1SET_GPIO45_Msk (0x2000UL) /*!< GPIO45 (Bitfield-Mask: 0x01) */
#define GPIO_INT1SET_GPIO44_Pos (12UL) /*!< GPIO44 (Bit 12) */
#define GPIO_INT1SET_GPIO44_Msk (0x1000UL) /*!< GPIO44 (Bitfield-Mask: 0x01) */
#define GPIO_INT1SET_GPIO43_Pos (11UL) /*!< GPIO43 (Bit 11) */
#define GPIO_INT1SET_GPIO43_Msk (0x800UL) /*!< GPIO43 (Bitfield-Mask: 0x01) */
#define GPIO_INT1SET_GPIO42_Pos (10UL) /*!< GPIO42 (Bit 10) */
#define GPIO_INT1SET_GPIO42_Msk (0x400UL) /*!< GPIO42 (Bitfield-Mask: 0x01) */
#define GPIO_INT1SET_GPIO41_Pos (9UL) /*!< GPIO41 (Bit 9) */
#define GPIO_INT1SET_GPIO41_Msk (0x200UL) /*!< GPIO41 (Bitfield-Mask: 0x01) */
#define GPIO_INT1SET_GPIO40_Pos (8UL) /*!< GPIO40 (Bit 8) */
#define GPIO_INT1SET_GPIO40_Msk (0x100UL) /*!< GPIO40 (Bitfield-Mask: 0x01) */
#define GPIO_INT1SET_GPIO39_Pos (7UL) /*!< GPIO39 (Bit 7) */
#define GPIO_INT1SET_GPIO39_Msk (0x80UL) /*!< GPIO39 (Bitfield-Mask: 0x01) */
#define GPIO_INT1SET_GPIO38_Pos (6UL) /*!< GPIO38 (Bit 6) */
#define GPIO_INT1SET_GPIO38_Msk (0x40UL) /*!< GPIO38 (Bitfield-Mask: 0x01) */
#define GPIO_INT1SET_GPIO37_Pos (5UL) /*!< GPIO37 (Bit 5) */
#define GPIO_INT1SET_GPIO37_Msk (0x20UL) /*!< GPIO37 (Bitfield-Mask: 0x01) */
#define GPIO_INT1SET_GPIO36_Pos (4UL) /*!< GPIO36 (Bit 4) */
#define GPIO_INT1SET_GPIO36_Msk (0x10UL) /*!< GPIO36 (Bitfield-Mask: 0x01) */
#define GPIO_INT1SET_GPIO35_Pos (3UL) /*!< GPIO35 (Bit 3) */
#define GPIO_INT1SET_GPIO35_Msk (0x8UL) /*!< GPIO35 (Bitfield-Mask: 0x01) */
#define GPIO_INT1SET_GPIO34_Pos (2UL) /*!< GPIO34 (Bit 2) */
#define GPIO_INT1SET_GPIO34_Msk (0x4UL) /*!< GPIO34 (Bitfield-Mask: 0x01) */
#define GPIO_INT1SET_GPIO33_Pos (1UL) /*!< GPIO33 (Bit 1) */
#define GPIO_INT1SET_GPIO33_Msk (0x2UL) /*!< GPIO33 (Bitfield-Mask: 0x01) */
#define GPIO_INT1SET_GPIO32_Pos (0UL) /*!< GPIO32 (Bit 0) */
#define GPIO_INT1SET_GPIO32_Msk (0x1UL) /*!< GPIO32 (Bitfield-Mask: 0x01) */
/* =========================================================================================================================== */
/* ================ IOM0 ================ */
/* =========================================================================================================================== */
/* ========================================================= FIFO ========================================================== */
#define IOM0_FIFO_FIFO_Pos (0UL) /*!< FIFO (Bit 0) */
#define IOM0_FIFO_FIFO_Msk (0xffffffffUL) /*!< FIFO (Bitfield-Mask: 0xffffffff) */
/* ======================================================== FIFOPTR ======================================================== */
#define IOM0_FIFOPTR_FIFO1REM_Pos (24UL) /*!< FIFO1REM (Bit 24) */
#define IOM0_FIFOPTR_FIFO1REM_Msk (0xff000000UL) /*!< FIFO1REM (Bitfield-Mask: 0xff) */
#define IOM0_FIFOPTR_FIFO1SIZ_Pos (16UL) /*!< FIFO1SIZ (Bit 16) */
#define IOM0_FIFOPTR_FIFO1SIZ_Msk (0xff0000UL) /*!< FIFO1SIZ (Bitfield-Mask: 0xff) */
#define IOM0_FIFOPTR_FIFO0REM_Pos (8UL) /*!< FIFO0REM (Bit 8) */
#define IOM0_FIFOPTR_FIFO0REM_Msk (0xff00UL) /*!< FIFO0REM (Bitfield-Mask: 0xff) */
#define IOM0_FIFOPTR_FIFO0SIZ_Pos (0UL) /*!< FIFO0SIZ (Bit 0) */
#define IOM0_FIFOPTR_FIFO0SIZ_Msk (0xffUL) /*!< FIFO0SIZ (Bitfield-Mask: 0xff) */
/* ======================================================== FIFOTHR ======================================================== */
#define IOM0_FIFOTHR_FIFOWTHR_Pos (8UL) /*!< FIFOWTHR (Bit 8) */
#define IOM0_FIFOTHR_FIFOWTHR_Msk (0x3f00UL) /*!< FIFOWTHR (Bitfield-Mask: 0x3f) */
#define IOM0_FIFOTHR_FIFORTHR_Pos (0UL) /*!< FIFORTHR (Bit 0) */
#define IOM0_FIFOTHR_FIFORTHR_Msk (0x3fUL) /*!< FIFORTHR (Bitfield-Mask: 0x3f) */
/* ======================================================== FIFOPOP ======================================================== */
#define IOM0_FIFOPOP_FIFODOUT_Pos (0UL) /*!< FIFODOUT (Bit 0) */
#define IOM0_FIFOPOP_FIFODOUT_Msk (0xffffffffUL) /*!< FIFODOUT (Bitfield-Mask: 0xffffffff) */
/* ======================================================= FIFOPUSH ======================================================== */
#define IOM0_FIFOPUSH_FIFODIN_Pos (0UL) /*!< FIFODIN (Bit 0) */
#define IOM0_FIFOPUSH_FIFODIN_Msk (0xffffffffUL) /*!< FIFODIN (Bitfield-Mask: 0xffffffff) */
/* ======================================================= FIFOCTRL ======================================================== */
#define IOM0_FIFOCTRL_FIFORSTN_Pos (1UL) /*!< FIFORSTN (Bit 1) */
#define IOM0_FIFOCTRL_FIFORSTN_Msk (0x2UL) /*!< FIFORSTN (Bitfield-Mask: 0x01) */
#define IOM0_FIFOCTRL_POPWR_Pos (0UL) /*!< POPWR (Bit 0) */
#define IOM0_FIFOCTRL_POPWR_Msk (0x1UL) /*!< POPWR (Bitfield-Mask: 0x01) */
/* ======================================================== FIFOLOC ======================================================== */
#define IOM0_FIFOLOC_FIFORPTR_Pos (8UL) /*!< FIFORPTR (Bit 8) */
#define IOM0_FIFOLOC_FIFORPTR_Msk (0xf00UL) /*!< FIFORPTR (Bitfield-Mask: 0x0f) */
#define IOM0_FIFOLOC_FIFOWPTR_Pos (0UL) /*!< FIFOWPTR (Bit 0) */
#define IOM0_FIFOLOC_FIFOWPTR_Msk (0xfUL) /*!< FIFOWPTR (Bitfield-Mask: 0x0f) */
/* ========================================================= INTEN ========================================================= */
#define IOM0_INTEN_CQERR_Pos (14UL) /*!< CQERR (Bit 14) */
#define IOM0_INTEN_CQERR_Msk (0x4000UL) /*!< CQERR (Bitfield-Mask: 0x01) */
#define IOM0_INTEN_CQUPD_Pos (13UL) /*!< CQUPD (Bit 13) */
#define IOM0_INTEN_CQUPD_Msk (0x2000UL) /*!< CQUPD (Bitfield-Mask: 0x01) */
#define IOM0_INTEN_CQPAUSED_Pos (12UL) /*!< CQPAUSED (Bit 12) */
#define IOM0_INTEN_CQPAUSED_Msk (0x1000UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */
#define IOM0_INTEN_DERR_Pos (11UL) /*!< DERR (Bit 11) */
#define IOM0_INTEN_DERR_Msk (0x800UL) /*!< DERR (Bitfield-Mask: 0x01) */
#define IOM0_INTEN_DCMP_Pos (10UL) /*!< DCMP (Bit 10) */
#define IOM0_INTEN_DCMP_Msk (0x400UL) /*!< DCMP (Bitfield-Mask: 0x01) */
#define IOM0_INTEN_ARB_Pos (9UL) /*!< ARB (Bit 9) */
#define IOM0_INTEN_ARB_Msk (0x200UL) /*!< ARB (Bitfield-Mask: 0x01) */
#define IOM0_INTEN_STOP_Pos (8UL) /*!< STOP (Bit 8) */
#define IOM0_INTEN_STOP_Msk (0x100UL) /*!< STOP (Bitfield-Mask: 0x01) */
#define IOM0_INTEN_START_Pos (7UL) /*!< START (Bit 7) */
#define IOM0_INTEN_START_Msk (0x80UL) /*!< START (Bitfield-Mask: 0x01) */
#define IOM0_INTEN_ICMD_Pos (6UL) /*!< ICMD (Bit 6) */
#define IOM0_INTEN_ICMD_Msk (0x40UL) /*!< ICMD (Bitfield-Mask: 0x01) */
#define IOM0_INTEN_IACC_Pos (5UL) /*!< IACC (Bit 5) */
#define IOM0_INTEN_IACC_Msk (0x20UL) /*!< IACC (Bitfield-Mask: 0x01) */
#define IOM0_INTEN_NAK_Pos (4UL) /*!< NAK (Bit 4) */
#define IOM0_INTEN_NAK_Msk (0x10UL) /*!< NAK (Bitfield-Mask: 0x01) */
#define IOM0_INTEN_FOVFL_Pos (3UL) /*!< FOVFL (Bit 3) */
#define IOM0_INTEN_FOVFL_Msk (0x8UL) /*!< FOVFL (Bitfield-Mask: 0x01) */
#define IOM0_INTEN_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */
#define IOM0_INTEN_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */
#define IOM0_INTEN_THR_Pos (1UL) /*!< THR (Bit 1) */
#define IOM0_INTEN_THR_Msk (0x2UL) /*!< THR (Bitfield-Mask: 0x01) */
#define IOM0_INTEN_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */
#define IOM0_INTEN_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */
/* ======================================================== INTSTAT ======================================================== */
#define IOM0_INTSTAT_CQERR_Pos (14UL) /*!< CQERR (Bit 14) */
#define IOM0_INTSTAT_CQERR_Msk (0x4000UL) /*!< CQERR (Bitfield-Mask: 0x01) */
#define IOM0_INTSTAT_CQUPD_Pos (13UL) /*!< CQUPD (Bit 13) */
#define IOM0_INTSTAT_CQUPD_Msk (0x2000UL) /*!< CQUPD (Bitfield-Mask: 0x01) */
#define IOM0_INTSTAT_CQPAUSED_Pos (12UL) /*!< CQPAUSED (Bit 12) */
#define IOM0_INTSTAT_CQPAUSED_Msk (0x1000UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */
#define IOM0_INTSTAT_DERR_Pos (11UL) /*!< DERR (Bit 11) */
#define IOM0_INTSTAT_DERR_Msk (0x800UL) /*!< DERR (Bitfield-Mask: 0x01) */
#define IOM0_INTSTAT_DCMP_Pos (10UL) /*!< DCMP (Bit 10) */
#define IOM0_INTSTAT_DCMP_Msk (0x400UL) /*!< DCMP (Bitfield-Mask: 0x01) */
#define IOM0_INTSTAT_ARB_Pos (9UL) /*!< ARB (Bit 9) */
#define IOM0_INTSTAT_ARB_Msk (0x200UL) /*!< ARB (Bitfield-Mask: 0x01) */
#define IOM0_INTSTAT_STOP_Pos (8UL) /*!< STOP (Bit 8) */
#define IOM0_INTSTAT_STOP_Msk (0x100UL) /*!< STOP (Bitfield-Mask: 0x01) */
#define IOM0_INTSTAT_START_Pos (7UL) /*!< START (Bit 7) */
#define IOM0_INTSTAT_START_Msk (0x80UL) /*!< START (Bitfield-Mask: 0x01) */
#define IOM0_INTSTAT_ICMD_Pos (6UL) /*!< ICMD (Bit 6) */
#define IOM0_INTSTAT_ICMD_Msk (0x40UL) /*!< ICMD (Bitfield-Mask: 0x01) */
#define IOM0_INTSTAT_IACC_Pos (5UL) /*!< IACC (Bit 5) */
#define IOM0_INTSTAT_IACC_Msk (0x20UL) /*!< IACC (Bitfield-Mask: 0x01) */
#define IOM0_INTSTAT_NAK_Pos (4UL) /*!< NAK (Bit 4) */
#define IOM0_INTSTAT_NAK_Msk (0x10UL) /*!< NAK (Bitfield-Mask: 0x01) */
#define IOM0_INTSTAT_FOVFL_Pos (3UL) /*!< FOVFL (Bit 3) */
#define IOM0_INTSTAT_FOVFL_Msk (0x8UL) /*!< FOVFL (Bitfield-Mask: 0x01) */
#define IOM0_INTSTAT_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */
#define IOM0_INTSTAT_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */
#define IOM0_INTSTAT_THR_Pos (1UL) /*!< THR (Bit 1) */
#define IOM0_INTSTAT_THR_Msk (0x2UL) /*!< THR (Bitfield-Mask: 0x01) */
#define IOM0_INTSTAT_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */
#define IOM0_INTSTAT_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */
/* ======================================================== INTCLR ========================================================= */
#define IOM0_INTCLR_CQERR_Pos (14UL) /*!< CQERR (Bit 14) */
#define IOM0_INTCLR_CQERR_Msk (0x4000UL) /*!< CQERR (Bitfield-Mask: 0x01) */
#define IOM0_INTCLR_CQUPD_Pos (13UL) /*!< CQUPD (Bit 13) */
#define IOM0_INTCLR_CQUPD_Msk (0x2000UL) /*!< CQUPD (Bitfield-Mask: 0x01) */
#define IOM0_INTCLR_CQPAUSED_Pos (12UL) /*!< CQPAUSED (Bit 12) */
#define IOM0_INTCLR_CQPAUSED_Msk (0x1000UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */
#define IOM0_INTCLR_DERR_Pos (11UL) /*!< DERR (Bit 11) */
#define IOM0_INTCLR_DERR_Msk (0x800UL) /*!< DERR (Bitfield-Mask: 0x01) */
#define IOM0_INTCLR_DCMP_Pos (10UL) /*!< DCMP (Bit 10) */
#define IOM0_INTCLR_DCMP_Msk (0x400UL) /*!< DCMP (Bitfield-Mask: 0x01) */
#define IOM0_INTCLR_ARB_Pos (9UL) /*!< ARB (Bit 9) */
#define IOM0_INTCLR_ARB_Msk (0x200UL) /*!< ARB (Bitfield-Mask: 0x01) */
#define IOM0_INTCLR_STOP_Pos (8UL) /*!< STOP (Bit 8) */
#define IOM0_INTCLR_STOP_Msk (0x100UL) /*!< STOP (Bitfield-Mask: 0x01) */
#define IOM0_INTCLR_START_Pos (7UL) /*!< START (Bit 7) */
#define IOM0_INTCLR_START_Msk (0x80UL) /*!< START (Bitfield-Mask: 0x01) */
#define IOM0_INTCLR_ICMD_Pos (6UL) /*!< ICMD (Bit 6) */
#define IOM0_INTCLR_ICMD_Msk (0x40UL) /*!< ICMD (Bitfield-Mask: 0x01) */
#define IOM0_INTCLR_IACC_Pos (5UL) /*!< IACC (Bit 5) */
#define IOM0_INTCLR_IACC_Msk (0x20UL) /*!< IACC (Bitfield-Mask: 0x01) */
#define IOM0_INTCLR_NAK_Pos (4UL) /*!< NAK (Bit 4) */
#define IOM0_INTCLR_NAK_Msk (0x10UL) /*!< NAK (Bitfield-Mask: 0x01) */
#define IOM0_INTCLR_FOVFL_Pos (3UL) /*!< FOVFL (Bit 3) */
#define IOM0_INTCLR_FOVFL_Msk (0x8UL) /*!< FOVFL (Bitfield-Mask: 0x01) */
#define IOM0_INTCLR_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */
#define IOM0_INTCLR_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */
#define IOM0_INTCLR_THR_Pos (1UL) /*!< THR (Bit 1) */
#define IOM0_INTCLR_THR_Msk (0x2UL) /*!< THR (Bitfield-Mask: 0x01) */
#define IOM0_INTCLR_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */
#define IOM0_INTCLR_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */
/* ======================================================== INTSET ========================================================= */
#define IOM0_INTSET_CQERR_Pos (14UL) /*!< CQERR (Bit 14) */
#define IOM0_INTSET_CQERR_Msk (0x4000UL) /*!< CQERR (Bitfield-Mask: 0x01) */
#define IOM0_INTSET_CQUPD_Pos (13UL) /*!< CQUPD (Bit 13) */
#define IOM0_INTSET_CQUPD_Msk (0x2000UL) /*!< CQUPD (Bitfield-Mask: 0x01) */
#define IOM0_INTSET_CQPAUSED_Pos (12UL) /*!< CQPAUSED (Bit 12) */
#define IOM0_INTSET_CQPAUSED_Msk (0x1000UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */
#define IOM0_INTSET_DERR_Pos (11UL) /*!< DERR (Bit 11) */
#define IOM0_INTSET_DERR_Msk (0x800UL) /*!< DERR (Bitfield-Mask: 0x01) */
#define IOM0_INTSET_DCMP_Pos (10UL) /*!< DCMP (Bit 10) */
#define IOM0_INTSET_DCMP_Msk (0x400UL) /*!< DCMP (Bitfield-Mask: 0x01) */
#define IOM0_INTSET_ARB_Pos (9UL) /*!< ARB (Bit 9) */
#define IOM0_INTSET_ARB_Msk (0x200UL) /*!< ARB (Bitfield-Mask: 0x01) */
#define IOM0_INTSET_STOP_Pos (8UL) /*!< STOP (Bit 8) */
#define IOM0_INTSET_STOP_Msk (0x100UL) /*!< STOP (Bitfield-Mask: 0x01) */
#define IOM0_INTSET_START_Pos (7UL) /*!< START (Bit 7) */
#define IOM0_INTSET_START_Msk (0x80UL) /*!< START (Bitfield-Mask: 0x01) */
#define IOM0_INTSET_ICMD_Pos (6UL) /*!< ICMD (Bit 6) */
#define IOM0_INTSET_ICMD_Msk (0x40UL) /*!< ICMD (Bitfield-Mask: 0x01) */
#define IOM0_INTSET_IACC_Pos (5UL) /*!< IACC (Bit 5) */
#define IOM0_INTSET_IACC_Msk (0x20UL) /*!< IACC (Bitfield-Mask: 0x01) */
#define IOM0_INTSET_NAK_Pos (4UL) /*!< NAK (Bit 4) */
#define IOM0_INTSET_NAK_Msk (0x10UL) /*!< NAK (Bitfield-Mask: 0x01) */
#define IOM0_INTSET_FOVFL_Pos (3UL) /*!< FOVFL (Bit 3) */
#define IOM0_INTSET_FOVFL_Msk (0x8UL) /*!< FOVFL (Bitfield-Mask: 0x01) */
#define IOM0_INTSET_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */
#define IOM0_INTSET_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */
#define IOM0_INTSET_THR_Pos (1UL) /*!< THR (Bit 1) */
#define IOM0_INTSET_THR_Msk (0x2UL) /*!< THR (Bitfield-Mask: 0x01) */
#define IOM0_INTSET_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */
#define IOM0_INTSET_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */
/* ======================================================== CLKCFG ========================================================= */
#define IOM0_CLKCFG_TOTPER_Pos (24UL) /*!< TOTPER (Bit 24) */
#define IOM0_CLKCFG_TOTPER_Msk (0xff000000UL) /*!< TOTPER (Bitfield-Mask: 0xff) */
#define IOM0_CLKCFG_LOWPER_Pos (16UL) /*!< LOWPER (Bit 16) */
#define IOM0_CLKCFG_LOWPER_Msk (0xff0000UL) /*!< LOWPER (Bitfield-Mask: 0xff) */
#define IOM0_CLKCFG_DIVEN_Pos (12UL) /*!< DIVEN (Bit 12) */
#define IOM0_CLKCFG_DIVEN_Msk (0x1000UL) /*!< DIVEN (Bitfield-Mask: 0x01) */
#define IOM0_CLKCFG_DIV3_Pos (11UL) /*!< DIV3 (Bit 11) */
#define IOM0_CLKCFG_DIV3_Msk (0x800UL) /*!< DIV3 (Bitfield-Mask: 0x01) */
#define IOM0_CLKCFG_FSEL_Pos (8UL) /*!< FSEL (Bit 8) */
#define IOM0_CLKCFG_FSEL_Msk (0x700UL) /*!< FSEL (Bitfield-Mask: 0x07) */
#define IOM0_CLKCFG_IOCLKEN_Pos (0UL) /*!< IOCLKEN (Bit 0) */
#define IOM0_CLKCFG_IOCLKEN_Msk (0x1UL) /*!< IOCLKEN (Bitfield-Mask: 0x01) */
/* ====================================================== SUBMODCTRL ======================================================= */
#define IOM0_SUBMODCTRL_SMOD1TYPE_Pos (5UL) /*!< SMOD1TYPE (Bit 5) */
#define IOM0_SUBMODCTRL_SMOD1TYPE_Msk (0xe0UL) /*!< SMOD1TYPE (Bitfield-Mask: 0x07) */
#define IOM0_SUBMODCTRL_SMOD1EN_Pos (4UL) /*!< SMOD1EN (Bit 4) */
#define IOM0_SUBMODCTRL_SMOD1EN_Msk (0x10UL) /*!< SMOD1EN (Bitfield-Mask: 0x01) */
#define IOM0_SUBMODCTRL_SMOD0TYPE_Pos (1UL) /*!< SMOD0TYPE (Bit 1) */
#define IOM0_SUBMODCTRL_SMOD0TYPE_Msk (0xeUL) /*!< SMOD0TYPE (Bitfield-Mask: 0x07) */
#define IOM0_SUBMODCTRL_SMOD0EN_Pos (0UL) /*!< SMOD0EN (Bit 0) */
#define IOM0_SUBMODCTRL_SMOD0EN_Msk (0x1UL) /*!< SMOD0EN (Bitfield-Mask: 0x01) */
/* ========================================================== CMD ========================================================== */
#define IOM0_CMD_OFFSETLO_Pos (24UL) /*!< OFFSETLO (Bit 24) */
#define IOM0_CMD_OFFSETLO_Msk (0xff000000UL) /*!< OFFSETLO (Bitfield-Mask: 0xff) */
#define IOM0_CMD_CMDSEL_Pos (20UL) /*!< CMDSEL (Bit 20) */
#define IOM0_CMD_CMDSEL_Msk (0x300000UL) /*!< CMDSEL (Bitfield-Mask: 0x03) */
#define IOM0_CMD_TSIZE_Pos (8UL) /*!< TSIZE (Bit 8) */
#define IOM0_CMD_TSIZE_Msk (0xfff00UL) /*!< TSIZE (Bitfield-Mask: 0xfff) */
#define IOM0_CMD_CONT_Pos (7UL) /*!< CONT (Bit 7) */
#define IOM0_CMD_CONT_Msk (0x80UL) /*!< CONT (Bitfield-Mask: 0x01) */
#define IOM0_CMD_OFFSETCNT_Pos (5UL) /*!< OFFSETCNT (Bit 5) */
#define IOM0_CMD_OFFSETCNT_Msk (0x60UL) /*!< OFFSETCNT (Bitfield-Mask: 0x03) */
#define IOM0_CMD_CMD_Pos (0UL) /*!< CMD (Bit 0) */
#define IOM0_CMD_CMD_Msk (0x1fUL) /*!< CMD (Bitfield-Mask: 0x1f) */
/* ========================================================== DCX ========================================================== */
#define IOM0_DCX_DCXEN_Pos (4UL) /*!< DCXEN (Bit 4) */
#define IOM0_DCX_DCXEN_Msk (0x10UL) /*!< DCXEN (Bitfield-Mask: 0x01) */
#define IOM0_DCX_CE3OUT_Pos (3UL) /*!< CE3OUT (Bit 3) */
#define IOM0_DCX_CE3OUT_Msk (0x8UL) /*!< CE3OUT (Bitfield-Mask: 0x01) */
#define IOM0_DCX_CE2OUT_Pos (2UL) /*!< CE2OUT (Bit 2) */
#define IOM0_DCX_CE2OUT_Msk (0x4UL) /*!< CE2OUT (Bitfield-Mask: 0x01) */
#define IOM0_DCX_CE1OUT_Pos (1UL) /*!< CE1OUT (Bit 1) */
#define IOM0_DCX_CE1OUT_Msk (0x2UL) /*!< CE1OUT (Bitfield-Mask: 0x01) */
#define IOM0_DCX_CE0OUT_Pos (0UL) /*!< CE0OUT (Bit 0) */
#define IOM0_DCX_CE0OUT_Msk (0x1UL) /*!< CE0OUT (Bitfield-Mask: 0x01) */
/* ======================================================= OFFSETHI ======================================================== */
#define IOM0_OFFSETHI_OFFSETHI_Pos (0UL) /*!< OFFSETHI (Bit 0) */
#define IOM0_OFFSETHI_OFFSETHI_Msk (0xffffUL) /*!< OFFSETHI (Bitfield-Mask: 0xffff) */
/* ======================================================== CMDSTAT ======================================================== */
#define IOM0_CMDSTAT_CTSIZE_Pos (8UL) /*!< CTSIZE (Bit 8) */
#define IOM0_CMDSTAT_CTSIZE_Msk (0xfff00UL) /*!< CTSIZE (Bitfield-Mask: 0xfff) */
#define IOM0_CMDSTAT_CMDSTAT_Pos (5UL) /*!< CMDSTAT (Bit 5) */
#define IOM0_CMDSTAT_CMDSTAT_Msk (0xe0UL) /*!< CMDSTAT (Bitfield-Mask: 0x07) */
#define IOM0_CMDSTAT_CCMD_Pos (0UL) /*!< CCMD (Bit 0) */
#define IOM0_CMDSTAT_CCMD_Msk (0x1fUL) /*!< CCMD (Bitfield-Mask: 0x1f) */
/* ======================================================= DMATRIGEN ======================================================= */
#define IOM0_DMATRIGEN_DTHREN_Pos (1UL) /*!< DTHREN (Bit 1) */
#define IOM0_DMATRIGEN_DTHREN_Msk (0x2UL) /*!< DTHREN (Bitfield-Mask: 0x01) */
#define IOM0_DMATRIGEN_DCMDCMPEN_Pos (0UL) /*!< DCMDCMPEN (Bit 0) */
#define IOM0_DMATRIGEN_DCMDCMPEN_Msk (0x1UL) /*!< DCMDCMPEN (Bitfield-Mask: 0x01) */
/* ====================================================== DMATRIGSTAT ====================================================== */
#define IOM0_DMATRIGSTAT_DTOTCMP_Pos (2UL) /*!< DTOTCMP (Bit 2) */
#define IOM0_DMATRIGSTAT_DTOTCMP_Msk (0x4UL) /*!< DTOTCMP (Bitfield-Mask: 0x01) */
#define IOM0_DMATRIGSTAT_DTHR_Pos (1UL) /*!< DTHR (Bit 1) */
#define IOM0_DMATRIGSTAT_DTHR_Msk (0x2UL) /*!< DTHR (Bitfield-Mask: 0x01) */
#define IOM0_DMATRIGSTAT_DCMDCMP_Pos (0UL) /*!< DCMDCMP (Bit 0) */
#define IOM0_DMATRIGSTAT_DCMDCMP_Msk (0x1UL) /*!< DCMDCMP (Bitfield-Mask: 0x01) */
/* ======================================================== DMACFG ========================================================= */
#define IOM0_DMACFG_DPWROFF_Pos (9UL) /*!< DPWROFF (Bit 9) */
#define IOM0_DMACFG_DPWROFF_Msk (0x200UL) /*!< DPWROFF (Bitfield-Mask: 0x01) */
#define IOM0_DMACFG_DMAPRI_Pos (8UL) /*!< DMAPRI (Bit 8) */
#define IOM0_DMACFG_DMAPRI_Msk (0x100UL) /*!< DMAPRI (Bitfield-Mask: 0x01) */
#define IOM0_DMACFG_DMADIR_Pos (1UL) /*!< DMADIR (Bit 1) */
#define IOM0_DMACFG_DMADIR_Msk (0x2UL) /*!< DMADIR (Bitfield-Mask: 0x01) */
#define IOM0_DMACFG_DMAEN_Pos (0UL) /*!< DMAEN (Bit 0) */
#define IOM0_DMACFG_DMAEN_Msk (0x1UL) /*!< DMAEN (Bitfield-Mask: 0x01) */
/* ====================================================== DMATOTCOUNT ====================================================== */
#define IOM0_DMATOTCOUNT_TOTCOUNT_Pos (0UL) /*!< TOTCOUNT (Bit 0) */
#define IOM0_DMATOTCOUNT_TOTCOUNT_Msk (0xfffUL) /*!< TOTCOUNT (Bitfield-Mask: 0xfff) */
/* ====================================================== DMATARGADDR ====================================================== */
#define IOM0_DMATARGADDR_TARGADDR28_Pos (28UL) /*!< TARGADDR28 (Bit 28) */
#define IOM0_DMATARGADDR_TARGADDR28_Msk (0x10000000UL) /*!< TARGADDR28 (Bitfield-Mask: 0x01) */
#define IOM0_DMATARGADDR_TARGADDR_Pos (0UL) /*!< TARGADDR (Bit 0) */
#define IOM0_DMATARGADDR_TARGADDR_Msk (0xfffffUL) /*!< TARGADDR (Bitfield-Mask: 0xfffff) */
/* ======================================================== DMASTAT ======================================================== */
#define IOM0_DMASTAT_DMAERR_Pos (2UL) /*!< DMAERR (Bit 2) */
#define IOM0_DMASTAT_DMAERR_Msk (0x4UL) /*!< DMAERR (Bitfield-Mask: 0x01) */
#define IOM0_DMASTAT_DMACPL_Pos (1UL) /*!< DMACPL (Bit 1) */
#define IOM0_DMASTAT_DMACPL_Msk (0x2UL) /*!< DMACPL (Bitfield-Mask: 0x01) */
#define IOM0_DMASTAT_DMATIP_Pos (0UL) /*!< DMATIP (Bit 0) */
#define IOM0_DMASTAT_DMATIP_Msk (0x1UL) /*!< DMATIP (Bitfield-Mask: 0x01) */
/* ========================================================= CQCFG ========================================================= */
#define IOM0_CQCFG_CQPRI_Pos (1UL) /*!< CQPRI (Bit 1) */
#define IOM0_CQCFG_CQPRI_Msk (0x2UL) /*!< CQPRI (Bitfield-Mask: 0x01) */
#define IOM0_CQCFG_CQEN_Pos (0UL) /*!< CQEN (Bit 0) */
#define IOM0_CQCFG_CQEN_Msk (0x1UL) /*!< CQEN (Bitfield-Mask: 0x01) */
/* ======================================================== CQADDR ========================================================= */
#define IOM0_CQADDR_CQADDR28_Pos (28UL) /*!< CQADDR28 (Bit 28) */
#define IOM0_CQADDR_CQADDR28_Msk (0x10000000UL) /*!< CQADDR28 (Bitfield-Mask: 0x01) */
#define IOM0_CQADDR_CQADDR_Pos (2UL) /*!< CQADDR (Bit 2) */
#define IOM0_CQADDR_CQADDR_Msk (0xffffcUL) /*!< CQADDR (Bitfield-Mask: 0x3ffff) */
/* ======================================================== CQSTAT ========================================================= */
#define IOM0_CQSTAT_CQERR_Pos (2UL) /*!< CQERR (Bit 2) */
#define IOM0_CQSTAT_CQERR_Msk (0x4UL) /*!< CQERR (Bitfield-Mask: 0x01) */
#define IOM0_CQSTAT_CQPAUSED_Pos (1UL) /*!< CQPAUSED (Bit 1) */
#define IOM0_CQSTAT_CQPAUSED_Msk (0x2UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */
#define IOM0_CQSTAT_CQTIP_Pos (0UL) /*!< CQTIP (Bit 0) */
#define IOM0_CQSTAT_CQTIP_Msk (0x1UL) /*!< CQTIP (Bitfield-Mask: 0x01) */
/* ======================================================== CQFLAGS ======================================================== */
#define IOM0_CQFLAGS_CQIRQMASK_Pos (16UL) /*!< CQIRQMASK (Bit 16) */
#define IOM0_CQFLAGS_CQIRQMASK_Msk (0xffff0000UL) /*!< CQIRQMASK (Bitfield-Mask: 0xffff) */
#define IOM0_CQFLAGS_CQFLAGS_Pos (0UL) /*!< CQFLAGS (Bit 0) */
#define IOM0_CQFLAGS_CQFLAGS_Msk (0xffffUL) /*!< CQFLAGS (Bitfield-Mask: 0xffff) */
/* ====================================================== CQSETCLEAR ======================================================= */
#define IOM0_CQSETCLEAR_CQFCLR_Pos (16UL) /*!< CQFCLR (Bit 16) */
#define IOM0_CQSETCLEAR_CQFCLR_Msk (0xff0000UL) /*!< CQFCLR (Bitfield-Mask: 0xff) */
#define IOM0_CQSETCLEAR_CQFTGL_Pos (8UL) /*!< CQFTGL (Bit 8) */
#define IOM0_CQSETCLEAR_CQFTGL_Msk (0xff00UL) /*!< CQFTGL (Bitfield-Mask: 0xff) */
#define IOM0_CQSETCLEAR_CQFSET_Pos (0UL) /*!< CQFSET (Bit 0) */
#define IOM0_CQSETCLEAR_CQFSET_Msk (0xffUL) /*!< CQFSET (Bitfield-Mask: 0xff) */
/* ======================================================= CQPAUSEEN ======================================================= */
#define IOM0_CQPAUSEEN_CQPEN_Pos (0UL) /*!< CQPEN (Bit 0) */
#define IOM0_CQPAUSEEN_CQPEN_Msk (0xffffUL) /*!< CQPEN (Bitfield-Mask: 0xffff) */
/* ======================================================= CQCURIDX ======================================================== */
#define IOM0_CQCURIDX_CQCURIDX_Pos (0UL) /*!< CQCURIDX (Bit 0) */
#define IOM0_CQCURIDX_CQCURIDX_Msk (0xffUL) /*!< CQCURIDX (Bitfield-Mask: 0xff) */
/* ======================================================= CQENDIDX ======================================================== */
#define IOM0_CQENDIDX_CQENDIDX_Pos (0UL) /*!< CQENDIDX (Bit 0) */
#define IOM0_CQENDIDX_CQENDIDX_Msk (0xffUL) /*!< CQENDIDX (Bitfield-Mask: 0xff) */
/* ======================================================== STATUS ========================================================= */
#define IOM0_STATUS_IDLEST_Pos (2UL) /*!< IDLEST (Bit 2) */
#define IOM0_STATUS_IDLEST_Msk (0x4UL) /*!< IDLEST (Bitfield-Mask: 0x01) */
#define IOM0_STATUS_CMDACT_Pos (1UL) /*!< CMDACT (Bit 1) */
#define IOM0_STATUS_CMDACT_Msk (0x2UL) /*!< CMDACT (Bitfield-Mask: 0x01) */
#define IOM0_STATUS_ERR_Pos (0UL) /*!< ERR (Bit 0) */
#define IOM0_STATUS_ERR_Msk (0x1UL) /*!< ERR (Bitfield-Mask: 0x01) */
/* ======================================================== MSPICFG ======================================================== */
#define IOM0_MSPICFG_MSPIRST_Pos (30UL) /*!< MSPIRST (Bit 30) */
#define IOM0_MSPICFG_MSPIRST_Msk (0x40000000UL) /*!< MSPIRST (Bitfield-Mask: 0x01) */
#define IOM0_MSPICFG_DOUTDLY_Pos (27UL) /*!< DOUTDLY (Bit 27) */
#define IOM0_MSPICFG_DOUTDLY_Msk (0x38000000UL) /*!< DOUTDLY (Bitfield-Mask: 0x07) */
#define IOM0_MSPICFG_DINDLY_Pos (24UL) /*!< DINDLY (Bit 24) */
#define IOM0_MSPICFG_DINDLY_Msk (0x7000000UL) /*!< DINDLY (Bitfield-Mask: 0x07) */
#define IOM0_MSPICFG_SPILSB_Pos (23UL) /*!< SPILSB (Bit 23) */
#define IOM0_MSPICFG_SPILSB_Msk (0x800000UL) /*!< SPILSB (Bitfield-Mask: 0x01) */
#define IOM0_MSPICFG_RDFCPOL_Pos (22UL) /*!< RDFCPOL (Bit 22) */
#define IOM0_MSPICFG_RDFCPOL_Msk (0x400000UL) /*!< RDFCPOL (Bitfield-Mask: 0x01) */
#define IOM0_MSPICFG_WTFCPOL_Pos (21UL) /*!< WTFCPOL (Bit 21) */
#define IOM0_MSPICFG_WTFCPOL_Msk (0x200000UL) /*!< WTFCPOL (Bitfield-Mask: 0x01) */
#define IOM0_MSPICFG_WTFCIRQ_Pos (20UL) /*!< WTFCIRQ (Bit 20) */
#define IOM0_MSPICFG_WTFCIRQ_Msk (0x100000UL) /*!< WTFCIRQ (Bitfield-Mask: 0x01) */
#define IOM0_MSPICFG_MOSIINV_Pos (18UL) /*!< MOSIINV (Bit 18) */
#define IOM0_MSPICFG_MOSIINV_Msk (0x40000UL) /*!< MOSIINV (Bitfield-Mask: 0x01) */
#define IOM0_MSPICFG_RDFC_Pos (17UL) /*!< RDFC (Bit 17) */
#define IOM0_MSPICFG_RDFC_Msk (0x20000UL) /*!< RDFC (Bitfield-Mask: 0x01) */
#define IOM0_MSPICFG_WTFC_Pos (16UL) /*!< WTFC (Bit 16) */
#define IOM0_MSPICFG_WTFC_Msk (0x10000UL) /*!< WTFC (Bitfield-Mask: 0x01) */
#define IOM0_MSPICFG_FULLDUP_Pos (2UL) /*!< FULLDUP (Bit 2) */
#define IOM0_MSPICFG_FULLDUP_Msk (0x4UL) /*!< FULLDUP (Bitfield-Mask: 0x01) */
#define IOM0_MSPICFG_SPHA_Pos (1UL) /*!< SPHA (Bit 1) */
#define IOM0_MSPICFG_SPHA_Msk (0x2UL) /*!< SPHA (Bitfield-Mask: 0x01) */
#define IOM0_MSPICFG_SPOL_Pos (0UL) /*!< SPOL (Bit 0) */
#define IOM0_MSPICFG_SPOL_Msk (0x1UL) /*!< SPOL (Bitfield-Mask: 0x01) */
/* ======================================================== MI2CCFG ======================================================== */
#define IOM0_MI2CCFG_STRDIS_Pos (24UL) /*!< STRDIS (Bit 24) */
#define IOM0_MI2CCFG_STRDIS_Msk (0x1000000UL) /*!< STRDIS (Bitfield-Mask: 0x01) */
#define IOM0_MI2CCFG_SMPCNT_Pos (16UL) /*!< SMPCNT (Bit 16) */
#define IOM0_MI2CCFG_SMPCNT_Msk (0xff0000UL) /*!< SMPCNT (Bitfield-Mask: 0xff) */
#define IOM0_MI2CCFG_SDAENDLY_Pos (12UL) /*!< SDAENDLY (Bit 12) */
#define IOM0_MI2CCFG_SDAENDLY_Msk (0xf000UL) /*!< SDAENDLY (Bitfield-Mask: 0x0f) */
#define IOM0_MI2CCFG_SCLENDLY_Pos (8UL) /*!< SCLENDLY (Bit 8) */
#define IOM0_MI2CCFG_SCLENDLY_Msk (0xf00UL) /*!< SCLENDLY (Bitfield-Mask: 0x0f) */
#define IOM0_MI2CCFG_MI2CRST_Pos (6UL) /*!< MI2CRST (Bit 6) */
#define IOM0_MI2CCFG_MI2CRST_Msk (0x40UL) /*!< MI2CRST (Bitfield-Mask: 0x01) */
#define IOM0_MI2CCFG_SDADLY_Pos (4UL) /*!< SDADLY (Bit 4) */
#define IOM0_MI2CCFG_SDADLY_Msk (0x30UL) /*!< SDADLY (Bitfield-Mask: 0x03) */
#define IOM0_MI2CCFG_ARBEN_Pos (2UL) /*!< ARBEN (Bit 2) */
#define IOM0_MI2CCFG_ARBEN_Msk (0x4UL) /*!< ARBEN (Bitfield-Mask: 0x01) */
#define IOM0_MI2CCFG_I2CLSB_Pos (1UL) /*!< I2CLSB (Bit 1) */
#define IOM0_MI2CCFG_I2CLSB_Msk (0x2UL) /*!< I2CLSB (Bitfield-Mask: 0x01) */
#define IOM0_MI2CCFG_ADDRSZ_Pos (0UL) /*!< ADDRSZ (Bit 0) */
#define IOM0_MI2CCFG_ADDRSZ_Msk (0x1UL) /*!< ADDRSZ (Bitfield-Mask: 0x01) */
/* ======================================================== DEVCFG ========================================================= */
#define IOM0_DEVCFG_DEVADDR_Pos (0UL) /*!< DEVADDR (Bit 0) */
#define IOM0_DEVCFG_DEVADDR_Msk (0x3ffUL) /*!< DEVADDR (Bitfield-Mask: 0x3ff) */
/* ======================================================== IOMDBG ========================================================= */
#define IOM0_IOMDBG_DBGDATA_Pos (3UL) /*!< DBGDATA (Bit 3) */
#define IOM0_IOMDBG_DBGDATA_Msk (0xfffffff8UL) /*!< DBGDATA (Bitfield-Mask: 0x1fffffff) */
#define IOM0_IOMDBG_APBCLKON_Pos (2UL) /*!< APBCLKON (Bit 2) */
#define IOM0_IOMDBG_APBCLKON_Msk (0x4UL) /*!< APBCLKON (Bitfield-Mask: 0x01) */
#define IOM0_IOMDBG_IOCLKON_Pos (1UL) /*!< IOCLKON (Bit 1) */
#define IOM0_IOMDBG_IOCLKON_Msk (0x2UL) /*!< IOCLKON (Bitfield-Mask: 0x01) */
#define IOM0_IOMDBG_DBGEN_Pos (0UL) /*!< DBGEN (Bit 0) */
#define IOM0_IOMDBG_DBGEN_Msk (0x1UL) /*!< DBGEN (Bitfield-Mask: 0x01) */
/* =========================================================================================================================== */
/* ================ IOSLAVE ================ */
/* =========================================================================================================================== */
/* ======================================================== FIFOPTR ======================================================== */
#define IOSLAVE_FIFOPTR_FIFOSIZ_Pos (8UL) /*!< FIFOSIZ (Bit 8) */
#define IOSLAVE_FIFOPTR_FIFOSIZ_Msk (0xff00UL) /*!< FIFOSIZ (Bitfield-Mask: 0xff) */
#define IOSLAVE_FIFOPTR_FIFOPTR_Pos (0UL) /*!< FIFOPTR (Bit 0) */
#define IOSLAVE_FIFOPTR_FIFOPTR_Msk (0xffUL) /*!< FIFOPTR (Bitfield-Mask: 0xff) */
/* ======================================================== FIFOCFG ======================================================== */
#define IOSLAVE_FIFOCFG_ROBASE_Pos (24UL) /*!< ROBASE (Bit 24) */
#define IOSLAVE_FIFOCFG_ROBASE_Msk (0x3f000000UL) /*!< ROBASE (Bitfield-Mask: 0x3f) */
#define IOSLAVE_FIFOCFG_FIFOMAX_Pos (8UL) /*!< FIFOMAX (Bit 8) */
#define IOSLAVE_FIFOCFG_FIFOMAX_Msk (0x3f00UL) /*!< FIFOMAX (Bitfield-Mask: 0x3f) */
#define IOSLAVE_FIFOCFG_FIFOBASE_Pos (0UL) /*!< FIFOBASE (Bit 0) */
#define IOSLAVE_FIFOCFG_FIFOBASE_Msk (0x1fUL) /*!< FIFOBASE (Bitfield-Mask: 0x1f) */
/* ======================================================== FIFOTHR ======================================================== */
#define IOSLAVE_FIFOTHR_FIFOTHR_Pos (0UL) /*!< FIFOTHR (Bit 0) */
#define IOSLAVE_FIFOTHR_FIFOTHR_Msk (0xffUL) /*!< FIFOTHR (Bitfield-Mask: 0xff) */
/* ========================================================= FUPD ========================================================== */
#define IOSLAVE_FUPD_IOREAD_Pos (1UL) /*!< IOREAD (Bit 1) */
#define IOSLAVE_FUPD_IOREAD_Msk (0x2UL) /*!< IOREAD (Bitfield-Mask: 0x01) */
#define IOSLAVE_FUPD_FIFOUPD_Pos (0UL) /*!< FIFOUPD (Bit 0) */
#define IOSLAVE_FUPD_FIFOUPD_Msk (0x1UL) /*!< FIFOUPD (Bitfield-Mask: 0x01) */
/* ======================================================== FIFOCTR ======================================================== */
#define IOSLAVE_FIFOCTR_FIFOCTR_Pos (0UL) /*!< FIFOCTR (Bit 0) */
#define IOSLAVE_FIFOCTR_FIFOCTR_Msk (0x3ffUL) /*!< FIFOCTR (Bitfield-Mask: 0x3ff) */
/* ======================================================== FIFOINC ======================================================== */
#define IOSLAVE_FIFOINC_FIFOINC_Pos (0UL) /*!< FIFOINC (Bit 0) */
#define IOSLAVE_FIFOINC_FIFOINC_Msk (0x3ffUL) /*!< FIFOINC (Bitfield-Mask: 0x3ff) */
/* ========================================================== CFG ========================================================== */
#define IOSLAVE_CFG_IFCEN_Pos (31UL) /*!< IFCEN (Bit 31) */
#define IOSLAVE_CFG_IFCEN_Msk (0x80000000UL) /*!< IFCEN (Bitfield-Mask: 0x01) */
#define IOSLAVE_CFG_I2CADDR_Pos (8UL) /*!< I2CADDR (Bit 8) */
#define IOSLAVE_CFG_I2CADDR_Msk (0xfff00UL) /*!< I2CADDR (Bitfield-Mask: 0xfff) */
#define IOSLAVE_CFG_STARTRD_Pos (4UL) /*!< STARTRD (Bit 4) */
#define IOSLAVE_CFG_STARTRD_Msk (0x10UL) /*!< STARTRD (Bitfield-Mask: 0x01) */
#define IOSLAVE_CFG_LSB_Pos (2UL) /*!< LSB (Bit 2) */
#define IOSLAVE_CFG_LSB_Msk (0x4UL) /*!< LSB (Bitfield-Mask: 0x01) */
#define IOSLAVE_CFG_SPOL_Pos (1UL) /*!< SPOL (Bit 1) */
#define IOSLAVE_CFG_SPOL_Msk (0x2UL) /*!< SPOL (Bitfield-Mask: 0x01) */
#define IOSLAVE_CFG_IFCSEL_Pos (0UL) /*!< IFCSEL (Bit 0) */
#define IOSLAVE_CFG_IFCSEL_Msk (0x1UL) /*!< IFCSEL (Bitfield-Mask: 0x01) */
/* ========================================================= PRENC ========================================================= */
#define IOSLAVE_PRENC_PRENC_Pos (0UL) /*!< PRENC (Bit 0) */
#define IOSLAVE_PRENC_PRENC_Msk (0x1fUL) /*!< PRENC (Bitfield-Mask: 0x1f) */
/* ======================================================= IOINTCTL ======================================================== */
#define IOSLAVE_IOINTCTL_IOINTSET_Pos (24UL) /*!< IOINTSET (Bit 24) */
#define IOSLAVE_IOINTCTL_IOINTSET_Msk (0xff000000UL) /*!< IOINTSET (Bitfield-Mask: 0xff) */
#define IOSLAVE_IOINTCTL_IOINTCLR_Pos (16UL) /*!< IOINTCLR (Bit 16) */
#define IOSLAVE_IOINTCTL_IOINTCLR_Msk (0x10000UL) /*!< IOINTCLR (Bitfield-Mask: 0x01) */
#define IOSLAVE_IOINTCTL_IOINT_Pos (8UL) /*!< IOINT (Bit 8) */
#define IOSLAVE_IOINTCTL_IOINT_Msk (0xff00UL) /*!< IOINT (Bitfield-Mask: 0xff) */
#define IOSLAVE_IOINTCTL_IOINTEN_Pos (0UL) /*!< IOINTEN (Bit 0) */
#define IOSLAVE_IOINTCTL_IOINTEN_Msk (0xffUL) /*!< IOINTEN (Bitfield-Mask: 0xff) */
/* ======================================================== GENADD ========================================================= */
#define IOSLAVE_GENADD_GADATA_Pos (0UL) /*!< GADATA (Bit 0) */
#define IOSLAVE_GENADD_GADATA_Msk (0xffUL) /*!< GADATA (Bitfield-Mask: 0xff) */
/* ========================================================= INTEN ========================================================= */
#define IOSLAVE_INTEN_XCMPWR_Pos (9UL) /*!< XCMPWR (Bit 9) */
#define IOSLAVE_INTEN_XCMPWR_Msk (0x200UL) /*!< XCMPWR (Bitfield-Mask: 0x01) */
#define IOSLAVE_INTEN_XCMPWF_Pos (8UL) /*!< XCMPWF (Bit 8) */
#define IOSLAVE_INTEN_XCMPWF_Msk (0x100UL) /*!< XCMPWF (Bitfield-Mask: 0x01) */
#define IOSLAVE_INTEN_XCMPRR_Pos (7UL) /*!< XCMPRR (Bit 7) */
#define IOSLAVE_INTEN_XCMPRR_Msk (0x80UL) /*!< XCMPRR (Bitfield-Mask: 0x01) */
#define IOSLAVE_INTEN_XCMPRF_Pos (6UL) /*!< XCMPRF (Bit 6) */
#define IOSLAVE_INTEN_XCMPRF_Msk (0x40UL) /*!< XCMPRF (Bitfield-Mask: 0x01) */
#define IOSLAVE_INTEN_IOINTW_Pos (5UL) /*!< IOINTW (Bit 5) */
#define IOSLAVE_INTEN_IOINTW_Msk (0x20UL) /*!< IOINTW (Bitfield-Mask: 0x01) */
#define IOSLAVE_INTEN_GENAD_Pos (4UL) /*!< GENAD (Bit 4) */
#define IOSLAVE_INTEN_GENAD_Msk (0x10UL) /*!< GENAD (Bitfield-Mask: 0x01) */
#define IOSLAVE_INTEN_FRDERR_Pos (3UL) /*!< FRDERR (Bit 3) */
#define IOSLAVE_INTEN_FRDERR_Msk (0x8UL) /*!< FRDERR (Bitfield-Mask: 0x01) */
#define IOSLAVE_INTEN_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */
#define IOSLAVE_INTEN_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */
#define IOSLAVE_INTEN_FOVFL_Pos (1UL) /*!< FOVFL (Bit 1) */
#define IOSLAVE_INTEN_FOVFL_Msk (0x2UL) /*!< FOVFL (Bitfield-Mask: 0x01) */
#define IOSLAVE_INTEN_FSIZE_Pos (0UL) /*!< FSIZE (Bit 0) */
#define IOSLAVE_INTEN_FSIZE_Msk (0x1UL) /*!< FSIZE (Bitfield-Mask: 0x01) */
/* ======================================================== INTSTAT ======================================================== */
#define IOSLAVE_INTSTAT_XCMPWR_Pos (9UL) /*!< XCMPWR (Bit 9) */
#define IOSLAVE_INTSTAT_XCMPWR_Msk (0x200UL) /*!< XCMPWR (Bitfield-Mask: 0x01) */
#define IOSLAVE_INTSTAT_XCMPWF_Pos (8UL) /*!< XCMPWF (Bit 8) */
#define IOSLAVE_INTSTAT_XCMPWF_Msk (0x100UL) /*!< XCMPWF (Bitfield-Mask: 0x01) */
#define IOSLAVE_INTSTAT_XCMPRR_Pos (7UL) /*!< XCMPRR (Bit 7) */
#define IOSLAVE_INTSTAT_XCMPRR_Msk (0x80UL) /*!< XCMPRR (Bitfield-Mask: 0x01) */
#define IOSLAVE_INTSTAT_XCMPRF_Pos (6UL) /*!< XCMPRF (Bit 6) */
#define IOSLAVE_INTSTAT_XCMPRF_Msk (0x40UL) /*!< XCMPRF (Bitfield-Mask: 0x01) */
#define IOSLAVE_INTSTAT_IOINTW_Pos (5UL) /*!< IOINTW (Bit 5) */
#define IOSLAVE_INTSTAT_IOINTW_Msk (0x20UL) /*!< IOINTW (Bitfield-Mask: 0x01) */
#define IOSLAVE_INTSTAT_GENAD_Pos (4UL) /*!< GENAD (Bit 4) */
#define IOSLAVE_INTSTAT_GENAD_Msk (0x10UL) /*!< GENAD (Bitfield-Mask: 0x01) */
#define IOSLAVE_INTSTAT_FRDERR_Pos (3UL) /*!< FRDERR (Bit 3) */
#define IOSLAVE_INTSTAT_FRDERR_Msk (0x8UL) /*!< FRDERR (Bitfield-Mask: 0x01) */
#define IOSLAVE_INTSTAT_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */
#define IOSLAVE_INTSTAT_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */
#define IOSLAVE_INTSTAT_FOVFL_Pos (1UL) /*!< FOVFL (Bit 1) */
#define IOSLAVE_INTSTAT_FOVFL_Msk (0x2UL) /*!< FOVFL (Bitfield-Mask: 0x01) */
#define IOSLAVE_INTSTAT_FSIZE_Pos (0UL) /*!< FSIZE (Bit 0) */
#define IOSLAVE_INTSTAT_FSIZE_Msk (0x1UL) /*!< FSIZE (Bitfield-Mask: 0x01) */
/* ======================================================== INTCLR ========================================================= */
#define IOSLAVE_INTCLR_XCMPWR_Pos (9UL) /*!< XCMPWR (Bit 9) */
#define IOSLAVE_INTCLR_XCMPWR_Msk (0x200UL) /*!< XCMPWR (Bitfield-Mask: 0x01) */
#define IOSLAVE_INTCLR_XCMPWF_Pos (8UL) /*!< XCMPWF (Bit 8) */
#define IOSLAVE_INTCLR_XCMPWF_Msk (0x100UL) /*!< XCMPWF (Bitfield-Mask: 0x01) */
#define IOSLAVE_INTCLR_XCMPRR_Pos (7UL) /*!< XCMPRR (Bit 7) */
#define IOSLAVE_INTCLR_XCMPRR_Msk (0x80UL) /*!< XCMPRR (Bitfield-Mask: 0x01) */
#define IOSLAVE_INTCLR_XCMPRF_Pos (6UL) /*!< XCMPRF (Bit 6) */
#define IOSLAVE_INTCLR_XCMPRF_Msk (0x40UL) /*!< XCMPRF (Bitfield-Mask: 0x01) */
#define IOSLAVE_INTCLR_IOINTW_Pos (5UL) /*!< IOINTW (Bit 5) */
#define IOSLAVE_INTCLR_IOINTW_Msk (0x20UL) /*!< IOINTW (Bitfield-Mask: 0x01) */
#define IOSLAVE_INTCLR_GENAD_Pos (4UL) /*!< GENAD (Bit 4) */
#define IOSLAVE_INTCLR_GENAD_Msk (0x10UL) /*!< GENAD (Bitfield-Mask: 0x01) */
#define IOSLAVE_INTCLR_FRDERR_Pos (3UL) /*!< FRDERR (Bit 3) */
#define IOSLAVE_INTCLR_FRDERR_Msk (0x8UL) /*!< FRDERR (Bitfield-Mask: 0x01) */
#define IOSLAVE_INTCLR_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */
#define IOSLAVE_INTCLR_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */
#define IOSLAVE_INTCLR_FOVFL_Pos (1UL) /*!< FOVFL (Bit 1) */
#define IOSLAVE_INTCLR_FOVFL_Msk (0x2UL) /*!< FOVFL (Bitfield-Mask: 0x01) */
#define IOSLAVE_INTCLR_FSIZE_Pos (0UL) /*!< FSIZE (Bit 0) */
#define IOSLAVE_INTCLR_FSIZE_Msk (0x1UL) /*!< FSIZE (Bitfield-Mask: 0x01) */
/* ======================================================== INTSET ========================================================= */
#define IOSLAVE_INTSET_XCMPWR_Pos (9UL) /*!< XCMPWR (Bit 9) */
#define IOSLAVE_INTSET_XCMPWR_Msk (0x200UL) /*!< XCMPWR (Bitfield-Mask: 0x01) */
#define IOSLAVE_INTSET_XCMPWF_Pos (8UL) /*!< XCMPWF (Bit 8) */
#define IOSLAVE_INTSET_XCMPWF_Msk (0x100UL) /*!< XCMPWF (Bitfield-Mask: 0x01) */
#define IOSLAVE_INTSET_XCMPRR_Pos (7UL) /*!< XCMPRR (Bit 7) */
#define IOSLAVE_INTSET_XCMPRR_Msk (0x80UL) /*!< XCMPRR (Bitfield-Mask: 0x01) */
#define IOSLAVE_INTSET_XCMPRF_Pos (6UL) /*!< XCMPRF (Bit 6) */
#define IOSLAVE_INTSET_XCMPRF_Msk (0x40UL) /*!< XCMPRF (Bitfield-Mask: 0x01) */
#define IOSLAVE_INTSET_IOINTW_Pos (5UL) /*!< IOINTW (Bit 5) */
#define IOSLAVE_INTSET_IOINTW_Msk (0x20UL) /*!< IOINTW (Bitfield-Mask: 0x01) */
#define IOSLAVE_INTSET_GENAD_Pos (4UL) /*!< GENAD (Bit 4) */
#define IOSLAVE_INTSET_GENAD_Msk (0x10UL) /*!< GENAD (Bitfield-Mask: 0x01) */
#define IOSLAVE_INTSET_FRDERR_Pos (3UL) /*!< FRDERR (Bit 3) */
#define IOSLAVE_INTSET_FRDERR_Msk (0x8UL) /*!< FRDERR (Bitfield-Mask: 0x01) */
#define IOSLAVE_INTSET_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */
#define IOSLAVE_INTSET_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */
#define IOSLAVE_INTSET_FOVFL_Pos (1UL) /*!< FOVFL (Bit 1) */
#define IOSLAVE_INTSET_FOVFL_Msk (0x2UL) /*!< FOVFL (Bitfield-Mask: 0x01) */
#define IOSLAVE_INTSET_FSIZE_Pos (0UL) /*!< FSIZE (Bit 0) */
#define IOSLAVE_INTSET_FSIZE_Msk (0x1UL) /*!< FSIZE (Bitfield-Mask: 0x01) */
/* ====================================================== REGACCINTEN ====================================================== */
#define IOSLAVE_REGACCINTEN_REGACC_Pos (0UL) /*!< REGACC (Bit 0) */
#define IOSLAVE_REGACCINTEN_REGACC_Msk (0xffffffffUL) /*!< REGACC (Bitfield-Mask: 0xffffffff) */
/* ===================================================== REGACCINTSTAT ===================================================== */
#define IOSLAVE_REGACCINTSTAT_REGACC_Pos (0UL) /*!< REGACC (Bit 0) */
#define IOSLAVE_REGACCINTSTAT_REGACC_Msk (0xffffffffUL) /*!< REGACC (Bitfield-Mask: 0xffffffff) */
/* ===================================================== REGACCINTCLR ====================================================== */
#define IOSLAVE_REGACCINTCLR_REGACC_Pos (0UL) /*!< REGACC (Bit 0) */
#define IOSLAVE_REGACCINTCLR_REGACC_Msk (0xffffffffUL) /*!< REGACC (Bitfield-Mask: 0xffffffff) */
/* ===================================================== REGACCINTSET ====================================================== */
#define IOSLAVE_REGACCINTSET_REGACC_Pos (0UL) /*!< REGACC (Bit 0) */
#define IOSLAVE_REGACCINTSET_REGACC_Msk (0xffffffffUL) /*!< REGACC (Bitfield-Mask: 0xffffffff) */
/* =========================================================================================================================== */
/* ================ MCUCTRL ================ */
/* =========================================================================================================================== */
/* ======================================================== CHIPPN ========================================================= */
#define MCUCTRL_CHIPPN_PARTNUM_Pos (0UL) /*!< PARTNUM (Bit 0) */
#define MCUCTRL_CHIPPN_PARTNUM_Msk (0xffffffffUL) /*!< PARTNUM (Bitfield-Mask: 0xffffffff) */
/* ======================================================== CHIPID0 ======================================================== */
#define MCUCTRL_CHIPID0_CHIPID0_Pos (0UL) /*!< CHIPID0 (Bit 0) */
#define MCUCTRL_CHIPID0_CHIPID0_Msk (0xffffffffUL) /*!< CHIPID0 (Bitfield-Mask: 0xffffffff) */
/* ======================================================== CHIPID1 ======================================================== */
#define MCUCTRL_CHIPID1_CHIPID1_Pos (0UL) /*!< CHIPID1 (Bit 0) */
#define MCUCTRL_CHIPID1_CHIPID1_Msk (0xffffffffUL) /*!< CHIPID1 (Bitfield-Mask: 0xffffffff) */
/* ======================================================== CHIPREV ======================================================== */
#define MCUCTRL_CHIPREV_SIPART_Pos (8UL) /*!< SIPART (Bit 8) */
#define MCUCTRL_CHIPREV_SIPART_Msk (0xfff00UL) /*!< SIPART (Bitfield-Mask: 0xfff) */
#define MCUCTRL_CHIPREV_REVMAJ_Pos (4UL) /*!< REVMAJ (Bit 4) */
#define MCUCTRL_CHIPREV_REVMAJ_Msk (0xf0UL) /*!< REVMAJ (Bitfield-Mask: 0x0f) */
#define MCUCTRL_CHIPREV_REVMIN_Pos (0UL) /*!< REVMIN (Bit 0) */
#define MCUCTRL_CHIPREV_REVMIN_Msk (0xfUL) /*!< REVMIN (Bitfield-Mask: 0x0f) */
/* ======================================================= VENDORID ======================================================== */
#define MCUCTRL_VENDORID_VENDORID_Pos (0UL) /*!< VENDORID (Bit 0) */
#define MCUCTRL_VENDORID_VENDORID_Msk (0xffffffffUL) /*!< VENDORID (Bitfield-Mask: 0xffffffff) */
/* ========================================================== SKU ========================================================== */
#define MCUCTRL_SKU_SECBOOT_Pos (2UL) /*!< SECBOOT (Bit 2) */
#define MCUCTRL_SKU_SECBOOT_Msk (0x4UL) /*!< SECBOOT (Bitfield-Mask: 0x01) */
#define MCUCTRL_SKU_ALLOWBLE_Pos (1UL) /*!< ALLOWBLE (Bit 1) */
#define MCUCTRL_SKU_ALLOWBLE_Msk (0x2UL) /*!< ALLOWBLE (Bitfield-Mask: 0x01) */
#define MCUCTRL_SKU_ALLOWBURST_Pos (0UL) /*!< ALLOWBURST (Bit 0) */
#define MCUCTRL_SKU_ALLOWBURST_Msk (0x1UL) /*!< ALLOWBURST (Bitfield-Mask: 0x01) */
/* ===================================================== FEATUREENABLE ===================================================== */
#define MCUCTRL_FEATUREENABLE_BURSTAVAIL_Pos (6UL) /*!< BURSTAVAIL (Bit 6) */
#define MCUCTRL_FEATUREENABLE_BURSTAVAIL_Msk (0x40UL) /*!< BURSTAVAIL (Bitfield-Mask: 0x01) */
#define MCUCTRL_FEATUREENABLE_BURSTACK_Pos (5UL) /*!< BURSTACK (Bit 5) */
#define MCUCTRL_FEATUREENABLE_BURSTACK_Msk (0x20UL) /*!< BURSTACK (Bitfield-Mask: 0x01) */
#define MCUCTRL_FEATUREENABLE_BURSTREQ_Pos (4UL) /*!< BURSTREQ (Bit 4) */
#define MCUCTRL_FEATUREENABLE_BURSTREQ_Msk (0x10UL) /*!< BURSTREQ (Bitfield-Mask: 0x01) */
#define MCUCTRL_FEATUREENABLE_BLEAVAIL_Pos (2UL) /*!< BLEAVAIL (Bit 2) */
#define MCUCTRL_FEATUREENABLE_BLEAVAIL_Msk (0x4UL) /*!< BLEAVAIL (Bitfield-Mask: 0x01) */
#define MCUCTRL_FEATUREENABLE_BLEACK_Pos (1UL) /*!< BLEACK (Bit 1) */
#define MCUCTRL_FEATUREENABLE_BLEACK_Msk (0x2UL) /*!< BLEACK (Bitfield-Mask: 0x01) */
#define MCUCTRL_FEATUREENABLE_BLEREQ_Pos (0UL) /*!< BLEREQ (Bit 0) */
#define MCUCTRL_FEATUREENABLE_BLEREQ_Msk (0x1UL) /*!< BLEREQ (Bitfield-Mask: 0x01) */
/* ======================================================= DEBUGGER ======================================================== */
#define MCUCTRL_DEBUGGER_LOCKOUT_Pos (0UL) /*!< LOCKOUT (Bit 0) */
#define MCUCTRL_DEBUGGER_LOCKOUT_Msk (0x1UL) /*!< LOCKOUT (Bitfield-Mask: 0x01) */
/* ======================================================== BODCTRL ======================================================== */
#define MCUCTRL_BODCTRL_BODHVREFSEL_Pos (5UL) /*!< BODHVREFSEL (Bit 5) */
#define MCUCTRL_BODCTRL_BODHVREFSEL_Msk (0x20UL) /*!< BODHVREFSEL (Bitfield-Mask: 0x01) */
#define MCUCTRL_BODCTRL_BODLVREFSEL_Pos (4UL) /*!< BODLVREFSEL (Bit 4) */
#define MCUCTRL_BODCTRL_BODLVREFSEL_Msk (0x10UL) /*!< BODLVREFSEL (Bitfield-Mask: 0x01) */
#define MCUCTRL_BODCTRL_BODFPWD_Pos (3UL) /*!< BODFPWD (Bit 3) */
#define MCUCTRL_BODCTRL_BODFPWD_Msk (0x8UL) /*!< BODFPWD (Bitfield-Mask: 0x01) */
#define MCUCTRL_BODCTRL_BODCPWD_Pos (2UL) /*!< BODCPWD (Bit 2) */
#define MCUCTRL_BODCTRL_BODCPWD_Msk (0x4UL) /*!< BODCPWD (Bitfield-Mask: 0x01) */
#define MCUCTRL_BODCTRL_BODHPWD_Pos (1UL) /*!< BODHPWD (Bit 1) */
#define MCUCTRL_BODCTRL_BODHPWD_Msk (0x2UL) /*!< BODHPWD (Bitfield-Mask: 0x01) */
#define MCUCTRL_BODCTRL_BODLPWD_Pos (0UL) /*!< BODLPWD (Bit 0) */
#define MCUCTRL_BODCTRL_BODLPWD_Msk (0x1UL) /*!< BODLPWD (Bitfield-Mask: 0x01) */
/* ======================================================= ADCPWRDLY ======================================================= */
#define MCUCTRL_ADCPWRDLY_ADCPWR1_Pos (8UL) /*!< ADCPWR1 (Bit 8) */
#define MCUCTRL_ADCPWRDLY_ADCPWR1_Msk (0xff00UL) /*!< ADCPWR1 (Bitfield-Mask: 0xff) */
#define MCUCTRL_ADCPWRDLY_ADCPWR0_Pos (0UL) /*!< ADCPWR0 (Bit 0) */
#define MCUCTRL_ADCPWRDLY_ADCPWR0_Msk (0xffUL) /*!< ADCPWR0 (Bitfield-Mask: 0xff) */
/* ======================================================== ADCCAL ========================================================= */
#define MCUCTRL_ADCCAL_ADCCALIBRATED_Pos (1UL) /*!< ADCCALIBRATED (Bit 1) */
#define MCUCTRL_ADCCAL_ADCCALIBRATED_Msk (0x2UL) /*!< ADCCALIBRATED (Bitfield-Mask: 0x01) */
#define MCUCTRL_ADCCAL_CALONPWRUP_Pos (0UL) /*!< CALONPWRUP (Bit 0) */
#define MCUCTRL_ADCCAL_CALONPWRUP_Msk (0x1UL) /*!< CALONPWRUP (Bitfield-Mask: 0x01) */
/* ====================================================== ADCBATTLOAD ====================================================== */
#define MCUCTRL_ADCBATTLOAD_BATTLOAD_Pos (0UL) /*!< BATTLOAD (Bit 0) */
#define MCUCTRL_ADCBATTLOAD_BATTLOAD_Msk (0x1UL) /*!< BATTLOAD (Bitfield-Mask: 0x01) */
/* ======================================================== ADCTRIM ======================================================== */
#define MCUCTRL_ADCTRIM_ADCRFBUFIBTRIM_Pos (11UL) /*!< ADCRFBUFIBTRIM (Bit 11) */
#define MCUCTRL_ADCTRIM_ADCRFBUFIBTRIM_Msk (0x1800UL) /*!< ADCRFBUFIBTRIM (Bitfield-Mask: 0x03) */
#define MCUCTRL_ADCTRIM_ADCREFBUFTRIM_Pos (6UL) /*!< ADCREFBUFTRIM (Bit 6) */
#define MCUCTRL_ADCTRIM_ADCREFBUFTRIM_Msk (0x7c0UL) /*!< ADCREFBUFTRIM (Bitfield-Mask: 0x1f) */
#define MCUCTRL_ADCTRIM_ADCREFKEEPIBTRIM_Pos (0UL) /*!< ADCREFKEEPIBTRIM (Bit 0) */
#define MCUCTRL_ADCTRIM_ADCREFKEEPIBTRIM_Msk (0x3UL) /*!< ADCREFKEEPIBTRIM (Bitfield-Mask: 0x03) */
/* ====================================================== ADCREFCOMP ======================================================= */
#define MCUCTRL_ADCREFCOMP_ADCRFCMPEN_Pos (16UL) /*!< ADCRFCMPEN (Bit 16) */
#define MCUCTRL_ADCREFCOMP_ADCRFCMPEN_Msk (0x10000UL) /*!< ADCRFCMPEN (Bitfield-Mask: 0x01) */
#define MCUCTRL_ADCREFCOMP_ADCREFKEEPTRIM_Pos (8UL) /*!< ADCREFKEEPTRIM (Bit 8) */
#define MCUCTRL_ADCREFCOMP_ADCREFKEEPTRIM_Msk (0x1f00UL) /*!< ADCREFKEEPTRIM (Bitfield-Mask: 0x1f) */
#define MCUCTRL_ADCREFCOMP_ADC_REFCOMP_OUT_Pos (0UL) /*!< ADC_REFCOMP_OUT (Bit 0) */
#define MCUCTRL_ADCREFCOMP_ADC_REFCOMP_OUT_Msk (0x1UL) /*!< ADC_REFCOMP_OUT (Bitfield-Mask: 0x01) */
/* ======================================================= XTALCTRL ======================================================== */
#define MCUCTRL_XTALCTRL_XTALICOMPTRIM_Pos (8UL) /*!< XTALICOMPTRIM (Bit 8) */
#define MCUCTRL_XTALCTRL_XTALICOMPTRIM_Msk (0x300UL) /*!< XTALICOMPTRIM (Bitfield-Mask: 0x03) */
#define MCUCTRL_XTALCTRL_XTALIBUFTRIM_Pos (6UL) /*!< XTALIBUFTRIM (Bit 6) */
#define MCUCTRL_XTALCTRL_XTALIBUFTRIM_Msk (0xc0UL) /*!< XTALIBUFTRIM (Bitfield-Mask: 0x03) */
#define MCUCTRL_XTALCTRL_PWDBODXTAL_Pos (5UL) /*!< PWDBODXTAL (Bit 5) */
#define MCUCTRL_XTALCTRL_PWDBODXTAL_Msk (0x20UL) /*!< PWDBODXTAL (Bitfield-Mask: 0x01) */
#define MCUCTRL_XTALCTRL_PDNBCMPRXTAL_Pos (4UL) /*!< PDNBCMPRXTAL (Bit 4) */
#define MCUCTRL_XTALCTRL_PDNBCMPRXTAL_Msk (0x10UL) /*!< PDNBCMPRXTAL (Bitfield-Mask: 0x01) */
#define MCUCTRL_XTALCTRL_PDNBCOREXTAL_Pos (3UL) /*!< PDNBCOREXTAL (Bit 3) */
#define MCUCTRL_XTALCTRL_PDNBCOREXTAL_Msk (0x8UL) /*!< PDNBCOREXTAL (Bitfield-Mask: 0x01) */
#define MCUCTRL_XTALCTRL_BYPCMPRXTAL_Pos (2UL) /*!< BYPCMPRXTAL (Bit 2) */
#define MCUCTRL_XTALCTRL_BYPCMPRXTAL_Msk (0x4UL) /*!< BYPCMPRXTAL (Bitfield-Mask: 0x01) */
#define MCUCTRL_XTALCTRL_FDBKDSBLXTAL_Pos (1UL) /*!< FDBKDSBLXTAL (Bit 1) */
#define MCUCTRL_XTALCTRL_FDBKDSBLXTAL_Msk (0x2UL) /*!< FDBKDSBLXTAL (Bitfield-Mask: 0x01) */
#define MCUCTRL_XTALCTRL_XTALSWE_Pos (0UL) /*!< XTALSWE (Bit 0) */
#define MCUCTRL_XTALCTRL_XTALSWE_Msk (0x1UL) /*!< XTALSWE (Bitfield-Mask: 0x01) */
/* ====================================================== XTALGENCTRL ====================================================== */
#define MCUCTRL_XTALGENCTRL_XTALKSBIASTRIM_Pos (8UL) /*!< XTALKSBIASTRIM (Bit 8) */
#define MCUCTRL_XTALGENCTRL_XTALKSBIASTRIM_Msk (0x3f00UL) /*!< XTALKSBIASTRIM (Bitfield-Mask: 0x3f) */
#define MCUCTRL_XTALGENCTRL_XTALBIASTRIM_Pos (2UL) /*!< XTALBIASTRIM (Bit 2) */
#define MCUCTRL_XTALGENCTRL_XTALBIASTRIM_Msk (0xfcUL) /*!< XTALBIASTRIM (Bitfield-Mask: 0x3f) */
#define MCUCTRL_XTALGENCTRL_ACWARMUP_Pos (0UL) /*!< ACWARMUP (Bit 0) */
#define MCUCTRL_XTALGENCTRL_ACWARMUP_Msk (0x3UL) /*!< ACWARMUP (Bitfield-Mask: 0x03) */
/* ======================================================= MISCCTRL ======================================================== */
#define MCUCTRL_MISCCTRL_BLE_RESETN_Pos (5UL) /*!< BLE_RESETN (Bit 5) */
#define MCUCTRL_MISCCTRL_BLE_RESETN_Msk (0x20UL) /*!< BLE_RESETN (Bitfield-Mask: 0x01) */
#define MCUCTRL_MISCCTRL_RESERVED_RW_0_Pos (0UL) /*!< RESERVED_RW_0 (Bit 0) */
#define MCUCTRL_MISCCTRL_RESERVED_RW_0_Msk (0x1fUL) /*!< RESERVED_RW_0 (Bitfield-Mask: 0x1f) */
/* ====================================================== BOOTLOADER ======================================================= */
#define MCUCTRL_BOOTLOADER_SECBOOTONRST_Pos (30UL) /*!< SECBOOTONRST (Bit 30) */
#define MCUCTRL_BOOTLOADER_SECBOOTONRST_Msk (0xc0000000UL) /*!< SECBOOTONRST (Bitfield-Mask: 0x03) */
#define MCUCTRL_BOOTLOADER_SECBOOT_Pos (28UL) /*!< SECBOOT (Bit 28) */
#define MCUCTRL_BOOTLOADER_SECBOOT_Msk (0x30000000UL) /*!< SECBOOT (Bitfield-Mask: 0x03) */
#define MCUCTRL_BOOTLOADER_SECBOOTFEATURE_Pos (26UL) /*!< SECBOOTFEATURE (Bit 26) */
#define MCUCTRL_BOOTLOADER_SECBOOTFEATURE_Msk (0xc000000UL) /*!< SECBOOTFEATURE (Bitfield-Mask: 0x03) */
#define MCUCTRL_BOOTLOADER_PROTLOCK_Pos (2UL) /*!< PROTLOCK (Bit 2) */
#define MCUCTRL_BOOTLOADER_PROTLOCK_Msk (0x4UL) /*!< PROTLOCK (Bitfield-Mask: 0x01) */
#define MCUCTRL_BOOTLOADER_SBLOCK_Pos (1UL) /*!< SBLOCK (Bit 1) */
#define MCUCTRL_BOOTLOADER_SBLOCK_Msk (0x2UL) /*!< SBLOCK (Bitfield-Mask: 0x01) */
#define MCUCTRL_BOOTLOADER_BOOTLOADERLOW_Pos (0UL) /*!< BOOTLOADERLOW (Bit 0) */
#define MCUCTRL_BOOTLOADER_BOOTLOADERLOW_Msk (0x1UL) /*!< BOOTLOADERLOW (Bitfield-Mask: 0x01) */
/* ====================================================== SHADOWVALID ====================================================== */
#define MCUCTRL_SHADOWVALID_INFO0_VALID_Pos (2UL) /*!< INFO0_VALID (Bit 2) */
#define MCUCTRL_SHADOWVALID_INFO0_VALID_Msk (0x4UL) /*!< INFO0_VALID (Bitfield-Mask: 0x01) */
#define MCUCTRL_SHADOWVALID_BLDSLEEP_Pos (1UL) /*!< BLDSLEEP (Bit 1) */
#define MCUCTRL_SHADOWVALID_BLDSLEEP_Msk (0x2UL) /*!< BLDSLEEP (Bitfield-Mask: 0x01) */
#define MCUCTRL_SHADOWVALID_VALID_Pos (0UL) /*!< VALID (Bit 0) */
#define MCUCTRL_SHADOWVALID_VALID_Msk (0x1UL) /*!< VALID (Bitfield-Mask: 0x01) */
/* ======================================================= SCRATCH0 ======================================================== */
#define MCUCTRL_SCRATCH0_SCRATCH0_Pos (0UL) /*!< SCRATCH0 (Bit 0) */
#define MCUCTRL_SCRATCH0_SCRATCH0_Msk (0xffffffffUL) /*!< SCRATCH0 (Bitfield-Mask: 0xffffffff) */
/* ======================================================= SCRATCH1 ======================================================== */
#define MCUCTRL_SCRATCH1_SCRATCH1_Pos (0UL) /*!< SCRATCH1 (Bit 0) */
#define MCUCTRL_SCRATCH1_SCRATCH1_Msk (0xffffffffUL) /*!< SCRATCH1 (Bitfield-Mask: 0xffffffff) */
/* ==================================================== ICODEFAULTADDR ===================================================== */
#define MCUCTRL_ICODEFAULTADDR_ICODEFAULTADDR_Pos (0UL) /*!< ICODEFAULTADDR (Bit 0) */
#define MCUCTRL_ICODEFAULTADDR_ICODEFAULTADDR_Msk (0xffffffffUL) /*!< ICODEFAULTADDR (Bitfield-Mask: 0xffffffff) */
/* ==================================================== DCODEFAULTADDR ===================================================== */
#define MCUCTRL_DCODEFAULTADDR_DCODEFAULTADDR_Pos (0UL) /*!< DCODEFAULTADDR (Bit 0) */
#define MCUCTRL_DCODEFAULTADDR_DCODEFAULTADDR_Msk (0xffffffffUL) /*!< DCODEFAULTADDR (Bitfield-Mask: 0xffffffff) */
/* ===================================================== SYSFAULTADDR ====================================================== */
#define MCUCTRL_SYSFAULTADDR_SYSFAULTADDR_Pos (0UL) /*!< SYSFAULTADDR (Bit 0) */
#define MCUCTRL_SYSFAULTADDR_SYSFAULTADDR_Msk (0xffffffffUL) /*!< SYSFAULTADDR (Bitfield-Mask: 0xffffffff) */
/* ====================================================== FAULTSTATUS ====================================================== */
#define MCUCTRL_FAULTSTATUS_SYSFAULT_Pos (2UL) /*!< SYSFAULT (Bit 2) */
#define MCUCTRL_FAULTSTATUS_SYSFAULT_Msk (0x4UL) /*!< SYSFAULT (Bitfield-Mask: 0x01) */
#define MCUCTRL_FAULTSTATUS_DCODEFAULT_Pos (1UL) /*!< DCODEFAULT (Bit 1) */
#define MCUCTRL_FAULTSTATUS_DCODEFAULT_Msk (0x2UL) /*!< DCODEFAULT (Bitfield-Mask: 0x01) */
#define MCUCTRL_FAULTSTATUS_ICODEFAULT_Pos (0UL) /*!< ICODEFAULT (Bit 0) */
#define MCUCTRL_FAULTSTATUS_ICODEFAULT_Msk (0x1UL) /*!< ICODEFAULT (Bitfield-Mask: 0x01) */
/* ==================================================== FAULTCAPTUREEN ===================================================== */
#define MCUCTRL_FAULTCAPTUREEN_FAULTCAPTUREEN_Pos (0UL) /*!< FAULTCAPTUREEN (Bit 0) */
#define MCUCTRL_FAULTCAPTUREEN_FAULTCAPTUREEN_Msk (0x1UL) /*!< FAULTCAPTUREEN (Bitfield-Mask: 0x01) */
/* ========================================================= DBGR1 ========================================================= */
#define MCUCTRL_DBGR1_ONETO8_Pos (0UL) /*!< ONETO8 (Bit 0) */
#define MCUCTRL_DBGR1_ONETO8_Msk (0xffffffffUL) /*!< ONETO8 (Bitfield-Mask: 0xffffffff) */
/* ========================================================= DBGR2 ========================================================= */
#define MCUCTRL_DBGR2_COOLCODE_Pos (0UL) /*!< COOLCODE (Bit 0) */
#define MCUCTRL_DBGR2_COOLCODE_Msk (0xffffffffUL) /*!< COOLCODE (Bitfield-Mask: 0xffffffff) */
/* ======================================================= PMUENABLE ======================================================= */
#define MCUCTRL_PMUENABLE_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */
#define MCUCTRL_PMUENABLE_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
/* ======================================================= TPIUCTRL ======================================================== */
#define MCUCTRL_TPIUCTRL_CLKSEL_Pos (8UL) /*!< CLKSEL (Bit 8) */
#define MCUCTRL_TPIUCTRL_CLKSEL_Msk (0x700UL) /*!< CLKSEL (Bitfield-Mask: 0x07) */
#define MCUCTRL_TPIUCTRL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */
#define MCUCTRL_TPIUCTRL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
/* ====================================================== OTAPOINTER ======================================================= */
#define MCUCTRL_OTAPOINTER_OTAPOINTER_Pos (2UL) /*!< OTAPOINTER (Bit 2) */
#define MCUCTRL_OTAPOINTER_OTAPOINTER_Msk (0xfffffffcUL) /*!< OTAPOINTER (Bitfield-Mask: 0x3fffffff) */
#define MCUCTRL_OTAPOINTER_OTASBLUPDATE_Pos (1UL) /*!< OTASBLUPDATE (Bit 1) */
#define MCUCTRL_OTAPOINTER_OTASBLUPDATE_Msk (0x2UL) /*!< OTASBLUPDATE (Bitfield-Mask: 0x01) */
#define MCUCTRL_OTAPOINTER_OTAVALID_Pos (0UL) /*!< OTAVALID (Bit 0) */
#define MCUCTRL_OTAPOINTER_OTAVALID_Msk (0x1UL) /*!< OTAVALID (Bitfield-Mask: 0x01) */
/* ====================================================== APBDMACTRL ======================================================= */
#define MCUCTRL_APBDMACTRL_HYSTERESIS_Pos (8UL) /*!< HYSTERESIS (Bit 8) */
#define MCUCTRL_APBDMACTRL_HYSTERESIS_Msk (0xff00UL) /*!< HYSTERESIS (Bitfield-Mask: 0xff) */
#define MCUCTRL_APBDMACTRL_DECODEABORT_Pos (1UL) /*!< DECODEABORT (Bit 1) */
#define MCUCTRL_APBDMACTRL_DECODEABORT_Msk (0x2UL) /*!< DECODEABORT (Bitfield-Mask: 0x01) */
#define MCUCTRL_APBDMACTRL_DMA_ENABLE_Pos (0UL) /*!< DMA_ENABLE (Bit 0) */
#define MCUCTRL_APBDMACTRL_DMA_ENABLE_Msk (0x1UL) /*!< DMA_ENABLE (Bitfield-Mask: 0x01) */
/* ======================================================= SRAMMODE ======================================================== */
#define MCUCTRL_SRAMMODE_DPREFETCH_CACHE_Pos (5UL) /*!< DPREFETCH_CACHE (Bit 5) */
#define MCUCTRL_SRAMMODE_DPREFETCH_CACHE_Msk (0x20UL) /*!< DPREFETCH_CACHE (Bitfield-Mask: 0x01) */
#define MCUCTRL_SRAMMODE_DPREFETCH_Pos (4UL) /*!< DPREFETCH (Bit 4) */
#define MCUCTRL_SRAMMODE_DPREFETCH_Msk (0x10UL) /*!< DPREFETCH (Bitfield-Mask: 0x01) */
#define MCUCTRL_SRAMMODE_IPREFETCH_CACHE_Pos (1UL) /*!< IPREFETCH_CACHE (Bit 1) */
#define MCUCTRL_SRAMMODE_IPREFETCH_CACHE_Msk (0x2UL) /*!< IPREFETCH_CACHE (Bitfield-Mask: 0x01) */
#define MCUCTRL_SRAMMODE_IPREFETCH_Pos (0UL) /*!< IPREFETCH (Bit 0) */
#define MCUCTRL_SRAMMODE_IPREFETCH_Msk (0x1UL) /*!< IPREFETCH (Bitfield-Mask: 0x01) */
/* ====================================================== KEXTCLKSEL ======================================================= */
#define MCUCTRL_KEXTCLKSEL_KEXTCLKSEL_Pos (0UL) /*!< KEXTCLKSEL (Bit 0) */
#define MCUCTRL_KEXTCLKSEL_KEXTCLKSEL_Msk (0xffffffffUL) /*!< KEXTCLKSEL (Bitfield-Mask: 0xffffffff) */
/* ======================================================= SIMOBUCK1 ======================================================= */
#define MCUCTRL_SIMOBUCK1_RESERVED_RW_23_Pos (28UL) /*!< RESERVED_RW_23 (Bit 28) */
#define MCUCTRL_SIMOBUCK1_RESERVED_RW_23_Msk (0xf0000000UL) /*!< RESERVED_RW_23 (Bitfield-Mask: 0x0f) */
#define MCUCTRL_SIMOBUCK1_SIMOBUCKMEMLPTRIM_Pos (22UL) /*!< SIMOBUCKMEMLPTRIM (Bit 22) */
#define MCUCTRL_SIMOBUCK1_SIMOBUCKMEMLPTRIM_Msk (0xfc00000UL) /*!< SIMOBUCKMEMLPTRIM (Bitfield-Mask: 0x3f) */
#define MCUCTRL_SIMOBUCK1_RESERVED_RW_00_Pos (0UL) /*!< RESERVED_RW_00 (Bit 0) */
#define MCUCTRL_SIMOBUCK1_RESERVED_RW_00_Msk (0x3fffffUL) /*!< RESERVED_RW_00 (Bitfield-Mask: 0x3fffff) */
/* ======================================================= SIMOBUCK2 ======================================================= */
#define MCUCTRL_SIMOBUCK2_RESERVED_RW_30_Pos (30UL) /*!< RESERVED_RW_30 (Bit 30) */
#define MCUCTRL_SIMOBUCK2_RESERVED_RW_30_Msk (0xc0000000UL) /*!< RESERVED_RW_30 (Bitfield-Mask: 0x03) */
#define MCUCTRL_SIMOBUCK2_SIMOBUCKCORELEAKAGETRIM_Pos (28UL) /*!< SIMOBUCKCORELEAKAGETRIM (Bit 28) */
#define MCUCTRL_SIMOBUCK2_SIMOBUCKCORELEAKAGETRIM_Msk (0x30000000UL) /*!< SIMOBUCKCORELEAKAGETRIM (Bitfield-Mask: 0x03) */
#define MCUCTRL_SIMOBUCK2_RESERVED_RW_24_Pos (24UL) /*!< RESERVED_RW_24 (Bit 24) */
#define MCUCTRL_SIMOBUCK2_RESERVED_RW_24_Msk (0xf000000UL) /*!< RESERVED_RW_24 (Bitfield-Mask: 0x0f) */
#define MCUCTRL_SIMOBUCK2_SIMOBUCKCORELPLOWTONTRIM_Pos (20UL) /*!< SIMOBUCKCORELPLOWTONTRIM (Bit 20) */
#define MCUCTRL_SIMOBUCK2_SIMOBUCKCORELPLOWTONTRIM_Msk (0xf00000UL) /*!< SIMOBUCKCORELPLOWTONTRIM (Bitfield-Mask: 0x0f) */
#define MCUCTRL_SIMOBUCK2_SIMOBUCKCORELPHIGHTONTRIM_Pos (16UL) /*!< SIMOBUCKCORELPHIGHTONTRIM (Bit 16) */
#define MCUCTRL_SIMOBUCK2_SIMOBUCKCORELPHIGHTONTRIM_Msk (0xf0000UL) /*!< SIMOBUCKCORELPHIGHTONTRIM (Bitfield-Mask: 0x0f) */
#define MCUCTRL_SIMOBUCK2_RESERVED_RW_5_Pos (5UL) /*!< RESERVED_RW_5 (Bit 5) */
#define MCUCTRL_SIMOBUCK2_RESERVED_RW_5_Msk (0xffe0UL) /*!< RESERVED_RW_5 (Bitfield-Mask: 0x7ff) */
#define MCUCTRL_SIMOBUCK2_SIMOBUCKTONGENTRIM_Pos (0UL) /*!< SIMOBUCKTONGENTRIM (Bit 0) */
#define MCUCTRL_SIMOBUCK2_SIMOBUCKTONGENTRIM_Msk (0x1fUL) /*!< SIMOBUCKTONGENTRIM (Bitfield-Mask: 0x1f) */
/* ======================================================= SIMOBUCK3 ======================================================= */
#define MCUCTRL_SIMOBUCK3_RESERVED_RW_31_Pos (31UL) /*!< RESERVED_RW_31 (Bit 31) */
#define MCUCTRL_SIMOBUCK3_RESERVED_RW_31_Msk (0x80000000UL) /*!< RESERVED_RW_31 (Bitfield-Mask: 0x01) */
#define MCUCTRL_SIMOBUCK3_SIMOBUCKMEMLPHIGHTONTRIM_Pos (27UL) /*!< SIMOBUCKMEMLPHIGHTONTRIM (Bit 27) */
#define MCUCTRL_SIMOBUCK3_SIMOBUCKMEMLPHIGHTONTRIM_Msk (0x78000000UL) /*!< SIMOBUCKMEMLPHIGHTONTRIM (Bitfield-Mask: 0x0f) */
#define MCUCTRL_SIMOBUCK3_RESERVED_RW_16_Pos (16UL) /*!< RESERVED_RW_16 (Bit 16) */
#define MCUCTRL_SIMOBUCK3_RESERVED_RW_16_Msk (0x7ff0000UL) /*!< RESERVED_RW_16 (Bitfield-Mask: 0x7ff) */
#define MCUCTRL_SIMOBUCK3_SIMOBUCKMEMLPLOWTOFFTRIM_Pos (12UL) /*!< SIMOBUCKMEMLPLOWTOFFTRIM (Bit 12) */
#define MCUCTRL_SIMOBUCK3_SIMOBUCKMEMLPLOWTOFFTRIM_Msk (0xf000UL) /*!< SIMOBUCKMEMLPLOWTOFFTRIM (Bitfield-Mask: 0x0f) */
#define MCUCTRL_SIMOBUCK3_SIMOBUCKMEMLPHIGHTOFFTRIM_Pos (8UL) /*!< SIMOBUCKMEMLPHIGHTOFFTRIM (Bit 8) */
#define MCUCTRL_SIMOBUCK3_SIMOBUCKMEMLPHIGHTOFFTRIM_Msk (0xf00UL) /*!< SIMOBUCKMEMLPHIGHTOFFTRIM (Bitfield-Mask: 0x0f) */
#define MCUCTRL_SIMOBUCK3_SIMOBUCKCORELPLOWTOFFTRIM_Pos (4UL) /*!< SIMOBUCKCORELPLOWTOFFTRIM (Bit 4) */
#define MCUCTRL_SIMOBUCK3_SIMOBUCKCORELPLOWTOFFTRIM_Msk (0xf0UL) /*!< SIMOBUCKCORELPLOWTOFFTRIM (Bitfield-Mask: 0x0f) */
#define MCUCTRL_SIMOBUCK3_SIMOBUCKCORELPHIGHTOFFTRIM_Pos (0UL) /*!< SIMOBUCKCORELPHIGHTOFFTRIM (Bit 0) */
#define MCUCTRL_SIMOBUCK3_SIMOBUCKCORELPHIGHTOFFTRIM_Msk (0xfUL) /*!< SIMOBUCKCORELPHIGHTOFFTRIM (Bitfield-Mask: 0x0f) */
/* ======================================================= SIMOBUCK4 ======================================================= */
#define MCUCTRL_SIMOBUCK4_SIMOBUCKCOMP2TIMEOUTEN_Pos (24UL) /*!< SIMOBUCKCOMP2TIMEOUTEN (Bit 24) */
#define MCUCTRL_SIMOBUCK4_SIMOBUCKCOMP2TIMEOUTEN_Msk (0x1000000UL) /*!< SIMOBUCKCOMP2TIMEOUTEN (Bitfield-Mask: 0x01) */
#define MCUCTRL_SIMOBUCK4_SIMOBUCKCOMP2LPEN_Pos (23UL) /*!< SIMOBUCKCOMP2LPEN (Bit 23) */
#define MCUCTRL_SIMOBUCK4_SIMOBUCKCOMP2LPEN_Msk (0x800000UL) /*!< SIMOBUCKCOMP2LPEN (Bitfield-Mask: 0x01) */
#define MCUCTRL_SIMOBUCK4_SIMOBUCKCLKDIVSEL_Pos (21UL) /*!< SIMOBUCKCLKDIVSEL (Bit 21) */
#define MCUCTRL_SIMOBUCK4_SIMOBUCKCLKDIVSEL_Msk (0x600000UL) /*!< SIMOBUCKCLKDIVSEL (Bitfield-Mask: 0x03) */
#define MCUCTRL_SIMOBUCK4_SIMOBUCKMEMLPLOWTONTRIM_Pos (0UL) /*!< SIMOBUCKMEMLPLOWTONTRIM (Bit 0) */
#define MCUCTRL_SIMOBUCK4_SIMOBUCKMEMLPLOWTONTRIM_Msk (0xfUL) /*!< SIMOBUCKMEMLPLOWTONTRIM (Bitfield-Mask: 0x0f) */
/* ======================================================= BLEBUCK2 ======================================================== */
#define MCUCTRL_BLEBUCK2_BLEBUCKTOND2ATRIM_Pos (12UL) /*!< BLEBUCKTOND2ATRIM (Bit 12) */
#define MCUCTRL_BLEBUCK2_BLEBUCKTOND2ATRIM_Msk (0x3f000UL) /*!< BLEBUCKTOND2ATRIM (Bitfield-Mask: 0x3f) */
#define MCUCTRL_BLEBUCK2_BLEBUCKTONHITRIM_Pos (6UL) /*!< BLEBUCKTONHITRIM (Bit 6) */
#define MCUCTRL_BLEBUCK2_BLEBUCKTONHITRIM_Msk (0xfc0UL) /*!< BLEBUCKTONHITRIM (Bitfield-Mask: 0x3f) */
#define MCUCTRL_BLEBUCK2_BLEBUCKTONLOWTRIM_Pos (0UL) /*!< BLEBUCKTONLOWTRIM (Bit 0) */
#define MCUCTRL_BLEBUCK2_BLEBUCKTONLOWTRIM_Msk (0x3fUL) /*!< BLEBUCKTONLOWTRIM (Bitfield-Mask: 0x3f) */
/* ====================================================== FLASHWPROT0 ====================================================== */
#define MCUCTRL_FLASHWPROT0_FW0BITS_Pos (0UL) /*!< FW0BITS (Bit 0) */
#define MCUCTRL_FLASHWPROT0_FW0BITS_Msk (0xffffffffUL) /*!< FW0BITS (Bitfield-Mask: 0xffffffff) */
/* ====================================================== FLASHWPROT1 ====================================================== */
#define MCUCTRL_FLASHWPROT1_FW1BITS_Pos (0UL) /*!< FW1BITS (Bit 0) */
#define MCUCTRL_FLASHWPROT1_FW1BITS_Msk (0xffffffffUL) /*!< FW1BITS (Bitfield-Mask: 0xffffffff) */
/* ====================================================== FLASHRPROT0 ====================================================== */
#define MCUCTRL_FLASHRPROT0_FR0BITS_Pos (0UL) /*!< FR0BITS (Bit 0) */
#define MCUCTRL_FLASHRPROT0_FR0BITS_Msk (0xffffffffUL) /*!< FR0BITS (Bitfield-Mask: 0xffffffff) */
/* ====================================================== FLASHRPROT1 ====================================================== */
#define MCUCTRL_FLASHRPROT1_FR1BITS_Pos (0UL) /*!< FR1BITS (Bit 0) */
#define MCUCTRL_FLASHRPROT1_FR1BITS_Msk (0xffffffffUL) /*!< FR1BITS (Bitfield-Mask: 0xffffffff) */
/* ================================================= DMASRAMWRITEPROTECT0 ================================================== */
#define MCUCTRL_DMASRAMWRITEPROTECT0_DMA_WPROT0_Pos (0UL) /*!< DMA_WPROT0 (Bit 0) */
#define MCUCTRL_DMASRAMWRITEPROTECT0_DMA_WPROT0_Msk (0xffffffffUL) /*!< DMA_WPROT0 (Bitfield-Mask: 0xffffffff) */
/* ================================================= DMASRAMWRITEPROTECT1 ================================================== */
#define MCUCTRL_DMASRAMWRITEPROTECT1_DMA_WPROT1_Pos (0UL) /*!< DMA_WPROT1 (Bit 0) */
#define MCUCTRL_DMASRAMWRITEPROTECT1_DMA_WPROT1_Msk (0xffffUL) /*!< DMA_WPROT1 (Bitfield-Mask: 0xffff) */
/* ================================================== DMASRAMREADPROTECT0 ================================================== */
#define MCUCTRL_DMASRAMREADPROTECT0_DMA_RPROT0_Pos (0UL) /*!< DMA_RPROT0 (Bit 0) */
#define MCUCTRL_DMASRAMREADPROTECT0_DMA_RPROT0_Msk (0xffffffffUL) /*!< DMA_RPROT0 (Bitfield-Mask: 0xffffffff) */
/* ================================================== DMASRAMREADPROTECT1 ================================================== */
#define MCUCTRL_DMASRAMREADPROTECT1_DMA_RPROT1_Pos (0UL) /*!< DMA_RPROT1 (Bit 0) */
#define MCUCTRL_DMASRAMREADPROTECT1_DMA_RPROT1_Msk (0xffffUL) /*!< DMA_RPROT1 (Bitfield-Mask: 0xffff) */
/* =========================================================================================================================== */
/* ================ MSPI ================ */
/* =========================================================================================================================== */
/* ========================================================= CTRL ========================================================== */
#define MSPI_CTRL_XFERBYTES_Pos (16UL) /*!< XFERBYTES (Bit 16) */
#define MSPI_CTRL_XFERBYTES_Msk (0xffff0000UL) /*!< XFERBYTES (Bitfield-Mask: 0xffff) */
#define MSPI_CTRL_PIOSCRAMBLE_Pos (11UL) /*!< PIOSCRAMBLE (Bit 11) */
#define MSPI_CTRL_PIOSCRAMBLE_Msk (0x800UL) /*!< PIOSCRAMBLE (Bitfield-Mask: 0x01) */
#define MSPI_CTRL_TXRX_Pos (10UL) /*!< TXRX (Bit 10) */
#define MSPI_CTRL_TXRX_Msk (0x400UL) /*!< TXRX (Bitfield-Mask: 0x01) */
#define MSPI_CTRL_SENDI_Pos (9UL) /*!< SENDI (Bit 9) */
#define MSPI_CTRL_SENDI_Msk (0x200UL) /*!< SENDI (Bitfield-Mask: 0x01) */
#define MSPI_CTRL_SENDA_Pos (8UL) /*!< SENDA (Bit 8) */
#define MSPI_CTRL_SENDA_Msk (0x100UL) /*!< SENDA (Bitfield-Mask: 0x01) */
#define MSPI_CTRL_ENTURN_Pos (7UL) /*!< ENTURN (Bit 7) */
#define MSPI_CTRL_ENTURN_Msk (0x80UL) /*!< ENTURN (Bitfield-Mask: 0x01) */
#define MSPI_CTRL_BIGENDIAN_Pos (6UL) /*!< BIGENDIAN (Bit 6) */
#define MSPI_CTRL_BIGENDIAN_Msk (0x40UL) /*!< BIGENDIAN (Bitfield-Mask: 0x01) */
#define MSPI_CTRL_QUADCMD_Pos (3UL) /*!< QUADCMD (Bit 3) */
#define MSPI_CTRL_QUADCMD_Msk (0x8UL) /*!< QUADCMD (Bitfield-Mask: 0x01) */
#define MSPI_CTRL_BUSY_Pos (2UL) /*!< BUSY (Bit 2) */
#define MSPI_CTRL_BUSY_Msk (0x4UL) /*!< BUSY (Bitfield-Mask: 0x01) */
#define MSPI_CTRL_STATUS_Pos (1UL) /*!< STATUS (Bit 1) */
#define MSPI_CTRL_STATUS_Msk (0x2UL) /*!< STATUS (Bitfield-Mask: 0x01) */
#define MSPI_CTRL_START_Pos (0UL) /*!< START (Bit 0) */
#define MSPI_CTRL_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
/* ========================================================== CFG ========================================================== */
#define MSPI_CFG_CPOL_Pos (17UL) /*!< CPOL (Bit 17) */
#define MSPI_CFG_CPOL_Msk (0x20000UL) /*!< CPOL (Bitfield-Mask: 0x01) */
#define MSPI_CFG_CPHA_Pos (16UL) /*!< CPHA (Bit 16) */
#define MSPI_CFG_CPHA_Msk (0x10000UL) /*!< CPHA (Bitfield-Mask: 0x01) */
#define MSPI_CFG_TURNAROUND_Pos (8UL) /*!< TURNAROUND (Bit 8) */
#define MSPI_CFG_TURNAROUND_Msk (0x3f00UL) /*!< TURNAROUND (Bitfield-Mask: 0x3f) */
#define MSPI_CFG_SEPIO_Pos (7UL) /*!< SEPIO (Bit 7) */
#define MSPI_CFG_SEPIO_Msk (0x80UL) /*!< SEPIO (Bitfield-Mask: 0x01) */
#define MSPI_CFG_ISIZE_Pos (6UL) /*!< ISIZE (Bit 6) */
#define MSPI_CFG_ISIZE_Msk (0x40UL) /*!< ISIZE (Bitfield-Mask: 0x01) */
#define MSPI_CFG_ASIZE_Pos (4UL) /*!< ASIZE (Bit 4) */
#define MSPI_CFG_ASIZE_Msk (0x30UL) /*!< ASIZE (Bitfield-Mask: 0x03) */
#define MSPI_CFG_DEVCFG_Pos (0UL) /*!< DEVCFG (Bit 0) */
#define MSPI_CFG_DEVCFG_Msk (0xfUL) /*!< DEVCFG (Bitfield-Mask: 0x0f) */
/* ========================================================= ADDR ========================================================== */
#define MSPI_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
#define MSPI_ADDR_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
/* ========================================================= INSTR ========================================================= */
#define MSPI_INSTR_INSTR_Pos (0UL) /*!< INSTR (Bit 0) */
#define MSPI_INSTR_INSTR_Msk (0xffffUL) /*!< INSTR (Bitfield-Mask: 0xffff) */
/* ======================================================== TXFIFO ========================================================= */
#define MSPI_TXFIFO_TXFIFO_Pos (0UL) /*!< TXFIFO (Bit 0) */
#define MSPI_TXFIFO_TXFIFO_Msk (0xffffffffUL) /*!< TXFIFO (Bitfield-Mask: 0xffffffff) */
/* ======================================================== RXFIFO ========================================================= */
#define MSPI_RXFIFO_RXFIFO_Pos (0UL) /*!< RXFIFO (Bit 0) */
#define MSPI_RXFIFO_RXFIFO_Msk (0xffffffffUL) /*!< RXFIFO (Bitfield-Mask: 0xffffffff) */
/* ======================================================= TXENTRIES ======================================================= */
#define MSPI_TXENTRIES_TXENTRIES_Pos (0UL) /*!< TXENTRIES (Bit 0) */
#define MSPI_TXENTRIES_TXENTRIES_Msk (0x1fUL) /*!< TXENTRIES (Bitfield-Mask: 0x1f) */
/* ======================================================= RXENTRIES ======================================================= */
#define MSPI_RXENTRIES_RXENTRIES_Pos (0UL) /*!< RXENTRIES (Bit 0) */
#define MSPI_RXENTRIES_RXENTRIES_Msk (0x1fUL) /*!< RXENTRIES (Bitfield-Mask: 0x1f) */
/* ======================================================= THRESHOLD ======================================================= */
#define MSPI_THRESHOLD_RXTHRESH_Pos (8UL) /*!< RXTHRESH (Bit 8) */
#define MSPI_THRESHOLD_RXTHRESH_Msk (0x1f00UL) /*!< RXTHRESH (Bitfield-Mask: 0x1f) */
#define MSPI_THRESHOLD_TXTHRESH_Pos (0UL) /*!< TXTHRESH (Bit 0) */
#define MSPI_THRESHOLD_TXTHRESH_Msk (0x1fUL) /*!< TXTHRESH (Bitfield-Mask: 0x1f) */
/* ======================================================== MSPICFG ======================================================== */
#define MSPI_MSPICFG_PRSTN_Pos (31UL) /*!< PRSTN (Bit 31) */
#define MSPI_MSPICFG_PRSTN_Msk (0x80000000UL) /*!< PRSTN (Bitfield-Mask: 0x01) */
#define MSPI_MSPICFG_IPRSTN_Pos (30UL) /*!< IPRSTN (Bit 30) */
#define MSPI_MSPICFG_IPRSTN_Msk (0x40000000UL) /*!< IPRSTN (Bitfield-Mask: 0x01) */
#define MSPI_MSPICFG_FIFORESET_Pos (29UL) /*!< FIFORESET (Bit 29) */
#define MSPI_MSPICFG_FIFORESET_Msk (0x20000000UL) /*!< FIFORESET (Bitfield-Mask: 0x01) */
#define MSPI_MSPICFG_CLKDIV_Pos (8UL) /*!< CLKDIV (Bit 8) */
#define MSPI_MSPICFG_CLKDIV_Msk (0x3f00UL) /*!< CLKDIV (Bitfield-Mask: 0x3f) */
#define MSPI_MSPICFG_IOMSEL_Pos (4UL) /*!< IOMSEL (Bit 4) */
#define MSPI_MSPICFG_IOMSEL_Msk (0x70UL) /*!< IOMSEL (Bitfield-Mask: 0x07) */
#define MSPI_MSPICFG_TXNEG_Pos (3UL) /*!< TXNEG (Bit 3) */
#define MSPI_MSPICFG_TXNEG_Msk (0x8UL) /*!< TXNEG (Bitfield-Mask: 0x01) */
#define MSPI_MSPICFG_RXNEG_Pos (2UL) /*!< RXNEG (Bit 2) */
#define MSPI_MSPICFG_RXNEG_Msk (0x4UL) /*!< RXNEG (Bitfield-Mask: 0x01) */
#define MSPI_MSPICFG_RXCAP_Pos (1UL) /*!< RXCAP (Bit 1) */
#define MSPI_MSPICFG_RXCAP_Msk (0x2UL) /*!< RXCAP (Bitfield-Mask: 0x01) */
#define MSPI_MSPICFG_APBCLK_Pos (0UL) /*!< APBCLK (Bit 0) */
#define MSPI_MSPICFG_APBCLK_Msk (0x1UL) /*!< APBCLK (Bitfield-Mask: 0x01) */
/* ======================================================== PADCFG ========================================================= */
#define MSPI_PADCFG_REVCS_Pos (21UL) /*!< REVCS (Bit 21) */
#define MSPI_PADCFG_REVCS_Msk (0x200000UL) /*!< REVCS (Bitfield-Mask: 0x01) */
#define MSPI_PADCFG_IN3_Pos (20UL) /*!< IN3 (Bit 20) */
#define MSPI_PADCFG_IN3_Msk (0x100000UL) /*!< IN3 (Bitfield-Mask: 0x01) */
#define MSPI_PADCFG_IN2_Pos (19UL) /*!< IN2 (Bit 19) */
#define MSPI_PADCFG_IN2_Msk (0x80000UL) /*!< IN2 (Bitfield-Mask: 0x01) */
#define MSPI_PADCFG_IN1_Pos (18UL) /*!< IN1 (Bit 18) */
#define MSPI_PADCFG_IN1_Msk (0x40000UL) /*!< IN1 (Bitfield-Mask: 0x01) */
#define MSPI_PADCFG_IN0_Pos (16UL) /*!< IN0 (Bit 16) */
#define MSPI_PADCFG_IN0_Msk (0x30000UL) /*!< IN0 (Bitfield-Mask: 0x03) */
#define MSPI_PADCFG_OUT7_Pos (4UL) /*!< OUT7 (Bit 4) */
#define MSPI_PADCFG_OUT7_Msk (0x10UL) /*!< OUT7 (Bitfield-Mask: 0x01) */
#define MSPI_PADCFG_OUT6_Pos (3UL) /*!< OUT6 (Bit 3) */
#define MSPI_PADCFG_OUT6_Msk (0x8UL) /*!< OUT6 (Bitfield-Mask: 0x01) */
#define MSPI_PADCFG_OUT5_Pos (2UL) /*!< OUT5 (Bit 2) */
#define MSPI_PADCFG_OUT5_Msk (0x4UL) /*!< OUT5 (Bitfield-Mask: 0x01) */
#define MSPI_PADCFG_OUT4_Pos (1UL) /*!< OUT4 (Bit 1) */
#define MSPI_PADCFG_OUT4_Msk (0x2UL) /*!< OUT4 (Bitfield-Mask: 0x01) */
#define MSPI_PADCFG_OUT3_Pos (0UL) /*!< OUT3 (Bit 0) */
#define MSPI_PADCFG_OUT3_Msk (0x1UL) /*!< OUT3 (Bitfield-Mask: 0x01) */
/* ======================================================= PADOUTEN ======================================================== */
#define MSPI_PADOUTEN_OUTEN_Pos (0UL) /*!< OUTEN (Bit 0) */
#define MSPI_PADOUTEN_OUTEN_Msk (0x1ffUL) /*!< OUTEN (Bitfield-Mask: 0x1ff) */
/* ========================================================= FLASH ========================================================= */
#define MSPI_FLASH_READINSTR_Pos (24UL) /*!< READINSTR (Bit 24) */
#define MSPI_FLASH_READINSTR_Msk (0xff000000UL) /*!< READINSTR (Bitfield-Mask: 0xff) */
#define MSPI_FLASH_WRITEINSTR_Pos (16UL) /*!< WRITEINSTR (Bit 16) */
#define MSPI_FLASH_WRITEINSTR_Msk (0xff0000UL) /*!< WRITEINSTR (Bitfield-Mask: 0xff) */
#define MSPI_FLASH_XIPMIXED_Pos (8UL) /*!< XIPMIXED (Bit 8) */
#define MSPI_FLASH_XIPMIXED_Msk (0x700UL) /*!< XIPMIXED (Bitfield-Mask: 0x07) */
#define MSPI_FLASH_XIPSENDI_Pos (7UL) /*!< XIPSENDI (Bit 7) */
#define MSPI_FLASH_XIPSENDI_Msk (0x80UL) /*!< XIPSENDI (Bitfield-Mask: 0x01) */
#define MSPI_FLASH_XIPSENDA_Pos (6UL) /*!< XIPSENDA (Bit 6) */
#define MSPI_FLASH_XIPSENDA_Msk (0x40UL) /*!< XIPSENDA (Bitfield-Mask: 0x01) */
#define MSPI_FLASH_XIPENTURN_Pos (5UL) /*!< XIPENTURN (Bit 5) */
#define MSPI_FLASH_XIPENTURN_Msk (0x20UL) /*!< XIPENTURN (Bitfield-Mask: 0x01) */
#define MSPI_FLASH_XIPBIGENDIAN_Pos (4UL) /*!< XIPBIGENDIAN (Bit 4) */
#define MSPI_FLASH_XIPBIGENDIAN_Msk (0x10UL) /*!< XIPBIGENDIAN (Bitfield-Mask: 0x01) */
#define MSPI_FLASH_XIPACK_Pos (2UL) /*!< XIPACK (Bit 2) */
#define MSPI_FLASH_XIPACK_Msk (0xcUL) /*!< XIPACK (Bitfield-Mask: 0x03) */
#define MSPI_FLASH_XIPEN_Pos (0UL) /*!< XIPEN (Bit 0) */
#define MSPI_FLASH_XIPEN_Msk (0x1UL) /*!< XIPEN (Bitfield-Mask: 0x01) */
/* ====================================================== SCRAMBLING ======================================================= */
#define MSPI_SCRAMBLING_SCRENABLE_Pos (31UL) /*!< SCRENABLE (Bit 31) */
#define MSPI_SCRAMBLING_SCRENABLE_Msk (0x80000000UL) /*!< SCRENABLE (Bitfield-Mask: 0x01) */
#define MSPI_SCRAMBLING_SCREND_Pos (16UL) /*!< SCREND (Bit 16) */
#define MSPI_SCRAMBLING_SCREND_Msk (0x3ff0000UL) /*!< SCREND (Bitfield-Mask: 0x3ff) */
#define MSPI_SCRAMBLING_SCRSTART_Pos (0UL) /*!< SCRSTART (Bit 0) */
#define MSPI_SCRAMBLING_SCRSTART_Msk (0x3ffUL) /*!< SCRSTART (Bitfield-Mask: 0x3ff) */
/* ========================================================= INTEN ========================================================= */
#define MSPI_INTEN_SCRERR_Pos (12UL) /*!< SCRERR (Bit 12) */
#define MSPI_INTEN_SCRERR_Msk (0x1000UL) /*!< SCRERR (Bitfield-Mask: 0x01) */
#define MSPI_INTEN_CQERR_Pos (11UL) /*!< CQERR (Bit 11) */
#define MSPI_INTEN_CQERR_Msk (0x800UL) /*!< CQERR (Bitfield-Mask: 0x01) */
#define MSPI_INTEN_CQPAUSED_Pos (10UL) /*!< CQPAUSED (Bit 10) */
#define MSPI_INTEN_CQPAUSED_Msk (0x400UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */
#define MSPI_INTEN_CQUPD_Pos (9UL) /*!< CQUPD (Bit 9) */
#define MSPI_INTEN_CQUPD_Msk (0x200UL) /*!< CQUPD (Bitfield-Mask: 0x01) */
#define MSPI_INTEN_CQCMP_Pos (8UL) /*!< CQCMP (Bit 8) */
#define MSPI_INTEN_CQCMP_Msk (0x100UL) /*!< CQCMP (Bitfield-Mask: 0x01) */
#define MSPI_INTEN_DERR_Pos (7UL) /*!< DERR (Bit 7) */
#define MSPI_INTEN_DERR_Msk (0x80UL) /*!< DERR (Bitfield-Mask: 0x01) */
#define MSPI_INTEN_DCMP_Pos (6UL) /*!< DCMP (Bit 6) */
#define MSPI_INTEN_DCMP_Msk (0x40UL) /*!< DCMP (Bitfield-Mask: 0x01) */
#define MSPI_INTEN_RXF_Pos (5UL) /*!< RXF (Bit 5) */
#define MSPI_INTEN_RXF_Msk (0x20UL) /*!< RXF (Bitfield-Mask: 0x01) */
#define MSPI_INTEN_RXO_Pos (4UL) /*!< RXO (Bit 4) */
#define MSPI_INTEN_RXO_Msk (0x10UL) /*!< RXO (Bitfield-Mask: 0x01) */
#define MSPI_INTEN_RXU_Pos (3UL) /*!< RXU (Bit 3) */
#define MSPI_INTEN_RXU_Msk (0x8UL) /*!< RXU (Bitfield-Mask: 0x01) */
#define MSPI_INTEN_TXO_Pos (2UL) /*!< TXO (Bit 2) */
#define MSPI_INTEN_TXO_Msk (0x4UL) /*!< TXO (Bitfield-Mask: 0x01) */
#define MSPI_INTEN_TXE_Pos (1UL) /*!< TXE (Bit 1) */
#define MSPI_INTEN_TXE_Msk (0x2UL) /*!< TXE (Bitfield-Mask: 0x01) */
#define MSPI_INTEN_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */
#define MSPI_INTEN_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */
/* ======================================================== INTSTAT ======================================================== */
#define MSPI_INTSTAT_SCRERR_Pos (12UL) /*!< SCRERR (Bit 12) */
#define MSPI_INTSTAT_SCRERR_Msk (0x1000UL) /*!< SCRERR (Bitfield-Mask: 0x01) */
#define MSPI_INTSTAT_CQERR_Pos (11UL) /*!< CQERR (Bit 11) */
#define MSPI_INTSTAT_CQERR_Msk (0x800UL) /*!< CQERR (Bitfield-Mask: 0x01) */
#define MSPI_INTSTAT_CQPAUSED_Pos (10UL) /*!< CQPAUSED (Bit 10) */
#define MSPI_INTSTAT_CQPAUSED_Msk (0x400UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */
#define MSPI_INTSTAT_CQUPD_Pos (9UL) /*!< CQUPD (Bit 9) */
#define MSPI_INTSTAT_CQUPD_Msk (0x200UL) /*!< CQUPD (Bitfield-Mask: 0x01) */
#define MSPI_INTSTAT_CQCMP_Pos (8UL) /*!< CQCMP (Bit 8) */
#define MSPI_INTSTAT_CQCMP_Msk (0x100UL) /*!< CQCMP (Bitfield-Mask: 0x01) */
#define MSPI_INTSTAT_DERR_Pos (7UL) /*!< DERR (Bit 7) */
#define MSPI_INTSTAT_DERR_Msk (0x80UL) /*!< DERR (Bitfield-Mask: 0x01) */
#define MSPI_INTSTAT_DCMP_Pos (6UL) /*!< DCMP (Bit 6) */
#define MSPI_INTSTAT_DCMP_Msk (0x40UL) /*!< DCMP (Bitfield-Mask: 0x01) */
#define MSPI_INTSTAT_RXF_Pos (5UL) /*!< RXF (Bit 5) */
#define MSPI_INTSTAT_RXF_Msk (0x20UL) /*!< RXF (Bitfield-Mask: 0x01) */
#define MSPI_INTSTAT_RXO_Pos (4UL) /*!< RXO (Bit 4) */
#define MSPI_INTSTAT_RXO_Msk (0x10UL) /*!< RXO (Bitfield-Mask: 0x01) */
#define MSPI_INTSTAT_RXU_Pos (3UL) /*!< RXU (Bit 3) */
#define MSPI_INTSTAT_RXU_Msk (0x8UL) /*!< RXU (Bitfield-Mask: 0x01) */
#define MSPI_INTSTAT_TXO_Pos (2UL) /*!< TXO (Bit 2) */
#define MSPI_INTSTAT_TXO_Msk (0x4UL) /*!< TXO (Bitfield-Mask: 0x01) */
#define MSPI_INTSTAT_TXE_Pos (1UL) /*!< TXE (Bit 1) */
#define MSPI_INTSTAT_TXE_Msk (0x2UL) /*!< TXE (Bitfield-Mask: 0x01) */
#define MSPI_INTSTAT_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */
#define MSPI_INTSTAT_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */
/* ======================================================== INTCLR ========================================================= */
#define MSPI_INTCLR_SCRERR_Pos (12UL) /*!< SCRERR (Bit 12) */
#define MSPI_INTCLR_SCRERR_Msk (0x1000UL) /*!< SCRERR (Bitfield-Mask: 0x01) */
#define MSPI_INTCLR_CQERR_Pos (11UL) /*!< CQERR (Bit 11) */
#define MSPI_INTCLR_CQERR_Msk (0x800UL) /*!< CQERR (Bitfield-Mask: 0x01) */
#define MSPI_INTCLR_CQPAUSED_Pos (10UL) /*!< CQPAUSED (Bit 10) */
#define MSPI_INTCLR_CQPAUSED_Msk (0x400UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */
#define MSPI_INTCLR_CQUPD_Pos (9UL) /*!< CQUPD (Bit 9) */
#define MSPI_INTCLR_CQUPD_Msk (0x200UL) /*!< CQUPD (Bitfield-Mask: 0x01) */
#define MSPI_INTCLR_CQCMP_Pos (8UL) /*!< CQCMP (Bit 8) */
#define MSPI_INTCLR_CQCMP_Msk (0x100UL) /*!< CQCMP (Bitfield-Mask: 0x01) */
#define MSPI_INTCLR_DERR_Pos (7UL) /*!< DERR (Bit 7) */
#define MSPI_INTCLR_DERR_Msk (0x80UL) /*!< DERR (Bitfield-Mask: 0x01) */
#define MSPI_INTCLR_DCMP_Pos (6UL) /*!< DCMP (Bit 6) */
#define MSPI_INTCLR_DCMP_Msk (0x40UL) /*!< DCMP (Bitfield-Mask: 0x01) */
#define MSPI_INTCLR_RXF_Pos (5UL) /*!< RXF (Bit 5) */
#define MSPI_INTCLR_RXF_Msk (0x20UL) /*!< RXF (Bitfield-Mask: 0x01) */
#define MSPI_INTCLR_RXO_Pos (4UL) /*!< RXO (Bit 4) */
#define MSPI_INTCLR_RXO_Msk (0x10UL) /*!< RXO (Bitfield-Mask: 0x01) */
#define MSPI_INTCLR_RXU_Pos (3UL) /*!< RXU (Bit 3) */
#define MSPI_INTCLR_RXU_Msk (0x8UL) /*!< RXU (Bitfield-Mask: 0x01) */
#define MSPI_INTCLR_TXO_Pos (2UL) /*!< TXO (Bit 2) */
#define MSPI_INTCLR_TXO_Msk (0x4UL) /*!< TXO (Bitfield-Mask: 0x01) */
#define MSPI_INTCLR_TXE_Pos (1UL) /*!< TXE (Bit 1) */
#define MSPI_INTCLR_TXE_Msk (0x2UL) /*!< TXE (Bitfield-Mask: 0x01) */
#define MSPI_INTCLR_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */
#define MSPI_INTCLR_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */
/* ======================================================== INTSET ========================================================= */
#define MSPI_INTSET_SCRERR_Pos (12UL) /*!< SCRERR (Bit 12) */
#define MSPI_INTSET_SCRERR_Msk (0x1000UL) /*!< SCRERR (Bitfield-Mask: 0x01) */
#define MSPI_INTSET_CQERR_Pos (11UL) /*!< CQERR (Bit 11) */
#define MSPI_INTSET_CQERR_Msk (0x800UL) /*!< CQERR (Bitfield-Mask: 0x01) */
#define MSPI_INTSET_CQPAUSED_Pos (10UL) /*!< CQPAUSED (Bit 10) */
#define MSPI_INTSET_CQPAUSED_Msk (0x400UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */
#define MSPI_INTSET_CQUPD_Pos (9UL) /*!< CQUPD (Bit 9) */
#define MSPI_INTSET_CQUPD_Msk (0x200UL) /*!< CQUPD (Bitfield-Mask: 0x01) */
#define MSPI_INTSET_CQCMP_Pos (8UL) /*!< CQCMP (Bit 8) */
#define MSPI_INTSET_CQCMP_Msk (0x100UL) /*!< CQCMP (Bitfield-Mask: 0x01) */
#define MSPI_INTSET_DERR_Pos (7UL) /*!< DERR (Bit 7) */
#define MSPI_INTSET_DERR_Msk (0x80UL) /*!< DERR (Bitfield-Mask: 0x01) */
#define MSPI_INTSET_DCMP_Pos (6UL) /*!< DCMP (Bit 6) */
#define MSPI_INTSET_DCMP_Msk (0x40UL) /*!< DCMP (Bitfield-Mask: 0x01) */
#define MSPI_INTSET_RXF_Pos (5UL) /*!< RXF (Bit 5) */
#define MSPI_INTSET_RXF_Msk (0x20UL) /*!< RXF (Bitfield-Mask: 0x01) */
#define MSPI_INTSET_RXO_Pos (4UL) /*!< RXO (Bit 4) */
#define MSPI_INTSET_RXO_Msk (0x10UL) /*!< RXO (Bitfield-Mask: 0x01) */
#define MSPI_INTSET_RXU_Pos (3UL) /*!< RXU (Bit 3) */
#define MSPI_INTSET_RXU_Msk (0x8UL) /*!< RXU (Bitfield-Mask: 0x01) */
#define MSPI_INTSET_TXO_Pos (2UL) /*!< TXO (Bit 2) */
#define MSPI_INTSET_TXO_Msk (0x4UL) /*!< TXO (Bitfield-Mask: 0x01) */
#define MSPI_INTSET_TXE_Pos (1UL) /*!< TXE (Bit 1) */
#define MSPI_INTSET_TXE_Msk (0x2UL) /*!< TXE (Bitfield-Mask: 0x01) */
#define MSPI_INTSET_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */
#define MSPI_INTSET_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */
/* ======================================================== DMACFG ========================================================= */
#define MSPI_DMACFG_DMAPWROFF_Pos (18UL) /*!< DMAPWROFF (Bit 18) */
#define MSPI_DMACFG_DMAPWROFF_Msk (0x40000UL) /*!< DMAPWROFF (Bitfield-Mask: 0x01) */
#define MSPI_DMACFG_DMAPRI_Pos (3UL) /*!< DMAPRI (Bit 3) */
#define MSPI_DMACFG_DMAPRI_Msk (0x18UL) /*!< DMAPRI (Bitfield-Mask: 0x03) */
#define MSPI_DMACFG_DMADIR_Pos (2UL) /*!< DMADIR (Bit 2) */
#define MSPI_DMACFG_DMADIR_Msk (0x4UL) /*!< DMADIR (Bitfield-Mask: 0x01) */
#define MSPI_DMACFG_DMAEN_Pos (0UL) /*!< DMAEN (Bit 0) */
#define MSPI_DMACFG_DMAEN_Msk (0x3UL) /*!< DMAEN (Bitfield-Mask: 0x03) */
/* ======================================================== DMASTAT ======================================================== */
#define MSPI_DMASTAT_SCRERR_Pos (3UL) /*!< SCRERR (Bit 3) */
#define MSPI_DMASTAT_SCRERR_Msk (0x8UL) /*!< SCRERR (Bitfield-Mask: 0x01) */
#define MSPI_DMASTAT_DMAERR_Pos (2UL) /*!< DMAERR (Bit 2) */
#define MSPI_DMASTAT_DMAERR_Msk (0x4UL) /*!< DMAERR (Bitfield-Mask: 0x01) */
#define MSPI_DMASTAT_DMACPL_Pos (1UL) /*!< DMACPL (Bit 1) */
#define MSPI_DMASTAT_DMACPL_Msk (0x2UL) /*!< DMACPL (Bitfield-Mask: 0x01) */
#define MSPI_DMASTAT_DMATIP_Pos (0UL) /*!< DMATIP (Bit 0) */
#define MSPI_DMASTAT_DMATIP_Msk (0x1UL) /*!< DMATIP (Bitfield-Mask: 0x01) */
/* ====================================================== DMATARGADDR ====================================================== */
#define MSPI_DMATARGADDR_TARGADDR_Pos (0UL) /*!< TARGADDR (Bit 0) */
#define MSPI_DMATARGADDR_TARGADDR_Msk (0xffffffffUL) /*!< TARGADDR (Bitfield-Mask: 0xffffffff) */
/* ====================================================== DMADEVADDR ======================================================= */
#define MSPI_DMADEVADDR_DEVADDR_Pos (0UL) /*!< DEVADDR (Bit 0) */
#define MSPI_DMADEVADDR_DEVADDR_Msk (0xffffffffUL) /*!< DEVADDR (Bitfield-Mask: 0xffffffff) */
/* ====================================================== DMATOTCOUNT ====================================================== */
#define MSPI_DMATOTCOUNT_TOTCOUNT_Pos (0UL) /*!< TOTCOUNT (Bit 0) */
#define MSPI_DMATOTCOUNT_TOTCOUNT_Msk (0xffffUL) /*!< TOTCOUNT (Bitfield-Mask: 0xffff) */
/* ======================================================= DMABCOUNT ======================================================= */
#define MSPI_DMABCOUNT_BCOUNT_Pos (0UL) /*!< BCOUNT (Bit 0) */
#define MSPI_DMABCOUNT_BCOUNT_Msk (0xffUL) /*!< BCOUNT (Bitfield-Mask: 0xff) */
/* ======================================================= DMATHRESH ======================================================= */
#define MSPI_DMATHRESH_DMATHRESH_Pos (0UL) /*!< DMATHRESH (Bit 0) */
#define MSPI_DMATHRESH_DMATHRESH_Msk (0xfUL) /*!< DMATHRESH (Bitfield-Mask: 0x0f) */
/* ========================================================= CQCFG ========================================================= */
#define MSPI_CQCFG_CQAUTOCLEARMASK_Pos (3UL) /*!< CQAUTOCLEARMASK (Bit 3) */
#define MSPI_CQCFG_CQAUTOCLEARMASK_Msk (0x8UL) /*!< CQAUTOCLEARMASK (Bitfield-Mask: 0x01) */
#define MSPI_CQCFG_CQPWROFF_Pos (2UL) /*!< CQPWROFF (Bit 2) */
#define MSPI_CQCFG_CQPWROFF_Msk (0x4UL) /*!< CQPWROFF (Bitfield-Mask: 0x01) */
#define MSPI_CQCFG_CQPRI_Pos (1UL) /*!< CQPRI (Bit 1) */
#define MSPI_CQCFG_CQPRI_Msk (0x2UL) /*!< CQPRI (Bitfield-Mask: 0x01) */
#define MSPI_CQCFG_CQEN_Pos (0UL) /*!< CQEN (Bit 0) */
#define MSPI_CQCFG_CQEN_Msk (0x1UL) /*!< CQEN (Bitfield-Mask: 0x01) */
/* ======================================================== CQADDR ========================================================= */
#define MSPI_CQADDR_CQADDR_Pos (0UL) /*!< CQADDR (Bit 0) */
#define MSPI_CQADDR_CQADDR_Msk (0x1fffffffUL) /*!< CQADDR (Bitfield-Mask: 0x1fffffff) */
/* ======================================================== CQSTAT ========================================================= */
#define MSPI_CQSTAT_CQPAUSED_Pos (3UL) /*!< CQPAUSED (Bit 3) */
#define MSPI_CQSTAT_CQPAUSED_Msk (0x8UL) /*!< CQPAUSED (Bitfield-Mask: 0x01) */
#define MSPI_CQSTAT_CQERR_Pos (2UL) /*!< CQERR (Bit 2) */
#define MSPI_CQSTAT_CQERR_Msk (0x4UL) /*!< CQERR (Bitfield-Mask: 0x01) */
#define MSPI_CQSTAT_CQCPL_Pos (1UL) /*!< CQCPL (Bit 1) */
#define MSPI_CQSTAT_CQCPL_Msk (0x2UL) /*!< CQCPL (Bitfield-Mask: 0x01) */
#define MSPI_CQSTAT_CQTIP_Pos (0UL) /*!< CQTIP (Bit 0) */
#define MSPI_CQSTAT_CQTIP_Msk (0x1UL) /*!< CQTIP (Bitfield-Mask: 0x01) */
/* ======================================================== CQFLAGS ======================================================== */
#define MSPI_CQFLAGS_CQFLAGS_Pos (0UL) /*!< CQFLAGS (Bit 0) */
#define MSPI_CQFLAGS_CQFLAGS_Msk (0xffffUL) /*!< CQFLAGS (Bitfield-Mask: 0xffff) */
/* ====================================================== CQSETCLEAR ======================================================= */
#define MSPI_CQSETCLEAR_CQFCLR_Pos (16UL) /*!< CQFCLR (Bit 16) */
#define MSPI_CQSETCLEAR_CQFCLR_Msk (0xff0000UL) /*!< CQFCLR (Bitfield-Mask: 0xff) */
#define MSPI_CQSETCLEAR_CQFTOGGLE_Pos (8UL) /*!< CQFTOGGLE (Bit 8) */
#define MSPI_CQSETCLEAR_CQFTOGGLE_Msk (0xff00UL) /*!< CQFTOGGLE (Bitfield-Mask: 0xff) */
#define MSPI_CQSETCLEAR_CQFSET_Pos (0UL) /*!< CQFSET (Bit 0) */
#define MSPI_CQSETCLEAR_CQFSET_Msk (0xffUL) /*!< CQFSET (Bitfield-Mask: 0xff) */
/* ======================================================== CQPAUSE ======================================================== */
#define MSPI_CQPAUSE_CQMASK_Pos (0UL) /*!< CQMASK (Bit 0) */
#define MSPI_CQPAUSE_CQMASK_Msk (0xffffUL) /*!< CQMASK (Bitfield-Mask: 0xffff) */
/* ======================================================= CQCURIDX ======================================================== */
#define MSPI_CQCURIDX_CQCURIDX_Pos (0UL) /*!< CQCURIDX (Bit 0) */
#define MSPI_CQCURIDX_CQCURIDX_Msk (0xffUL) /*!< CQCURIDX (Bitfield-Mask: 0xff) */
/* ======================================================= CQENDIDX ======================================================== */
#define MSPI_CQENDIDX_CQENDIDX_Pos (0UL) /*!< CQENDIDX (Bit 0) */
#define MSPI_CQENDIDX_CQENDIDX_Msk (0xffUL) /*!< CQENDIDX (Bitfield-Mask: 0xff) */
/* =========================================================================================================================== */
/* ================ PDM ================ */
/* =========================================================================================================================== */
/* ========================================================= PCFG ========================================================== */
#define PDM_PCFG_LRSWAP_Pos (31UL) /*!< LRSWAP (Bit 31) */
#define PDM_PCFG_LRSWAP_Msk (0x80000000UL) /*!< LRSWAP (Bitfield-Mask: 0x01) */
#define PDM_PCFG_PGARIGHT_Pos (26UL) /*!< PGARIGHT (Bit 26) */
#define PDM_PCFG_PGARIGHT_Msk (0x7c000000UL) /*!< PGARIGHT (Bitfield-Mask: 0x1f) */
#define PDM_PCFG_PGALEFT_Pos (21UL) /*!< PGALEFT (Bit 21) */
#define PDM_PCFG_PGALEFT_Msk (0x3e00000UL) /*!< PGALEFT (Bitfield-Mask: 0x1f) */
#define PDM_PCFG_MCLKDIV_Pos (17UL) /*!< MCLKDIV (Bit 17) */
#define PDM_PCFG_MCLKDIV_Msk (0x60000UL) /*!< MCLKDIV (Bitfield-Mask: 0x03) */
#define PDM_PCFG_SINCRATE_Pos (10UL) /*!< SINCRATE (Bit 10) */
#define PDM_PCFG_SINCRATE_Msk (0x1fc00UL) /*!< SINCRATE (Bitfield-Mask: 0x7f) */
#define PDM_PCFG_ADCHPD_Pos (9UL) /*!< ADCHPD (Bit 9) */
#define PDM_PCFG_ADCHPD_Msk (0x200UL) /*!< ADCHPD (Bitfield-Mask: 0x01) */
#define PDM_PCFG_HPCUTOFF_Pos (5UL) /*!< HPCUTOFF (Bit 5) */
#define PDM_PCFG_HPCUTOFF_Msk (0x1e0UL) /*!< HPCUTOFF (Bitfield-Mask: 0x0f) */
#define PDM_PCFG_CYCLES_Pos (2UL) /*!< CYCLES (Bit 2) */
#define PDM_PCFG_CYCLES_Msk (0x1cUL) /*!< CYCLES (Bitfield-Mask: 0x07) */
#define PDM_PCFG_SOFTMUTE_Pos (1UL) /*!< SOFTMUTE (Bit 1) */
#define PDM_PCFG_SOFTMUTE_Msk (0x2UL) /*!< SOFTMUTE (Bitfield-Mask: 0x01) */
#define PDM_PCFG_PDMCOREEN_Pos (0UL) /*!< PDMCOREEN (Bit 0) */
#define PDM_PCFG_PDMCOREEN_Msk (0x1UL) /*!< PDMCOREEN (Bitfield-Mask: 0x01) */
/* ========================================================= VCFG ========================================================== */
#define PDM_VCFG_IOCLKEN_Pos (31UL) /*!< IOCLKEN (Bit 31) */
#define PDM_VCFG_IOCLKEN_Msk (0x80000000UL) /*!< IOCLKEN (Bitfield-Mask: 0x01) */
#define PDM_VCFG_RSTB_Pos (30UL) /*!< RSTB (Bit 30) */
#define PDM_VCFG_RSTB_Msk (0x40000000UL) /*!< RSTB (Bitfield-Mask: 0x01) */
#define PDM_VCFG_PDMCLKSEL_Pos (27UL) /*!< PDMCLKSEL (Bit 27) */
#define PDM_VCFG_PDMCLKSEL_Msk (0x38000000UL) /*!< PDMCLKSEL (Bitfield-Mask: 0x07) */
#define PDM_VCFG_PDMCLKEN_Pos (26UL) /*!< PDMCLKEN (Bit 26) */
#define PDM_VCFG_PDMCLKEN_Msk (0x4000000UL) /*!< PDMCLKEN (Bitfield-Mask: 0x01) */
#define PDM_VCFG_I2SEN_Pos (20UL) /*!< I2SEN (Bit 20) */
#define PDM_VCFG_I2SEN_Msk (0x100000UL) /*!< I2SEN (Bitfield-Mask: 0x01) */
#define PDM_VCFG_BCLKINV_Pos (19UL) /*!< BCLKINV (Bit 19) */
#define PDM_VCFG_BCLKINV_Msk (0x80000UL) /*!< BCLKINV (Bitfield-Mask: 0x01) */
#define PDM_VCFG_DMICKDEL_Pos (17UL) /*!< DMICKDEL (Bit 17) */
#define PDM_VCFG_DMICKDEL_Msk (0x20000UL) /*!< DMICKDEL (Bitfield-Mask: 0x01) */
#define PDM_VCFG_SELAP_Pos (16UL) /*!< SELAP (Bit 16) */
#define PDM_VCFG_SELAP_Msk (0x10000UL) /*!< SELAP (Bitfield-Mask: 0x01) */
#define PDM_VCFG_PCMPACK_Pos (8UL) /*!< PCMPACK (Bit 8) */
#define PDM_VCFG_PCMPACK_Msk (0x100UL) /*!< PCMPACK (Bitfield-Mask: 0x01) */
#define PDM_VCFG_CHSET_Pos (3UL) /*!< CHSET (Bit 3) */
#define PDM_VCFG_CHSET_Msk (0x18UL) /*!< CHSET (Bitfield-Mask: 0x03) */
/* ======================================================= VOICESTAT ======================================================= */
#define PDM_VOICESTAT_FIFOCNT_Pos (0UL) /*!< FIFOCNT (Bit 0) */
#define PDM_VOICESTAT_FIFOCNT_Msk (0x3fUL) /*!< FIFOCNT (Bitfield-Mask: 0x3f) */
/* ======================================================= FIFOREAD ======================================================== */
#define PDM_FIFOREAD_FIFOREAD_Pos (0UL) /*!< FIFOREAD (Bit 0) */
#define PDM_FIFOREAD_FIFOREAD_Msk (0xffffffffUL) /*!< FIFOREAD (Bitfield-Mask: 0xffffffff) */
/* ======================================================= FIFOFLUSH ======================================================= */
#define PDM_FIFOFLUSH_FIFOFLUSH_Pos (0UL) /*!< FIFOFLUSH (Bit 0) */
#define PDM_FIFOFLUSH_FIFOFLUSH_Msk (0x1UL) /*!< FIFOFLUSH (Bitfield-Mask: 0x01) */
/* ======================================================== FIFOTHR ======================================================== */
#define PDM_FIFOTHR_FIFOTHR_Pos (0UL) /*!< FIFOTHR (Bit 0) */
#define PDM_FIFOTHR_FIFOTHR_Msk (0x1fUL) /*!< FIFOTHR (Bitfield-Mask: 0x1f) */
/* ========================================================= INTEN ========================================================= */
#define PDM_INTEN_DERR_Pos (4UL) /*!< DERR (Bit 4) */
#define PDM_INTEN_DERR_Msk (0x10UL) /*!< DERR (Bitfield-Mask: 0x01) */
#define PDM_INTEN_DCMP_Pos (3UL) /*!< DCMP (Bit 3) */
#define PDM_INTEN_DCMP_Msk (0x8UL) /*!< DCMP (Bitfield-Mask: 0x01) */
#define PDM_INTEN_UNDFL_Pos (2UL) /*!< UNDFL (Bit 2) */
#define PDM_INTEN_UNDFL_Msk (0x4UL) /*!< UNDFL (Bitfield-Mask: 0x01) */
#define PDM_INTEN_OVF_Pos (1UL) /*!< OVF (Bit 1) */
#define PDM_INTEN_OVF_Msk (0x2UL) /*!< OVF (Bitfield-Mask: 0x01) */
#define PDM_INTEN_THR_Pos (0UL) /*!< THR (Bit 0) */
#define PDM_INTEN_THR_Msk (0x1UL) /*!< THR (Bitfield-Mask: 0x01) */
/* ======================================================== INTSTAT ======================================================== */
#define PDM_INTSTAT_DERR_Pos (4UL) /*!< DERR (Bit 4) */
#define PDM_INTSTAT_DERR_Msk (0x10UL) /*!< DERR (Bitfield-Mask: 0x01) */
#define PDM_INTSTAT_DCMP_Pos (3UL) /*!< DCMP (Bit 3) */
#define PDM_INTSTAT_DCMP_Msk (0x8UL) /*!< DCMP (Bitfield-Mask: 0x01) */
#define PDM_INTSTAT_UNDFL_Pos (2UL) /*!< UNDFL (Bit 2) */
#define PDM_INTSTAT_UNDFL_Msk (0x4UL) /*!< UNDFL (Bitfield-Mask: 0x01) */
#define PDM_INTSTAT_OVF_Pos (1UL) /*!< OVF (Bit 1) */
#define PDM_INTSTAT_OVF_Msk (0x2UL) /*!< OVF (Bitfield-Mask: 0x01) */
#define PDM_INTSTAT_THR_Pos (0UL) /*!< THR (Bit 0) */
#define PDM_INTSTAT_THR_Msk (0x1UL) /*!< THR (Bitfield-Mask: 0x01) */
/* ======================================================== INTCLR ========================================================= */
#define PDM_INTCLR_DERR_Pos (4UL) /*!< DERR (Bit 4) */
#define PDM_INTCLR_DERR_Msk (0x10UL) /*!< DERR (Bitfield-Mask: 0x01) */
#define PDM_INTCLR_DCMP_Pos (3UL) /*!< DCMP (Bit 3) */
#define PDM_INTCLR_DCMP_Msk (0x8UL) /*!< DCMP (Bitfield-Mask: 0x01) */
#define PDM_INTCLR_UNDFL_Pos (2UL) /*!< UNDFL (Bit 2) */
#define PDM_INTCLR_UNDFL_Msk (0x4UL) /*!< UNDFL (Bitfield-Mask: 0x01) */
#define PDM_INTCLR_OVF_Pos (1UL) /*!< OVF (Bit 1) */
#define PDM_INTCLR_OVF_Msk (0x2UL) /*!< OVF (Bitfield-Mask: 0x01) */
#define PDM_INTCLR_THR_Pos (0UL) /*!< THR (Bit 0) */
#define PDM_INTCLR_THR_Msk (0x1UL) /*!< THR (Bitfield-Mask: 0x01) */
/* ======================================================== INTSET ========================================================= */
#define PDM_INTSET_DERR_Pos (4UL) /*!< DERR (Bit 4) */
#define PDM_INTSET_DERR_Msk (0x10UL) /*!< DERR (Bitfield-Mask: 0x01) */
#define PDM_INTSET_DCMP_Pos (3UL) /*!< DCMP (Bit 3) */
#define PDM_INTSET_DCMP_Msk (0x8UL) /*!< DCMP (Bitfield-Mask: 0x01) */
#define PDM_INTSET_UNDFL_Pos (2UL) /*!< UNDFL (Bit 2) */
#define PDM_INTSET_UNDFL_Msk (0x4UL) /*!< UNDFL (Bitfield-Mask: 0x01) */
#define PDM_INTSET_OVF_Pos (1UL) /*!< OVF (Bit 1) */
#define PDM_INTSET_OVF_Msk (0x2UL) /*!< OVF (Bitfield-Mask: 0x01) */
#define PDM_INTSET_THR_Pos (0UL) /*!< THR (Bit 0) */
#define PDM_INTSET_THR_Msk (0x1UL) /*!< THR (Bitfield-Mask: 0x01) */
/* ======================================================= DMATRIGEN ======================================================= */
#define PDM_DMATRIGEN_DTHR90_Pos (1UL) /*!< DTHR90 (Bit 1) */
#define PDM_DMATRIGEN_DTHR90_Msk (0x2UL) /*!< DTHR90 (Bitfield-Mask: 0x01) */
#define PDM_DMATRIGEN_DTHR_Pos (0UL) /*!< DTHR (Bit 0) */
#define PDM_DMATRIGEN_DTHR_Msk (0x1UL) /*!< DTHR (Bitfield-Mask: 0x01) */
/* ====================================================== DMATRIGSTAT ====================================================== */
#define PDM_DMATRIGSTAT_DTHR90STAT_Pos (1UL) /*!< DTHR90STAT (Bit 1) */
#define PDM_DMATRIGSTAT_DTHR90STAT_Msk (0x2UL) /*!< DTHR90STAT (Bitfield-Mask: 0x01) */
#define PDM_DMATRIGSTAT_DTHRSTAT_Pos (0UL) /*!< DTHRSTAT (Bit 0) */
#define PDM_DMATRIGSTAT_DTHRSTAT_Msk (0x1UL) /*!< DTHRSTAT (Bitfield-Mask: 0x01) */
/* ======================================================== DMACFG ========================================================= */
#define PDM_DMACFG_DPWROFF_Pos (10UL) /*!< DPWROFF (Bit 10) */
#define PDM_DMACFG_DPWROFF_Msk (0x400UL) /*!< DPWROFF (Bitfield-Mask: 0x01) */
#define PDM_DMACFG_DAUTOHIP_Pos (9UL) /*!< DAUTOHIP (Bit 9) */
#define PDM_DMACFG_DAUTOHIP_Msk (0x200UL) /*!< DAUTOHIP (Bitfield-Mask: 0x01) */
#define PDM_DMACFG_DMAPRI_Pos (8UL) /*!< DMAPRI (Bit 8) */
#define PDM_DMACFG_DMAPRI_Msk (0x100UL) /*!< DMAPRI (Bitfield-Mask: 0x01) */
#define PDM_DMACFG_DMADIR_Pos (2UL) /*!< DMADIR (Bit 2) */
#define PDM_DMACFG_DMADIR_Msk (0x4UL) /*!< DMADIR (Bitfield-Mask: 0x01) */
#define PDM_DMACFG_DMAEN_Pos (0UL) /*!< DMAEN (Bit 0) */
#define PDM_DMACFG_DMAEN_Msk (0x1UL) /*!< DMAEN (Bitfield-Mask: 0x01) */
/* ====================================================== DMATOTCOUNT ====================================================== */
#define PDM_DMATOTCOUNT_TOTCOUNT_Pos (0UL) /*!< TOTCOUNT (Bit 0) */
#define PDM_DMATOTCOUNT_TOTCOUNT_Msk (0xfffffUL) /*!< TOTCOUNT (Bitfield-Mask: 0xfffff) */
/* ====================================================== DMATARGADDR ====================================================== */
#define PDM_DMATARGADDR_UTARGADDR_Pos (20UL) /*!< UTARGADDR (Bit 20) */
#define PDM_DMATARGADDR_UTARGADDR_Msk (0xfff00000UL) /*!< UTARGADDR (Bitfield-Mask: 0xfff) */
#define PDM_DMATARGADDR_LTARGADDR_Pos (0UL) /*!< LTARGADDR (Bit 0) */
#define PDM_DMATARGADDR_LTARGADDR_Msk (0xfffffUL) /*!< LTARGADDR (Bitfield-Mask: 0xfffff) */
/* ======================================================== DMASTAT ======================================================== */
#define PDM_DMASTAT_DMAERR_Pos (2UL) /*!< DMAERR (Bit 2) */
#define PDM_DMASTAT_DMAERR_Msk (0x4UL) /*!< DMAERR (Bitfield-Mask: 0x01) */
#define PDM_DMASTAT_DMACPL_Pos (1UL) /*!< DMACPL (Bit 1) */
#define PDM_DMASTAT_DMACPL_Msk (0x2UL) /*!< DMACPL (Bitfield-Mask: 0x01) */
#define PDM_DMASTAT_DMATIP_Pos (0UL) /*!< DMATIP (Bit 0) */
#define PDM_DMASTAT_DMATIP_Msk (0x1UL) /*!< DMATIP (Bitfield-Mask: 0x01) */
/* =========================================================================================================================== */
/* ================ PWRCTRL ================ */
/* =========================================================================================================================== */
/* ======================================================= SUPPLYSRC ======================================================= */
#define PWRCTRL_SUPPLYSRC_BLEBUCKEN_Pos (0UL) /*!< BLEBUCKEN (Bit 0) */
#define PWRCTRL_SUPPLYSRC_BLEBUCKEN_Msk (0x1UL) /*!< BLEBUCKEN (Bitfield-Mask: 0x01) */
/* ===================================================== SUPPLYSTATUS ====================================================== */
#define PWRCTRL_SUPPLYSTATUS_BLEBUCKON_Pos (1UL) /*!< BLEBUCKON (Bit 1) */
#define PWRCTRL_SUPPLYSTATUS_BLEBUCKON_Msk (0x2UL) /*!< BLEBUCKON (Bitfield-Mask: 0x01) */
#define PWRCTRL_SUPPLYSTATUS_SIMOBUCKON_Pos (0UL) /*!< SIMOBUCKON (Bit 0) */
#define PWRCTRL_SUPPLYSTATUS_SIMOBUCKON_Msk (0x1UL) /*!< SIMOBUCKON (Bitfield-Mask: 0x01) */
/* ======================================================= DEVPWREN ======================================================== */
#define PWRCTRL_DEVPWREN_PWRBLEL_Pos (13UL) /*!< PWRBLEL (Bit 13) */
#define PWRCTRL_DEVPWREN_PWRBLEL_Msk (0x2000UL) /*!< PWRBLEL (Bitfield-Mask: 0x01) */
#define PWRCTRL_DEVPWREN_PWRPDM_Pos (12UL) /*!< PWRPDM (Bit 12) */
#define PWRCTRL_DEVPWREN_PWRPDM_Msk (0x1000UL) /*!< PWRPDM (Bitfield-Mask: 0x01) */
#define PWRCTRL_DEVPWREN_PWRMSPI_Pos (11UL) /*!< PWRMSPI (Bit 11) */
#define PWRCTRL_DEVPWREN_PWRMSPI_Msk (0x800UL) /*!< PWRMSPI (Bitfield-Mask: 0x01) */
#define PWRCTRL_DEVPWREN_PWRSCARD_Pos (10UL) /*!< PWRSCARD (Bit 10) */
#define PWRCTRL_DEVPWREN_PWRSCARD_Msk (0x400UL) /*!< PWRSCARD (Bitfield-Mask: 0x01) */
#define PWRCTRL_DEVPWREN_PWRADC_Pos (9UL) /*!< PWRADC (Bit 9) */
#define PWRCTRL_DEVPWREN_PWRADC_Msk (0x200UL) /*!< PWRADC (Bitfield-Mask: 0x01) */
#define PWRCTRL_DEVPWREN_PWRUART1_Pos (8UL) /*!< PWRUART1 (Bit 8) */
#define PWRCTRL_DEVPWREN_PWRUART1_Msk (0x100UL) /*!< PWRUART1 (Bitfield-Mask: 0x01) */
#define PWRCTRL_DEVPWREN_PWRUART0_Pos (7UL) /*!< PWRUART0 (Bit 7) */
#define PWRCTRL_DEVPWREN_PWRUART0_Msk (0x80UL) /*!< PWRUART0 (Bitfield-Mask: 0x01) */
#define PWRCTRL_DEVPWREN_PWRIOM5_Pos (6UL) /*!< PWRIOM5 (Bit 6) */
#define PWRCTRL_DEVPWREN_PWRIOM5_Msk (0x40UL) /*!< PWRIOM5 (Bitfield-Mask: 0x01) */
#define PWRCTRL_DEVPWREN_PWRIOM4_Pos (5UL) /*!< PWRIOM4 (Bit 5) */
#define PWRCTRL_DEVPWREN_PWRIOM4_Msk (0x20UL) /*!< PWRIOM4 (Bitfield-Mask: 0x01) */
#define PWRCTRL_DEVPWREN_PWRIOM3_Pos (4UL) /*!< PWRIOM3 (Bit 4) */
#define PWRCTRL_DEVPWREN_PWRIOM3_Msk (0x10UL) /*!< PWRIOM3 (Bitfield-Mask: 0x01) */
#define PWRCTRL_DEVPWREN_PWRIOM2_Pos (3UL) /*!< PWRIOM2 (Bit 3) */
#define PWRCTRL_DEVPWREN_PWRIOM2_Msk (0x8UL) /*!< PWRIOM2 (Bitfield-Mask: 0x01) */
#define PWRCTRL_DEVPWREN_PWRIOM1_Pos (2UL) /*!< PWRIOM1 (Bit 2) */
#define PWRCTRL_DEVPWREN_PWRIOM1_Msk (0x4UL) /*!< PWRIOM1 (Bitfield-Mask: 0x01) */
#define PWRCTRL_DEVPWREN_PWRIOM0_Pos (1UL) /*!< PWRIOM0 (Bit 1) */
#define PWRCTRL_DEVPWREN_PWRIOM0_Msk (0x2UL) /*!< PWRIOM0 (Bitfield-Mask: 0x01) */
#define PWRCTRL_DEVPWREN_PWRIOS_Pos (0UL) /*!< PWRIOS (Bit 0) */
#define PWRCTRL_DEVPWREN_PWRIOS_Msk (0x1UL) /*!< PWRIOS (Bitfield-Mask: 0x01) */
/* ===================================================== MEMPWDINSLEEP ===================================================== */
#define PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_Pos (31UL) /*!< CACHEPWDSLP (Bit 31) */
#define PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_Msk (0x80000000UL) /*!< CACHEPWDSLP (Bitfield-Mask: 0x01) */
#define PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP_Pos (14UL) /*!< FLASH1PWDSLP (Bit 14) */
#define PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP_Msk (0x4000UL) /*!< FLASH1PWDSLP (Bitfield-Mask: 0x01) */
#define PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_Pos (13UL) /*!< FLASH0PWDSLP (Bit 13) */
#define PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_Msk (0x2000UL) /*!< FLASH0PWDSLP (Bitfield-Mask: 0x01) */
#define PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_Pos (3UL) /*!< SRAMPWDSLP (Bit 3) */
#define PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_Msk (0x1ff8UL) /*!< SRAMPWDSLP (Bitfield-Mask: 0x3ff) */
#define PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_Pos (0UL) /*!< DTCMPWDSLP (Bit 0) */
#define PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_Msk (0x7UL) /*!< DTCMPWDSLP (Bitfield-Mask: 0x07) */
/* ======================================================= MEMPWREN ======================================================== */
#define PWRCTRL_MEMPWREN_CACHEB2_Pos (31UL) /*!< CACHEB2 (Bit 31) */
#define PWRCTRL_MEMPWREN_CACHEB2_Msk (0x80000000UL) /*!< CACHEB2 (Bitfield-Mask: 0x01) */
#define PWRCTRL_MEMPWREN_CACHEB0_Pos (30UL) /*!< CACHEB0 (Bit 30) */
#define PWRCTRL_MEMPWREN_CACHEB0_Msk (0x40000000UL) /*!< CACHEB0 (Bitfield-Mask: 0x01) */
#define PWRCTRL_MEMPWREN_FLASH1_Pos (14UL) /*!< FLASH1 (Bit 14) */
#define PWRCTRL_MEMPWREN_FLASH1_Msk (0x4000UL) /*!< FLASH1 (Bitfield-Mask: 0x01) */
#define PWRCTRL_MEMPWREN_FLASH0_Pos (13UL) /*!< FLASH0 (Bit 13) */
#define PWRCTRL_MEMPWREN_FLASH0_Msk (0x2000UL) /*!< FLASH0 (Bitfield-Mask: 0x01) */
#define PWRCTRL_MEMPWREN_SRAM_Pos (3UL) /*!< SRAM (Bit 3) */
#define PWRCTRL_MEMPWREN_SRAM_Msk (0x1ff8UL) /*!< SRAM (Bitfield-Mask: 0x3ff) */
#define PWRCTRL_MEMPWREN_DTCM_Pos (0UL) /*!< DTCM (Bit 0) */
#define PWRCTRL_MEMPWREN_DTCM_Msk (0x7UL) /*!< DTCM (Bitfield-Mask: 0x07) */
/* ===================================================== MEMPWRSTATUS ====================================================== */
#define PWRCTRL_MEMPWRSTATUS_CACHEB2_Pos (16UL) /*!< CACHEB2 (Bit 16) */
#define PWRCTRL_MEMPWRSTATUS_CACHEB2_Msk (0x10000UL) /*!< CACHEB2 (Bitfield-Mask: 0x01) */
#define PWRCTRL_MEMPWRSTATUS_CACHEB0_Pos (15UL) /*!< CACHEB0 (Bit 15) */
#define PWRCTRL_MEMPWRSTATUS_CACHEB0_Msk (0x8000UL) /*!< CACHEB0 (Bitfield-Mask: 0x01) */
#define PWRCTRL_MEMPWRSTATUS_FLASH1_Pos (14UL) /*!< FLASH1 (Bit 14) */
#define PWRCTRL_MEMPWRSTATUS_FLASH1_Msk (0x4000UL) /*!< FLASH1 (Bitfield-Mask: 0x01) */
#define PWRCTRL_MEMPWRSTATUS_FLASH0_Pos (13UL) /*!< FLASH0 (Bit 13) */
#define PWRCTRL_MEMPWRSTATUS_FLASH0_Msk (0x2000UL) /*!< FLASH0 (Bitfield-Mask: 0x01) */
#define PWRCTRL_MEMPWRSTATUS_SRAM9_Pos (12UL) /*!< SRAM9 (Bit 12) */
#define PWRCTRL_MEMPWRSTATUS_SRAM9_Msk (0x1000UL) /*!< SRAM9 (Bitfield-Mask: 0x01) */
#define PWRCTRL_MEMPWRSTATUS_SRAM8_Pos (11UL) /*!< SRAM8 (Bit 11) */
#define PWRCTRL_MEMPWRSTATUS_SRAM8_Msk (0x800UL) /*!< SRAM8 (Bitfield-Mask: 0x01) */
#define PWRCTRL_MEMPWRSTATUS_SRAM7_Pos (10UL) /*!< SRAM7 (Bit 10) */
#define PWRCTRL_MEMPWRSTATUS_SRAM7_Msk (0x400UL) /*!< SRAM7 (Bitfield-Mask: 0x01) */
#define PWRCTRL_MEMPWRSTATUS_SRAM6_Pos (9UL) /*!< SRAM6 (Bit 9) */
#define PWRCTRL_MEMPWRSTATUS_SRAM6_Msk (0x200UL) /*!< SRAM6 (Bitfield-Mask: 0x01) */
#define PWRCTRL_MEMPWRSTATUS_SRAM5_Pos (8UL) /*!< SRAM5 (Bit 8) */
#define PWRCTRL_MEMPWRSTATUS_SRAM5_Msk (0x100UL) /*!< SRAM5 (Bitfield-Mask: 0x01) */
#define PWRCTRL_MEMPWRSTATUS_SRAM4_Pos (7UL) /*!< SRAM4 (Bit 7) */
#define PWRCTRL_MEMPWRSTATUS_SRAM4_Msk (0x80UL) /*!< SRAM4 (Bitfield-Mask: 0x01) */
#define PWRCTRL_MEMPWRSTATUS_SRAM3_Pos (6UL) /*!< SRAM3 (Bit 6) */
#define PWRCTRL_MEMPWRSTATUS_SRAM3_Msk (0x40UL) /*!< SRAM3 (Bitfield-Mask: 0x01) */
#define PWRCTRL_MEMPWRSTATUS_SRAM2_Pos (5UL) /*!< SRAM2 (Bit 5) */
#define PWRCTRL_MEMPWRSTATUS_SRAM2_Msk (0x20UL) /*!< SRAM2 (Bitfield-Mask: 0x01) */
#define PWRCTRL_MEMPWRSTATUS_SRAM1_Pos (4UL) /*!< SRAM1 (Bit 4) */
#define PWRCTRL_MEMPWRSTATUS_SRAM1_Msk (0x10UL) /*!< SRAM1 (Bitfield-Mask: 0x01) */
#define PWRCTRL_MEMPWRSTATUS_SRAM0_Pos (3UL) /*!< SRAM0 (Bit 3) */
#define PWRCTRL_MEMPWRSTATUS_SRAM0_Msk (0x8UL) /*!< SRAM0 (Bitfield-Mask: 0x01) */
#define PWRCTRL_MEMPWRSTATUS_DTCM1_Pos (2UL) /*!< DTCM1 (Bit 2) */
#define PWRCTRL_MEMPWRSTATUS_DTCM1_Msk (0x4UL) /*!< DTCM1 (Bitfield-Mask: 0x01) */
#define PWRCTRL_MEMPWRSTATUS_DTCM01_Pos (1UL) /*!< DTCM01 (Bit 1) */
#define PWRCTRL_MEMPWRSTATUS_DTCM01_Msk (0x2UL) /*!< DTCM01 (Bitfield-Mask: 0x01) */
#define PWRCTRL_MEMPWRSTATUS_DTCM00_Pos (0UL) /*!< DTCM00 (Bit 0) */
#define PWRCTRL_MEMPWRSTATUS_DTCM00_Msk (0x1UL) /*!< DTCM00 (Bitfield-Mask: 0x01) */
/* ===================================================== DEVPWRSTATUS ====================================================== */
#define PWRCTRL_DEVPWRSTATUS_BLEH_Pos (9UL) /*!< BLEH (Bit 9) */
#define PWRCTRL_DEVPWRSTATUS_BLEH_Msk (0x200UL) /*!< BLEH (Bitfield-Mask: 0x01) */
#define PWRCTRL_DEVPWRSTATUS_BLEL_Pos (8UL) /*!< BLEL (Bit 8) */
#define PWRCTRL_DEVPWRSTATUS_BLEL_Msk (0x100UL) /*!< BLEL (Bitfield-Mask: 0x01) */
#define PWRCTRL_DEVPWRSTATUS_PWRPDM_Pos (7UL) /*!< PWRPDM (Bit 7) */
#define PWRCTRL_DEVPWRSTATUS_PWRPDM_Msk (0x80UL) /*!< PWRPDM (Bitfield-Mask: 0x01) */
#define PWRCTRL_DEVPWRSTATUS_PWRMSPI_Pos (6UL) /*!< PWRMSPI (Bit 6) */
#define PWRCTRL_DEVPWRSTATUS_PWRMSPI_Msk (0x40UL) /*!< PWRMSPI (Bitfield-Mask: 0x01) */
#define PWRCTRL_DEVPWRSTATUS_PWRADC_Pos (5UL) /*!< PWRADC (Bit 5) */
#define PWRCTRL_DEVPWRSTATUS_PWRADC_Msk (0x20UL) /*!< PWRADC (Bitfield-Mask: 0x01) */
#define PWRCTRL_DEVPWRSTATUS_HCPC_Pos (4UL) /*!< HCPC (Bit 4) */
#define PWRCTRL_DEVPWRSTATUS_HCPC_Msk (0x10UL) /*!< HCPC (Bitfield-Mask: 0x01) */
#define PWRCTRL_DEVPWRSTATUS_HCPB_Pos (3UL) /*!< HCPB (Bit 3) */
#define PWRCTRL_DEVPWRSTATUS_HCPB_Msk (0x8UL) /*!< HCPB (Bitfield-Mask: 0x01) */
#define PWRCTRL_DEVPWRSTATUS_HCPA_Pos (2UL) /*!< HCPA (Bit 2) */
#define PWRCTRL_DEVPWRSTATUS_HCPA_Msk (0x4UL) /*!< HCPA (Bitfield-Mask: 0x01) */
#define PWRCTRL_DEVPWRSTATUS_MCUH_Pos (1UL) /*!< MCUH (Bit 1) */
#define PWRCTRL_DEVPWRSTATUS_MCUH_Msk (0x2UL) /*!< MCUH (Bitfield-Mask: 0x01) */
#define PWRCTRL_DEVPWRSTATUS_MCUL_Pos (0UL) /*!< MCUL (Bit 0) */
#define PWRCTRL_DEVPWRSTATUS_MCUL_Msk (0x1UL) /*!< MCUL (Bitfield-Mask: 0x01) */
/* ======================================================= SRAMCTRL ======================================================== */
#define PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_Pos (8UL) /*!< SRAMLIGHTSLEEP (Bit 8) */
#define PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_Msk (0xfff00UL) /*!< SRAMLIGHTSLEEP (Bitfield-Mask: 0xfff) */
#define PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_Pos (2UL) /*!< SRAMMASTERCLKGATE (Bit 2) */
#define PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_Msk (0x4UL) /*!< SRAMMASTERCLKGATE (Bitfield-Mask: 0x01) */
#define PWRCTRL_SRAMCTRL_SRAMCLKGATE_Pos (1UL) /*!< SRAMCLKGATE (Bit 1) */
#define PWRCTRL_SRAMCTRL_SRAMCLKGATE_Msk (0x2UL) /*!< SRAMCLKGATE (Bitfield-Mask: 0x01) */
/* ======================================================= ADCSTATUS ======================================================= */
#define PWRCTRL_ADCSTATUS_REFBUFPWD_Pos (5UL) /*!< REFBUFPWD (Bit 5) */
#define PWRCTRL_ADCSTATUS_REFBUFPWD_Msk (0x20UL) /*!< REFBUFPWD (Bitfield-Mask: 0x01) */
#define PWRCTRL_ADCSTATUS_REFKEEPPWD_Pos (4UL) /*!< REFKEEPPWD (Bit 4) */
#define PWRCTRL_ADCSTATUS_REFKEEPPWD_Msk (0x10UL) /*!< REFKEEPPWD (Bitfield-Mask: 0x01) */
#define PWRCTRL_ADCSTATUS_VBATPWD_Pos (3UL) /*!< VBATPWD (Bit 3) */
#define PWRCTRL_ADCSTATUS_VBATPWD_Msk (0x8UL) /*!< VBATPWD (Bitfield-Mask: 0x01) */
#define PWRCTRL_ADCSTATUS_VPTATPWD_Pos (2UL) /*!< VPTATPWD (Bit 2) */
#define PWRCTRL_ADCSTATUS_VPTATPWD_Msk (0x4UL) /*!< VPTATPWD (Bitfield-Mask: 0x01) */
#define PWRCTRL_ADCSTATUS_BGTPWD_Pos (1UL) /*!< BGTPWD (Bit 1) */
#define PWRCTRL_ADCSTATUS_BGTPWD_Msk (0x2UL) /*!< BGTPWD (Bitfield-Mask: 0x01) */
#define PWRCTRL_ADCSTATUS_ADCPWD_Pos (0UL) /*!< ADCPWD (Bit 0) */
#define PWRCTRL_ADCSTATUS_ADCPWD_Msk (0x1UL) /*!< ADCPWD (Bitfield-Mask: 0x01) */
/* ========================================================= MISC ========================================================== */
#define PWRCTRL_MISC_MEMVRLPBLE_Pos (6UL) /*!< MEMVRLPBLE (Bit 6) */
#define PWRCTRL_MISC_MEMVRLPBLE_Msk (0x40UL) /*!< MEMVRLPBLE (Bitfield-Mask: 0x01) */
#define PWRCTRL_MISC_FORCEMEMVRLPTIMERS_Pos (3UL) /*!< FORCEMEMVRLPTIMERS (Bit 3) */
#define PWRCTRL_MISC_FORCEMEMVRLPTIMERS_Msk (0x8UL) /*!< FORCEMEMVRLPTIMERS (Bitfield-Mask: 0x01) */
/* ===================================================== DEVPWREVENTEN ===================================================== */
#define PWRCTRL_DEVPWREVENTEN_BURSTEVEN_Pos (31UL) /*!< BURSTEVEN (Bit 31) */
#define PWRCTRL_DEVPWREVENTEN_BURSTEVEN_Msk (0x80000000UL) /*!< BURSTEVEN (Bitfield-Mask: 0x01) */
#define PWRCTRL_DEVPWREVENTEN_BURSTFEATUREEVEN_Pos (30UL) /*!< BURSTFEATUREEVEN (Bit 30) */
#define PWRCTRL_DEVPWREVENTEN_BURSTFEATUREEVEN_Msk (0x40000000UL) /*!< BURSTFEATUREEVEN (Bitfield-Mask: 0x01) */
#define PWRCTRL_DEVPWREVENTEN_BLEFEATUREEVEN_Pos (29UL) /*!< BLEFEATUREEVEN (Bit 29) */
#define PWRCTRL_DEVPWREVENTEN_BLEFEATUREEVEN_Msk (0x20000000UL) /*!< BLEFEATUREEVEN (Bitfield-Mask: 0x01) */
#define PWRCTRL_DEVPWREVENTEN_BLELEVEN_Pos (8UL) /*!< BLELEVEN (Bit 8) */
#define PWRCTRL_DEVPWREVENTEN_BLELEVEN_Msk (0x100UL) /*!< BLELEVEN (Bitfield-Mask: 0x01) */
#define PWRCTRL_DEVPWREVENTEN_PDMEVEN_Pos (7UL) /*!< PDMEVEN (Bit 7) */
#define PWRCTRL_DEVPWREVENTEN_PDMEVEN_Msk (0x80UL) /*!< PDMEVEN (Bitfield-Mask: 0x01) */
#define PWRCTRL_DEVPWREVENTEN_MSPIEVEN_Pos (6UL) /*!< MSPIEVEN (Bit 6) */
#define PWRCTRL_DEVPWREVENTEN_MSPIEVEN_Msk (0x40UL) /*!< MSPIEVEN (Bitfield-Mask: 0x01) */
#define PWRCTRL_DEVPWREVENTEN_ADCEVEN_Pos (5UL) /*!< ADCEVEN (Bit 5) */
#define PWRCTRL_DEVPWREVENTEN_ADCEVEN_Msk (0x20UL) /*!< ADCEVEN (Bitfield-Mask: 0x01) */
#define PWRCTRL_DEVPWREVENTEN_HCPCEVEN_Pos (4UL) /*!< HCPCEVEN (Bit 4) */
#define PWRCTRL_DEVPWREVENTEN_HCPCEVEN_Msk (0x10UL) /*!< HCPCEVEN (Bitfield-Mask: 0x01) */
#define PWRCTRL_DEVPWREVENTEN_HCPBEVEN_Pos (3UL) /*!< HCPBEVEN (Bit 3) */
#define PWRCTRL_DEVPWREVENTEN_HCPBEVEN_Msk (0x8UL) /*!< HCPBEVEN (Bitfield-Mask: 0x01) */
#define PWRCTRL_DEVPWREVENTEN_HCPAEVEN_Pos (2UL) /*!< HCPAEVEN (Bit 2) */
#define PWRCTRL_DEVPWREVENTEN_HCPAEVEN_Msk (0x4UL) /*!< HCPAEVEN (Bitfield-Mask: 0x01) */
#define PWRCTRL_DEVPWREVENTEN_MCUHEVEN_Pos (1UL) /*!< MCUHEVEN (Bit 1) */
#define PWRCTRL_DEVPWREVENTEN_MCUHEVEN_Msk (0x2UL) /*!< MCUHEVEN (Bitfield-Mask: 0x01) */
#define PWRCTRL_DEVPWREVENTEN_MCULEVEN_Pos (0UL) /*!< MCULEVEN (Bit 0) */
#define PWRCTRL_DEVPWREVENTEN_MCULEVEN_Msk (0x1UL) /*!< MCULEVEN (Bitfield-Mask: 0x01) */
/* ===================================================== MEMPWREVENTEN ===================================================== */
#define PWRCTRL_MEMPWREVENTEN_CACHEB2EN_Pos (31UL) /*!< CACHEB2EN (Bit 31) */
#define PWRCTRL_MEMPWREVENTEN_CACHEB2EN_Msk (0x80000000UL) /*!< CACHEB2EN (Bitfield-Mask: 0x01) */
#define PWRCTRL_MEMPWREVENTEN_CACHEB0EN_Pos (30UL) /*!< CACHEB0EN (Bit 30) */
#define PWRCTRL_MEMPWREVENTEN_CACHEB0EN_Msk (0x40000000UL) /*!< CACHEB0EN (Bitfield-Mask: 0x01) */
#define PWRCTRL_MEMPWREVENTEN_FLASH1EN_Pos (14UL) /*!< FLASH1EN (Bit 14) */
#define PWRCTRL_MEMPWREVENTEN_FLASH1EN_Msk (0x4000UL) /*!< FLASH1EN (Bitfield-Mask: 0x01) */
#define PWRCTRL_MEMPWREVENTEN_FLASH0EN_Pos (13UL) /*!< FLASH0EN (Bit 13) */
#define PWRCTRL_MEMPWREVENTEN_FLASH0EN_Msk (0x2000UL) /*!< FLASH0EN (Bitfield-Mask: 0x01) */
#define PWRCTRL_MEMPWREVENTEN_SRAMEN_Pos (3UL) /*!< SRAMEN (Bit 3) */
#define PWRCTRL_MEMPWREVENTEN_SRAMEN_Msk (0x1ff8UL) /*!< SRAMEN (Bitfield-Mask: 0x3ff) */
#define PWRCTRL_MEMPWREVENTEN_DTCMEN_Pos (0UL) /*!< DTCMEN (Bit 0) */
#define PWRCTRL_MEMPWREVENTEN_DTCMEN_Msk (0x7UL) /*!< DTCMEN (Bitfield-Mask: 0x07) */
/* =========================================================================================================================== */
/* ================ RSTGEN ================ */
/* =========================================================================================================================== */
/* ========================================================== CFG ========================================================== */
#define RSTGEN_CFG_WDREN_Pos (1UL) /*!< WDREN (Bit 1) */
#define RSTGEN_CFG_WDREN_Msk (0x2UL) /*!< WDREN (Bitfield-Mask: 0x01) */
#define RSTGEN_CFG_BODHREN_Pos (0UL) /*!< BODHREN (Bit 0) */
#define RSTGEN_CFG_BODHREN_Msk (0x1UL) /*!< BODHREN (Bitfield-Mask: 0x01) */
/* ========================================================= SWPOI ========================================================= */
#define RSTGEN_SWPOI_SWPOIKEY_Pos (0UL) /*!< SWPOIKEY (Bit 0) */
#define RSTGEN_SWPOI_SWPOIKEY_Msk (0xffUL) /*!< SWPOIKEY (Bitfield-Mask: 0xff) */
/* ========================================================= SWPOR ========================================================= */
#define RSTGEN_SWPOR_SWPORKEY_Pos (0UL) /*!< SWPORKEY (Bit 0) */
#define RSTGEN_SWPOR_SWPORKEY_Msk (0xffUL) /*!< SWPORKEY (Bitfield-Mask: 0xff) */
/* ======================================================== TPIURST ======================================================== */
#define RSTGEN_TPIURST_TPIURST_Pos (0UL) /*!< TPIURST (Bit 0) */
#define RSTGEN_TPIURST_TPIURST_Msk (0x1UL) /*!< TPIURST (Bitfield-Mask: 0x01) */
/* ========================================================= INTEN ========================================================= */
#define RSTGEN_INTEN_BODH_Pos (0UL) /*!< BODH (Bit 0) */
#define RSTGEN_INTEN_BODH_Msk (0x1UL) /*!< BODH (Bitfield-Mask: 0x01) */
/* ======================================================== INTSTAT ======================================================== */
#define RSTGEN_INTSTAT_BODH_Pos (0UL) /*!< BODH (Bit 0) */
#define RSTGEN_INTSTAT_BODH_Msk (0x1UL) /*!< BODH (Bitfield-Mask: 0x01) */
/* ======================================================== INTCLR ========================================================= */
#define RSTGEN_INTCLR_BODH_Pos (0UL) /*!< BODH (Bit 0) */
#define RSTGEN_INTCLR_BODH_Msk (0x1UL) /*!< BODH (Bitfield-Mask: 0x01) */
/* ======================================================== INTSET ========================================================= */
#define RSTGEN_INTSET_BODH_Pos (0UL) /*!< BODH (Bit 0) */
#define RSTGEN_INTSET_BODH_Msk (0x1UL) /*!< BODH (Bitfield-Mask: 0x01) */
/* ========================================================= STAT ========================================================== */
#define RSTGEN_STAT_SBOOT_Pos (31UL) /*!< SBOOT (Bit 31) */
#define RSTGEN_STAT_SBOOT_Msk (0x80000000UL) /*!< SBOOT (Bitfield-Mask: 0x01) */
#define RSTGEN_STAT_FBOOT_Pos (30UL) /*!< FBOOT (Bit 30) */
#define RSTGEN_STAT_FBOOT_Msk (0x40000000UL) /*!< FBOOT (Bitfield-Mask: 0x01) */
#define RSTGEN_STAT_BOBSTAT_Pos (10UL) /*!< BOBSTAT (Bit 10) */
#define RSTGEN_STAT_BOBSTAT_Msk (0x400UL) /*!< BOBSTAT (Bitfield-Mask: 0x01) */
#define RSTGEN_STAT_BOFSTAT_Pos (9UL) /*!< BOFSTAT (Bit 9) */
#define RSTGEN_STAT_BOFSTAT_Msk (0x200UL) /*!< BOFSTAT (Bitfield-Mask: 0x01) */
#define RSTGEN_STAT_BOCSTAT_Pos (8UL) /*!< BOCSTAT (Bit 8) */
#define RSTGEN_STAT_BOCSTAT_Msk (0x100UL) /*!< BOCSTAT (Bitfield-Mask: 0x01) */
#define RSTGEN_STAT_BOUSTAT_Pos (7UL) /*!< BOUSTAT (Bit 7) */
#define RSTGEN_STAT_BOUSTAT_Msk (0x80UL) /*!< BOUSTAT (Bitfield-Mask: 0x01) */
#define RSTGEN_STAT_WDRSTAT_Pos (6UL) /*!< WDRSTAT (Bit 6) */
#define RSTGEN_STAT_WDRSTAT_Msk (0x40UL) /*!< WDRSTAT (Bitfield-Mask: 0x01) */
#define RSTGEN_STAT_DBGRSTAT_Pos (5UL) /*!< DBGRSTAT (Bit 5) */
#define RSTGEN_STAT_DBGRSTAT_Msk (0x20UL) /*!< DBGRSTAT (Bitfield-Mask: 0x01) */
#define RSTGEN_STAT_POIRSTAT_Pos (4UL) /*!< POIRSTAT (Bit 4) */
#define RSTGEN_STAT_POIRSTAT_Msk (0x10UL) /*!< POIRSTAT (Bitfield-Mask: 0x01) */
#define RSTGEN_STAT_SWRSTAT_Pos (3UL) /*!< SWRSTAT (Bit 3) */
#define RSTGEN_STAT_SWRSTAT_Msk (0x8UL) /*!< SWRSTAT (Bitfield-Mask: 0x01) */
#define RSTGEN_STAT_BORSTAT_Pos (2UL) /*!< BORSTAT (Bit 2) */
#define RSTGEN_STAT_BORSTAT_Msk (0x4UL) /*!< BORSTAT (Bitfield-Mask: 0x01) */
#define RSTGEN_STAT_PORSTAT_Pos (1UL) /*!< PORSTAT (Bit 1) */
#define RSTGEN_STAT_PORSTAT_Msk (0x2UL) /*!< PORSTAT (Bitfield-Mask: 0x01) */
#define RSTGEN_STAT_EXRSTAT_Pos (0UL) /*!< EXRSTAT (Bit 0) */
#define RSTGEN_STAT_EXRSTAT_Msk (0x1UL) /*!< EXRSTAT (Bitfield-Mask: 0x01) */
/* =========================================================================================================================== */
/* ================ RTC ================ */
/* =========================================================================================================================== */
/* ======================================================== CTRLOW ========================================================= */
#define RTC_CTRLOW_CTRHR_Pos (24UL) /*!< CTRHR (Bit 24) */
#define RTC_CTRLOW_CTRHR_Msk (0x3f000000UL) /*!< CTRHR (Bitfield-Mask: 0x3f) */
#define RTC_CTRLOW_CTRMIN_Pos (16UL) /*!< CTRMIN (Bit 16) */
#define RTC_CTRLOW_CTRMIN_Msk (0x7f0000UL) /*!< CTRMIN (Bitfield-Mask: 0x7f) */
#define RTC_CTRLOW_CTRSEC_Pos (8UL) /*!< CTRSEC (Bit 8) */
#define RTC_CTRLOW_CTRSEC_Msk (0x7f00UL) /*!< CTRSEC (Bitfield-Mask: 0x7f) */
#define RTC_CTRLOW_CTR100_Pos (0UL) /*!< CTR100 (Bit 0) */
#define RTC_CTRLOW_CTR100_Msk (0xffUL) /*!< CTR100 (Bitfield-Mask: 0xff) */
/* ========================================================= CTRUP ========================================================= */
#define RTC_CTRUP_CTERR_Pos (31UL) /*!< CTERR (Bit 31) */
#define RTC_CTRUP_CTERR_Msk (0x80000000UL) /*!< CTERR (Bitfield-Mask: 0x01) */
#define RTC_CTRUP_CEB_Pos (28UL) /*!< CEB (Bit 28) */
#define RTC_CTRUP_CEB_Msk (0x10000000UL) /*!< CEB (Bitfield-Mask: 0x01) */
#define RTC_CTRUP_CB_Pos (27UL) /*!< CB (Bit 27) */
#define RTC_CTRUP_CB_Msk (0x8000000UL) /*!< CB (Bitfield-Mask: 0x01) */
#define RTC_CTRUP_CTRWKDY_Pos (24UL) /*!< CTRWKDY (Bit 24) */
#define RTC_CTRUP_CTRWKDY_Msk (0x7000000UL) /*!< CTRWKDY (Bitfield-Mask: 0x07) */
#define RTC_CTRUP_CTRYR_Pos (16UL) /*!< CTRYR (Bit 16) */
#define RTC_CTRUP_CTRYR_Msk (0xff0000UL) /*!< CTRYR (Bitfield-Mask: 0xff) */
#define RTC_CTRUP_CTRMO_Pos (8UL) /*!< CTRMO (Bit 8) */
#define RTC_CTRUP_CTRMO_Msk (0x1f00UL) /*!< CTRMO (Bitfield-Mask: 0x1f) */
#define RTC_CTRUP_CTRDATE_Pos (0UL) /*!< CTRDATE (Bit 0) */
#define RTC_CTRUP_CTRDATE_Msk (0x3fUL) /*!< CTRDATE (Bitfield-Mask: 0x3f) */
/* ======================================================== ALMLOW ========================================================= */
#define RTC_ALMLOW_ALMHR_Pos (24UL) /*!< ALMHR (Bit 24) */
#define RTC_ALMLOW_ALMHR_Msk (0x3f000000UL) /*!< ALMHR (Bitfield-Mask: 0x3f) */
#define RTC_ALMLOW_ALMMIN_Pos (16UL) /*!< ALMMIN (Bit 16) */
#define RTC_ALMLOW_ALMMIN_Msk (0x7f0000UL) /*!< ALMMIN (Bitfield-Mask: 0x7f) */
#define RTC_ALMLOW_ALMSEC_Pos (8UL) /*!< ALMSEC (Bit 8) */
#define RTC_ALMLOW_ALMSEC_Msk (0x7f00UL) /*!< ALMSEC (Bitfield-Mask: 0x7f) */
#define RTC_ALMLOW_ALM100_Pos (0UL) /*!< ALM100 (Bit 0) */
#define RTC_ALMLOW_ALM100_Msk (0xffUL) /*!< ALM100 (Bitfield-Mask: 0xff) */
/* ========================================================= ALMUP ========================================================= */
#define RTC_ALMUP_ALMWKDY_Pos (16UL) /*!< ALMWKDY (Bit 16) */
#define RTC_ALMUP_ALMWKDY_Msk (0x70000UL) /*!< ALMWKDY (Bitfield-Mask: 0x07) */
#define RTC_ALMUP_ALMMO_Pos (8UL) /*!< ALMMO (Bit 8) */
#define RTC_ALMUP_ALMMO_Msk (0x1f00UL) /*!< ALMMO (Bitfield-Mask: 0x1f) */
#define RTC_ALMUP_ALMDATE_Pos (0UL) /*!< ALMDATE (Bit 0) */
#define RTC_ALMUP_ALMDATE_Msk (0x3fUL) /*!< ALMDATE (Bitfield-Mask: 0x3f) */
/* ======================================================== RTCCTL ========================================================= */
#define RTC_RTCCTL_HR1224_Pos (5UL) /*!< HR1224 (Bit 5) */
#define RTC_RTCCTL_HR1224_Msk (0x20UL) /*!< HR1224 (Bitfield-Mask: 0x01) */
#define RTC_RTCCTL_RSTOP_Pos (4UL) /*!< RSTOP (Bit 4) */
#define RTC_RTCCTL_RSTOP_Msk (0x10UL) /*!< RSTOP (Bitfield-Mask: 0x01) */
#define RTC_RTCCTL_RPT_Pos (1UL) /*!< RPT (Bit 1) */
#define RTC_RTCCTL_RPT_Msk (0xeUL) /*!< RPT (Bitfield-Mask: 0x07) */
#define RTC_RTCCTL_WRTC_Pos (0UL) /*!< WRTC (Bit 0) */
#define RTC_RTCCTL_WRTC_Msk (0x1UL) /*!< WRTC (Bitfield-Mask: 0x01) */
/* ========================================================= INTEN ========================================================= */
#define RTC_INTEN_ALM_Pos (0UL) /*!< ALM (Bit 0) */
#define RTC_INTEN_ALM_Msk (0x1UL) /*!< ALM (Bitfield-Mask: 0x01) */
/* ======================================================== INTSTAT ======================================================== */
#define RTC_INTSTAT_ALM_Pos (0UL) /*!< ALM (Bit 0) */
#define RTC_INTSTAT_ALM_Msk (0x1UL) /*!< ALM (Bitfield-Mask: 0x01) */
/* ======================================================== INTCLR ========================================================= */
#define RTC_INTCLR_ALM_Pos (0UL) /*!< ALM (Bit 0) */
#define RTC_INTCLR_ALM_Msk (0x1UL) /*!< ALM (Bitfield-Mask: 0x01) */
/* ======================================================== INTSET ========================================================= */
#define RTC_INTSET_ALM_Pos (0UL) /*!< ALM (Bit 0) */
#define RTC_INTSET_ALM_Msk (0x1UL) /*!< ALM (Bitfield-Mask: 0x01) */
/* =========================================================================================================================== */
/* ================ SCARD ================ */
/* =========================================================================================================================== */
/* ========================================================== SR =========================================================== */
#define SCARD_SR_FHF_Pos (6UL) /*!< FHF (Bit 6) */
#define SCARD_SR_FHF_Msk (0x40UL) /*!< FHF (Bitfield-Mask: 0x01) */
#define SCARD_SR_FT2REND_Pos (5UL) /*!< FT2REND (Bit 5) */
#define SCARD_SR_FT2REND_Msk (0x20UL) /*!< FT2REND (Bitfield-Mask: 0x01) */
#define SCARD_SR_PE_Pos (4UL) /*!< PE (Bit 4) */
#define SCARD_SR_PE_Msk (0x10UL) /*!< PE (Bitfield-Mask: 0x01) */
#define SCARD_SR_OVR_Pos (3UL) /*!< OVR (Bit 3) */
#define SCARD_SR_OVR_Msk (0x8UL) /*!< OVR (Bitfield-Mask: 0x01) */
#define SCARD_SR_FER_Pos (2UL) /*!< FER (Bit 2) */
#define SCARD_SR_FER_Msk (0x4UL) /*!< FER (Bitfield-Mask: 0x01) */
#define SCARD_SR_TBERBF_Pos (1UL) /*!< TBERBF (Bit 1) */
#define SCARD_SR_TBERBF_Msk (0x2UL) /*!< TBERBF (Bitfield-Mask: 0x01) */
#define SCARD_SR_FNE_Pos (0UL) /*!< FNE (Bit 0) */
#define SCARD_SR_FNE_Msk (0x1UL) /*!< FNE (Bitfield-Mask: 0x01) */
/* ========================================================== IER ========================================================== */
#define SCARD_IER_FHFEN_Pos (6UL) /*!< FHFEN (Bit 6) */
#define SCARD_IER_FHFEN_Msk (0x40UL) /*!< FHFEN (Bitfield-Mask: 0x01) */
#define SCARD_IER_FT2RENDEN_Pos (5UL) /*!< FT2RENDEN (Bit 5) */
#define SCARD_IER_FT2RENDEN_Msk (0x20UL) /*!< FT2RENDEN (Bitfield-Mask: 0x01) */
#define SCARD_IER_PEEN_Pos (4UL) /*!< PEEN (Bit 4) */
#define SCARD_IER_PEEN_Msk (0x10UL) /*!< PEEN (Bitfield-Mask: 0x01) */
#define SCARD_IER_OVREN_Pos (3UL) /*!< OVREN (Bit 3) */
#define SCARD_IER_OVREN_Msk (0x8UL) /*!< OVREN (Bitfield-Mask: 0x01) */
#define SCARD_IER_FEREN_Pos (2UL) /*!< FEREN (Bit 2) */
#define SCARD_IER_FEREN_Msk (0x4UL) /*!< FEREN (Bitfield-Mask: 0x01) */
#define SCARD_IER_TBERBFEN_Pos (1UL) /*!< TBERBFEN (Bit 1) */
#define SCARD_IER_TBERBFEN_Msk (0x2UL) /*!< TBERBFEN (Bitfield-Mask: 0x01) */
#define SCARD_IER_FNEEN_Pos (0UL) /*!< FNEEN (Bit 0) */
#define SCARD_IER_FNEEN_Msk (0x1UL) /*!< FNEEN (Bitfield-Mask: 0x01) */
/* ========================================================== TCR ========================================================== */
#define SCARD_TCR_DMAMD_Pos (7UL) /*!< DMAMD (Bit 7) */
#define SCARD_TCR_DMAMD_Msk (0x80UL) /*!< DMAMD (Bitfield-Mask: 0x01) */
#define SCARD_TCR_FIP_Pos (6UL) /*!< FIP (Bit 6) */
#define SCARD_TCR_FIP_Msk (0x40UL) /*!< FIP (Bitfield-Mask: 0x01) */
#define SCARD_TCR_AUTOCONV_Pos (5UL) /*!< AUTOCONV (Bit 5) */
#define SCARD_TCR_AUTOCONV_Msk (0x20UL) /*!< AUTOCONV (Bitfield-Mask: 0x01) */
#define SCARD_TCR_PROT_Pos (4UL) /*!< PROT (Bit 4) */
#define SCARD_TCR_PROT_Msk (0x10UL) /*!< PROT (Bitfield-Mask: 0x01) */
#define SCARD_TCR_TR_Pos (3UL) /*!< TR (Bit 3) */
#define SCARD_TCR_TR_Msk (0x8UL) /*!< TR (Bitfield-Mask: 0x01) */
#define SCARD_TCR_LCT_Pos (2UL) /*!< LCT (Bit 2) */
#define SCARD_TCR_LCT_Msk (0x4UL) /*!< LCT (Bitfield-Mask: 0x01) */
#define SCARD_TCR_SS_Pos (1UL) /*!< SS (Bit 1) */
#define SCARD_TCR_SS_Msk (0x2UL) /*!< SS (Bitfield-Mask: 0x01) */
#define SCARD_TCR_CONV_Pos (0UL) /*!< CONV (Bit 0) */
#define SCARD_TCR_CONV_Msk (0x1UL) /*!< CONV (Bitfield-Mask: 0x01) */
/* ========================================================== UCR ========================================================== */
#define SCARD_UCR_RETXEN_Pos (3UL) /*!< RETXEN (Bit 3) */
#define SCARD_UCR_RETXEN_Msk (0x8UL) /*!< RETXEN (Bitfield-Mask: 0x01) */
#define SCARD_UCR_RSTIN_Pos (2UL) /*!< RSTIN (Bit 2) */
#define SCARD_UCR_RSTIN_Msk (0x4UL) /*!< RSTIN (Bitfield-Mask: 0x01) */
#define SCARD_UCR_RIU_Pos (1UL) /*!< RIU (Bit 1) */
#define SCARD_UCR_RIU_Msk (0x2UL) /*!< RIU (Bitfield-Mask: 0x01) */
#define SCARD_UCR_CST_Pos (0UL) /*!< CST (Bit 0) */
#define SCARD_UCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */
/* ========================================================== DR =========================================================== */
#define SCARD_DR_DR_Pos (0UL) /*!< DR (Bit 0) */
#define SCARD_DR_DR_Msk (0xffUL) /*!< DR (Bitfield-Mask: 0xff) */
/* ========================================================= BPRL ========================================================== */
#define SCARD_BPRL_BPRL_Pos (0UL) /*!< BPRL (Bit 0) */
#define SCARD_BPRL_BPRL_Msk (0xffUL) /*!< BPRL (Bitfield-Mask: 0xff) */
/* ========================================================= BPRH ========================================================== */
#define SCARD_BPRH_BPRH_Pos (0UL) /*!< BPRH (Bit 0) */
#define SCARD_BPRH_BPRH_Msk (0xfUL) /*!< BPRH (Bitfield-Mask: 0x0f) */
/* ========================================================= UCR1 ========================================================== */
#define SCARD_UCR1_ENLASTB_Pos (5UL) /*!< ENLASTB (Bit 5) */
#define SCARD_UCR1_ENLASTB_Msk (0x20UL) /*!< ENLASTB (Bitfield-Mask: 0x01) */
#define SCARD_UCR1_CLKIOV_Pos (4UL) /*!< CLKIOV (Bit 4) */
#define SCARD_UCR1_CLKIOV_Msk (0x10UL) /*!< CLKIOV (Bitfield-Mask: 0x01) */
#define SCARD_UCR1_T1PAREN_Pos (3UL) /*!< T1PAREN (Bit 3) */
#define SCARD_UCR1_T1PAREN_Msk (0x8UL) /*!< T1PAREN (Bitfield-Mask: 0x01) */
#define SCARD_UCR1_STSP_Pos (2UL) /*!< STSP (Bit 2) */
#define SCARD_UCR1_STSP_Msk (0x4UL) /*!< STSP (Bitfield-Mask: 0x01) */
#define SCARD_UCR1_PR_Pos (0UL) /*!< PR (Bit 0) */
#define SCARD_UCR1_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */
/* ========================================================== SR1 ========================================================== */
#define SCARD_SR1_IDLE_Pos (3UL) /*!< IDLE (Bit 3) */
#define SCARD_SR1_IDLE_Msk (0x8UL) /*!< IDLE (Bitfield-Mask: 0x01) */
#define SCARD_SR1_SYNCEND_Pos (2UL) /*!< SYNCEND (Bit 2) */
#define SCARD_SR1_SYNCEND_Msk (0x4UL) /*!< SYNCEND (Bitfield-Mask: 0x01) */
#define SCARD_SR1_PRL_Pos (1UL) /*!< PRL (Bit 1) */
#define SCARD_SR1_PRL_Msk (0x2UL) /*!< PRL (Bitfield-Mask: 0x01) */
#define SCARD_SR1_ECNTOVER_Pos (0UL) /*!< ECNTOVER (Bit 0) */
#define SCARD_SR1_ECNTOVER_Msk (0x1UL) /*!< ECNTOVER (Bitfield-Mask: 0x01) */
/* ========================================================= IER1 ========================================================== */
#define SCARD_IER1_SYNCENDEN_Pos (2UL) /*!< SYNCENDEN (Bit 2) */
#define SCARD_IER1_SYNCENDEN_Msk (0x4UL) /*!< SYNCENDEN (Bitfield-Mask: 0x01) */
#define SCARD_IER1_PRLEN_Pos (1UL) /*!< PRLEN (Bit 1) */
#define SCARD_IER1_PRLEN_Msk (0x2UL) /*!< PRLEN (Bitfield-Mask: 0x01) */
#define SCARD_IER1_ECNTOVEREN_Pos (0UL) /*!< ECNTOVEREN (Bit 0) */
#define SCARD_IER1_ECNTOVEREN_Msk (0x1UL) /*!< ECNTOVEREN (Bitfield-Mask: 0x01) */
/* ========================================================= ECNTL ========================================================= */
#define SCARD_ECNTL_ECNTL_Pos (0UL) /*!< ECNTL (Bit 0) */
#define SCARD_ECNTL_ECNTL_Msk (0xffUL) /*!< ECNTL (Bitfield-Mask: 0xff) */
/* ========================================================= ECNTH ========================================================= */
#define SCARD_ECNTH_ECNTH_Pos (0UL) /*!< ECNTH (Bit 0) */
#define SCARD_ECNTH_ECNTH_Msk (0xffUL) /*!< ECNTH (Bitfield-Mask: 0xff) */
/* ========================================================== GTR ========================================================== */
#define SCARD_GTR_GTR_Pos (0UL) /*!< GTR (Bit 0) */
#define SCARD_GTR_GTR_Msk (0xffUL) /*!< GTR (Bitfield-Mask: 0xff) */
/* ======================================================== RETXCNT ======================================================== */
#define SCARD_RETXCNT_RETXCNT_Pos (0UL) /*!< RETXCNT (Bit 0) */
#define SCARD_RETXCNT_RETXCNT_Msk (0xfUL) /*!< RETXCNT (Bitfield-Mask: 0x0f) */
/* ====================================================== RETXCNTRMI ======================================================= */
#define SCARD_RETXCNTRMI_RETXCNTRMI_Pos (0UL) /*!< RETXCNTRMI (Bit 0) */
#define SCARD_RETXCNTRMI_RETXCNTRMI_Msk (0xfUL) /*!< RETXCNTRMI (Bitfield-Mask: 0x0f) */
/* ======================================================== CLKCTRL ======================================================== */
#define SCARD_CLKCTRL_APBCLKEN_Pos (1UL) /*!< APBCLKEN (Bit 1) */
#define SCARD_CLKCTRL_APBCLKEN_Msk (0x2UL) /*!< APBCLKEN (Bitfield-Mask: 0x01) */
#define SCARD_CLKCTRL_CLKEN_Pos (0UL) /*!< CLKEN (Bit 0) */
#define SCARD_CLKCTRL_CLKEN_Msk (0x1UL) /*!< CLKEN (Bitfield-Mask: 0x01) */
/* =========================================================================================================================== */
/* ================ SECURITY ================ */
/* =========================================================================================================================== */
/* ========================================================= CTRL ========================================================== */
#define SECURITY_CTRL_CRCERROR_Pos (31UL) /*!< CRCERROR (Bit 31) */
#define SECURITY_CTRL_CRCERROR_Msk (0x80000000UL) /*!< CRCERROR (Bitfield-Mask: 0x01) */
#define SECURITY_CTRL_FUNCTION_Pos (4UL) /*!< FUNCTION (Bit 4) */
#define SECURITY_CTRL_FUNCTION_Msk (0xf0UL) /*!< FUNCTION (Bitfield-Mask: 0x0f) */
#define SECURITY_CTRL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */
#define SECURITY_CTRL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
/* ======================================================== SRCADDR ======================================================== */
#define SECURITY_SRCADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
#define SECURITY_SRCADDR_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
/* ========================================================== LEN ========================================================== */
#define SECURITY_LEN_LEN_Pos (2UL) /*!< LEN (Bit 2) */
#define SECURITY_LEN_LEN_Msk (0xffffcUL) /*!< LEN (Bitfield-Mask: 0x3ffff) */
/* ======================================================== RESULT ========================================================= */
#define SECURITY_RESULT_CRC_Pos (0UL) /*!< CRC (Bit 0) */
#define SECURITY_RESULT_CRC_Msk (0xffffffffUL) /*!< CRC (Bitfield-Mask: 0xffffffff) */
/* ======================================================= LOCKCTRL ======================================================== */
#define SECURITY_LOCKCTRL_SELECT_Pos (0UL) /*!< SELECT (Bit 0) */
#define SECURITY_LOCKCTRL_SELECT_Msk (0xffUL) /*!< SELECT (Bitfield-Mask: 0xff) */
/* ======================================================= LOCKSTAT ======================================================== */
#define SECURITY_LOCKSTAT_STATUS_Pos (0UL) /*!< STATUS (Bit 0) */
#define SECURITY_LOCKSTAT_STATUS_Msk (0xffffffffUL) /*!< STATUS (Bitfield-Mask: 0xffffffff) */
/* ========================================================= KEY0 ========================================================== */
#define SECURITY_KEY0_KEY0_Pos (0UL) /*!< KEY0 (Bit 0) */
#define SECURITY_KEY0_KEY0_Msk (0xffffffffUL) /*!< KEY0 (Bitfield-Mask: 0xffffffff) */
/* ========================================================= KEY1 ========================================================== */
#define SECURITY_KEY1_KEY1_Pos (0UL) /*!< KEY1 (Bit 0) */
#define SECURITY_KEY1_KEY1_Msk (0xffffffffUL) /*!< KEY1 (Bitfield-Mask: 0xffffffff) */
/* ========================================================= KEY2 ========================================================== */
#define SECURITY_KEY2_KEY2_Pos (0UL) /*!< KEY2 (Bit 0) */
#define SECURITY_KEY2_KEY2_Msk (0xffffffffUL) /*!< KEY2 (Bitfield-Mask: 0xffffffff) */
/* ========================================================= KEY3 ========================================================== */
#define SECURITY_KEY3_KEY3_Pos (0UL) /*!< KEY3 (Bit 0) */
#define SECURITY_KEY3_KEY3_Msk (0xffffffffUL) /*!< KEY3 (Bitfield-Mask: 0xffffffff) */
/* =========================================================================================================================== */
/* ================ UART0 ================ */
/* =========================================================================================================================== */
/* ========================================================== DR =========================================================== */
#define UART0_DR_OEDATA_Pos (11UL) /*!< OEDATA (Bit 11) */
#define UART0_DR_OEDATA_Msk (0x800UL) /*!< OEDATA (Bitfield-Mask: 0x01) */
#define UART0_DR_BEDATA_Pos (10UL) /*!< BEDATA (Bit 10) */
#define UART0_DR_BEDATA_Msk (0x400UL) /*!< BEDATA (Bitfield-Mask: 0x01) */
#define UART0_DR_PEDATA_Pos (9UL) /*!< PEDATA (Bit 9) */
#define UART0_DR_PEDATA_Msk (0x200UL) /*!< PEDATA (Bitfield-Mask: 0x01) */
#define UART0_DR_FEDATA_Pos (8UL) /*!< FEDATA (Bit 8) */
#define UART0_DR_FEDATA_Msk (0x100UL) /*!< FEDATA (Bitfield-Mask: 0x01) */
#define UART0_DR_DATA_Pos (0UL) /*!< DATA (Bit 0) */
#define UART0_DR_DATA_Msk (0xffUL) /*!< DATA (Bitfield-Mask: 0xff) */
/* ========================================================== RSR ========================================================== */
#define UART0_RSR_OESTAT_Pos (3UL) /*!< OESTAT (Bit 3) */
#define UART0_RSR_OESTAT_Msk (0x8UL) /*!< OESTAT (Bitfield-Mask: 0x01) */
#define UART0_RSR_BESTAT_Pos (2UL) /*!< BESTAT (Bit 2) */
#define UART0_RSR_BESTAT_Msk (0x4UL) /*!< BESTAT (Bitfield-Mask: 0x01) */
#define UART0_RSR_PESTAT_Pos (1UL) /*!< PESTAT (Bit 1) */
#define UART0_RSR_PESTAT_Msk (0x2UL) /*!< PESTAT (Bitfield-Mask: 0x01) */
#define UART0_RSR_FESTAT_Pos (0UL) /*!< FESTAT (Bit 0) */
#define UART0_RSR_FESTAT_Msk (0x1UL) /*!< FESTAT (Bitfield-Mask: 0x01) */
/* ========================================================== FR =========================================================== */
#define UART0_FR_TXBUSY_Pos (8UL) /*!< TXBUSY (Bit 8) */
#define UART0_FR_TXBUSY_Msk (0x100UL) /*!< TXBUSY (Bitfield-Mask: 0x01) */
#define UART0_FR_TXFE_Pos (7UL) /*!< TXFE (Bit 7) */
#define UART0_FR_TXFE_Msk (0x80UL) /*!< TXFE (Bitfield-Mask: 0x01) */
#define UART0_FR_RXFF_Pos (6UL) /*!< RXFF (Bit 6) */
#define UART0_FR_RXFF_Msk (0x40UL) /*!< RXFF (Bitfield-Mask: 0x01) */
#define UART0_FR_TXFF_Pos (5UL) /*!< TXFF (Bit 5) */
#define UART0_FR_TXFF_Msk (0x20UL) /*!< TXFF (Bitfield-Mask: 0x01) */
#define UART0_FR_RXFE_Pos (4UL) /*!< RXFE (Bit 4) */
#define UART0_FR_RXFE_Msk (0x10UL) /*!< RXFE (Bitfield-Mask: 0x01) */
#define UART0_FR_BUSY_Pos (3UL) /*!< BUSY (Bit 3) */
#define UART0_FR_BUSY_Msk (0x8UL) /*!< BUSY (Bitfield-Mask: 0x01) */
#define UART0_FR_DCD_Pos (2UL) /*!< DCD (Bit 2) */
#define UART0_FR_DCD_Msk (0x4UL) /*!< DCD (Bitfield-Mask: 0x01) */
#define UART0_FR_DSR_Pos (1UL) /*!< DSR (Bit 1) */
#define UART0_FR_DSR_Msk (0x2UL) /*!< DSR (Bitfield-Mask: 0x01) */
#define UART0_FR_CTS_Pos (0UL) /*!< CTS (Bit 0) */
#define UART0_FR_CTS_Msk (0x1UL) /*!< CTS (Bitfield-Mask: 0x01) */
/* ========================================================= ILPR ========================================================== */
#define UART0_ILPR_ILPDVSR_Pos (0UL) /*!< ILPDVSR (Bit 0) */
#define UART0_ILPR_ILPDVSR_Msk (0xffUL) /*!< ILPDVSR (Bitfield-Mask: 0xff) */
/* ========================================================= IBRD ========================================================== */
#define UART0_IBRD_DIVINT_Pos (0UL) /*!< DIVINT (Bit 0) */
#define UART0_IBRD_DIVINT_Msk (0xffffUL) /*!< DIVINT (Bitfield-Mask: 0xffff) */
/* ========================================================= FBRD ========================================================== */
#define UART0_FBRD_DIVFRAC_Pos (0UL) /*!< DIVFRAC (Bit 0) */
#define UART0_FBRD_DIVFRAC_Msk (0x3fUL) /*!< DIVFRAC (Bitfield-Mask: 0x3f) */
/* ========================================================= LCRH ========================================================== */
#define UART0_LCRH_SPS_Pos (7UL) /*!< SPS (Bit 7) */
#define UART0_LCRH_SPS_Msk (0x80UL) /*!< SPS (Bitfield-Mask: 0x01) */
#define UART0_LCRH_WLEN_Pos (5UL) /*!< WLEN (Bit 5) */
#define UART0_LCRH_WLEN_Msk (0x60UL) /*!< WLEN (Bitfield-Mask: 0x03) */
#define UART0_LCRH_FEN_Pos (4UL) /*!< FEN (Bit 4) */
#define UART0_LCRH_FEN_Msk (0x10UL) /*!< FEN (Bitfield-Mask: 0x01) */
#define UART0_LCRH_STP2_Pos (3UL) /*!< STP2 (Bit 3) */
#define UART0_LCRH_STP2_Msk (0x8UL) /*!< STP2 (Bitfield-Mask: 0x01) */
#define UART0_LCRH_EPS_Pos (2UL) /*!< EPS (Bit 2) */
#define UART0_LCRH_EPS_Msk (0x4UL) /*!< EPS (Bitfield-Mask: 0x01) */
#define UART0_LCRH_PEN_Pos (1UL) /*!< PEN (Bit 1) */
#define UART0_LCRH_PEN_Msk (0x2UL) /*!< PEN (Bitfield-Mask: 0x01) */
#define UART0_LCRH_BRK_Pos (0UL) /*!< BRK (Bit 0) */
#define UART0_LCRH_BRK_Msk (0x1UL) /*!< BRK (Bitfield-Mask: 0x01) */
/* ========================================================== CR =========================================================== */
#define UART0_CR_CTSEN_Pos (15UL) /*!< CTSEN (Bit 15) */
#define UART0_CR_CTSEN_Msk (0x8000UL) /*!< CTSEN (Bitfield-Mask: 0x01) */
#define UART0_CR_RTSEN_Pos (14UL) /*!< RTSEN (Bit 14) */
#define UART0_CR_RTSEN_Msk (0x4000UL) /*!< RTSEN (Bitfield-Mask: 0x01) */
#define UART0_CR_OUT2_Pos (13UL) /*!< OUT2 (Bit 13) */
#define UART0_CR_OUT2_Msk (0x2000UL) /*!< OUT2 (Bitfield-Mask: 0x01) */
#define UART0_CR_OUT1_Pos (12UL) /*!< OUT1 (Bit 12) */
#define UART0_CR_OUT1_Msk (0x1000UL) /*!< OUT1 (Bitfield-Mask: 0x01) */
#define UART0_CR_RTS_Pos (11UL) /*!< RTS (Bit 11) */
#define UART0_CR_RTS_Msk (0x800UL) /*!< RTS (Bitfield-Mask: 0x01) */
#define UART0_CR_DTR_Pos (10UL) /*!< DTR (Bit 10) */
#define UART0_CR_DTR_Msk (0x400UL) /*!< DTR (Bitfield-Mask: 0x01) */
#define UART0_CR_RXE_Pos (9UL) /*!< RXE (Bit 9) */
#define UART0_CR_RXE_Msk (0x200UL) /*!< RXE (Bitfield-Mask: 0x01) */
#define UART0_CR_TXE_Pos (8UL) /*!< TXE (Bit 8) */
#define UART0_CR_TXE_Msk (0x100UL) /*!< TXE (Bitfield-Mask: 0x01) */
#define UART0_CR_LBE_Pos (7UL) /*!< LBE (Bit 7) */
#define UART0_CR_LBE_Msk (0x80UL) /*!< LBE (Bitfield-Mask: 0x01) */
#define UART0_CR_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */
#define UART0_CR_CLKSEL_Msk (0x70UL) /*!< CLKSEL (Bitfield-Mask: 0x07) */
#define UART0_CR_CLKEN_Pos (3UL) /*!< CLKEN (Bit 3) */
#define UART0_CR_CLKEN_Msk (0x8UL) /*!< CLKEN (Bitfield-Mask: 0x01) */
#define UART0_CR_SIRLP_Pos (2UL) /*!< SIRLP (Bit 2) */
#define UART0_CR_SIRLP_Msk (0x4UL) /*!< SIRLP (Bitfield-Mask: 0x01) */
#define UART0_CR_SIREN_Pos (1UL) /*!< SIREN (Bit 1) */
#define UART0_CR_SIREN_Msk (0x2UL) /*!< SIREN (Bitfield-Mask: 0x01) */
#define UART0_CR_UARTEN_Pos (0UL) /*!< UARTEN (Bit 0) */
#define UART0_CR_UARTEN_Msk (0x1UL) /*!< UARTEN (Bitfield-Mask: 0x01) */
/* ========================================================= IFLS ========================================================== */
#define UART0_IFLS_RXIFLSEL_Pos (3UL) /*!< RXIFLSEL (Bit 3) */
#define UART0_IFLS_RXIFLSEL_Msk (0x38UL) /*!< RXIFLSEL (Bitfield-Mask: 0x07) */
#define UART0_IFLS_TXIFLSEL_Pos (0UL) /*!< TXIFLSEL (Bit 0) */
#define UART0_IFLS_TXIFLSEL_Msk (0x7UL) /*!< TXIFLSEL (Bitfield-Mask: 0x07) */
/* ========================================================== IER ========================================================== */
#define UART0_IER_OEIM_Pos (10UL) /*!< OEIM (Bit 10) */
#define UART0_IER_OEIM_Msk (0x400UL) /*!< OEIM (Bitfield-Mask: 0x01) */
#define UART0_IER_BEIM_Pos (9UL) /*!< BEIM (Bit 9) */
#define UART0_IER_BEIM_Msk (0x200UL) /*!< BEIM (Bitfield-Mask: 0x01) */
#define UART0_IER_PEIM_Pos (8UL) /*!< PEIM (Bit 8) */
#define UART0_IER_PEIM_Msk (0x100UL) /*!< PEIM (Bitfield-Mask: 0x01) */
#define UART0_IER_FEIM_Pos (7UL) /*!< FEIM (Bit 7) */
#define UART0_IER_FEIM_Msk (0x80UL) /*!< FEIM (Bitfield-Mask: 0x01) */
#define UART0_IER_RTIM_Pos (6UL) /*!< RTIM (Bit 6) */
#define UART0_IER_RTIM_Msk (0x40UL) /*!< RTIM (Bitfield-Mask: 0x01) */
#define UART0_IER_TXIM_Pos (5UL) /*!< TXIM (Bit 5) */
#define UART0_IER_TXIM_Msk (0x20UL) /*!< TXIM (Bitfield-Mask: 0x01) */
#define UART0_IER_RXIM_Pos (4UL) /*!< RXIM (Bit 4) */
#define UART0_IER_RXIM_Msk (0x10UL) /*!< RXIM (Bitfield-Mask: 0x01) */
#define UART0_IER_DSRMIM_Pos (3UL) /*!< DSRMIM (Bit 3) */
#define UART0_IER_DSRMIM_Msk (0x8UL) /*!< DSRMIM (Bitfield-Mask: 0x01) */
#define UART0_IER_DCDMIM_Pos (2UL) /*!< DCDMIM (Bit 2) */
#define UART0_IER_DCDMIM_Msk (0x4UL) /*!< DCDMIM (Bitfield-Mask: 0x01) */
#define UART0_IER_CTSMIM_Pos (1UL) /*!< CTSMIM (Bit 1) */
#define UART0_IER_CTSMIM_Msk (0x2UL) /*!< CTSMIM (Bitfield-Mask: 0x01) */
#define UART0_IER_TXCMPMIM_Pos (0UL) /*!< TXCMPMIM (Bit 0) */
#define UART0_IER_TXCMPMIM_Msk (0x1UL) /*!< TXCMPMIM (Bitfield-Mask: 0x01) */
/* ========================================================== IES ========================================================== */
#define UART0_IES_OERIS_Pos (10UL) /*!< OERIS (Bit 10) */
#define UART0_IES_OERIS_Msk (0x400UL) /*!< OERIS (Bitfield-Mask: 0x01) */
#define UART0_IES_BERIS_Pos (9UL) /*!< BERIS (Bit 9) */
#define UART0_IES_BERIS_Msk (0x200UL) /*!< BERIS (Bitfield-Mask: 0x01) */
#define UART0_IES_PERIS_Pos (8UL) /*!< PERIS (Bit 8) */
#define UART0_IES_PERIS_Msk (0x100UL) /*!< PERIS (Bitfield-Mask: 0x01) */
#define UART0_IES_FERIS_Pos (7UL) /*!< FERIS (Bit 7) */
#define UART0_IES_FERIS_Msk (0x80UL) /*!< FERIS (Bitfield-Mask: 0x01) */
#define UART0_IES_RTRIS_Pos (6UL) /*!< RTRIS (Bit 6) */
#define UART0_IES_RTRIS_Msk (0x40UL) /*!< RTRIS (Bitfield-Mask: 0x01) */
#define UART0_IES_TXRIS_Pos (5UL) /*!< TXRIS (Bit 5) */
#define UART0_IES_TXRIS_Msk (0x20UL) /*!< TXRIS (Bitfield-Mask: 0x01) */
#define UART0_IES_RXRIS_Pos (4UL) /*!< RXRIS (Bit 4) */
#define UART0_IES_RXRIS_Msk (0x10UL) /*!< RXRIS (Bitfield-Mask: 0x01) */
#define UART0_IES_DSRMRIS_Pos (3UL) /*!< DSRMRIS (Bit 3) */
#define UART0_IES_DSRMRIS_Msk (0x8UL) /*!< DSRMRIS (Bitfield-Mask: 0x01) */
#define UART0_IES_DCDMRIS_Pos (2UL) /*!< DCDMRIS (Bit 2) */
#define UART0_IES_DCDMRIS_Msk (0x4UL) /*!< DCDMRIS (Bitfield-Mask: 0x01) */
#define UART0_IES_CTSMRIS_Pos (1UL) /*!< CTSMRIS (Bit 1) */
#define UART0_IES_CTSMRIS_Msk (0x2UL) /*!< CTSMRIS (Bitfield-Mask: 0x01) */
#define UART0_IES_TXCMPMRIS_Pos (0UL) /*!< TXCMPMRIS (Bit 0) */
#define UART0_IES_TXCMPMRIS_Msk (0x1UL) /*!< TXCMPMRIS (Bitfield-Mask: 0x01) */
/* ========================================================== MIS ========================================================== */
#define UART0_MIS_OEMIS_Pos (10UL) /*!< OEMIS (Bit 10) */
#define UART0_MIS_OEMIS_Msk (0x400UL) /*!< OEMIS (Bitfield-Mask: 0x01) */
#define UART0_MIS_BEMIS_Pos (9UL) /*!< BEMIS (Bit 9) */
#define UART0_MIS_BEMIS_Msk (0x200UL) /*!< BEMIS (Bitfield-Mask: 0x01) */
#define UART0_MIS_PEMIS_Pos (8UL) /*!< PEMIS (Bit 8) */
#define UART0_MIS_PEMIS_Msk (0x100UL) /*!< PEMIS (Bitfield-Mask: 0x01) */
#define UART0_MIS_FEMIS_Pos (7UL) /*!< FEMIS (Bit 7) */
#define UART0_MIS_FEMIS_Msk (0x80UL) /*!< FEMIS (Bitfield-Mask: 0x01) */
#define UART0_MIS_RTMIS_Pos (6UL) /*!< RTMIS (Bit 6) */
#define UART0_MIS_RTMIS_Msk (0x40UL) /*!< RTMIS (Bitfield-Mask: 0x01) */
#define UART0_MIS_TXMIS_Pos (5UL) /*!< TXMIS (Bit 5) */
#define UART0_MIS_TXMIS_Msk (0x20UL) /*!< TXMIS (Bitfield-Mask: 0x01) */
#define UART0_MIS_RXMIS_Pos (4UL) /*!< RXMIS (Bit 4) */
#define UART0_MIS_RXMIS_Msk (0x10UL) /*!< RXMIS (Bitfield-Mask: 0x01) */
#define UART0_MIS_DSRMMIS_Pos (3UL) /*!< DSRMMIS (Bit 3) */
#define UART0_MIS_DSRMMIS_Msk (0x8UL) /*!< DSRMMIS (Bitfield-Mask: 0x01) */
#define UART0_MIS_DCDMMIS_Pos (2UL) /*!< DCDMMIS (Bit 2) */
#define UART0_MIS_DCDMMIS_Msk (0x4UL) /*!< DCDMMIS (Bitfield-Mask: 0x01) */
#define UART0_MIS_CTSMMIS_Pos (1UL) /*!< CTSMMIS (Bit 1) */
#define UART0_MIS_CTSMMIS_Msk (0x2UL) /*!< CTSMMIS (Bitfield-Mask: 0x01) */
#define UART0_MIS_TXCMPMMIS_Pos (0UL) /*!< TXCMPMMIS (Bit 0) */
#define UART0_MIS_TXCMPMMIS_Msk (0x1UL) /*!< TXCMPMMIS (Bitfield-Mask: 0x01) */
/* ========================================================== IEC ========================================================== */
#define UART0_IEC_OEIC_Pos (10UL) /*!< OEIC (Bit 10) */
#define UART0_IEC_OEIC_Msk (0x400UL) /*!< OEIC (Bitfield-Mask: 0x01) */
#define UART0_IEC_BEIC_Pos (9UL) /*!< BEIC (Bit 9) */
#define UART0_IEC_BEIC_Msk (0x200UL) /*!< BEIC (Bitfield-Mask: 0x01) */
#define UART0_IEC_PEIC_Pos (8UL) /*!< PEIC (Bit 8) */
#define UART0_IEC_PEIC_Msk (0x100UL) /*!< PEIC (Bitfield-Mask: 0x01) */
#define UART0_IEC_FEIC_Pos (7UL) /*!< FEIC (Bit 7) */
#define UART0_IEC_FEIC_Msk (0x80UL) /*!< FEIC (Bitfield-Mask: 0x01) */
#define UART0_IEC_RTIC_Pos (6UL) /*!< RTIC (Bit 6) */
#define UART0_IEC_RTIC_Msk (0x40UL) /*!< RTIC (Bitfield-Mask: 0x01) */
#define UART0_IEC_TXIC_Pos (5UL) /*!< TXIC (Bit 5) */
#define UART0_IEC_TXIC_Msk (0x20UL) /*!< TXIC (Bitfield-Mask: 0x01) */
#define UART0_IEC_RXIC_Pos (4UL) /*!< RXIC (Bit 4) */
#define UART0_IEC_RXIC_Msk (0x10UL) /*!< RXIC (Bitfield-Mask: 0x01) */
#define UART0_IEC_DSRMIC_Pos (3UL) /*!< DSRMIC (Bit 3) */
#define UART0_IEC_DSRMIC_Msk (0x8UL) /*!< DSRMIC (Bitfield-Mask: 0x01) */
#define UART0_IEC_DCDMIC_Pos (2UL) /*!< DCDMIC (Bit 2) */
#define UART0_IEC_DCDMIC_Msk (0x4UL) /*!< DCDMIC (Bitfield-Mask: 0x01) */
#define UART0_IEC_CTSMIC_Pos (1UL) /*!< CTSMIC (Bit 1) */
#define UART0_IEC_CTSMIC_Msk (0x2UL) /*!< CTSMIC (Bitfield-Mask: 0x01) */
#define UART0_IEC_TXCMPMIC_Pos (0UL) /*!< TXCMPMIC (Bit 0) */
#define UART0_IEC_TXCMPMIC_Msk (0x1UL) /*!< TXCMPMIC (Bitfield-Mask: 0x01) */
/* =========================================================================================================================== */
/* ================ VCOMP ================ */
/* =========================================================================================================================== */
/* ========================================================== CFG ========================================================== */
#define VCOMP_CFG_LVLSEL_Pos (16UL) /*!< LVLSEL (Bit 16) */
#define VCOMP_CFG_LVLSEL_Msk (0xf0000UL) /*!< LVLSEL (Bitfield-Mask: 0x0f) */
#define VCOMP_CFG_NSEL_Pos (8UL) /*!< NSEL (Bit 8) */
#define VCOMP_CFG_NSEL_Msk (0x300UL) /*!< NSEL (Bitfield-Mask: 0x03) */
#define VCOMP_CFG_PSEL_Pos (0UL) /*!< PSEL (Bit 0) */
#define VCOMP_CFG_PSEL_Msk (0x3UL) /*!< PSEL (Bitfield-Mask: 0x03) */
/* ========================================================= STAT ========================================================== */
#define VCOMP_STAT_PWDSTAT_Pos (1UL) /*!< PWDSTAT (Bit 1) */
#define VCOMP_STAT_PWDSTAT_Msk (0x2UL) /*!< PWDSTAT (Bitfield-Mask: 0x01) */
#define VCOMP_STAT_CMPOUT_Pos (0UL) /*!< CMPOUT (Bit 0) */
#define VCOMP_STAT_CMPOUT_Msk (0x1UL) /*!< CMPOUT (Bitfield-Mask: 0x01) */
/* ======================================================== PWDKEY ========================================================= */
#define VCOMP_PWDKEY_PWDKEY_Pos (0UL) /*!< PWDKEY (Bit 0) */
#define VCOMP_PWDKEY_PWDKEY_Msk (0xffffffffUL) /*!< PWDKEY (Bitfield-Mask: 0xffffffff) */
/* ========================================================= INTEN ========================================================= */
#define VCOMP_INTEN_OUTHI_Pos (1UL) /*!< OUTHI (Bit 1) */
#define VCOMP_INTEN_OUTHI_Msk (0x2UL) /*!< OUTHI (Bitfield-Mask: 0x01) */
#define VCOMP_INTEN_OUTLOW_Pos (0UL) /*!< OUTLOW (Bit 0) */
#define VCOMP_INTEN_OUTLOW_Msk (0x1UL) /*!< OUTLOW (Bitfield-Mask: 0x01) */
/* ======================================================== INTSTAT ======================================================== */
#define VCOMP_INTSTAT_OUTHI_Pos (1UL) /*!< OUTHI (Bit 1) */
#define VCOMP_INTSTAT_OUTHI_Msk (0x2UL) /*!< OUTHI (Bitfield-Mask: 0x01) */
#define VCOMP_INTSTAT_OUTLOW_Pos (0UL) /*!< OUTLOW (Bit 0) */
#define VCOMP_INTSTAT_OUTLOW_Msk (0x1UL) /*!< OUTLOW (Bitfield-Mask: 0x01) */
/* ======================================================== INTCLR ========================================================= */
#define VCOMP_INTCLR_OUTHI_Pos (1UL) /*!< OUTHI (Bit 1) */
#define VCOMP_INTCLR_OUTHI_Msk (0x2UL) /*!< OUTHI (Bitfield-Mask: 0x01) */
#define VCOMP_INTCLR_OUTLOW_Pos (0UL) /*!< OUTLOW (Bit 0) */
#define VCOMP_INTCLR_OUTLOW_Msk (0x1UL) /*!< OUTLOW (Bitfield-Mask: 0x01) */
/* ======================================================== INTSET ========================================================= */
#define VCOMP_INTSET_OUTHI_Pos (1UL) /*!< OUTHI (Bit 1) */
#define VCOMP_INTSET_OUTHI_Msk (0x2UL) /*!< OUTHI (Bitfield-Mask: 0x01) */
#define VCOMP_INTSET_OUTLOW_Pos (0UL) /*!< OUTLOW (Bit 0) */
#define VCOMP_INTSET_OUTLOW_Msk (0x1UL) /*!< OUTLOW (Bitfield-Mask: 0x01) */
/* =========================================================================================================================== */
/* ================ WDT ================ */
/* =========================================================================================================================== */
/* ========================================================== CFG ========================================================== */
#define WDT_CFG_CLKSEL_Pos (24UL) /*!< CLKSEL (Bit 24) */
#define WDT_CFG_CLKSEL_Msk (0x7000000UL) /*!< CLKSEL (Bitfield-Mask: 0x07) */
#define WDT_CFG_INTVAL_Pos (16UL) /*!< INTVAL (Bit 16) */
#define WDT_CFG_INTVAL_Msk (0xff0000UL) /*!< INTVAL (Bitfield-Mask: 0xff) */
#define WDT_CFG_RESVAL_Pos (8UL) /*!< RESVAL (Bit 8) */
#define WDT_CFG_RESVAL_Msk (0xff00UL) /*!< RESVAL (Bitfield-Mask: 0xff) */
#define WDT_CFG_RESEN_Pos (2UL) /*!< RESEN (Bit 2) */
#define WDT_CFG_RESEN_Msk (0x4UL) /*!< RESEN (Bitfield-Mask: 0x01) */
#define WDT_CFG_INTEN_Pos (1UL) /*!< INTEN (Bit 1) */
#define WDT_CFG_INTEN_Msk (0x2UL) /*!< INTEN (Bitfield-Mask: 0x01) */
#define WDT_CFG_WDTEN_Pos (0UL) /*!< WDTEN (Bit 0) */
#define WDT_CFG_WDTEN_Msk (0x1UL) /*!< WDTEN (Bitfield-Mask: 0x01) */
/* ========================================================= RSTRT ========================================================= */
#define WDT_RSTRT_RSTRT_Pos (0UL) /*!< RSTRT (Bit 0) */
#define WDT_RSTRT_RSTRT_Msk (0xffUL) /*!< RSTRT (Bitfield-Mask: 0xff) */
/* ========================================================= LOCK ========================================================== */
#define WDT_LOCK_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */
#define WDT_LOCK_LOCK_Msk (0xffUL) /*!< LOCK (Bitfield-Mask: 0xff) */
/* ========================================================= COUNT ========================================================= */
#define WDT_COUNT_COUNT_Pos (0UL) /*!< COUNT (Bit 0) */
#define WDT_COUNT_COUNT_Msk (0xffUL) /*!< COUNT (Bitfield-Mask: 0xff) */
/* ========================================================= INTEN ========================================================= */
#define WDT_INTEN_WDTINT_Pos (0UL) /*!< WDTINT (Bit 0) */
#define WDT_INTEN_WDTINT_Msk (0x1UL) /*!< WDTINT (Bitfield-Mask: 0x01) */
/* ======================================================== INTSTAT ======================================================== */
#define WDT_INTSTAT_WDTINT_Pos (0UL) /*!< WDTINT (Bit 0) */
#define WDT_INTSTAT_WDTINT_Msk (0x1UL) /*!< WDTINT (Bitfield-Mask: 0x01) */
/* ======================================================== INTCLR ========================================================= */
#define WDT_INTCLR_WDTINT_Pos (0UL) /*!< WDTINT (Bit 0) */
#define WDT_INTCLR_WDTINT_Msk (0x1UL) /*!< WDTINT (Bitfield-Mask: 0x01) */
/* ======================================================== INTSET ========================================================= */
#define WDT_INTSET_WDTINT_Pos (0UL) /*!< WDTINT (Bit 0) */
#define WDT_INTSET_WDTINT_Msk (0x1UL) /*!< WDTINT (Bitfield-Mask: 0x01) */
/** @} */ /* End of group PosMask_peripherals */
/* =========================================================================================================================== */
/* ================ Enumerated Values Peripheral Section ================ */
/* =========================================================================================================================== */
/** @addtogroup EnumValue_peripherals
* @{
*/
/* =========================================================================================================================== */
/* ================ ADC ================ */
/* =========================================================================================================================== */
/* ========================================================== CFG ========================================================== */
/* ================================================ ADC CFG CLKSEL [24..25] ================================================ */
typedef enum { /*!< ADC_CFG_CLKSEL */
ADC_CFG_CLKSEL_OFF = 0, /*!< OFF : Off mode. The HFRC or HFRC_DIV2 clock must be selected
for the ADC to function. The ADC controller automatically
shuts off the clock in it's low power modes. When setting
ADCEN to '0', the CLKSEL should remain set to one of the
two clock selects for proper power down sequencing. */
ADC_CFG_CLKSEL_HFRC = 1, /*!< HFRC : HFRC Core Clock divided by (CORESEL+1) */
ADC_CFG_CLKSEL_HFRC_DIV2 = 2, /*!< HFRC_DIV2 : HFRC Core Clock / 2 further divided by (CORESEL+1) */
} ADC_CFG_CLKSEL_Enum;
/* =============================================== ADC CFG TRIGPOL [19..19] ================================================ */
typedef enum { /*!< ADC_CFG_TRIGPOL */
ADC_CFG_TRIGPOL_RISING_EDGE = 0, /*!< RISING_EDGE : Trigger on rising edge. */
ADC_CFG_TRIGPOL_FALLING_EDGE = 1, /*!< FALLING_EDGE : Trigger on falling edge. */
} ADC_CFG_TRIGPOL_Enum;
/* =============================================== ADC CFG TRIGSEL [16..18] ================================================ */
typedef enum { /*!< ADC_CFG_TRIGSEL */
ADC_CFG_TRIGSEL_EXT0 = 0, /*!< EXT0 : Off chip External Trigger0 (ADC_ET0) */
ADC_CFG_TRIGSEL_EXT1 = 1, /*!< EXT1 : Off chip External Trigger1 (ADC_ET1) */
ADC_CFG_TRIGSEL_EXT2 = 2, /*!< EXT2 : Off chip External Trigger2 (ADC_ET2) */
ADC_CFG_TRIGSEL_EXT3 = 3, /*!< EXT3 : Off chip External Trigger3 (ADC_ET3) */
ADC_CFG_TRIGSEL_VCOMP = 4, /*!< VCOMP : Voltage Comparator Output */
ADC_CFG_TRIGSEL_SWT = 7, /*!< SWT : Software Trigger */
} ADC_CFG_TRIGSEL_Enum;
/* ============================================== ADC CFG DFIFORDEN [12..12] =============================================== */
typedef enum { /*!< ADC_CFG_DFIFORDEN */
ADC_CFG_DFIFORDEN_DIS = 0, /*!< DIS : Destructive Reads are prevented. Reads to the FIFOPR register
will not POP an entry off the FIFO. */
ADC_CFG_DFIFORDEN_EN = 1, /*!< EN : Reads to the FIFOPR registger will automatically pop an
entry off the FIFO. */
} ADC_CFG_DFIFORDEN_Enum;
/* ================================================= ADC CFG REFSEL [8..9] ================================================= */
typedef enum { /*!< ADC_CFG_REFSEL */
ADC_CFG_REFSEL_INT2P0 = 0, /*!< INT2P0 : Internal 2.0V Bandgap Reference Voltage */
ADC_CFG_REFSEL_INT1P5 = 1, /*!< INT1P5 : Internal 1.5V Bandgap Reference Voltage */
ADC_CFG_REFSEL_EXT2P0 = 2, /*!< EXT2P0 : Off Chip 2.0V Reference */
ADC_CFG_REFSEL_EXT1P5 = 3, /*!< EXT1P5 : Off Chip 1.5V Reference */
} ADC_CFG_REFSEL_Enum;
/* ================================================= ADC CFG CKMODE [4..4] ================================================= */
typedef enum { /*!< ADC_CFG_CKMODE */
ADC_CFG_CKMODE_LPCKMODE = 0, /*!< LPCKMODE : Disable the clock between scans for LPMODE0. Set
LPCKMODE to 0x1 while configuring the ADC. */
ADC_CFG_CKMODE_LLCKMODE = 1, /*!< LLCKMODE : Low Latency Clock Mode. When set, HFRC and the adc_clk
will remain on while in functioning in LPMODE0. */
} ADC_CFG_CKMODE_Enum;
/* ================================================= ADC CFG LPMODE [3..3] ================================================= */
typedef enum { /*!< ADC_CFG_LPMODE */
ADC_CFG_LPMODE_MODE0 = 0, /*!< MODE0 : Low Power Mode 0. Leaves the ADC fully powered between
scans with minimum latency between a trigger event and
sample data collection. */
ADC_CFG_LPMODE_MODE1 = 1, /*!< MODE1 : Low Power Mode 1. Powers down all circuity and clocks
associated with the ADC until the next trigger event. Between
scans, the reference buffer requires up to 50us of delay
from a scan trigger event before the conversion will commence
while operating in this mode. */
} ADC_CFG_LPMODE_Enum;
/* ================================================= ADC CFG RPTEN [2..2] ================================================== */
typedef enum { /*!< ADC_CFG_RPTEN */
ADC_CFG_RPTEN_SINGLE_SCAN = 0, /*!< SINGLE_SCAN : In Single Scan Mode, the ADC will complete a single
scan upon each trigger event. */
ADC_CFG_RPTEN_REPEATING_SCAN = 1, /*!< REPEATING_SCAN : In Repeating Scan Mode, the ADC will complete
it's first scan upon the initial trigger event and all
subsequent scans will occur at regular intervals defined
by the configuration programmed for the CTTMRA3 internal
timer until the timer is disabled or the ADC is disabled.
When disabling the ADC (setting ADCEN to '0'), the RPTEN
bit should be cleared. */
} ADC_CFG_RPTEN_Enum;
/* ================================================= ADC CFG ADCEN [0..0] ================================================== */
typedef enum { /*!< ADC_CFG_ADCEN */
ADC_CFG_ADCEN_DIS = 0, /*!< DIS : Disable the ADC module. */
ADC_CFG_ADCEN_EN = 1, /*!< EN : Enable the ADC module. */
} ADC_CFG_ADCEN_Enum;
/* ========================================================= STAT ========================================================== */
/* ================================================ ADC STAT PWDSTAT [0..0] ================================================ */
typedef enum { /*!< ADC_STAT_PWDSTAT */
ADC_STAT_PWDSTAT_ON = 0, /*!< ON : Powered on. */
ADC_STAT_PWDSTAT_POWERED_DOWN = 1, /*!< POWERED_DOWN : ADC Low Power Mode 1. */
} ADC_STAT_PWDSTAT_Enum;
/* ========================================================== SWT ========================================================== */
/* ================================================== ADC SWT SWT [0..7] =================================================== */
typedef enum { /*!< ADC_SWT_SWT */
ADC_SWT_SWT_GEN_SW_TRIGGER = 55, /*!< GEN_SW_TRIGGER : Writing this value generates a software trigger. */
} ADC_SWT_SWT_Enum;
/* ======================================================== SL0CFG ========================================================= */
/* ============================================== ADC SL0CFG ADSEL0 [24..26] =============================================== */
typedef enum { /*!< ADC_SL0CFG_ADSEL0 */
ADC_SL0CFG_ADSEL0_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
module for this slot. */
ADC_SL0CFG_ADSEL0_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
module for this slot. */
ADC_SL0CFG_ADSEL0_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
module for this slot. */
ADC_SL0CFG_ADSEL0_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
module for this slot. */
ADC_SL0CFG_ADSEL0_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
divide module for this slot. */
ADC_SL0CFG_ADSEL0_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
divide module for this slot. */
ADC_SL0CFG_ADSEL0_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
divide module for this slot. */
ADC_SL0CFG_ADSEL0_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
divide module for this slot. */
} ADC_SL0CFG_ADSEL0_Enum;
/* ============================================== ADC SL0CFG PRMODE0 [16..17] ============================================== */
typedef enum { /*!< ADC_SL0CFG_PRMODE0 */
ADC_SL0CFG_PRMODE0_P14B = 0, /*!< P14B : 14-bit precision mode */
ADC_SL0CFG_PRMODE0_P12B = 1, /*!< P12B : 12-bit precision mode */
ADC_SL0CFG_PRMODE0_P10B = 2, /*!< P10B : 10-bit precision mode */
ADC_SL0CFG_PRMODE0_P8B = 3, /*!< P8B : 8-bit precision mode */
} ADC_SL0CFG_PRMODE0_Enum;
/* =============================================== ADC SL0CFG CHSEL0 [8..11] =============================================== */
typedef enum { /*!< ADC_SL0CFG_CHSEL0 */
ADC_SL0CFG_CHSEL0_SE0 = 0, /*!< SE0 : single ended external GPIO connection to pad16. */
ADC_SL0CFG_CHSEL0_SE1 = 1, /*!< SE1 : single ended external GPIO connection to pad29. */
ADC_SL0CFG_CHSEL0_SE2 = 2, /*!< SE2 : single ended external GPIO connection to pad11. */
ADC_SL0CFG_CHSEL0_SE3 = 3, /*!< SE3 : single ended external GPIO connection to pad31. */
ADC_SL0CFG_CHSEL0_SE4 = 4, /*!< SE4 : single ended external GPIO connection to pad32. */
ADC_SL0CFG_CHSEL0_SE5 = 5, /*!< SE5 : single ended external GPIO connection to pad33. */
ADC_SL0CFG_CHSEL0_SE6 = 6, /*!< SE6 : single ended external GPIO connection to pad34. */
ADC_SL0CFG_CHSEL0_SE7 = 7, /*!< SE7 : single ended external GPIO connection to pad35. */
ADC_SL0CFG_CHSEL0_SE8 = 8, /*!< SE8 : single ended external GPIO connection to pad13. */
ADC_SL0CFG_CHSEL0_SE9 = 9, /*!< SE9 : single ended external GPIO connection to pad12. */
ADC_SL0CFG_CHSEL0_DF0 = 10, /*!< DF0 : differential external GPIO connections to pad12(N) and
pad13(P). */
ADC_SL0CFG_CHSEL0_DF1 = 11, /*!< DF1 : differential external GPIO connections to pad15(N) and
pad14(P). */
ADC_SL0CFG_CHSEL0_TEMP = 12, /*!< TEMP : internal temperature sensor. */
ADC_SL0CFG_CHSEL0_BATT = 13, /*!< BATT : internal voltage divide-by-3 connection. */
ADC_SL0CFG_CHSEL0_VSS = 14, /*!< VSS : Input VSS */
} ADC_SL0CFG_CHSEL0_Enum;
/* ================================================ ADC SL0CFG WCEN0 [1..1] ================================================ */
typedef enum { /*!< ADC_SL0CFG_WCEN0 */
ADC_SL0CFG_WCEN0_WCEN = 1, /*!< WCEN : Enable the window compare for slot 0. */
} ADC_SL0CFG_WCEN0_Enum;
/* ================================================ ADC SL0CFG SLEN0 [0..0] ================================================ */
typedef enum { /*!< ADC_SL0CFG_SLEN0 */
ADC_SL0CFG_SLEN0_SLEN = 1, /*!< SLEN : Enable slot 0 for ADC conversions. */
} ADC_SL0CFG_SLEN0_Enum;
/* ======================================================== SL1CFG ========================================================= */
/* ============================================== ADC SL1CFG ADSEL1 [24..26] =============================================== */
typedef enum { /*!< ADC_SL1CFG_ADSEL1 */
ADC_SL1CFG_ADSEL1_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
module for this slot. */
ADC_SL1CFG_ADSEL1_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
module for this slot. */
ADC_SL1CFG_ADSEL1_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
module for this slot. */
ADC_SL1CFG_ADSEL1_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
module for this slot. */
ADC_SL1CFG_ADSEL1_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
divide module for this slot. */
ADC_SL1CFG_ADSEL1_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
divide module for this slot. */
ADC_SL1CFG_ADSEL1_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
divide module for this slot. */
ADC_SL1CFG_ADSEL1_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
divide module for this slot. */
} ADC_SL1CFG_ADSEL1_Enum;
/* ============================================== ADC SL1CFG PRMODE1 [16..17] ============================================== */
typedef enum { /*!< ADC_SL1CFG_PRMODE1 */
ADC_SL1CFG_PRMODE1_P14B = 0, /*!< P14B : 14-bit precision mode */
ADC_SL1CFG_PRMODE1_P12B = 1, /*!< P12B : 12-bit precision mode */
ADC_SL1CFG_PRMODE1_P10B = 2, /*!< P10B : 10-bit precision mode */
ADC_SL1CFG_PRMODE1_P8B = 3, /*!< P8B : 8-bit precision mode */
} ADC_SL1CFG_PRMODE1_Enum;
/* =============================================== ADC SL1CFG CHSEL1 [8..11] =============================================== */
typedef enum { /*!< ADC_SL1CFG_CHSEL1 */
ADC_SL1CFG_CHSEL1_SE0 = 0, /*!< SE0 : single ended external GPIO connection to pad16. */
ADC_SL1CFG_CHSEL1_SE1 = 1, /*!< SE1 : single ended external GPIO connection to pad29. */
ADC_SL1CFG_CHSEL1_SE2 = 2, /*!< SE2 : single ended external GPIO connection to pad11. */
ADC_SL1CFG_CHSEL1_SE3 = 3, /*!< SE3 : single ended external GPIO connection to pad31. */
ADC_SL1CFG_CHSEL1_SE4 = 4, /*!< SE4 : single ended external GPIO connection to pad32. */
ADC_SL1CFG_CHSEL1_SE5 = 5, /*!< SE5 : single ended external GPIO connection to pad33. */
ADC_SL1CFG_CHSEL1_SE6 = 6, /*!< SE6 : single ended external GPIO connection to pad34. */
ADC_SL1CFG_CHSEL1_SE7 = 7, /*!< SE7 : single ended external GPIO connection to pad35. */
ADC_SL1CFG_CHSEL1_SE8 = 8, /*!< SE8 : single ended external GPIO connection to pad13. */
ADC_SL1CFG_CHSEL1_SE9 = 9, /*!< SE9 : single ended external GPIO connection to pad12. */
ADC_SL1CFG_CHSEL1_DF0 = 10, /*!< DF0 : differential external GPIO connections to pad12(N) and
pad13(P). */
ADC_SL1CFG_CHSEL1_DF1 = 11, /*!< DF1 : differential external GPIO connections to pad15(N) and
pad14(P). */
ADC_SL1CFG_CHSEL1_TEMP = 12, /*!< TEMP : internal temperature sensor. */
ADC_SL1CFG_CHSEL1_BATT = 13, /*!< BATT : internal voltage divide-by-3 connection. */
ADC_SL1CFG_CHSEL1_VSS = 14, /*!< VSS : Input VSS */
} ADC_SL1CFG_CHSEL1_Enum;
/* ================================================ ADC SL1CFG WCEN1 [1..1] ================================================ */
typedef enum { /*!< ADC_SL1CFG_WCEN1 */
ADC_SL1CFG_WCEN1_WCEN = 1, /*!< WCEN : Enable the window compare for slot 1. */
} ADC_SL1CFG_WCEN1_Enum;
/* ================================================ ADC SL1CFG SLEN1 [0..0] ================================================ */
typedef enum { /*!< ADC_SL1CFG_SLEN1 */
ADC_SL1CFG_SLEN1_SLEN = 1, /*!< SLEN : Enable slot 1 for ADC conversions. */
} ADC_SL1CFG_SLEN1_Enum;
/* ======================================================== SL2CFG ========================================================= */
/* ============================================== ADC SL2CFG ADSEL2 [24..26] =============================================== */
typedef enum { /*!< ADC_SL2CFG_ADSEL2 */
ADC_SL2CFG_ADSEL2_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
module for this slot. */
ADC_SL2CFG_ADSEL2_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
module for this slot. */
ADC_SL2CFG_ADSEL2_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
module for this slot. */
ADC_SL2CFG_ADSEL2_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
module for this slot. */
ADC_SL2CFG_ADSEL2_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
divide module for this slot. */
ADC_SL2CFG_ADSEL2_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
divide module for this slot. */
ADC_SL2CFG_ADSEL2_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
divide module for this slot. */
ADC_SL2CFG_ADSEL2_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
divide module for this slot. */
} ADC_SL2CFG_ADSEL2_Enum;
/* ============================================== ADC SL2CFG PRMODE2 [16..17] ============================================== */
typedef enum { /*!< ADC_SL2CFG_PRMODE2 */
ADC_SL2CFG_PRMODE2_P14B = 0, /*!< P14B : 14-bit precision mode */
ADC_SL2CFG_PRMODE2_P12B = 1, /*!< P12B : 12-bit precision mode */
ADC_SL2CFG_PRMODE2_P10B = 2, /*!< P10B : 10-bit precision mode */
ADC_SL2CFG_PRMODE2_P8B = 3, /*!< P8B : 8-bit precision mode */
} ADC_SL2CFG_PRMODE2_Enum;
/* =============================================== ADC SL2CFG CHSEL2 [8..11] =============================================== */
typedef enum { /*!< ADC_SL2CFG_CHSEL2 */
ADC_SL2CFG_CHSEL2_SE0 = 0, /*!< SE0 : single ended external GPIO connection to pad16. */
ADC_SL2CFG_CHSEL2_SE1 = 1, /*!< SE1 : single ended external GPIO connection to pad29. */
ADC_SL2CFG_CHSEL2_SE2 = 2, /*!< SE2 : single ended external GPIO connection to pad11. */
ADC_SL2CFG_CHSEL2_SE3 = 3, /*!< SE3 : single ended external GPIO connection to pad31. */
ADC_SL2CFG_CHSEL2_SE4 = 4, /*!< SE4 : single ended external GPIO connection to pad32. */
ADC_SL2CFG_CHSEL2_SE5 = 5, /*!< SE5 : single ended external GPIO connection to pad33. */
ADC_SL2CFG_CHSEL2_SE6 = 6, /*!< SE6 : single ended external GPIO connection to pad34. */
ADC_SL2CFG_CHSEL2_SE7 = 7, /*!< SE7 : single ended external GPIO connection to pad35. */
ADC_SL2CFG_CHSEL2_SE8 = 8, /*!< SE8 : single ended external GPIO connection to pad13. */
ADC_SL2CFG_CHSEL2_SE9 = 9, /*!< SE9 : single ended external GPIO connection to pad12. */
ADC_SL2CFG_CHSEL2_DF0 = 10, /*!< DF0 : differential external GPIO connections to pad12(N) and
pad13(P). */
ADC_SL2CFG_CHSEL2_DF1 = 11, /*!< DF1 : differential external GPIO connections to pad15(N) and
pad14(P). */
ADC_SL2CFG_CHSEL2_TEMP = 12, /*!< TEMP : internal temperature sensor. */
ADC_SL2CFG_CHSEL2_BATT = 13, /*!< BATT : internal voltage divide-by-3 connection. */
ADC_SL2CFG_CHSEL2_VSS = 14, /*!< VSS : Input VSS */
} ADC_SL2CFG_CHSEL2_Enum;
/* ================================================ ADC SL2CFG WCEN2 [1..1] ================================================ */
typedef enum { /*!< ADC_SL2CFG_WCEN2 */
ADC_SL2CFG_WCEN2_WCEN = 1, /*!< WCEN : Enable the window compare for slot 2. */
} ADC_SL2CFG_WCEN2_Enum;
/* ================================================ ADC SL2CFG SLEN2 [0..0] ================================================ */
typedef enum { /*!< ADC_SL2CFG_SLEN2 */
ADC_SL2CFG_SLEN2_SLEN = 1, /*!< SLEN : Enable slot 2 for ADC conversions. */
} ADC_SL2CFG_SLEN2_Enum;
/* ======================================================== SL3CFG ========================================================= */
/* ============================================== ADC SL3CFG ADSEL3 [24..26] =============================================== */
typedef enum { /*!< ADC_SL3CFG_ADSEL3 */
ADC_SL3CFG_ADSEL3_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
module for this slot. */
ADC_SL3CFG_ADSEL3_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
module for this slot. */
ADC_SL3CFG_ADSEL3_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
module for this slot. */
ADC_SL3CFG_ADSEL3_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
module for this slot. */
ADC_SL3CFG_ADSEL3_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
divide module for this slot. */
ADC_SL3CFG_ADSEL3_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
divide module for this slot. */
ADC_SL3CFG_ADSEL3_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
divide module for this slot. */
ADC_SL3CFG_ADSEL3_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
divide module for this slot. */
} ADC_SL3CFG_ADSEL3_Enum;
/* ============================================== ADC SL3CFG PRMODE3 [16..17] ============================================== */
typedef enum { /*!< ADC_SL3CFG_PRMODE3 */
ADC_SL3CFG_PRMODE3_P14B = 0, /*!< P14B : 14-bit precision mode */
ADC_SL3CFG_PRMODE3_P12B = 1, /*!< P12B : 12-bit precision mode */
ADC_SL3CFG_PRMODE3_P10B = 2, /*!< P10B : 10-bit precision mode */
ADC_SL3CFG_PRMODE3_P8B = 3, /*!< P8B : 8-bit precision mode */
} ADC_SL3CFG_PRMODE3_Enum;
/* =============================================== ADC SL3CFG CHSEL3 [8..11] =============================================== */
typedef enum { /*!< ADC_SL3CFG_CHSEL3 */
ADC_SL3CFG_CHSEL3_SE0 = 0, /*!< SE0 : single ended external GPIO connection to pad16. */
ADC_SL3CFG_CHSEL3_SE1 = 1, /*!< SE1 : single ended external GPIO connection to pad29. */
ADC_SL3CFG_CHSEL3_SE2 = 2, /*!< SE2 : single ended external GPIO connection to pad11. */
ADC_SL3CFG_CHSEL3_SE3 = 3, /*!< SE3 : single ended external GPIO connection to pad31. */
ADC_SL3CFG_CHSEL3_SE4 = 4, /*!< SE4 : single ended external GPIO connection to pad32. */
ADC_SL3CFG_CHSEL3_SE5 = 5, /*!< SE5 : single ended external GPIO connection to pad33. */
ADC_SL3CFG_CHSEL3_SE6 = 6, /*!< SE6 : single ended external GPIO connection to pad34. */
ADC_SL3CFG_CHSEL3_SE7 = 7, /*!< SE7 : single ended external GPIO connection to pad35. */
ADC_SL3CFG_CHSEL3_SE8 = 8, /*!< SE8 : single ended external GPIO connection to pad13. */
ADC_SL3CFG_CHSEL3_SE9 = 9, /*!< SE9 : single ended external GPIO connection to pad12. */
ADC_SL3CFG_CHSEL3_DF0 = 10, /*!< DF0 : differential external GPIO connections to pad12(N) and
pad13(P). */
ADC_SL3CFG_CHSEL3_DF1 = 11, /*!< DF1 : differential external GPIO connections to pad15(N) and
pad14(P). */
ADC_SL3CFG_CHSEL3_TEMP = 12, /*!< TEMP : internal temperature sensor. */
ADC_SL3CFG_CHSEL3_BATT = 13, /*!< BATT : internal voltage divide-by-3 connection. */
ADC_SL3CFG_CHSEL3_VSS = 14, /*!< VSS : Input VSS */
} ADC_SL3CFG_CHSEL3_Enum;
/* ================================================ ADC SL3CFG WCEN3 [1..1] ================================================ */
typedef enum { /*!< ADC_SL3CFG_WCEN3 */
ADC_SL3CFG_WCEN3_WCEN = 1, /*!< WCEN : Enable the window compare for slot 3. */
} ADC_SL3CFG_WCEN3_Enum;
/* ================================================ ADC SL3CFG SLEN3 [0..0] ================================================ */
typedef enum { /*!< ADC_SL3CFG_SLEN3 */
ADC_SL3CFG_SLEN3_SLEN = 1, /*!< SLEN : Enable slot 3 for ADC conversions. */
} ADC_SL3CFG_SLEN3_Enum;
/* ======================================================== SL4CFG ========================================================= */
/* ============================================== ADC SL4CFG ADSEL4 [24..26] =============================================== */
typedef enum { /*!< ADC_SL4CFG_ADSEL4 */
ADC_SL4CFG_ADSEL4_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
module for this slot. */
ADC_SL4CFG_ADSEL4_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
module for this slot. */
ADC_SL4CFG_ADSEL4_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
module for this slot. */
ADC_SL4CFG_ADSEL4_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
module for this slot. */
ADC_SL4CFG_ADSEL4_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
divide module for this slot. */
ADC_SL4CFG_ADSEL4_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
divide module for this slot. */
ADC_SL4CFG_ADSEL4_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
divide module for this slot. */
ADC_SL4CFG_ADSEL4_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
divide module for this slot. */
} ADC_SL4CFG_ADSEL4_Enum;
/* ============================================== ADC SL4CFG PRMODE4 [16..17] ============================================== */
typedef enum { /*!< ADC_SL4CFG_PRMODE4 */
ADC_SL4CFG_PRMODE4_P14B = 0, /*!< P14B : 14-bit precision mode */
ADC_SL4CFG_PRMODE4_P12B = 1, /*!< P12B : 12-bit precision mode */
ADC_SL4CFG_PRMODE4_P10B = 2, /*!< P10B : 10-bit precision mode */
ADC_SL4CFG_PRMODE4_P8B = 3, /*!< P8B : 8-bit precision mode */
} ADC_SL4CFG_PRMODE4_Enum;
/* =============================================== ADC SL4CFG CHSEL4 [8..11] =============================================== */
typedef enum { /*!< ADC_SL4CFG_CHSEL4 */
ADC_SL4CFG_CHSEL4_SE0 = 0, /*!< SE0 : single ended external GPIO connection to pad16. */
ADC_SL4CFG_CHSEL4_SE1 = 1, /*!< SE1 : single ended external GPIO connection to pad29. */
ADC_SL4CFG_CHSEL4_SE2 = 2, /*!< SE2 : single ended external GPIO connection to pad11. */
ADC_SL4CFG_CHSEL4_SE3 = 3, /*!< SE3 : single ended external GPIO connection to pad31. */
ADC_SL4CFG_CHSEL4_SE4 = 4, /*!< SE4 : single ended external GPIO connection to pad32. */
ADC_SL4CFG_CHSEL4_SE5 = 5, /*!< SE5 : single ended external GPIO connection to pad33. */
ADC_SL4CFG_CHSEL4_SE6 = 6, /*!< SE6 : single ended external GPIO connection to pad34. */
ADC_SL4CFG_CHSEL4_SE7 = 7, /*!< SE7 : single ended external GPIO connection to pad35. */
ADC_SL4CFG_CHSEL4_SE8 = 8, /*!< SE8 : single ended external GPIO connection to pad13. */
ADC_SL4CFG_CHSEL4_SE9 = 9, /*!< SE9 : single ended external GPIO connection to pad12. */
ADC_SL4CFG_CHSEL4_DF0 = 10, /*!< DF0 : differential external GPIO connections to pad12(N) and
pad13(P). */
ADC_SL4CFG_CHSEL4_DF1 = 11, /*!< DF1 : differential external GPIO connections to pad15(N) and
pad14(P). */
ADC_SL4CFG_CHSEL4_TEMP = 12, /*!< TEMP : internal temperature sensor. */
ADC_SL4CFG_CHSEL4_BATT = 13, /*!< BATT : internal voltage divide-by-3 connection. */
ADC_SL4CFG_CHSEL4_VSS = 14, /*!< VSS : Input VSS */
} ADC_SL4CFG_CHSEL4_Enum;
/* ================================================ ADC SL4CFG WCEN4 [1..1] ================================================ */
typedef enum { /*!< ADC_SL4CFG_WCEN4 */
ADC_SL4CFG_WCEN4_WCEN = 1, /*!< WCEN : Enable the window compare for slot 4. */
} ADC_SL4CFG_WCEN4_Enum;
/* ================================================ ADC SL4CFG SLEN4 [0..0] ================================================ */
typedef enum { /*!< ADC_SL4CFG_SLEN4 */
ADC_SL4CFG_SLEN4_SLEN = 1, /*!< SLEN : Enable slot 4 for ADC conversions. */
} ADC_SL4CFG_SLEN4_Enum;
/* ======================================================== SL5CFG ========================================================= */
/* ============================================== ADC SL5CFG ADSEL5 [24..26] =============================================== */
typedef enum { /*!< ADC_SL5CFG_ADSEL5 */
ADC_SL5CFG_ADSEL5_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
module for this slot. */
ADC_SL5CFG_ADSEL5_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
module for this slot. */
ADC_SL5CFG_ADSEL5_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
module for this slot. */
ADC_SL5CFG_ADSEL5_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
module for this slot. */
ADC_SL5CFG_ADSEL5_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
divide module for this slot. */
ADC_SL5CFG_ADSEL5_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
divide module for this slot. */
ADC_SL5CFG_ADSEL5_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
divide module for this slot. */
ADC_SL5CFG_ADSEL5_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
divide module for this slot. */
} ADC_SL5CFG_ADSEL5_Enum;
/* ============================================== ADC SL5CFG PRMODE5 [16..17] ============================================== */
typedef enum { /*!< ADC_SL5CFG_PRMODE5 */
ADC_SL5CFG_PRMODE5_P14B = 0, /*!< P14B : 14-bit precision mode */
ADC_SL5CFG_PRMODE5_P12B = 1, /*!< P12B : 12-bit precision mode */
ADC_SL5CFG_PRMODE5_P10B = 2, /*!< P10B : 10-bit precision mode */
ADC_SL5CFG_PRMODE5_P8B = 3, /*!< P8B : 8-bit precision mode */
} ADC_SL5CFG_PRMODE5_Enum;
/* =============================================== ADC SL5CFG CHSEL5 [8..11] =============================================== */
typedef enum { /*!< ADC_SL5CFG_CHSEL5 */
ADC_SL5CFG_CHSEL5_SE0 = 0, /*!< SE0 : single ended external GPIO connection to pad16. */
ADC_SL5CFG_CHSEL5_SE1 = 1, /*!< SE1 : single ended external GPIO connection to pad29. */
ADC_SL5CFG_CHSEL5_SE2 = 2, /*!< SE2 : single ended external GPIO connection to pad11. */
ADC_SL5CFG_CHSEL5_SE3 = 3, /*!< SE3 : single ended external GPIO connection to pad31. */
ADC_SL5CFG_CHSEL5_SE4 = 4, /*!< SE4 : single ended external GPIO connection to pad32. */
ADC_SL5CFG_CHSEL5_SE5 = 5, /*!< SE5 : single ended external GPIO connection to pad33. */
ADC_SL5CFG_CHSEL5_SE6 = 6, /*!< SE6 : single ended external GPIO connection to pad34. */
ADC_SL5CFG_CHSEL5_SE7 = 7, /*!< SE7 : single ended external GPIO connection to pad35. */
ADC_SL5CFG_CHSEL5_SE8 = 8, /*!< SE8 : single ended external GPIO connection to pad13. */
ADC_SL5CFG_CHSEL5_SE9 = 9, /*!< SE9 : single ended external GPIO connection to pad12. */
ADC_SL5CFG_CHSEL5_DF0 = 10, /*!< DF0 : differential external GPIO connections to pad12(N) and
pad13(P). */
ADC_SL5CFG_CHSEL5_DF1 = 11, /*!< DF1 : differential external GPIO connections to pad15(N) and
pad14(P). */
ADC_SL5CFG_CHSEL5_TEMP = 12, /*!< TEMP : internal temperature sensor. */
ADC_SL5CFG_CHSEL5_BATT = 13, /*!< BATT : internal voltage divide-by-3 connection. */
ADC_SL5CFG_CHSEL5_VSS = 14, /*!< VSS : Input VSS */
} ADC_SL5CFG_CHSEL5_Enum;
/* ================================================ ADC SL5CFG WCEN5 [1..1] ================================================ */
typedef enum { /*!< ADC_SL5CFG_WCEN5 */
ADC_SL5CFG_WCEN5_WCEN = 1, /*!< WCEN : Enable the window compare for slot 5. */
} ADC_SL5CFG_WCEN5_Enum;
/* ================================================ ADC SL5CFG SLEN5 [0..0] ================================================ */
typedef enum { /*!< ADC_SL5CFG_SLEN5 */
ADC_SL5CFG_SLEN5_SLEN = 1, /*!< SLEN : Enable slot 5 for ADC conversions. */
} ADC_SL5CFG_SLEN5_Enum;
/* ======================================================== SL6CFG ========================================================= */
/* ============================================== ADC SL6CFG ADSEL6 [24..26] =============================================== */
typedef enum { /*!< ADC_SL6CFG_ADSEL6 */
ADC_SL6CFG_ADSEL6_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
module for this slot. */
ADC_SL6CFG_ADSEL6_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
module for this slot. */
ADC_SL6CFG_ADSEL6_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
module for this slot. */
ADC_SL6CFG_ADSEL6_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
module for this slot. */
ADC_SL6CFG_ADSEL6_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
divide module for this slot. */
ADC_SL6CFG_ADSEL6_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
divide module for this slot. */
ADC_SL6CFG_ADSEL6_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
divide module for this slot. */
ADC_SL6CFG_ADSEL6_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
divide module for this slot. */
} ADC_SL6CFG_ADSEL6_Enum;
/* ============================================== ADC SL6CFG PRMODE6 [16..17] ============================================== */
typedef enum { /*!< ADC_SL6CFG_PRMODE6 */
ADC_SL6CFG_PRMODE6_P14B = 0, /*!< P14B : 14-bit precision mode */
ADC_SL6CFG_PRMODE6_P12B = 1, /*!< P12B : 12-bit precision mode */
ADC_SL6CFG_PRMODE6_P10B = 2, /*!< P10B : 10-bit precision mode */
ADC_SL6CFG_PRMODE6_P8B = 3, /*!< P8B : 8-bit precision mode */
} ADC_SL6CFG_PRMODE6_Enum;
/* =============================================== ADC SL6CFG CHSEL6 [8..11] =============================================== */
typedef enum { /*!< ADC_SL6CFG_CHSEL6 */
ADC_SL6CFG_CHSEL6_SE0 = 0, /*!< SE0 : single ended external GPIO connection to pad16. */
ADC_SL6CFG_CHSEL6_SE1 = 1, /*!< SE1 : single ended external GPIO connection to pad29. */
ADC_SL6CFG_CHSEL6_SE2 = 2, /*!< SE2 : single ended external GPIO connection to pad11. */
ADC_SL6CFG_CHSEL6_SE3 = 3, /*!< SE3 : single ended external GPIO connection to pad31. */
ADC_SL6CFG_CHSEL6_SE4 = 4, /*!< SE4 : single ended external GPIO connection to pad32. */
ADC_SL6CFG_CHSEL6_SE5 = 5, /*!< SE5 : single ended external GPIO connection to pad33. */
ADC_SL6CFG_CHSEL6_SE6 = 6, /*!< SE6 : single ended external GPIO connection to pad34. */
ADC_SL6CFG_CHSEL6_SE7 = 7, /*!< SE7 : single ended external GPIO connection to pad35. */
ADC_SL6CFG_CHSEL6_SE8 = 8, /*!< SE8 : single ended external GPIO connection to pad13. */
ADC_SL6CFG_CHSEL6_SE9 = 9, /*!< SE9 : single ended external GPIO connection to pad12. */
ADC_SL6CFG_CHSEL6_DF0 = 10, /*!< DF0 : differential external GPIO connections to pad12(N) and
pad13(P). */
ADC_SL6CFG_CHSEL6_DF1 = 11, /*!< DF1 : differential external GPIO connections to pad15(N) and
pad14(P). */
ADC_SL6CFG_CHSEL6_TEMP = 12, /*!< TEMP : internal temperature sensor. */
ADC_SL6CFG_CHSEL6_BATT = 13, /*!< BATT : internal voltage divide-by-3 connection. */
ADC_SL6CFG_CHSEL6_VSS = 14, /*!< VSS : Input VSS */
} ADC_SL6CFG_CHSEL6_Enum;
/* ================================================ ADC SL6CFG WCEN6 [1..1] ================================================ */
typedef enum { /*!< ADC_SL6CFG_WCEN6 */
ADC_SL6CFG_WCEN6_WCEN = 1, /*!< WCEN : Enable the window compare for slot 6. */
} ADC_SL6CFG_WCEN6_Enum;
/* ================================================ ADC SL6CFG SLEN6 [0..0] ================================================ */
typedef enum { /*!< ADC_SL6CFG_SLEN6 */
ADC_SL6CFG_SLEN6_SLEN = 1, /*!< SLEN : Enable slot 6 for ADC conversions. */
} ADC_SL6CFG_SLEN6_Enum;
/* ======================================================== SL7CFG ========================================================= */
/* ============================================== ADC SL7CFG ADSEL7 [24..26] =============================================== */
typedef enum { /*!< ADC_SL7CFG_ADSEL7 */
ADC_SL7CFG_ADSEL7_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
module for this slot. */
ADC_SL7CFG_ADSEL7_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
module for this slot. */
ADC_SL7CFG_ADSEL7_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
module for this slot. */
ADC_SL7CFG_ADSEL7_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
module for this slot. */
ADC_SL7CFG_ADSEL7_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
divide module for this slot. */
ADC_SL7CFG_ADSEL7_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
divide module for this slot. */
ADC_SL7CFG_ADSEL7_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
divide module for this slot. */
ADC_SL7CFG_ADSEL7_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
divide module for this slot. */
} ADC_SL7CFG_ADSEL7_Enum;
/* ============================================== ADC SL7CFG PRMODE7 [16..17] ============================================== */
typedef enum { /*!< ADC_SL7CFG_PRMODE7 */
ADC_SL7CFG_PRMODE7_P14B = 0, /*!< P14B : 14-bit precision mode */
ADC_SL7CFG_PRMODE7_P12B = 1, /*!< P12B : 12-bit precision mode */
ADC_SL7CFG_PRMODE7_P10B = 2, /*!< P10B : 10-bit precision mode */
ADC_SL7CFG_PRMODE7_P8B = 3, /*!< P8B : 8-bit precision mode */
} ADC_SL7CFG_PRMODE7_Enum;
/* =============================================== ADC SL7CFG CHSEL7 [8..11] =============================================== */
typedef enum { /*!< ADC_SL7CFG_CHSEL7 */
ADC_SL7CFG_CHSEL7_SE0 = 0, /*!< SE0 : single ended external GPIO connection to pad16. */
ADC_SL7CFG_CHSEL7_SE1 = 1, /*!< SE1 : single ended external GPIO connection to pad29. */
ADC_SL7CFG_CHSEL7_SE2 = 2, /*!< SE2 : single ended external GPIO connection to pad11. */
ADC_SL7CFG_CHSEL7_SE3 = 3, /*!< SE3 : single ended external GPIO connection to pad31. */
ADC_SL7CFG_CHSEL7_SE4 = 4, /*!< SE4 : single ended external GPIO connection to pad32. */
ADC_SL7CFG_CHSEL7_SE5 = 5, /*!< SE5 : single ended external GPIO connection to pad33. */
ADC_SL7CFG_CHSEL7_SE6 = 6, /*!< SE6 : single ended external GPIO connection to pad34. */
ADC_SL7CFG_CHSEL7_SE7 = 7, /*!< SE7 : single ended external GPIO connection to pad35. */
ADC_SL7CFG_CHSEL7_SE8 = 8, /*!< SE8 : single ended external GPIO connection to pad13. */
ADC_SL7CFG_CHSEL7_SE9 = 9, /*!< SE9 : single ended external GPIO connection to pad12. */
ADC_SL7CFG_CHSEL7_DF0 = 10, /*!< DF0 : differential external GPIO connections to pad12(N) and
pad13(P). */
ADC_SL7CFG_CHSEL7_DF1 = 11, /*!< DF1 : differential external GPIO connections to pad15(N) and
pad14(P). */
ADC_SL7CFG_CHSEL7_TEMP = 12, /*!< TEMP : internal temperature sensor. */
ADC_SL7CFG_CHSEL7_BATT = 13, /*!< BATT : internal voltage divide-by-3 connection. */
ADC_SL7CFG_CHSEL7_VSS = 14, /*!< VSS : Input VSS */
} ADC_SL7CFG_CHSEL7_Enum;
/* ================================================ ADC SL7CFG WCEN7 [1..1] ================================================ */
typedef enum { /*!< ADC_SL7CFG_WCEN7 */
ADC_SL7CFG_WCEN7_WCEN = 1, /*!< WCEN : Enable the window compare for slot 7. */
} ADC_SL7CFG_WCEN7_Enum;
/* ================================================ ADC SL7CFG SLEN7 [0..0] ================================================ */
typedef enum { /*!< ADC_SL7CFG_SLEN7 */
ADC_SL7CFG_SLEN7_SLEN = 1, /*!< SLEN : Enable slot 7 for ADC conversions. */
} ADC_SL7CFG_SLEN7_Enum;
/* ========================================================= WULIM ========================================================= */
/* ========================================================= WLLIM ========================================================= */
/* ======================================================== SCWLIM ========================================================= */
/* ========================================================= FIFO ========================================================== */
/* ======================================================== FIFOPR ========================================================= */
/* ========================================================= INTEN ========================================================= */
/* ================================================= ADC INTEN DERR [7..7] ================================================= */
typedef enum { /*!< ADC_INTEN_DERR */
ADC_INTEN_DERR_DMAERROR = 1, /*!< DMAERROR : DMA Error Condition Occurred */
} ADC_INTEN_DERR_Enum;
/* ================================================= ADC INTEN DCMP [6..6] ================================================= */
typedef enum { /*!< ADC_INTEN_DCMP */
ADC_INTEN_DCMP_DMACOMPLETE = 1, /*!< DMACOMPLETE : DMA Completed a transfer */
} ADC_INTEN_DCMP_Enum;
/* ================================================ ADC INTEN WCINC [5..5] ================================================= */
typedef enum { /*!< ADC_INTEN_WCINC */
ADC_INTEN_WCINC_WCINCINT = 1, /*!< WCINCINT : Window comparitor voltage incursion interrupt. */
} ADC_INTEN_WCINC_Enum;
/* ================================================ ADC INTEN WCEXC [4..4] ================================================= */
typedef enum { /*!< ADC_INTEN_WCEXC */
ADC_INTEN_WCEXC_WCEXCINT = 1, /*!< WCEXCINT : Window comparitor voltage excursion interrupt. */
} ADC_INTEN_WCEXC_Enum;
/* =============================================== ADC INTEN FIFOOVR2 [3..3] =============================================== */
typedef enum { /*!< ADC_INTEN_FIFOOVR2 */
ADC_INTEN_FIFOOVR2_FIFOFULLINT = 1, /*!< FIFOFULLINT : FIFO 100 percent full interrupt. */
} ADC_INTEN_FIFOOVR2_Enum;
/* =============================================== ADC INTEN FIFOOVR1 [2..2] =============================================== */
typedef enum { /*!< ADC_INTEN_FIFOOVR1 */
ADC_INTEN_FIFOOVR1_FIFO75INT = 1, /*!< FIFO75INT : FIFO 75 percent full interrupt. */
} ADC_INTEN_FIFOOVR1_Enum;
/* ================================================ ADC INTEN SCNCMP [1..1] ================================================ */
typedef enum { /*!< ADC_INTEN_SCNCMP */
ADC_INTEN_SCNCMP_SCNCMPINT = 1, /*!< SCNCMPINT : ADC scan complete interrupt. */
} ADC_INTEN_SCNCMP_Enum;
/* ================================================ ADC INTEN CNVCMP [0..0] ================================================ */
typedef enum { /*!< ADC_INTEN_CNVCMP */
ADC_INTEN_CNVCMP_CNVCMPINT = 1, /*!< CNVCMPINT : ADC conversion complete interrupt. */
} ADC_INTEN_CNVCMP_Enum;
/* ======================================================== INTSTAT ======================================================== */
/* ================================================ ADC INTSTAT DERR [7..7] ================================================ */
typedef enum { /*!< ADC_INTSTAT_DERR */
ADC_INTSTAT_DERR_DMAERROR = 1, /*!< DMAERROR : DMA Error Condition Occurred */
} ADC_INTSTAT_DERR_Enum;
/* ================================================ ADC INTSTAT DCMP [6..6] ================================================ */
typedef enum { /*!< ADC_INTSTAT_DCMP */
ADC_INTSTAT_DCMP_DMACOMPLETE = 1, /*!< DMACOMPLETE : DMA Completed a transfer */
} ADC_INTSTAT_DCMP_Enum;
/* =============================================== ADC INTSTAT WCINC [5..5] ================================================ */
typedef enum { /*!< ADC_INTSTAT_WCINC */
ADC_INTSTAT_WCINC_WCINCINT = 1, /*!< WCINCINT : Window comparitor voltage incursion interrupt. */
} ADC_INTSTAT_WCINC_Enum;
/* =============================================== ADC INTSTAT WCEXC [4..4] ================================================ */
typedef enum { /*!< ADC_INTSTAT_WCEXC */
ADC_INTSTAT_WCEXC_WCEXCINT = 1, /*!< WCEXCINT : Window comparitor voltage excursion interrupt. */
} ADC_INTSTAT_WCEXC_Enum;
/* ============================================== ADC INTSTAT FIFOOVR2 [3..3] ============================================== */
typedef enum { /*!< ADC_INTSTAT_FIFOOVR2 */
ADC_INTSTAT_FIFOOVR2_FIFOFULLINT = 1, /*!< FIFOFULLINT : FIFO 100 percent full interrupt. */
} ADC_INTSTAT_FIFOOVR2_Enum;
/* ============================================== ADC INTSTAT FIFOOVR1 [2..2] ============================================== */
typedef enum { /*!< ADC_INTSTAT_FIFOOVR1 */
ADC_INTSTAT_FIFOOVR1_FIFO75INT = 1, /*!< FIFO75INT : FIFO 75 percent full interrupt. */
} ADC_INTSTAT_FIFOOVR1_Enum;
/* =============================================== ADC INTSTAT SCNCMP [1..1] =============================================== */
typedef enum { /*!< ADC_INTSTAT_SCNCMP */
ADC_INTSTAT_SCNCMP_SCNCMPINT = 1, /*!< SCNCMPINT : ADC scan complete interrupt. */
} ADC_INTSTAT_SCNCMP_Enum;
/* =============================================== ADC INTSTAT CNVCMP [0..0] =============================================== */
typedef enum { /*!< ADC_INTSTAT_CNVCMP */
ADC_INTSTAT_CNVCMP_CNVCMPINT = 1, /*!< CNVCMPINT : ADC conversion complete interrupt. */
} ADC_INTSTAT_CNVCMP_Enum;
/* ======================================================== INTCLR ========================================================= */
/* ================================================ ADC INTCLR DERR [7..7] ================================================= */
typedef enum { /*!< ADC_INTCLR_DERR */
ADC_INTCLR_DERR_DMAERROR = 1, /*!< DMAERROR : DMA Error Condition Occurred */
} ADC_INTCLR_DERR_Enum;
/* ================================================ ADC INTCLR DCMP [6..6] ================================================= */
typedef enum { /*!< ADC_INTCLR_DCMP */
ADC_INTCLR_DCMP_DMACOMPLETE = 1, /*!< DMACOMPLETE : DMA Completed a transfer */
} ADC_INTCLR_DCMP_Enum;
/* ================================================ ADC INTCLR WCINC [5..5] ================================================ */
typedef enum { /*!< ADC_INTCLR_WCINC */
ADC_INTCLR_WCINC_WCINCINT = 1, /*!< WCINCINT : Window comparitor voltage incursion interrupt. */
} ADC_INTCLR_WCINC_Enum;
/* ================================================ ADC INTCLR WCEXC [4..4] ================================================ */
typedef enum { /*!< ADC_INTCLR_WCEXC */
ADC_INTCLR_WCEXC_WCEXCINT = 1, /*!< WCEXCINT : Window comparitor voltage excursion interrupt. */
} ADC_INTCLR_WCEXC_Enum;
/* ============================================== ADC INTCLR FIFOOVR2 [3..3] =============================================== */
typedef enum { /*!< ADC_INTCLR_FIFOOVR2 */
ADC_INTCLR_FIFOOVR2_FIFOFULLINT = 1, /*!< FIFOFULLINT : FIFO 100 percent full interrupt. */
} ADC_INTCLR_FIFOOVR2_Enum;
/* ============================================== ADC INTCLR FIFOOVR1 [2..2] =============================================== */
typedef enum { /*!< ADC_INTCLR_FIFOOVR1 */
ADC_INTCLR_FIFOOVR1_FIFO75INT = 1, /*!< FIFO75INT : FIFO 75 percent full interrupt. */
} ADC_INTCLR_FIFOOVR1_Enum;
/* =============================================== ADC INTCLR SCNCMP [1..1] ================================================ */
typedef enum { /*!< ADC_INTCLR_SCNCMP */
ADC_INTCLR_SCNCMP_SCNCMPINT = 1, /*!< SCNCMPINT : ADC scan complete interrupt. */
} ADC_INTCLR_SCNCMP_Enum;
/* =============================================== ADC INTCLR CNVCMP [0..0] ================================================ */
typedef enum { /*!< ADC_INTCLR_CNVCMP */
ADC_INTCLR_CNVCMP_CNVCMPINT = 1, /*!< CNVCMPINT : ADC conversion complete interrupt. */
} ADC_INTCLR_CNVCMP_Enum;
/* ======================================================== INTSET ========================================================= */
/* ================================================ ADC INTSET DERR [7..7] ================================================= */
typedef enum { /*!< ADC_INTSET_DERR */
ADC_INTSET_DERR_DMAERROR = 1, /*!< DMAERROR : DMA Error Condition Occurred */
} ADC_INTSET_DERR_Enum;
/* ================================================ ADC INTSET DCMP [6..6] ================================================= */
typedef enum { /*!< ADC_INTSET_DCMP */
ADC_INTSET_DCMP_DMACOMPLETE = 1, /*!< DMACOMPLETE : DMA Completed a transfer */
} ADC_INTSET_DCMP_Enum;
/* ================================================ ADC INTSET WCINC [5..5] ================================================ */
typedef enum { /*!< ADC_INTSET_WCINC */
ADC_INTSET_WCINC_WCINCINT = 1, /*!< WCINCINT : Window comparitor voltage incursion interrupt. */
} ADC_INTSET_WCINC_Enum;
/* ================================================ ADC INTSET WCEXC [4..4] ================================================ */
typedef enum { /*!< ADC_INTSET_WCEXC */
ADC_INTSET_WCEXC_WCEXCINT = 1, /*!< WCEXCINT : Window comparitor voltage excursion interrupt. */
} ADC_INTSET_WCEXC_Enum;
/* ============================================== ADC INTSET FIFOOVR2 [3..3] =============================================== */
typedef enum { /*!< ADC_INTSET_FIFOOVR2 */
ADC_INTSET_FIFOOVR2_FIFOFULLINT = 1, /*!< FIFOFULLINT : FIFO 100 percent full interrupt. */
} ADC_INTSET_FIFOOVR2_Enum;
/* ============================================== ADC INTSET FIFOOVR1 [2..2] =============================================== */
typedef enum { /*!< ADC_INTSET_FIFOOVR1 */
ADC_INTSET_FIFOOVR1_FIFO75INT = 1, /*!< FIFO75INT : FIFO 75 percent full interrupt. */
} ADC_INTSET_FIFOOVR1_Enum;
/* =============================================== ADC INTSET SCNCMP [1..1] ================================================ */
typedef enum { /*!< ADC_INTSET_SCNCMP */
ADC_INTSET_SCNCMP_SCNCMPINT = 1, /*!< SCNCMPINT : ADC scan complete interrupt. */
} ADC_INTSET_SCNCMP_Enum;
/* =============================================== ADC INTSET CNVCMP [0..0] ================================================ */
typedef enum { /*!< ADC_INTSET_CNVCMP */
ADC_INTSET_CNVCMP_CNVCMPINT = 1, /*!< CNVCMPINT : ADC conversion complete interrupt. */
} ADC_INTSET_CNVCMP_Enum;
/* ======================================================= DMATRIGEN ======================================================= */
/* ====================================================== DMATRIGSTAT ====================================================== */
/* ======================================================== DMACFG ========================================================= */
/* ============================================== ADC DMACFG DMAMSK [17..17] =============================================== */
typedef enum { /*!< ADC_DMACFG_DMAMSK */
ADC_DMACFG_DMAMSK_DIS = 0, /*!< DIS : FIFO Contents are copied directly to memory without modification. */
ADC_DMACFG_DMAMSK_EN = 1, /*!< EN : Only the FIFODATA contents are copied to memory on DMA
transfers. The SLOTNUM and FIFOCNT contents are cleared
to zero. */
} ADC_DMACFG_DMAMSK_Enum;
/* ============================================ ADC DMACFG DMAHONSTAT [16..16] ============================================= */
typedef enum { /*!< ADC_DMACFG_DMAHONSTAT */
ADC_DMACFG_DMAHONSTAT_DIS = 0, /*!< DIS : ADC conversions will continue regardless of DMA status
register */
ADC_DMACFG_DMAHONSTAT_EN = 1, /*!< EN : ADC conversions will not progress if DMAERR or DMACPL bits
in DMA status register are set. */
} ADC_DMACFG_DMAHONSTAT_Enum;
/* ============================================== ADC DMACFG DMADYNPRI [9..9] ============================================== */
typedef enum { /*!< ADC_DMACFG_DMADYNPRI */
ADC_DMACFG_DMADYNPRI_DIS = 0, /*!< DIS : Disable dynamic priority (use DMAPRI setting only) */
ADC_DMACFG_DMADYNPRI_EN = 1, /*!< EN : Enable dynamic priority */
} ADC_DMACFG_DMADYNPRI_Enum;
/* =============================================== ADC DMACFG DMAPRI [8..8] ================================================ */
typedef enum { /*!< ADC_DMACFG_DMAPRI */
ADC_DMACFG_DMAPRI_LOW = 0, /*!< LOW : Low Priority (service as best effort) */
ADC_DMACFG_DMAPRI_HIGH = 1, /*!< HIGH : High Priority (service immediately) */
} ADC_DMACFG_DMAPRI_Enum;
/* =============================================== ADC DMACFG DMADIR [2..2] ================================================ */
typedef enum { /*!< ADC_DMACFG_DMADIR */
ADC_DMACFG_DMADIR_P2M = 0, /*!< P2M : Peripheral to Memory (SRAM) transaction */
ADC_DMACFG_DMADIR_M2P = 1, /*!< M2P : Memory to Peripheral transaction */
} ADC_DMACFG_DMADIR_Enum;
/* ================================================ ADC DMACFG DMAEN [0..0] ================================================ */
typedef enum { /*!< ADC_DMACFG_DMAEN */
ADC_DMACFG_DMAEN_DIS = 0, /*!< DIS : Disable DMA Function */
ADC_DMACFG_DMAEN_EN = 1, /*!< EN : Enable DMA Function */
} ADC_DMACFG_DMAEN_Enum;
/* ====================================================== DMATOTCOUNT ====================================================== */
/* ====================================================== DMATARGADDR ====================================================== */
/* ======================================================== DMASTAT ======================================================== */
/* =========================================================================================================================== */
/* ================ APBDMA ================ */
/* =========================================================================================================================== */
/* ======================================================== BBVALUE ======================================================== */
/* ====================================================== BBSETCLEAR ======================================================= */
/* ======================================================== BBINPUT ======================================================== */
/* ======================================================= DEBUGDATA ======================================================= */
/* ========================================================= DEBUG ========================================================= */
/* ============================================== APBDMA DEBUG DEBUGEN [0..3] ============================================== */
typedef enum { /*!< APBDMA_DEBUG_DEBUGEN */
APBDMA_DEBUG_DEBUGEN_OFF = 0, /*!< OFF : Debug Disabled */
APBDMA_DEBUG_DEBUGEN_ARB = 1, /*!< ARB : Debug Arb values */
} APBDMA_DEBUG_DEBUGEN_Enum;
/* =========================================================================================================================== */
/* ================ BLEIF ================ */
/* =========================================================================================================================== */
/* ========================================================= FIFO ========================================================== */
/* ======================================================== FIFOPTR ======================================================== */
/* ======================================================== FIFOTHR ======================================================== */
/* ======================================================== FIFOPOP ======================================================== */
/* ======================================================= FIFOPUSH ======================================================== */
/* ======================================================= FIFOCTRL ======================================================== */
/* ======================================================== FIFOLOC ======================================================== */
/* ======================================================== CLKCFG ========================================================= */
/* =============================================== BLEIF CLKCFG FSEL [8..10] =============================================== */
typedef enum { /*!< BLEIF_CLKCFG_FSEL */
BLEIF_CLKCFG_FSEL_MIN_PWR = 0, /*!< MIN_PWR : Selects the minimum power clock. This setting should
be used whenever the IOM is not active. */
BLEIF_CLKCFG_FSEL_HFRC = 1, /*!< HFRC : Selects the HFRC as the input clock. */
BLEIF_CLKCFG_FSEL_HFRC_DIV2 = 2, /*!< HFRC_DIV2 : Selects the HFRC / 2 as the input clock. */
BLEIF_CLKCFG_FSEL_HFRC_DIV4 = 3, /*!< HFRC_DIV4 : Selects the HFRC / 4 as the input clock. */
BLEIF_CLKCFG_FSEL_HFRC_DIV8 = 4, /*!< HFRC_DIV8 : Selects the HFRC / 8 as the input clock. */
BLEIF_CLKCFG_FSEL_HFRC_DIV16 = 5, /*!< HFRC_DIV16 : Selects the HFRC / 16 as the input clock. */
BLEIF_CLKCFG_FSEL_HFRC_DIV32 = 6, /*!< HFRC_DIV32 : Selects the HFRC / 32 as the input clock. */
BLEIF_CLKCFG_FSEL_HFRC_DIV64 = 7, /*!< HFRC_DIV64 : Selects the HFRC / 64 as the input clock. */
} BLEIF_CLKCFG_FSEL_Enum;
/* ========================================================== CMD ========================================================== */
/* ================================================= BLEIF CMD CMD [0..4] ================================================== */
typedef enum { /*!< BLEIF_CMD_CMD */
BLEIF_CMD_CMD_WRITE = 1, /*!< WRITE : Write command using count of offset bytes specified
in the OFFSETCNT field */
BLEIF_CMD_CMD_READ = 2, /*!< READ : Read command using count of offset bytes specified in
the OFFSETCNT field */
} BLEIF_CMD_CMD_Enum;
/* ======================================================== CMDRPT ========================================================= */
/* ======================================================= OFFSETHI ======================================================== */
/* ======================================================== CMDSTAT ======================================================== */
/* ============================================= BLEIF CMDSTAT CMDSTAT [5..7] ============================================== */
typedef enum { /*!< BLEIF_CMDSTAT_CMDSTAT */
BLEIF_CMDSTAT_CMDSTAT_ERR = 1, /*!< ERR : Error encountered with command */
BLEIF_CMDSTAT_CMDSTAT_ACTIVE = 2, /*!< ACTIVE : Actively processing command */
BLEIF_CMDSTAT_CMDSTAT_IDLE = 4, /*!< IDLE : Idle state, no active command, no error */
BLEIF_CMDSTAT_CMDSTAT_WAIT = 6, /*!< WAIT : Command in progress, but waiting on data from host */
} BLEIF_CMDSTAT_CMDSTAT_Enum;
/* ========================================================= INTEN ========================================================= */
/* ======================================================== INTSTAT ======================================================== */
/* ======================================================== INTCLR ========================================================= */
/* ======================================================== INTSET ========================================================= */
/* ======================================================= DMATRIGEN ======================================================= */
/* ====================================================== DMATRIGSTAT ====================================================== */
/* ======================================================== DMACFG ========================================================= */
/* ============================================== BLEIF DMACFG DPWROFF [9..9] ============================================== */
typedef enum { /*!< BLEIF_DMACFG_DPWROFF */
BLEIF_DMACFG_DPWROFF_DIS = 0, /*!< DIS : Power off disabled */
BLEIF_DMACFG_DPWROFF_EN = 1, /*!< EN : Power off enabled */
} BLEIF_DMACFG_DPWROFF_Enum;
/* ============================================== BLEIF DMACFG DMAPRI [8..8] =============================================== */
typedef enum { /*!< BLEIF_DMACFG_DMAPRI */
BLEIF_DMACFG_DMAPRI_LOW = 0, /*!< LOW : Low Priority (service as best effort) */
BLEIF_DMACFG_DMAPRI_HIGH = 1, /*!< HIGH : High Priority (service immediately) */
} BLEIF_DMACFG_DMAPRI_Enum;
/* ============================================== BLEIF DMACFG DMADIR [1..1] =============================================== */
typedef enum { /*!< BLEIF_DMACFG_DMADIR */
BLEIF_DMACFG_DMADIR_P2M = 0, /*!< P2M : Peripheral to Memory (SRAM) transaction. To be set when
doing IOM read operations, ie reading data from external
devices. */
BLEIF_DMACFG_DMADIR_M2P = 1, /*!< M2P : Memory to Peripheral transaction. To be set when doing
IOM write operations, ie writing data to external devices. */
} BLEIF_DMACFG_DMADIR_Enum;
/* =============================================== BLEIF DMACFG DMAEN [0..0] =============================================== */
typedef enum { /*!< BLEIF_DMACFG_DMAEN */
BLEIF_DMACFG_DMAEN_DIS = 0, /*!< DIS : Disable DMA Function */
BLEIF_DMACFG_DMAEN_EN = 1, /*!< EN : Enable DMA Function */
} BLEIF_DMACFG_DMAEN_Enum;
/* ====================================================== DMATOTCOUNT ====================================================== */
/* ====================================================== DMATARGADDR ====================================================== */
/* ======================================================== DMASTAT ======================================================== */
/* ========================================================= CQCFG ========================================================= */
/* =============================================== BLEIF CQCFG CQPRI [1..1] ================================================ */
typedef enum { /*!< BLEIF_CQCFG_CQPRI */
BLEIF_CQCFG_CQPRI_LOW = 0, /*!< LOW : Low Priority (service as best effort) */
BLEIF_CQCFG_CQPRI_HIGH = 1, /*!< HIGH : High Priority (service immediately) */
} BLEIF_CQCFG_CQPRI_Enum;
/* ================================================ BLEIF CQCFG CQEN [0..0] ================================================ */
typedef enum { /*!< BLEIF_CQCFG_CQEN */
BLEIF_CQCFG_CQEN_DIS = 0, /*!< DIS : Disable CQ Function */
BLEIF_CQCFG_CQEN_EN = 1, /*!< EN : Enable CQ Function */
} BLEIF_CQCFG_CQEN_Enum;
/* ======================================================== CQADDR ========================================================= */
/* ======================================================== CQSTAT ========================================================= */
/* ======================================================== CQFLAGS ======================================================== */
/* ====================================================== CQSETCLEAR ======================================================= */
/* ======================================================= CQPAUSEEN ======================================================= */
/* ============================================= BLEIF CQPAUSEEN CQPEN [0..15] ============================================= */
typedef enum { /*!< BLEIF_CQPAUSEEN_CQPEN */
BLEIF_CQPAUSEEN_CQPEN_CNTEQ = 32768, /*!< CNTEQ : Pauses command queue processing when HWCNT matches SWCNT */
BLEIF_CQPAUSEEN_CQPEN_BLEXOREN = 16384, /*!< BLEXOREN : Pause command queue when input BLE bit XORed with
SWFLAG4 is '1' */
BLEIF_CQPAUSEEN_CQPEN_IOMXOREN = 8192, /*!< IOMXOREN : Pause command queue when input IOM bit XORed with
SWFLAG3 is '1' */
BLEIF_CQPAUSEEN_CQPEN_GPIOXOREN = 4096, /*!< GPIOXOREN : Pause command queue when input GPIO irq_bit XORed
with SWFLAG2 is '1' */
BLEIF_CQPAUSEEN_CQPEN_MSPI1XNOREN = 2048, /*!< MSPI1XNOREN : Pause command queue when input MSPI1 bit XNORed
with SWFLAG1 is '1' */
BLEIF_CQPAUSEEN_CQPEN_MSPI0XNOREN = 1024, /*!< MSPI0XNOREN : Pause command queue when input MSPI0 bit XNORed
with SWFLAG0 is '1' */
BLEIF_CQPAUSEEN_CQPEN_MSPI1XOREN = 512, /*!< MSPI1XOREN : Pause command queue when input MSPI1 bit XORed
with SWFLAG1 is '1' */
BLEIF_CQPAUSEEN_CQPEN_MSPI0XOREN = 256, /*!< MSPI0XOREN : Pause command queue when input MSPI0 bit XORed
with SWFLAG0 is '1' */
BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN7 = 128, /*!< SWFLAGEN7 : Pause the command queue when software flag bit 7
is '1'. */
BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN6 = 64, /*!< SWFLAGEN6 : Pause the command queue when software flag bit 7
is '1' */
BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN5 = 32, /*!< SWFLAGEN5 : Pause the command queue when software flag bit 7
is '1' */
BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN4 = 16, /*!< SWFLAGEN4 : Pause the command queue when software flag bit 7
is '1' */
BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN3 = 8, /*!< SWFLAGEN3 : Pause the command queue when software flag bit 7
is '1' */
BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN2 = 4, /*!< SWFLAGEN2 : Pause the command queue when software flag bit 7
is '1' */
BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN1 = 2, /*!< SWFLAGEN1 : Pause the command queue when software flag bit 7
is '1' */
BLEIF_CQPAUSEEN_CQPEN_SWFLGEN0 = 1, /*!< SWFLGEN0 : Pause the command queue when software flag bit 7
is '1' */
} BLEIF_CQPAUSEEN_CQPEN_Enum;
/* ======================================================= CQCURIDX ======================================================== */
/* ======================================================= CQENDIDX ======================================================== */
/* ======================================================== STATUS ========================================================= */
/* ============================================== BLEIF STATUS IDLEST [2..2] =============================================== */
typedef enum { /*!< BLEIF_STATUS_IDLEST */
BLEIF_STATUS_IDLEST_IDLE = 1, /*!< IDLE : The I/O state machine is in the idle state. */
} BLEIF_STATUS_IDLEST_Enum;
/* ============================================== BLEIF STATUS CMDACT [1..1] =============================================== */
typedef enum { /*!< BLEIF_STATUS_CMDACT */
BLEIF_STATUS_CMDACT_ACTIVE = 1, /*!< ACTIVE : An I/O command is active. Indicates the active module
has an active command and is processing this. De-asserted
when the command is completed. */
} BLEIF_STATUS_CMDACT_Enum;
/* ================================================ BLEIF STATUS ERR [0..0] ================================================ */
typedef enum { /*!< BLEIF_STATUS_ERR */
BLEIF_STATUS_ERR_ERROR = 1, /*!< ERROR : Bit has been deprecated and will always return 0. */
} BLEIF_STATUS_ERR_Enum;
/* ======================================================== MSPICFG ======================================================== */
/* ============================================= BLEIF MSPICFG SPILSB [23..23] ============================================= */
typedef enum { /*!< BLEIF_MSPICFG_SPILSB */
BLEIF_MSPICFG_SPILSB_MSB = 0, /*!< MSB : Send and receive MSB bit first */
BLEIF_MSPICFG_SPILSB_LSB = 1, /*!< LSB : Send and receive LSB bit first */
} BLEIF_MSPICFG_SPILSB_Enum;
/* ============================================ BLEIF MSPICFG RDFCPOL [22..22] ============================================= */
typedef enum { /*!< BLEIF_MSPICFG_RDFCPOL */
BLEIF_MSPICFG_RDFCPOL_NORMAL = 0, /*!< NORMAL : SPI_STATUS signal from BLE Core high(1) creates flow
control and new read spi transactions will not be started
until the signal goes low.(default) */
BLEIF_MSPICFG_RDFCPOL_INVERTED = 1, /*!< INVERTED : SPI_STATUS signal from BLE Core low(0) creates flow
control and new read spi transactions will not be started
until the signal goes high. */
} BLEIF_MSPICFG_RDFCPOL_Enum;
/* ============================================ BLEIF MSPICFG WTFCPOL [21..21] ============================================= */
typedef enum { /*!< BLEIF_MSPICFG_WTFCPOL */
BLEIF_MSPICFG_WTFCPOL_NORMAL = 0, /*!< NORMAL : SPI_STATUS signal from BLE Core high(1) creates flow
control and new write spi transactions will not be started
until the signal goes low.(default) */
BLEIF_MSPICFG_WTFCPOL_INVERTED = 1, /*!< INVERTED : SPI_STATUS signal from BLE Core high(1) creates low(0)
control and new write spi transactions will not be started
until the signal goes high. */
} BLEIF_MSPICFG_WTFCPOL_Enum;
/* ============================================== BLEIF MSPICFG RDFC [17..17] ============================================== */
typedef enum { /*!< BLEIF_MSPICFG_RDFC */
BLEIF_MSPICFG_RDFC_DIS = 0, /*!< DIS : Read mode flow control disabled. */
BLEIF_MSPICFG_RDFC_EN = 1, /*!< EN : Read mode flow control enabled. */
} BLEIF_MSPICFG_RDFC_Enum;
/* ============================================== BLEIF MSPICFG WTFC [16..16] ============================================== */
typedef enum { /*!< BLEIF_MSPICFG_WTFC */
BLEIF_MSPICFG_WTFC_DIS = 0, /*!< DIS : Write mode flow control disabled. */
BLEIF_MSPICFG_WTFC_EN = 1, /*!< EN : Write mode flow control enabled. */
} BLEIF_MSPICFG_WTFC_Enum;
/* =============================================== BLEIF MSPICFG SPHA [1..1] =============================================== */
typedef enum { /*!< BLEIF_MSPICFG_SPHA */
BLEIF_MSPICFG_SPHA_SAMPLE_LEADING_EDGE = 0, /*!< SAMPLE_LEADING_EDGE : Sample on the leading (first) clock edge,
rising or falling dependant on the value of SPOL */
BLEIF_MSPICFG_SPHA_SAMPLE_TRAILING_EDGE = 1, /*!< SAMPLE_TRAILING_EDGE : Sample on the trailing (second) clock
edge, rising of falling dependant on the value of SPOL */
} BLEIF_MSPICFG_SPHA_Enum;
/* =============================================== BLEIF MSPICFG SPOL [0..0] =============================================== */
typedef enum { /*!< BLEIF_MSPICFG_SPOL */
BLEIF_MSPICFG_SPOL_CLK_BASE_0 = 0, /*!< CLK_BASE_0 : The initial value of the clock is 0. */
BLEIF_MSPICFG_SPOL_CLK_BASE_1 = 1, /*!< CLK_BASE_1 : The initial value of the clock is 1. */
} BLEIF_MSPICFG_SPOL_Enum;
/* ======================================================== BLECFG ========================================================= */
/* ============================================ BLEIF BLECFG SPIISOCTL [14..15] ============================================ */
typedef enum { /*!< BLEIF_BLECFG_SPIISOCTL */
BLEIF_BLECFG_SPIISOCTL_ON = 3, /*!< ON : SPI signals from BLE Core to/from MCU Core are isolated. */
BLEIF_BLECFG_SPIISOCTL_OFF = 2, /*!< OFF : SPI signals from BLE Core to/from MCU Core are not isolated. */
BLEIF_BLECFG_SPIISOCTL_AUTO = 0, /*!< AUTO : SPI signals from BLE Core to/from MCU Core are automatically
isolated by the logic */
} BLEIF_BLECFG_SPIISOCTL_Enum;
/* ============================================ BLEIF BLECFG PWRISOCTL [12..13] ============================================ */
typedef enum { /*!< BLEIF_BLECFG_PWRISOCTL */
BLEIF_BLECFG_PWRISOCTL_ON = 3, /*!< ON : BLEH power signal isolation to on (isolated). */
BLEIF_BLECFG_PWRISOCTL_OFF = 2, /*!< OFF : BLEH power signal isolation to off (not isolated). */
BLEIF_BLECFG_PWRISOCTL_AUTO = 0, /*!< AUTO : BLEH Power signal isolation is controlled automatically
through the interface logic */
} BLEIF_BLECFG_PWRISOCTL_Enum;
/* ============================================ BLEIF BLECFG BLEHREQCTL [6..7] ============================================= */
typedef enum { /*!< BLEIF_BLECFG_BLEHREQCTL */
BLEIF_BLECFG_BLEHREQCTL_ON = 3, /*!< ON : BLEH Power-on reg signal is set to on (1). */
BLEIF_BLECFG_BLEHREQCTL_OFF = 2, /*!< OFF : BLEH Power-on signal is set to off (0). */
BLEIF_BLECFG_BLEHREQCTL_AUTO = 0, /*!< AUTO : BLEH Power-on signal is controlled by the PWRSM logic
and automatically controlled */
} BLEIF_BLECFG_BLEHREQCTL_Enum;
/* ============================================ BLEIF BLECFG DCDCFLGCTL [4..5] ============================================= */
typedef enum { /*!< BLEIF_BLECFG_DCDCFLGCTL */
BLEIF_BLECFG_DCDCFLGCTL_ON = 3, /*!< ON : DCDC Flag signal is set to on (1). */
BLEIF_BLECFG_DCDCFLGCTL_OFF = 2, /*!< OFF : DCDC Flag signal is set to off (0). */
BLEIF_BLECFG_DCDCFLGCTL_AUTO = 0, /*!< AUTO : DCDC Flag signal is controlled by the PWRSM logic and
automatically controlled */
} BLEIF_BLECFG_DCDCFLGCTL_Enum;
/* ============================================= BLEIF BLECFG WAKEUPCTL [2..3] ============================================= */
typedef enum { /*!< BLEIF_BLECFG_WAKEUPCTL */
BLEIF_BLECFG_WAKEUPCTL_ON = 3, /*!< ON : Wake signal is set to on (1). */
BLEIF_BLECFG_WAKEUPCTL_OFF = 2, /*!< OFF : Wake signal is set to off (0). */
BLEIF_BLECFG_WAKEUPCTL_AUTO = 0, /*!< AUTO : Wake signal is controlled by the PWRSM logic and automatically
controlled */
} BLEIF_BLECFG_WAKEUPCTL_Enum;
/* ============================================== BLEIF BLECFG BLERSTN [1..1] ============================================== */
typedef enum { /*!< BLEIF_BLECFG_BLERSTN */
BLEIF_BLECFG_BLERSTN_ACTIVE = 1, /*!< ACTIVE : The reset signal is active (0) */
BLEIF_BLECFG_BLERSTN_INACTIVE = 0, /*!< INACTIVE : The reset signal is inactive (1) */
} BLEIF_BLECFG_BLERSTN_Enum;
/* ============================================== BLEIF BLECFG PWRSMEN [0..0] ============================================== */
typedef enum { /*!< BLEIF_BLECFG_PWRSMEN */
BLEIF_BLECFG_PWRSMEN_ON = 1, /*!< ON : Internal power state machine is enabled and will sequence
the BLEH power domain as indicated in the design document.
Overrides for the power signals are not enabled. */
BLEIF_BLECFG_PWRSMEN_OFF = 0, /*!< OFF : Internal power state machine is disabled and will not
sequence the BLEH power domain. The values of the overrides
will be used to drive the output sequencing signals */
} BLEIF_BLECFG_PWRSMEN_Enum;
/* ======================================================== PWRCMD ========================================================= */
/* ======================================================== BSTATUS ======================================================== */
/* ============================================== BLEIF BSTATUS PWRST [8..10] ============================================== */
typedef enum { /*!< BLEIF_BSTATUS_PWRST */
BLEIF_BSTATUS_PWRST_OFF = 0, /*!< OFF : Internal power state machine is disabled and will not
sequence the BLEH power domain. The values of the overrides
will be used to drive the output sequencing signals */
BLEIF_BSTATUS_PWRST_INIT = 1, /*!< INIT : Initialization state. BLEH not powered */
BLEIF_BSTATUS_PWRST_PWRON = 2, /*!< PWRON : Waiting for the powerup of the BLEH */
BLEIF_BSTATUS_PWRST_ACTIVE = 3, /*!< ACTIVE : The BLE Core is powered and active */
BLEIF_BSTATUS_PWRST_SLEEP = 6, /*!< SLEEP : The BLE Core has entered sleep mode and the power request
is inactive */
BLEIF_BSTATUS_PWRST_SHUTDOWN = 4, /*!< SHUTDOWN : The BLE Core is in shutdown mode */
} BLEIF_BSTATUS_PWRST_Enum;
/* ============================================= BLEIF BSTATUS B2MSTATE [0..2] ============================================= */
typedef enum { /*!< BLEIF_BSTATUS_B2MSTATE */
BLEIF_BSTATUS_B2MSTATE_RESET = 0, /*!< RESET : Reset State */
BLEIF_BSTATUS_B2MSTATE_Sleep = 1, /*!< Sleep : Sleep state. */
BLEIF_BSTATUS_B2MSTATE_Standby = 2, /*!< Standby : Standby State */
BLEIF_BSTATUS_B2MSTATE_Idle = 3, /*!< Idle : Idle state */
BLEIF_BSTATUS_B2MSTATE_Active = 4, /*!< Active : Active state. */
} BLEIF_BSTATUS_B2MSTATE_Enum;
/* ======================================================== BLEDBG ========================================================= */
/* =========================================================================================================================== */
/* ================ CACHECTRL ================ */
/* =========================================================================================================================== */
/* ======================================================= CACHECFG ======================================================== */
/* =========================================== CACHECTRL CACHECFG CONFIG [4..7] ============================================ */
typedef enum { /*!< CACHECTRL_CACHECFG_CONFIG */
CACHECTRL_CACHECFG_CONFIG_W1_128B_512E = 4, /*!< W1_128B_512E : Direct mapped, 128-bit linesize, 512 entries
(4 SRAMs active) */
CACHECTRL_CACHECFG_CONFIG_W2_128B_512E = 5, /*!< W2_128B_512E : Two-way set associative, 128-bit linesize, 512
entries (8 SRAMs active) */
CACHECTRL_CACHECFG_CONFIG_W1_128B_1024E = 8, /*!< W1_128B_1024E : Direct mapped, 128-bit linesize, 1024 entries
(8 SRAMs active) */
} CACHECTRL_CACHECFG_CONFIG_Enum;
/* ======================================================= FLASHCFG ======================================================== */
/* ========================================== CACHECTRL FLASHCFG LPMMODE [12..13] ========================================== */
typedef enum { /*!< CACHECTRL_FLASHCFG_LPMMODE */
CACHECTRL_FLASHCFG_LPMMODE_NEVER = 0, /*!< NEVER : High power mode (LPM not used). */
CACHECTRL_FLASHCFG_LPMMODE_STANDBY = 1, /*!< STANDBY : Fast Standby mode. LPM deasserted for read operations,
but asserted while flash IDLE. */
CACHECTRL_FLASHCFG_LPMMODE_ALWAYS = 2, /*!< ALWAYS : Low Power mode. LPM always asserted for reads. LPM_RD_WAIT
must be programmed to accomodate longer read access times. */
} CACHECTRL_FLASHCFG_LPMMODE_Enum;
/* ========================================================= CTRL ========================================================== */
/* =========================================== CACHECTRL CTRL RESET_STAT [1..1] ============================================ */
typedef enum { /*!< CACHECTRL_CTRL_RESET_STAT */
CACHECTRL_CTRL_RESET_STAT_CLEAR = 1, /*!< CLEAR : Clear Cache Stats */
} CACHECTRL_CTRL_RESET_STAT_Enum;
/* ======================================================= NCR0START ======================================================= */
/* ======================================================== NCR0END ======================================================== */
/* ======================================================= NCR1START ======================================================= */
/* ======================================================== NCR1END ======================================================== */
/* ========================================================= DMON0 ========================================================= */
/* ========================================================= DMON1 ========================================================= */
/* ========================================================= DMON2 ========================================================= */
/* ========================================================= DMON3 ========================================================= */
/* ========================================================= IMON0 ========================================================= */
/* ========================================================= IMON1 ========================================================= */
/* ========================================================= IMON2 ========================================================= */
/* ========================================================= IMON3 ========================================================= */
/* =========================================================================================================================== */
/* ================ CLKGEN ================ */
/* =========================================================================================================================== */
/* ========================================================= CALXT ========================================================= */
/* ========================================================= CALRC ========================================================= */
/* ======================================================== ACALCTR ======================================================== */
/* ========================================================= OCTRL ========================================================= */
/* =============================================== CLKGEN OCTRL ACAL [8..10] =============================================== */
typedef enum { /*!< CLKGEN_OCTRL_ACAL */
CLKGEN_OCTRL_ACAL_DIS = 0, /*!< DIS : Disable Autocalibration */
CLKGEN_OCTRL_ACAL_1024SEC = 2, /*!< 1024SEC : Autocalibrate every 1024 seconds. Once autocalibration
is done, an interrupt will be triggered at the end of 1024
seconds. */
CLKGEN_OCTRL_ACAL_512SEC = 3, /*!< 512SEC : Autocalibrate every 512 seconds. Once autocalibration
is done, an interrupt will be trigged at the end of 512
seconds. */
CLKGEN_OCTRL_ACAL_XTFREQ = 6, /*!< XTFREQ : Frequency measurement using XT. The XT clock is normally
considered much more accurate than the LFRC clock source. */
CLKGEN_OCTRL_ACAL_EXTFREQ = 7, /*!< EXTFREQ : Frequency measurement using external clock. */
} CLKGEN_OCTRL_ACAL_Enum;
/* =============================================== CLKGEN OCTRL OSEL [7..7] ================================================ */
typedef enum { /*!< CLKGEN_OCTRL_OSEL */
CLKGEN_OCTRL_OSEL_RTC_XT = 0, /*!< RTC_XT : RTC uses the XT */
CLKGEN_OCTRL_OSEL_RTC_LFRC = 1, /*!< RTC_LFRC : RTC uses the LFRC */
} CLKGEN_OCTRL_OSEL_Enum;
/* ================================================ CLKGEN OCTRL FOS [6..6] ================================================ */
typedef enum { /*!< CLKGEN_OCTRL_FOS */
CLKGEN_OCTRL_FOS_DIS = 0, /*!< DIS : Disable the oscillator switch on failure function. */
CLKGEN_OCTRL_FOS_EN = 1, /*!< EN : Enable the oscillator switch on failure function. */
} CLKGEN_OCTRL_FOS_Enum;
/* ============================================== CLKGEN OCTRL STOPRC [1..1] =============================================== */
typedef enum { /*!< CLKGEN_OCTRL_STOPRC */
CLKGEN_OCTRL_STOPRC_EN = 0, /*!< EN : Enable the LFRC Oscillator to drive the RTC */
CLKGEN_OCTRL_STOPRC_STOP = 1, /*!< STOP : Stop the LFRC Oscillator when driving the RTC */
} CLKGEN_OCTRL_STOPRC_Enum;
/* ============================================== CLKGEN OCTRL STOPXT [0..0] =============================================== */
typedef enum { /*!< CLKGEN_OCTRL_STOPXT */
CLKGEN_OCTRL_STOPXT_EN = 0, /*!< EN : Enable the XT Oscillator to drive the RTC */
CLKGEN_OCTRL_STOPXT_STOP = 1, /*!< STOP : Stop the XT Oscillator when driving the RTC */
} CLKGEN_OCTRL_STOPXT_Enum;
/* ======================================================== CLKOUT ========================================================= */
/* =============================================== CLKGEN CLKOUT CKEN [7..7] =============================================== */
typedef enum { /*!< CLKGEN_CLKOUT_CKEN */
CLKGEN_CLKOUT_CKEN_DIS = 0, /*!< DIS : Disable CLKOUT */
CLKGEN_CLKOUT_CKEN_EN = 1, /*!< EN : Enable CLKOUT */
} CLKGEN_CLKOUT_CKEN_Enum;
/* ============================================== CLKGEN CLKOUT CKSEL [0..5] =============================================== */
typedef enum { /*!< CLKGEN_CLKOUT_CKSEL */
CLKGEN_CLKOUT_CKSEL_LFRC = 0, /*!< LFRC : Low Frequency RC */
CLKGEN_CLKOUT_CKSEL_XT_DIV2 = 1, /*!< XT_DIV2 : XT / 2 */
CLKGEN_CLKOUT_CKSEL_XT_DIV4 = 2, /*!< XT_DIV4 : XT / 4 */
CLKGEN_CLKOUT_CKSEL_XT_DIV8 = 3, /*!< XT_DIV8 : XT / 8 */
CLKGEN_CLKOUT_CKSEL_XT_DIV16 = 4, /*!< XT_DIV16 : XT / 16 */
CLKGEN_CLKOUT_CKSEL_XT_DIV32 = 5, /*!< XT_DIV32 : XT / 32 */
CLKGEN_CLKOUT_CKSEL_RTC_1Hz = 16, /*!< RTC_1Hz : 1 Hz as selected in RTC */
CLKGEN_CLKOUT_CKSEL_XT_DIV2M = 22, /*!< XT_DIV2M : XT / 2^21 */
CLKGEN_CLKOUT_CKSEL_XT = 23, /*!< XT : Crystal */
CLKGEN_CLKOUT_CKSEL_CG_100Hz = 24, /*!< CG_100Hz : 100 Hz as selected in CLKGEN */
CLKGEN_CLKOUT_CKSEL_HFRC = 25, /*!< HFRC : High Frequency RC */
CLKGEN_CLKOUT_CKSEL_HFRC_DIV4 = 26, /*!< HFRC_DIV4 : HFRC / 4 */
CLKGEN_CLKOUT_CKSEL_HFRC_DIV8 = 27, /*!< HFRC_DIV8 : HFRC / 8 */
CLKGEN_CLKOUT_CKSEL_HFRC_DIV16 = 28, /*!< HFRC_DIV16 : HFRC / 16 */
CLKGEN_CLKOUT_CKSEL_HFRC_DIV64 = 29, /*!< HFRC_DIV64 : HFRC / 64 */
CLKGEN_CLKOUT_CKSEL_HFRC_DIV128 = 30, /*!< HFRC_DIV128 : HFRC / 128 */
CLKGEN_CLKOUT_CKSEL_HFRC_DIV256 = 31, /*!< HFRC_DIV256 : HFRC / 256 */
CLKGEN_CLKOUT_CKSEL_HFRC_DIV512 = 32, /*!< HFRC_DIV512 : HFRC / 512 */
CLKGEN_CLKOUT_CKSEL_FLASH_CLK = 34, /*!< FLASH_CLK : Flash Clock */
CLKGEN_CLKOUT_CKSEL_LFRC_DIV2 = 35, /*!< LFRC_DIV2 : LFRC / 2 */
CLKGEN_CLKOUT_CKSEL_LFRC_DIV32 = 36, /*!< LFRC_DIV32 : LFRC / 32 */
CLKGEN_CLKOUT_CKSEL_LFRC_DIV512 = 37, /*!< LFRC_DIV512 : LFRC / 512 */
CLKGEN_CLKOUT_CKSEL_LFRC_DIV32K = 38, /*!< LFRC_DIV32K : LFRC / 32768 */
CLKGEN_CLKOUT_CKSEL_XT_DIV256 = 39, /*!< XT_DIV256 : XT / 256 */
CLKGEN_CLKOUT_CKSEL_XT_DIV8K = 40, /*!< XT_DIV8K : XT / 8192 */
CLKGEN_CLKOUT_CKSEL_XT_DIV64K = 41, /*!< XT_DIV64K : XT / 2^16 */
CLKGEN_CLKOUT_CKSEL_ULFRC_DIV16 = 42, /*!< ULFRC_DIV16 : Uncal LFRC / 16 */
CLKGEN_CLKOUT_CKSEL_ULFRC_DIV128 = 43, /*!< ULFRC_DIV128 : Uncal LFRC / 128 */
CLKGEN_CLKOUT_CKSEL_ULFRC_1Hz = 44, /*!< ULFRC_1Hz : Uncal LFRC / 1024 */
CLKGEN_CLKOUT_CKSEL_ULFRC_DIV4K = 45, /*!< ULFRC_DIV4K : Uncal LFRC / 4096 */
CLKGEN_CLKOUT_CKSEL_ULFRC_DIV1M = 46, /*!< ULFRC_DIV1M : Uncal LFRC / 2^20 */
CLKGEN_CLKOUT_CKSEL_HFRC_DIV64K = 47, /*!< HFRC_DIV64K : HFRC / 2^16 */
CLKGEN_CLKOUT_CKSEL_HFRC_DIV16M = 48, /*!< HFRC_DIV16M : HFRC / 2^24 */
CLKGEN_CLKOUT_CKSEL_LFRC_DIV1M = 49, /*!< LFRC_DIV1M : LFRC / 2^20 */
CLKGEN_CLKOUT_CKSEL_HFRCNE = 50, /*!< HFRCNE : HFRC (not autoenabled) */
CLKGEN_CLKOUT_CKSEL_HFRCNE_DIV8 = 51, /*!< HFRCNE_DIV8 : HFRC / 8 (not autoenabled) */
CLKGEN_CLKOUT_CKSEL_XTNE = 53, /*!< XTNE : XT (not autoenabled) */
CLKGEN_CLKOUT_CKSEL_XTNE_DIV16 = 54, /*!< XTNE_DIV16 : XT / 16 (not autoenabled) */
CLKGEN_CLKOUT_CKSEL_LFRCNE_DIV32 = 55, /*!< LFRCNE_DIV32 : LFRC / 32 (not autoenabled) */
CLKGEN_CLKOUT_CKSEL_LFRCNE = 57, /*!< LFRCNE : LFRC (not autoenabled) - Default for undefined values */
} CLKGEN_CLKOUT_CKSEL_Enum;
/* ======================================================== CLKKEY ========================================================= */
/* ============================================= CLKGEN CLKKEY CLKKEY [0..31] ============================================== */
typedef enum { /*!< CLKGEN_CLKKEY_CLKKEY */
CLKGEN_CLKKEY_CLKKEY_Key = 71, /*!< Key : Key value to unlock the register. */
} CLKGEN_CLKKEY_CLKKEY_Enum;
/* ========================================================= CCTRL ========================================================= */
/* ============================================== CLKGEN CCTRL CORESEL [0..0] ============================================== */
typedef enum { /*!< CLKGEN_CCTRL_CORESEL */
CLKGEN_CCTRL_CORESEL_HFRC = 0, /*!< HFRC : Core Clock is HFRC */
CLKGEN_CCTRL_CORESEL_HFRC_DIV2 = 1, /*!< HFRC_DIV2 : Core Clock is HFRC / 2 */
} CLKGEN_CCTRL_CORESEL_Enum;
/* ======================================================== STATUS ========================================================= */
/* ========================================================= HFADJ ========================================================= */
/* ============================================ CLKGEN HFADJ HFADJGAIN [21..23] ============================================ */
typedef enum { /*!< CLKGEN_HFADJ_HFADJGAIN */
CLKGEN_HFADJ_HFADJGAIN_Gain_of_1 = 0, /*!< Gain_of_1 : HF Adjust with Gain of 1 */
CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_2 = 1, /*!< Gain_of_1_in_2 : HF Adjust with Gain of 0.5 */
CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_4 = 2, /*!< Gain_of_1_in_4 : HF Adjust with Gain of 0.25 */
CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_8 = 3, /*!< Gain_of_1_in_8 : HF Adjust with Gain of 0.125 */
CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_16 = 4, /*!< Gain_of_1_in_16 : HF Adjust with Gain of 0.0625 */
CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_32 = 5, /*!< Gain_of_1_in_32 : HF Adjust with Gain of 0.03125 */
} CLKGEN_HFADJ_HFADJGAIN_Enum;
/* ============================================ CLKGEN HFADJ HFWARMUP [20..20] ============================================= */
typedef enum { /*!< CLKGEN_HFADJ_HFWARMUP */
CLKGEN_HFADJ_HFWARMUP_1SEC = 0, /*!< 1SEC : Autoadjust XT warmup period = 1-2 seconds */
CLKGEN_HFADJ_HFWARMUP_2SEC = 1, /*!< 2SEC : Autoadjust XT warmup period = 2-4 seconds */
} CLKGEN_HFADJ_HFWARMUP_Enum;
/* ============================================== CLKGEN HFADJ HFADJCK [1..3] ============================================== */
typedef enum { /*!< CLKGEN_HFADJ_HFADJCK */
CLKGEN_HFADJ_HFADJCK_4SEC = 0, /*!< 4SEC : Autoadjust repeat period = 4 seconds */
CLKGEN_HFADJ_HFADJCK_16SEC = 1, /*!< 16SEC : Autoadjust repeat period = 16 seconds */
CLKGEN_HFADJ_HFADJCK_32SEC = 2, /*!< 32SEC : Autoadjust repeat period = 32 seconds */
CLKGEN_HFADJ_HFADJCK_64SEC = 3, /*!< 64SEC : Autoadjust repeat period = 64 seconds */
CLKGEN_HFADJ_HFADJCK_128SEC = 4, /*!< 128SEC : Autoadjust repeat period = 128 seconds */
CLKGEN_HFADJ_HFADJCK_256SEC = 5, /*!< 256SEC : Autoadjust repeat period = 256 seconds */
CLKGEN_HFADJ_HFADJCK_512SEC = 6, /*!< 512SEC : Autoadjust repeat period = 512 seconds */
CLKGEN_HFADJ_HFADJCK_1024SEC = 7, /*!< 1024SEC : Autoadjust repeat period = 1024 seconds */
} CLKGEN_HFADJ_HFADJCK_Enum;
/* ============================================== CLKGEN HFADJ HFADJEN [0..0] ============================================== */
typedef enum { /*!< CLKGEN_HFADJ_HFADJEN */
CLKGEN_HFADJ_HFADJEN_DIS = 0, /*!< DIS : Disable the HFRC adjustment */
CLKGEN_HFADJ_HFADJEN_EN = 1, /*!< EN : Enable the HFRC adjustment */
} CLKGEN_HFADJ_HFADJEN_Enum;
/* ====================================================== CLOCKENSTAT ====================================================== */
/* ======================================== CLKGEN CLOCKENSTAT CLOCKENSTAT [0..31] ========================================= */
typedef enum { /*!< CLKGEN_CLOCKENSTAT_CLOCKENSTAT */
CLKGEN_CLOCKENSTAT_CLOCKENSTAT_ADC_CLKEN = 1, /*!< ADC_CLKEN : Clock enable for the ADC. */
CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_ACTIVITY_CLKEN = 2,/*!< APBDMA_ACTIVITY_CLKEN : Clock enable for the APBDMA ACTIVITY */
CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_AOH_CLKEN = 4,/*!< APBDMA_AOH_CLKEN : Clock enable for the APBDMA AOH DOMAIN */
CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_AOL_CLKEN = 8,/*!< APBDMA_AOL_CLKEN : Clock enable for the APBDMA AOL DOMAIN */
CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_APB_CLKEN = 16,/*!< APBDMA_APB_CLKEN : Clock enable for the APBDMA_APB */
CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_BLEL_CLKEN = 32,/*!< APBDMA_BLEL_CLKEN : Clock enable for the APBDMA_BLEL */
CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_HCPA_CLKEN = 64,/*!< APBDMA_HCPA_CLKEN : Clock enable for the APBDMA_HCPA */
CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_HCPB_CLKEN = 128,/*!< APBDMA_HCPB_CLKEN : Clock enable for the APBDMA_HCPB */
CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_HCPC_CLKEN = 256,/*!< APBDMA_HCPC_CLKEN : Clock enable for the APBDMA_HCPC */
CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_MSPI_CLKEN = 512,/*!< APBDMA_MSPI_CLKEN : Clock enable for the APBDMA_MSPI */
CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_PDM_CLKEN = 1024,/*!< APBDMA_PDM_CLKEN : Clock enable for the APBDMA_PDM */
CLKGEN_CLOCKENSTAT_CLOCKENSTAT_BLEIF_CLK_CLKEN = 2048,/*!< BLEIF_CLK_CLKEN : Clock enable for the BLEIF */
CLKGEN_CLOCKENSTAT_CLOCKENSTAT_BLEIF_CLK32K_CLKEN = 4096,/*!< BLEIF_CLK32K_CLKEN : Clock enable for the BLEIF 32khZ CLOCK */
CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER_CLKEN = 8192,/*!< CTIMER_CLKEN : Clock enable for the CTIMER BLOCK */
CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER0A_CLKEN = 16384,/*!< CTIMER0A_CLKEN : Clock enable for the CTIMER0A */
CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER0B_CLKEN = 32768,/*!< CTIMER0B_CLKEN : Clock enable for the CTIMER0B */
CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER1A_CLKEN = 65536,/*!< CTIMER1A_CLKEN : Clock enable for the CTIMER1A */
CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER1B_CLKEN = 131072,/*!< CTIMER1B_CLKEN : Clock enable for the CTIMER1B */
CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER2A_CLKEN = 262144,/*!< CTIMER2A_CLKEN : Clock enable for the CTIMER2A */
CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER2B_CLKEN = 524288,/*!< CTIMER2B_CLKEN : Clock enable for the CTIMER2B */
CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER3A_CLKEN = 1048576,/*!< CTIMER3A_CLKEN : Clock enable for the CTIMER3A */
CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER3B_CLKEN = 2097152,/*!< CTIMER3B_CLKEN : Clock enable for the CTIMER3B */
CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER4A_CLKEN = 4194304,/*!< CTIMER4A_CLKEN : Clock enable for the CTIMER4A */
CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER4B_CLKEN = 8388608,/*!< CTIMER4B_CLKEN : Clock enable for the CTIMER4B */
CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER5A_CLKEN = 16777216,/*!< CTIMER5A_CLKEN : Clock enable for the CTIMER5A */
CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER5B_CLKEN = 33554432,/*!< CTIMER5B_CLKEN : Clock enable for the CTIMER5B */
CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER6A_CLKEN = 67108864,/*!< CTIMER6A_CLKEN : Clock enable for the CTIMER6A */
CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER6B_CLKEN = 134217728,/*!< CTIMER6B_CLKEN : Clock enable for the CTIMER6B */
CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER7A_CLKEN = 268435456,/*!< CTIMER7A_CLKEN : Clock enable for the CTIMER7A */
CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER7B_CLKEN = 536870912,/*!< CTIMER7B_CLKEN : Clock enable for the CTIMER7B */
CLKGEN_CLOCKENSTAT_CLOCKENSTAT_DAP_CLKEN = 1073741824,/*!< DAP_CLKEN : Clock enable for the DAP */
CLKGEN_CLOCKENSTAT_CLOCKENSTAT_IOMSTRIFC0_CLKEN = -2147483648,/*!< IOMSTRIFC0_CLKEN : Clock enable for the IOMSTRIFC0 */
} CLKGEN_CLOCKENSTAT_CLOCKENSTAT_Enum;
/* ===================================================== CLOCKEN2STAT ====================================================== */
/* ======================================= CLKGEN CLOCKEN2STAT CLOCKEN2STAT [0..31] ======================================== */
typedef enum { /*!< CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT */
CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_IOMSTRIFC1_CLKEN = 1,/*!< IOMSTRIFC1_CLKEN : Clock enable for the IO MASTER 1 IFC INTERFACE */
CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_IOMSTRIFC2_CLKEN = 2,/*!< IOMSTRIFC2_CLKEN : Clock enable for the IO MASTER 2 IFC INTERFACE */
CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_IOMSTRIFC3_CLKEN = 4,/*!< IOMSTRIFC3_CLKEN : Clock enable for the IO MASTER 3 IFC INTERFACE */
CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_IOMSTRIFC4_CLKEN = 8,/*!< IOMSTRIFC4_CLKEN : Clock enable for the IO MASTER 4 IFC INTERFACE */
CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_IOMSTRIFC5_CLKEN = 16,/*!< IOMSTRIFC5_CLKEN : Clock enable for the IO MASTER 5 IFC INTERFACE */
CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_PDM_CLKEN = 32,/*!< PDM_CLKEN : Clock enable for the PDM */
CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_PDMIFC_CLKEN = 64,/*!< PDMIFC_CLKEN : Clock enable for the PDM INTERFACE */
CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_PWRCTRL_CLKEN = 128,/*!< PWRCTRL_CLKEN : Clock enable for the PWRCTRL */
CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_PWRCTRL_COUNT_CLKEN = 256,/*!< PWRCTRL_COUNT_CLKEN : Clock enable for the PWRCTRL counter */
CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_RSTGEN_CLKEN = 512,/*!< RSTGEN_CLKEN : Clock enable for the RSTGEN */
CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_SCARD_CLKEN = 1024,/*!< SCARD_CLKEN : Clock enable for the SCARD */
CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_SCARD_ALTAPB_CLKEN = 2048,/*!< SCARD_ALTAPB_CLKEN : Clock enable for the SCARD ALTAPB */
CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_STIMER_CNT_CLKEN = 4096,/*!< STIMER_CNT_CLKEN : Clock enable for the STIMER_CNT_CLKEN */
CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_TPIU_CLKEN = 8192,/*!< TPIU_CLKEN : Clock enable for the TPIU_CLKEN */
CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_UART0HF_CLKEN = 16384,/*!< UART0HF_CLKEN : Clock enable for the UART0 HF */
CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_UART1HF_CLKEN = 32768,/*!< UART1HF_CLKEN : Clock enable for the UART1 HF */
CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_XT_32KHZ_EN = 1073741824,/*!< XT_32KHZ_EN : Clock enable for the XT 32KHZ */
CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_FORCEHFRC = -2147483648,/*!< FORCEHFRC : HFRC is forced on Status. */
} CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_Enum;
/* ===================================================== CLOCKEN3STAT ====================================================== */
/* ======================================= CLKGEN CLOCKEN3STAT CLOCKEN3STAT [0..31] ======================================== */
typedef enum { /*!< CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT */
CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_DAP_enabled = 131072,/*!< DAP_enabled : DAP clock is enabled [17] */
CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_VCOMP_enabled = 262144,/*!< VCOMP_enabled : VCOMP powerdown indicator [18] */
CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_XTAL_enabled = 16777216,/*!< XTAL_enabled : XTAL is enabled [24] */
CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_HFRC_enabled = 33554432,/*!< HFRC_enabled : HFRC is enabled [25] */
CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_HFADJEN = 67108864,/*!< HFADJEN : HFRC Adjust enabled [26] */
CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_HFRC_en_out = 134217728,/*!< HFRC_en_out : HFRC Enabled out [27] */
CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_RTC_XT = 268435456,/*!< RTC_XT : RTC use XT [28] */
CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_clkout_xtal_en = 536870912,/*!< clkout_xtal_en : XTAL clkout enabled [29] */
CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_clkout_hfrc_en = 1073741824,/*!< clkout_hfrc_en : HFRC clkout enabled [30] */
CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_flashclk_en = -2147483648,/*!< flashclk_en : Flash clk is enabled [31] */
} CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_Enum;
/* ======================================================= FREQCTRL ======================================================== */
/* ============================================ CLKGEN FREQCTRL BURSTREQ [0..0] ============================================ */
typedef enum { /*!< CLKGEN_FREQCTRL_BURSTREQ */
CLKGEN_FREQCTRL_BURSTREQ_DIS = 0, /*!< DIS : Frequency for ARM core stays at 48MHz */
CLKGEN_FREQCTRL_BURSTREQ_EN = 1, /*!< EN : Frequency for ARM core is increased to 96MHz */
} CLKGEN_FREQCTRL_BURSTREQ_Enum;
/* ===================================================== BLEBUCKTONADJ ===================================================== */
/* ===================================== CLKGEN BLEBUCKTONADJ ZEROLENDETECTEN [27..27] ===================================== */
typedef enum { /*!< CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTEN */
CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTEN_DIS = 0, /*!< DIS : Disable Zero Length Detect */
CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTEN_EN = 1, /*!< EN : Enable Zero Length Detect */
} CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTEN_Enum;
/* ==================================== CLKGEN BLEBUCKTONADJ ZEROLENDETECTTRIM [23..26] ==================================== */
typedef enum { /*!< CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM */
CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_SetF = 15,/*!< SetF : Indicator send when the BLE BUCK asserts blebuck_comp1
for about 81us (10 percent margin of error) or more */
CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_SetE = 14,/*!< SetE : Indicator send when the BLE BUCK asserts blebuck_comp1
for about 75.6us (10 percent margin of error) or more */
CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_SetD = 13,/*!< SetD : Indicator send when the BLE BUCK asserts blebuck_comp1
for about 70.2us (10 percent margin of error) or more */
CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_SetC = 12,/*!< SetC : Indicator send when the BLE BUCK asserts blebuck_comp1
for about 64.8us (10 percent margin of error) or more */
CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_SetB = 11,/*!< SetB : Indicator send when the BLE BUCK asserts blebuck_comp1
for about 59.4us (10 percent margin of error) or more */
CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_SetA = 10,/*!< SetA : Indicator send when the BLE BUCK asserts blebuck_comp1
for about 54.0us (10 percent margin of error) or more */
CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set9 = 9,/*!< Set9 : Indicator send when the BLE BUCK asserts blebuck_comp1
for about 48.6us (10 percent margin of error) or more */
CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set8 = 8,/*!< Set8 : Indicator send when the BLE BUCK asserts blebuck_comp1
for about 43.2us (10 percent margin of error) or more */
CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set7 = 7,/*!< Set7 : Indicator send when the BLE BUCK asserts blebuck_comp1
for about 37.8us (10 percent margin of error) or more */
CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set6 = 6,/*!< Set6 : Indicator send when the BLE BUCK asserts blebuck_comp1
for about 32.4us (10 percent margin of error) or more */
CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set5 = 5,/*!< Set5 : Indicator send when the BLE BUCK asserts blebuck_comp1
for about 27.0us (10 percent margin of error) or more */
CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set4 = 4,/*!< Set4 : Indicator send when the BLE BUCK asserts blebuck_comp1
for about 21.6us (10 percent margin of error) or more */
CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set3 = 3,/*!< Set3 : Indicator send when the BLE BUCK asserts blebuck_comp1
for about 16.2us (10 percent margin of error) or more */
CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set2 = 2,/*!< Set2 : Indicator send when the BLE BUCK asserts blebuck_comp1
for about 10.8us (10 percent margin of error) or more */
CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set1 = 1,/*!< Set1 : Indicator send when the BLE BUCK asserts blebuck_comp1
for about 5.4us (10 percent margin of error) or more */
CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set0 = 0,/*!< Set0 : Indicator send when the BLE BUCK asserts blebuck_comp1
for about 2.0us (10 percent margin of error) or more */
} CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Enum;
/* ======================================= CLKGEN BLEBUCKTONADJ TONADJUSTEN [22..22] ======================================= */
typedef enum { /*!< CLKGEN_BLEBUCKTONADJ_TONADJUSTEN */
CLKGEN_BLEBUCKTONADJ_TONADJUSTEN_DIS = 0, /*!< DIS : Disable Adjust for BLE BUCK TON trim */
CLKGEN_BLEBUCKTONADJ_TONADJUSTEN_EN = 1, /*!< EN : Enable Adjust for BLE BUCK TON trim */
} CLKGEN_BLEBUCKTONADJ_TONADJUSTEN_Enum;
/* ===================================== CLKGEN BLEBUCKTONADJ TONADJUSTPERIOD [20..21] ===================================== */
typedef enum { /*!< CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD */
CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_HFRC_3KHz = 3,/*!< HFRC_3KHz : Adjust done for every 1 3KHz period */
CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_HFRC_12KHz = 2,/*!< HFRC_12KHz : Adjust done for every 1 12KHz period */
CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_HFRC_47KHz = 1,/*!< HFRC_47KHz : Adjust done for every 1 47KHz period */
CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_HFRC_94KHz = 0,/*!< HFRC_94KHz : Adjust done for every 1 94KHz period */
} CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_Enum;
/* ======================================================= INTRPTEN ======================================================== */
/* ====================================================== INTRPTSTAT ======================================================= */
/* ======================================================= INTRPTCLR ======================================================= */
/* ======================================================= INTRPTSET ======================================================= */
/* =========================================================================================================================== */
/* ================ CTIMER ================ */
/* =========================================================================================================================== */
/* ========================================================= TMR0 ========================================================== */
/* ======================================================== CMPRA0 ========================================================= */
/* ======================================================== CMPRB0 ========================================================= */
/* ========================================================= CTRL0 ========================================================= */
/* ============================================= CTIMER CTRL0 CTLINK0 [31..31] ============================================= */
typedef enum { /*!< CTIMER_CTRL0_CTLINK0 */
CTIMER_CTRL0_CTLINK0_TWO_16BIT_TIMERS = 0, /*!< TWO_16BIT_TIMERS : Use A0/B0 timers as two independent 16-bit
timers (default). */
CTIMER_CTRL0_CTLINK0_32BIT_TIMER = 1, /*!< 32BIT_TIMER : Link A0/B0 timers into a single 32-bit timer. */
} CTIMER_CTRL0_CTLINK0_Enum;
/* ============================================ CTIMER CTRL0 TMRB0POL [28..28] ============================================= */
typedef enum { /*!< CTIMER_CTRL0_TMRB0POL */
CTIMER_CTRL0_TMRB0POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINB0 pin is the same as the
timer output. */
CTIMER_CTRL0_TMRB0POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINB0 pin is the inverse of
the timer output. */
} CTIMER_CTRL0_TMRB0POL_Enum;
/* ============================================ CTIMER CTRL0 TMRB0CLR [27..27] ============================================= */
typedef enum { /*!< CTIMER_CTRL0_TMRB0CLR */
CTIMER_CTRL0_TMRB0CLR_RUN = 0, /*!< RUN : Allow counter/timer B0 to run */
CTIMER_CTRL0_TMRB0CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer B0 at 0x0000. */
} CTIMER_CTRL0_TMRB0CLR_Enum;
/* ============================================ CTIMER CTRL0 TMRB0IE1 [26..26] ============================================= */
typedef enum { /*!< CTIMER_CTRL0_TMRB0IE1 */
CTIMER_CTRL0_TMRB0IE1_DIS = 0, /*!< DIS : Disable counter/timer B0 from generating an interrupt
based on COMPR1. */
CTIMER_CTRL0_TMRB0IE1_EN = 1, /*!< EN : Enable counter/timer B0 to generate an interrupt based
on COMPR1. */
} CTIMER_CTRL0_TMRB0IE1_Enum;
/* ============================================ CTIMER CTRL0 TMRB0IE0 [25..25] ============================================= */
typedef enum { /*!< CTIMER_CTRL0_TMRB0IE0 */
CTIMER_CTRL0_TMRB0IE0_DIS = 0, /*!< DIS : Disable counter/timer B0 from generating an interrupt
based on COMPR0. */
CTIMER_CTRL0_TMRB0IE0_EN = 1, /*!< EN : Enable counter/timer B0 to generate an interrupt based
on COMPR0 */
} CTIMER_CTRL0_TMRB0IE0_Enum;
/* ============================================= CTIMER CTRL0 TMRB0FN [22..24] ============================================= */
typedef enum { /*!< CTIMER_CTRL0_TMRB0FN */
CTIMER_CTRL0_TMRB0FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
to CMPR0B0, stop. */
CTIMER_CTRL0_TMRB0FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
pulses). Count to CMPR0B0, restart. */
CTIMER_CTRL0_TMRB0FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B0, assert,
count to CMPR1B0, deassert, stop. */
CTIMER_CTRL0_TMRB0FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0B0, assert, count
to CMPR1B0, deassert, restart. */
CTIMER_CTRL0_TMRB0FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */
CTIMER_CTRL0_TMRB0FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */
CTIMER_CTRL0_TMRB0FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */
CTIMER_CTRL0_TMRB0FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */
} CTIMER_CTRL0_TMRB0FN_Enum;
/* ============================================ CTIMER CTRL0 TMRB0CLK [17..21] ============================================= */
typedef enum { /*!< CTIMER_CTRL0_TMRB0CLK */
CTIMER_CTRL0_TMRB0CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINB. */
CTIMER_CTRL0_TMRB0CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */
CTIMER_CTRL0_TMRB0CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */
CTIMER_CTRL0_TMRB0CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */
CTIMER_CTRL0_TMRB0CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */
CTIMER_CTRL0_TMRB0CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */
CTIMER_CTRL0_TMRB0CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */
CTIMER_CTRL0_TMRB0CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */
CTIMER_CTRL0_TMRB0CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */
CTIMER_CTRL0_TMRB0CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */
CTIMER_CTRL0_TMRB0CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */
CTIMER_CTRL0_TMRB0CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */
CTIMER_CTRL0_TMRB0CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */
CTIMER_CTRL0_TMRB0CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */
CTIMER_CTRL0_TMRB0CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */
CTIMER_CTRL0_TMRB0CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
available when MCU is in active mode) */
CTIMER_CTRL0_TMRB0CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */
CTIMER_CTRL0_TMRB0CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */
CTIMER_CTRL0_TMRB0CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */
CTIMER_CTRL0_TMRB0CLK_CTMRA0 = 20, /*!< CTMRA0 : Clock source is CTIMERA0 OUT. */
CTIMER_CTRL0_TMRB0CLK_CTMRB1 = 21, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */
CTIMER_CTRL0_TMRB0CLK_CTMRA1 = 22, /*!< CTMRA1 : Clock source is CTIMERA1 OUT. */
CTIMER_CTRL0_TMRB0CLK_CTMRA2 = 23, /*!< CTMRA2 : Clock source is CTIMERA2 OUT. */
CTIMER_CTRL0_TMRB0CLK_CTMRB2 = 24, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */
CTIMER_CTRL0_TMRB0CLK_CTMRB3 = 25, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */
CTIMER_CTRL0_TMRB0CLK_CTMRB4 = 26, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */
CTIMER_CTRL0_TMRB0CLK_CTMRB5 = 27, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */
CTIMER_CTRL0_TMRB0CLK_CTMRB6 = 28, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */
CTIMER_CTRL0_TMRB0CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */
CTIMER_CTRL0_TMRB0CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */
CTIMER_CTRL0_TMRB0CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */
} CTIMER_CTRL0_TMRB0CLK_Enum;
/* ============================================= CTIMER CTRL0 TMRB0EN [16..16] ============================================= */
typedef enum { /*!< CTIMER_CTRL0_TMRB0EN */
CTIMER_CTRL0_TMRB0EN_DIS = 0, /*!< DIS : Counter/Timer B0 Disable. */
CTIMER_CTRL0_TMRB0EN_EN = 1, /*!< EN : Counter/Timer B0 Enable. */
} CTIMER_CTRL0_TMRB0EN_Enum;
/* ============================================ CTIMER CTRL0 TMRA0POL [12..12] ============================================= */
typedef enum { /*!< CTIMER_CTRL0_TMRA0POL */
CTIMER_CTRL0_TMRA0POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINA0 pin is the same as the
timer output. */
CTIMER_CTRL0_TMRA0POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINA0 pin is the inverse of
the timer output. */
} CTIMER_CTRL0_TMRA0POL_Enum;
/* ============================================ CTIMER CTRL0 TMRA0CLR [11..11] ============================================= */
typedef enum { /*!< CTIMER_CTRL0_TMRA0CLR */
CTIMER_CTRL0_TMRA0CLR_RUN = 0, /*!< RUN : Allow counter/timer A0 to run */
CTIMER_CTRL0_TMRA0CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer A0 at 0x0000. */
} CTIMER_CTRL0_TMRA0CLR_Enum;
/* ============================================ CTIMER CTRL0 TMRA0IE1 [10..10] ============================================= */
typedef enum { /*!< CTIMER_CTRL0_TMRA0IE1 */
CTIMER_CTRL0_TMRA0IE1_DIS = 0, /*!< DIS : Disable counter/timer A0 from generating an interrupt
based on COMPR1. */
CTIMER_CTRL0_TMRA0IE1_EN = 1, /*!< EN : Enable counter/timer A0 to generate an interrupt based
on COMPR1. */
} CTIMER_CTRL0_TMRA0IE1_Enum;
/* ============================================= CTIMER CTRL0 TMRA0IE0 [9..9] ============================================== */
typedef enum { /*!< CTIMER_CTRL0_TMRA0IE0 */
CTIMER_CTRL0_TMRA0IE0_DIS = 0, /*!< DIS : Disable counter/timer A0 from generating an interrupt
based on COMPR0. */
CTIMER_CTRL0_TMRA0IE0_EN = 1, /*!< EN : Enable counter/timer A0 to generate an interrupt based
on COMPR0. */
} CTIMER_CTRL0_TMRA0IE0_Enum;
/* ============================================== CTIMER CTRL0 TMRA0FN [6..8] ============================================== */
typedef enum { /*!< CTIMER_CTRL0_TMRA0FN */
CTIMER_CTRL0_TMRA0FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
to CMPR0A0, stop. */
CTIMER_CTRL0_TMRA0FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
pulses). Count to CMPR0A0, restart. */
CTIMER_CTRL0_TMRA0FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A0, assert,
count to CMPR1A0, deassert, stop. */
CTIMER_CTRL0_TMRA0FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0A0, assert, count
to CMPR1A0, deassert, restart. */
CTIMER_CTRL0_TMRA0FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */
CTIMER_CTRL0_TMRA0FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */
CTIMER_CTRL0_TMRA0FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */
CTIMER_CTRL0_TMRA0FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */
} CTIMER_CTRL0_TMRA0FN_Enum;
/* ============================================= CTIMER CTRL0 TMRA0CLK [1..5] ============================================== */
typedef enum { /*!< CTIMER_CTRL0_TMRA0CLK */
CTIMER_CTRL0_TMRA0CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINA. */
CTIMER_CTRL0_TMRA0CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */
CTIMER_CTRL0_TMRA0CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */
CTIMER_CTRL0_TMRA0CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */
CTIMER_CTRL0_TMRA0CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */
CTIMER_CTRL0_TMRA0CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */
CTIMER_CTRL0_TMRA0CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */
CTIMER_CTRL0_TMRA0CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */
CTIMER_CTRL0_TMRA0CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */
CTIMER_CTRL0_TMRA0CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */
CTIMER_CTRL0_TMRA0CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */
CTIMER_CTRL0_TMRA0CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */
CTIMER_CTRL0_TMRA0CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */
CTIMER_CTRL0_TMRA0CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */
CTIMER_CTRL0_TMRA0CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */
CTIMER_CTRL0_TMRA0CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
available when MCU is in active mode) */
CTIMER_CTRL0_TMRA0CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */
CTIMER_CTRL0_TMRA0CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */
CTIMER_CTRL0_TMRA0CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */
CTIMER_CTRL0_TMRA0CLK_CTMRB0 = 20, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */
CTIMER_CTRL0_TMRA0CLK_CTMRA1 = 21, /*!< CTMRA1 : Clock source is CTIMERA1 OUT. */
CTIMER_CTRL0_TMRA0CLK_CTMRB1 = 22, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */
CTIMER_CTRL0_TMRA0CLK_CTMRA2 = 23, /*!< CTMRA2 : Clock source is CTIMERA2 OUT. */
CTIMER_CTRL0_TMRA0CLK_CTMRB2 = 24, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */
CTIMER_CTRL0_TMRA0CLK_CTMRB3 = 25, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */
CTIMER_CTRL0_TMRA0CLK_CTMRB4 = 26, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */
CTIMER_CTRL0_TMRA0CLK_CTMRB5 = 27, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */
CTIMER_CTRL0_TMRA0CLK_CTMRB6 = 28, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */
CTIMER_CTRL0_TMRA0CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */
CTIMER_CTRL0_TMRA0CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */
CTIMER_CTRL0_TMRA0CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */
} CTIMER_CTRL0_TMRA0CLK_Enum;
/* ============================================== CTIMER CTRL0 TMRA0EN [0..0] ============================================== */
typedef enum { /*!< CTIMER_CTRL0_TMRA0EN */
CTIMER_CTRL0_TMRA0EN_DIS = 0, /*!< DIS : Counter/Timer A0 Disable. */
CTIMER_CTRL0_TMRA0EN_EN = 1, /*!< EN : Counter/Timer A0 Enable. */
} CTIMER_CTRL0_TMRA0EN_Enum;
/* ======================================================= CMPRAUXA0 ======================================================= */
/* ======================================================= CMPRAUXB0 ======================================================= */
/* ========================================================= AUX0 ========================================================== */
/* ============================================ CTIMER AUX0 TMRB0EN23 [30..30] ============================================= */
typedef enum { /*!< CTIMER_AUX0_TMRB0EN23 */
CTIMER_AUX0_TMRB0EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */
CTIMER_AUX0_TMRB0EN23_EN = 0, /*!< EN : Enable enhanced functions. */
} CTIMER_AUX0_TMRB0EN23_Enum;
/* ============================================ CTIMER AUX0 TMRB0POL23 [29..29] ============================================ */
typedef enum { /*!< CTIMER_AUX0_TMRB0POL23 */
CTIMER_AUX0_TMRB0POL23_NORM = 0, /*!< NORM : Upper output normal polarity */
CTIMER_AUX0_TMRB0POL23_INV = 1, /*!< INV : Upper output inverted polarity. */
} CTIMER_AUX0_TMRB0POL23_Enum;
/* ============================================ CTIMER AUX0 TMRB0TINV [28..28] ============================================= */
typedef enum { /*!< CTIMER_AUX0_TMRB0TINV */
CTIMER_AUX0_TMRB0TINV_DIS = 0, /*!< DIS : Disable invert on trigger */
CTIMER_AUX0_TMRB0TINV_EN = 1, /*!< EN : Enable invert on trigger */
} CTIMER_AUX0_TMRB0TINV_Enum;
/* =========================================== CTIMER AUX0 TMRB0NOSYNC [27..27] ============================================ */
typedef enum { /*!< CTIMER_AUX0_TMRB0NOSYNC */
CTIMER_AUX0_TMRB0NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */
CTIMER_AUX0_TMRB0NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */
} CTIMER_AUX0_TMRB0NOSYNC_Enum;
/* ============================================ CTIMER AUX0 TMRB0TRIG [23..26] ============================================= */
typedef enum { /*!< CTIMER_AUX0_TMRB0TRIG */
CTIMER_AUX0_TMRB0TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */
CTIMER_AUX0_TMRB0TRIG_A0OUT = 1, /*!< A0OUT : Trigger source is CTIMERA0 OUT. */
CTIMER_AUX0_TMRB0TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */
CTIMER_AUX0_TMRB0TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */
CTIMER_AUX0_TMRB0TRIG_B2OUT = 4, /*!< B2OUT : Trigger source is CTIMERB2 OUT. */
CTIMER_AUX0_TMRB0TRIG_B5OUT = 5, /*!< B5OUT : Trigger source is CTIMERB5 OUT. */
CTIMER_AUX0_TMRB0TRIG_A4OUT = 6, /*!< A4OUT : Trigger source is CTIMERA4 OUT. */
CTIMER_AUX0_TMRB0TRIG_B4OUT = 7, /*!< B4OUT : Trigger source is CTIMERB4 OUT. */
CTIMER_AUX0_TMRB0TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */
CTIMER_AUX0_TMRB0TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */
CTIMER_AUX0_TMRB0TRIG_B7OUT2 = 10, /*!< B7OUT2 : Trigger source is CTIMERB7 OUT2. */
CTIMER_AUX0_TMRB0TRIG_A2OUT2 = 11, /*!< A2OUT2 : Trigger source is CTIMERA2 OUT2. */
CTIMER_AUX0_TMRB0TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */
CTIMER_AUX0_TMRB0TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */
CTIMER_AUX0_TMRB0TRIG_B5OUT2DUAL = 14, /*!< B5OUT2DUAL : Trigger source is CTIMERB5 OUT2, dual edge. */
CTIMER_AUX0_TMRB0TRIG_A5OUT2DUAL = 15, /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge. */
} CTIMER_AUX0_TMRB0TRIG_Enum;
/* ============================================ CTIMER AUX0 TMRA0EN23 [14..14] ============================================= */
typedef enum { /*!< CTIMER_AUX0_TMRA0EN23 */
CTIMER_AUX0_TMRA0EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */
CTIMER_AUX0_TMRA0EN23_EN = 0, /*!< EN : Enable enhanced functions. */
} CTIMER_AUX0_TMRA0EN23_Enum;
/* ============================================ CTIMER AUX0 TMRA0POL23 [13..13] ============================================ */
typedef enum { /*!< CTIMER_AUX0_TMRA0POL23 */
CTIMER_AUX0_TMRA0POL23_NORM = 0, /*!< NORM : Upper output normal polarity */
CTIMER_AUX0_TMRA0POL23_INV = 1, /*!< INV : Upper output inverted polarity. */
} CTIMER_AUX0_TMRA0POL23_Enum;
/* ============================================ CTIMER AUX0 TMRA0TINV [12..12] ============================================= */
typedef enum { /*!< CTIMER_AUX0_TMRA0TINV */
CTIMER_AUX0_TMRA0TINV_DIS = 0, /*!< DIS : Disable invert on trigger */
CTIMER_AUX0_TMRA0TINV_EN = 1, /*!< EN : Enable invert on trigger */
} CTIMER_AUX0_TMRA0TINV_Enum;
/* =========================================== CTIMER AUX0 TMRA0NOSYNC [11..11] ============================================ */
typedef enum { /*!< CTIMER_AUX0_TMRA0NOSYNC */
CTIMER_AUX0_TMRA0NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */
CTIMER_AUX0_TMRA0NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */
} CTIMER_AUX0_TMRA0NOSYNC_Enum;
/* ============================================= CTIMER AUX0 TMRA0TRIG [7..10] ============================================= */
typedef enum { /*!< CTIMER_AUX0_TMRA0TRIG */
CTIMER_AUX0_TMRA0TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */
CTIMER_AUX0_TMRA0TRIG_B0OUT = 1, /*!< B0OUT : Trigger source is CTIMERB0 OUT. */
CTIMER_AUX0_TMRA0TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */
CTIMER_AUX0_TMRA0TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */
CTIMER_AUX0_TMRA0TRIG_A1OUT = 4, /*!< A1OUT : Trigger source is CTIMERA1 OUT. */
CTIMER_AUX0_TMRA0TRIG_B1OUT = 5, /*!< B1OUT : Trigger source is CTIMERB1 OUT. */
CTIMER_AUX0_TMRA0TRIG_A5OUT = 6, /*!< A5OUT : Trigger source is CTIMERA5 OUT. */
CTIMER_AUX0_TMRA0TRIG_B5OUT = 7, /*!< B5OUT : Trigger source is CTIMERB5 OUT. */
CTIMER_AUX0_TMRA0TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */
CTIMER_AUX0_TMRA0TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */
CTIMER_AUX0_TMRA0TRIG_B6OUT2 = 10, /*!< B6OUT2 : Trigger source is CTIMERB6 OUT2. */
CTIMER_AUX0_TMRA0TRIG_A2OUT2 = 11, /*!< A2OUT2 : Trigger source is CTIMERA2 OUT2. */
CTIMER_AUX0_TMRA0TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */
CTIMER_AUX0_TMRA0TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */
CTIMER_AUX0_TMRA0TRIG_B4OUT2DUAL = 14, /*!< B4OUT2DUAL : Trigger source is CTIMERB4 OUT2, dual edge. */
CTIMER_AUX0_TMRA0TRIG_A4OUT2DUAL = 15, /*!< A4OUT2DUAL : Trigger source is CTIMERA4 OUT2, dual edge. */
} CTIMER_AUX0_TMRA0TRIG_Enum;
/* ========================================================= TMR1 ========================================================== */
/* ======================================================== CMPRA1 ========================================================= */
/* ======================================================== CMPRB1 ========================================================= */
/* ========================================================= CTRL1 ========================================================= */
/* ============================================= CTIMER CTRL1 CTLINK1 [31..31] ============================================= */
typedef enum { /*!< CTIMER_CTRL1_CTLINK1 */
CTIMER_CTRL1_CTLINK1_TWO_16BIT_TIMERS = 0, /*!< TWO_16BIT_TIMERS : Use A1/B1 timers as two independent 16-bit
timers (default). */
CTIMER_CTRL1_CTLINK1_32BIT_TIMER = 1, /*!< 32BIT_TIMER : Link A1/B1 timers into a single 32-bit timer. */
} CTIMER_CTRL1_CTLINK1_Enum;
/* ============================================ CTIMER CTRL1 TMRB1POL [28..28] ============================================= */
typedef enum { /*!< CTIMER_CTRL1_TMRB1POL */
CTIMER_CTRL1_TMRB1POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINB1 pin is the same as the
timer output. */
CTIMER_CTRL1_TMRB1POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINB1 pin is the inverse of
the timer output. */
} CTIMER_CTRL1_TMRB1POL_Enum;
/* ============================================ CTIMER CTRL1 TMRB1CLR [27..27] ============================================= */
typedef enum { /*!< CTIMER_CTRL1_TMRB1CLR */
CTIMER_CTRL1_TMRB1CLR_RUN = 0, /*!< RUN : Allow counter/timer B1 to run */
CTIMER_CTRL1_TMRB1CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer B1 at 0x0000. */
} CTIMER_CTRL1_TMRB1CLR_Enum;
/* ============================================ CTIMER CTRL1 TMRB1IE1 [26..26] ============================================= */
typedef enum { /*!< CTIMER_CTRL1_TMRB1IE1 */
CTIMER_CTRL1_TMRB1IE1_DIS = 0, /*!< DIS : Disable counter/timer B1 from generating an interrupt
based on COMPR1. */
CTIMER_CTRL1_TMRB1IE1_EN = 1, /*!< EN : Enable counter/timer B1 to generate an interrupt based
on COMPR1. */
} CTIMER_CTRL1_TMRB1IE1_Enum;
/* ============================================ CTIMER CTRL1 TMRB1IE0 [25..25] ============================================= */
typedef enum { /*!< CTIMER_CTRL1_TMRB1IE0 */
CTIMER_CTRL1_TMRB1IE0_DIS = 0, /*!< DIS : Disable counter/timer B1 from generating an interrupt
based on COMPR0. */
CTIMER_CTRL1_TMRB1IE0_EN = 1, /*!< EN : Enable counter/timer B1 to generate an interrupt based
on COMPR0 */
} CTIMER_CTRL1_TMRB1IE0_Enum;
/* ============================================= CTIMER CTRL1 TMRB1FN [22..24] ============================================= */
typedef enum { /*!< CTIMER_CTRL1_TMRB1FN */
CTIMER_CTRL1_TMRB1FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
to CMPR0B1, stop. */
CTIMER_CTRL1_TMRB1FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
pulses). Count to CMPR0B1, restart. */
CTIMER_CTRL1_TMRB1FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B1, assert,
count to CMPR1B1, deassert, stop. */
CTIMER_CTRL1_TMRB1FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0B1, assert, count
to CMPR1B1, deassert, restart. */
CTIMER_CTRL1_TMRB1FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */
CTIMER_CTRL1_TMRB1FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */
CTIMER_CTRL1_TMRB1FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */
CTIMER_CTRL1_TMRB1FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */
} CTIMER_CTRL1_TMRB1FN_Enum;
/* ============================================ CTIMER CTRL1 TMRB1CLK [17..21] ============================================= */
typedef enum { /*!< CTIMER_CTRL1_TMRB1CLK */
CTIMER_CTRL1_TMRB1CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINB. */
CTIMER_CTRL1_TMRB1CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */
CTIMER_CTRL1_TMRB1CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */
CTIMER_CTRL1_TMRB1CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */
CTIMER_CTRL1_TMRB1CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */
CTIMER_CTRL1_TMRB1CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */
CTIMER_CTRL1_TMRB1CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */
CTIMER_CTRL1_TMRB1CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */
CTIMER_CTRL1_TMRB1CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */
CTIMER_CTRL1_TMRB1CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */
CTIMER_CTRL1_TMRB1CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */
CTIMER_CTRL1_TMRB1CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */
CTIMER_CTRL1_TMRB1CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */
CTIMER_CTRL1_TMRB1CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */
CTIMER_CTRL1_TMRB1CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */
CTIMER_CTRL1_TMRB1CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
available when MCU is in active mode) */
CTIMER_CTRL1_TMRB1CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */
CTIMER_CTRL1_TMRB1CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */
CTIMER_CTRL1_TMRB1CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */
CTIMER_CTRL1_TMRB1CLK_CTMRA1 = 20, /*!< CTMRA1 : Clock source is CTIMERA1 OUT. */
CTIMER_CTRL1_TMRB1CLK_CTMRA0 = 21, /*!< CTMRA0 : Clock source is CTIMERA0 OUT. */
CTIMER_CTRL1_TMRB1CLK_CTMRB0 = 22, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */
CTIMER_CTRL1_TMRB1CLK_CTMRA2 = 23, /*!< CTMRA2 : Clock source is CTIMERA2 OUT. */
CTIMER_CTRL1_TMRB1CLK_CTMRB2 = 24, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */
CTIMER_CTRL1_TMRB1CLK_CTMRB3 = 25, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */
CTIMER_CTRL1_TMRB1CLK_CTMRB4 = 26, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */
CTIMER_CTRL1_TMRB1CLK_CTMRB5 = 27, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */
CTIMER_CTRL1_TMRB1CLK_CTMRB6 = 28, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */
CTIMER_CTRL1_TMRB1CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */
CTIMER_CTRL1_TMRB1CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */
CTIMER_CTRL1_TMRB1CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */
} CTIMER_CTRL1_TMRB1CLK_Enum;
/* ============================================= CTIMER CTRL1 TMRB1EN [16..16] ============================================= */
typedef enum { /*!< CTIMER_CTRL1_TMRB1EN */
CTIMER_CTRL1_TMRB1EN_DIS = 0, /*!< DIS : Counter/Timer B1 Disable. */
CTIMER_CTRL1_TMRB1EN_EN = 1, /*!< EN : Counter/Timer B1 Enable. */
} CTIMER_CTRL1_TMRB1EN_Enum;
/* ============================================ CTIMER CTRL1 TMRA1POL [12..12] ============================================= */
typedef enum { /*!< CTIMER_CTRL1_TMRA1POL */
CTIMER_CTRL1_TMRA1POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINA1 pin is the same as the
timer output. */
CTIMER_CTRL1_TMRA1POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINA1 pin is the inverse of
the timer output. */
} CTIMER_CTRL1_TMRA1POL_Enum;
/* ============================================ CTIMER CTRL1 TMRA1CLR [11..11] ============================================= */
typedef enum { /*!< CTIMER_CTRL1_TMRA1CLR */
CTIMER_CTRL1_TMRA1CLR_RUN = 0, /*!< RUN : Allow counter/timer A1 to run */
CTIMER_CTRL1_TMRA1CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer A1 at 0x0000. */
} CTIMER_CTRL1_TMRA1CLR_Enum;
/* ============================================ CTIMER CTRL1 TMRA1IE1 [10..10] ============================================= */
typedef enum { /*!< CTIMER_CTRL1_TMRA1IE1 */
CTIMER_CTRL1_TMRA1IE1_DIS = 0, /*!< DIS : Disable counter/timer A1 from generating an interrupt
based on COMPR1. */
CTIMER_CTRL1_TMRA1IE1_EN = 1, /*!< EN : Enable counter/timer A1 to generate an interrupt based
on COMPR1. */
} CTIMER_CTRL1_TMRA1IE1_Enum;
/* ============================================= CTIMER CTRL1 TMRA1IE0 [9..9] ============================================== */
typedef enum { /*!< CTIMER_CTRL1_TMRA1IE0 */
CTIMER_CTRL1_TMRA1IE0_DIS = 0, /*!< DIS : Disable counter/timer A1 from generating an interrupt
based on COMPR0. */
CTIMER_CTRL1_TMRA1IE0_EN = 1, /*!< EN : Enable counter/timer A1 to generate an interrupt based
on COMPR0. */
} CTIMER_CTRL1_TMRA1IE0_Enum;
/* ============================================== CTIMER CTRL1 TMRA1FN [6..8] ============================================== */
typedef enum { /*!< CTIMER_CTRL1_TMRA1FN */
CTIMER_CTRL1_TMRA1FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
to CMPR0A1, stop. */
CTIMER_CTRL1_TMRA1FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
pulses). Count to CMPR0A1, restart. */
CTIMER_CTRL1_TMRA1FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A1, assert,
count to CMPR1A1, deassert, stop. */
CTIMER_CTRL1_TMRA1FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0A1, assert, count
to CMPR1A1, deassert, restart. */
CTIMER_CTRL1_TMRA1FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */
CTIMER_CTRL1_TMRA1FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */
CTIMER_CTRL1_TMRA1FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */
CTIMER_CTRL1_TMRA1FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */
} CTIMER_CTRL1_TMRA1FN_Enum;
/* ============================================= CTIMER CTRL1 TMRA1CLK [1..5] ============================================== */
typedef enum { /*!< CTIMER_CTRL1_TMRA1CLK */
CTIMER_CTRL1_TMRA1CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINA. */
CTIMER_CTRL1_TMRA1CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */
CTIMER_CTRL1_TMRA1CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */
CTIMER_CTRL1_TMRA1CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */
CTIMER_CTRL1_TMRA1CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */
CTIMER_CTRL1_TMRA1CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */
CTIMER_CTRL1_TMRA1CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */
CTIMER_CTRL1_TMRA1CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */
CTIMER_CTRL1_TMRA1CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */
CTIMER_CTRL1_TMRA1CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */
CTIMER_CTRL1_TMRA1CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */
CTIMER_CTRL1_TMRA1CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */
CTIMER_CTRL1_TMRA1CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */
CTIMER_CTRL1_TMRA1CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */
CTIMER_CTRL1_TMRA1CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */
CTIMER_CTRL1_TMRA1CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
available when MCU is in active mode) */
CTIMER_CTRL1_TMRA1CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */
CTIMER_CTRL1_TMRA1CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */
CTIMER_CTRL1_TMRA1CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */
CTIMER_CTRL1_TMRA1CLK_CTMRB1 = 20, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */
CTIMER_CTRL1_TMRA1CLK_CTMRA0 = 21, /*!< CTMRA0 : Clock source is CTIMERA0 OUT. */
CTIMER_CTRL1_TMRA1CLK_CTMRB0 = 22, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */
CTIMER_CTRL1_TMRA1CLK_CTMRA2 = 23, /*!< CTMRA2 : Clock source is CTIMERA2 OUT. */
CTIMER_CTRL1_TMRA1CLK_CTMRB2 = 24, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */
CTIMER_CTRL1_TMRA1CLK_CTMRB3 = 25, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */
CTIMER_CTRL1_TMRA1CLK_CTMRB4 = 26, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */
CTIMER_CTRL1_TMRA1CLK_CTMRB5 = 27, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */
CTIMER_CTRL1_TMRA1CLK_CTMRB6 = 28, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */
CTIMER_CTRL1_TMRA1CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */
CTIMER_CTRL1_TMRA1CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */
CTIMER_CTRL1_TMRA1CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */
} CTIMER_CTRL1_TMRA1CLK_Enum;
/* ============================================== CTIMER CTRL1 TMRA1EN [0..0] ============================================== */
typedef enum { /*!< CTIMER_CTRL1_TMRA1EN */
CTIMER_CTRL1_TMRA1EN_DIS = 0, /*!< DIS : Counter/Timer A1 Disable. */
CTIMER_CTRL1_TMRA1EN_EN = 1, /*!< EN : Counter/Timer A1 Enable. */
} CTIMER_CTRL1_TMRA1EN_Enum;
/* ======================================================= CMPRAUXA1 ======================================================= */
/* ======================================================= CMPRAUXB1 ======================================================= */
/* ========================================================= AUX1 ========================================================== */
/* ============================================ CTIMER AUX1 TMRB1EN23 [30..30] ============================================= */
typedef enum { /*!< CTIMER_AUX1_TMRB1EN23 */
CTIMER_AUX1_TMRB1EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */
CTIMER_AUX1_TMRB1EN23_EN = 0, /*!< EN : Enable enhanced functions. */
} CTIMER_AUX1_TMRB1EN23_Enum;
/* ============================================ CTIMER AUX1 TMRB1POL23 [29..29] ============================================ */
typedef enum { /*!< CTIMER_AUX1_TMRB1POL23 */
CTIMER_AUX1_TMRB1POL23_NORM = 0, /*!< NORM : Upper output normal polarity */
CTIMER_AUX1_TMRB1POL23_INV = 1, /*!< INV : Upper output inverted polarity. */
} CTIMER_AUX1_TMRB1POL23_Enum;
/* ============================================ CTIMER AUX1 TMRB1TINV [28..28] ============================================= */
typedef enum { /*!< CTIMER_AUX1_TMRB1TINV */
CTIMER_AUX1_TMRB1TINV_DIS = 0, /*!< DIS : Disable invert on trigger */
CTIMER_AUX1_TMRB1TINV_EN = 1, /*!< EN : Enable invert on trigger */
} CTIMER_AUX1_TMRB1TINV_Enum;
/* =========================================== CTIMER AUX1 TMRB1NOSYNC [27..27] ============================================ */
typedef enum { /*!< CTIMER_AUX1_TMRB1NOSYNC */
CTIMER_AUX1_TMRB1NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */
CTIMER_AUX1_TMRB1NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */
} CTIMER_AUX1_TMRB1NOSYNC_Enum;
/* ============================================ CTIMER AUX1 TMRB1TRIG [23..26] ============================================= */
typedef enum { /*!< CTIMER_AUX1_TMRB1TRIG */
CTIMER_AUX1_TMRB1TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */
CTIMER_AUX1_TMRB1TRIG_A1OUT = 1, /*!< A1OUT : Trigger source is CTIMERA1 OUT. */
CTIMER_AUX1_TMRB1TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */
CTIMER_AUX1_TMRB1TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */
CTIMER_AUX1_TMRB1TRIG_A6OUT = 4, /*!< A6OUT : Trigger source is CTIMERA6 OUT. */
CTIMER_AUX1_TMRB1TRIG_B6OUT = 5, /*!< B6OUT : Trigger source is CTIMERB6 OUT. */
CTIMER_AUX1_TMRB1TRIG_A0OUT = 6, /*!< A0OUT : Trigger source is CTIMERA0 OUT. */
CTIMER_AUX1_TMRB1TRIG_B0OUT = 7, /*!< B0OUT : Trigger source is CTIMERB0 OUT. */
CTIMER_AUX1_TMRB1TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */
CTIMER_AUX1_TMRB1TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */
CTIMER_AUX1_TMRB1TRIG_A4OUT2 = 10, /*!< A4OUT2 : Trigger source is CTIMERA4 OUT2. */
CTIMER_AUX1_TMRB1TRIG_B4OUT2 = 11, /*!< B4OUT2 : Trigger source is CTIMERB4 OUT2. */
CTIMER_AUX1_TMRB1TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */
CTIMER_AUX1_TMRB1TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */
CTIMER_AUX1_TMRB1TRIG_B5OUT2DUAL = 14, /*!< B5OUT2DUAL : Trigger source is CTIMERB5 OUT2, dual edge. */
CTIMER_AUX1_TMRB1TRIG_A5OUT2DUAL = 15, /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge. */
} CTIMER_AUX1_TMRB1TRIG_Enum;
/* ============================================ CTIMER AUX1 TMRA1EN23 [14..14] ============================================= */
typedef enum { /*!< CTIMER_AUX1_TMRA1EN23 */
CTIMER_AUX1_TMRA1EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */
CTIMER_AUX1_TMRA1EN23_EN = 0, /*!< EN : Enable enhanced functions. */
} CTIMER_AUX1_TMRA1EN23_Enum;
/* ============================================ CTIMER AUX1 TMRA1POL23 [13..13] ============================================ */
typedef enum { /*!< CTIMER_AUX1_TMRA1POL23 */
CTIMER_AUX1_TMRA1POL23_NORMAL = 0, /*!< NORMAL : Upper output normal polarity */
CTIMER_AUX1_TMRA1POL23_INV = 1, /*!< INV : Upper output inverted polarity. */
} CTIMER_AUX1_TMRA1POL23_Enum;
/* ============================================ CTIMER AUX1 TMRA1TINV [12..12] ============================================= */
typedef enum { /*!< CTIMER_AUX1_TMRA1TINV */
CTIMER_AUX1_TMRA1TINV_DIS = 0, /*!< DIS : Disable invert on trigger */
CTIMER_AUX1_TMRA1TINV_EN = 1, /*!< EN : Enable invert on trigger */
} CTIMER_AUX1_TMRA1TINV_Enum;
/* =========================================== CTIMER AUX1 TMRA1NOSYNC [11..11] ============================================ */
typedef enum { /*!< CTIMER_AUX1_TMRA1NOSYNC */
CTIMER_AUX1_TMRA1NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */
CTIMER_AUX1_TMRA1NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */
} CTIMER_AUX1_TMRA1NOSYNC_Enum;
/* ============================================= CTIMER AUX1 TMRA1TRIG [7..10] ============================================= */
typedef enum { /*!< CTIMER_AUX1_TMRA1TRIG */
CTIMER_AUX1_TMRA1TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */
CTIMER_AUX1_TMRA1TRIG_B1OUT = 1, /*!< B1OUT : Trigger source is CTIMERB1 OUT. */
CTIMER_AUX1_TMRA1TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */
CTIMER_AUX1_TMRA1TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */
CTIMER_AUX1_TMRA1TRIG_A0OUT = 4, /*!< A0OUT : Trigger source is CTIMERA0 OUT. */
CTIMER_AUX1_TMRA1TRIG_B0OUT = 5, /*!< B0OUT : Trigger source is CTIMERB0 OUT. */
CTIMER_AUX1_TMRA1TRIG_A5OUT = 6, /*!< A5OUT : Trigger source is CTIMERA5 OUT. */
CTIMER_AUX1_TMRA1TRIG_B5OUT = 7, /*!< B5OUT : Trigger source is CTIMERB5 OUT. */
CTIMER_AUX1_TMRA1TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */
CTIMER_AUX1_TMRA1TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */
CTIMER_AUX1_TMRA1TRIG_A4OUT2 = 10, /*!< A4OUT2 : Trigger source is CTIMERA4 OUT2. */
CTIMER_AUX1_TMRA1TRIG_B4OUT2 = 11, /*!< B4OUT2 : Trigger source is CTIMERB4 OUT2. */
CTIMER_AUX1_TMRA1TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */
CTIMER_AUX1_TMRA1TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */
CTIMER_AUX1_TMRA1TRIG_B5OUT2DUAL = 14, /*!< B5OUT2DUAL : Trigger source is CTIMERB5 OUT2, dual edge. */
CTIMER_AUX1_TMRA1TRIG_A5OUT2DUAL = 15, /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge. */
} CTIMER_AUX1_TMRA1TRIG_Enum;
/* ========================================================= TMR2 ========================================================== */
/* ======================================================== CMPRA2 ========================================================= */
/* ======================================================== CMPRB2 ========================================================= */
/* ========================================================= CTRL2 ========================================================= */
/* ============================================= CTIMER CTRL2 CTLINK2 [31..31] ============================================= */
typedef enum { /*!< CTIMER_CTRL2_CTLINK2 */
CTIMER_CTRL2_CTLINK2_TWO_16BIT_TIMERS = 0, /*!< TWO_16BIT_TIMERS : Use A2/B2 timers as two independent 16-bit
timers (default). */
CTIMER_CTRL2_CTLINK2_32BIT_TIMER = 1, /*!< 32BIT_TIMER : Link A2/B2 timers into a single 32-bit timer. */
} CTIMER_CTRL2_CTLINK2_Enum;
/* ============================================ CTIMER CTRL2 TMRB2POL [28..28] ============================================= */
typedef enum { /*!< CTIMER_CTRL2_TMRB2POL */
CTIMER_CTRL2_TMRB2POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINB2 pin is the same as the
timer output. */
CTIMER_CTRL2_TMRB2POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINB2 pin is the inverse of
the timer output. */
} CTIMER_CTRL2_TMRB2POL_Enum;
/* ============================================ CTIMER CTRL2 TMRB2CLR [27..27] ============================================= */
typedef enum { /*!< CTIMER_CTRL2_TMRB2CLR */
CTIMER_CTRL2_TMRB2CLR_RUN = 0, /*!< RUN : Allow counter/timer B2 to run */
CTIMER_CTRL2_TMRB2CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer B2 at 0x0000. */
} CTIMER_CTRL2_TMRB2CLR_Enum;
/* ============================================ CTIMER CTRL2 TMRB2IE1 [26..26] ============================================= */
typedef enum { /*!< CTIMER_CTRL2_TMRB2IE1 */
CTIMER_CTRL2_TMRB2IE1_DIS = 0, /*!< DIS : Disable counter/timer B2 from generating an interrupt
based on COMPR1. */
CTIMER_CTRL2_TMRB2IE1_EN = 1, /*!< EN : Enable counter/timer B2 to generate an interrupt based
on COMPR1. */
} CTIMER_CTRL2_TMRB2IE1_Enum;
/* ============================================ CTIMER CTRL2 TMRB2IE0 [25..25] ============================================= */
typedef enum { /*!< CTIMER_CTRL2_TMRB2IE0 */
CTIMER_CTRL2_TMRB2IE0_DIS = 0, /*!< DIS : Disable counter/timer B2 from generating an interrupt
based on COMPR0. */
CTIMER_CTRL2_TMRB2IE0_EN = 1, /*!< EN : Enable counter/timer B2 to generate an interrupt based
on COMPR0 */
} CTIMER_CTRL2_TMRB2IE0_Enum;
/* ============================================= CTIMER CTRL2 TMRB2FN [22..24] ============================================= */
typedef enum { /*!< CTIMER_CTRL2_TMRB2FN */
CTIMER_CTRL2_TMRB2FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
to CMPR0B2, stop. */
CTIMER_CTRL2_TMRB2FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
pulses). Count to CMPR0B2, restart. */
CTIMER_CTRL2_TMRB2FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B2, assert,
count to CMPR1B2, deassert, stop. */
CTIMER_CTRL2_TMRB2FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0B2, assert, count
to CMPR1B2, deassert, restart. */
CTIMER_CTRL2_TMRB2FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */
CTIMER_CTRL2_TMRB2FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */
CTIMER_CTRL2_TMRB2FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */
CTIMER_CTRL2_TMRB2FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */
} CTIMER_CTRL2_TMRB2FN_Enum;
/* ============================================ CTIMER CTRL2 TMRB2CLK [17..21] ============================================= */
typedef enum { /*!< CTIMER_CTRL2_TMRB2CLK */
CTIMER_CTRL2_TMRB2CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINB. */
CTIMER_CTRL2_TMRB2CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */
CTIMER_CTRL2_TMRB2CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */
CTIMER_CTRL2_TMRB2CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */
CTIMER_CTRL2_TMRB2CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */
CTIMER_CTRL2_TMRB2CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */
CTIMER_CTRL2_TMRB2CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */
CTIMER_CTRL2_TMRB2CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */
CTIMER_CTRL2_TMRB2CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */
CTIMER_CTRL2_TMRB2CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */
CTIMER_CTRL2_TMRB2CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */
CTIMER_CTRL2_TMRB2CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */
CTIMER_CTRL2_TMRB2CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */
CTIMER_CTRL2_TMRB2CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */
CTIMER_CTRL2_TMRB2CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */
CTIMER_CTRL2_TMRB2CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
available when MCU is in active mode) */
CTIMER_CTRL2_TMRB2CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */
CTIMER_CTRL2_TMRB2CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */
CTIMER_CTRL2_TMRB2CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */
CTIMER_CTRL2_TMRB2CLK_CTMRA2 = 20, /*!< CTMRA2 : Clock source is CTIMERA2 OUT. */
CTIMER_CTRL2_TMRB2CLK_CTMRB3 = 21, /*!< CTMRB3 : Clock source is CTIMERA3 OUT. */
CTIMER_CTRL2_TMRB2CLK_CTMRA3 = 22, /*!< CTMRA3 : Clock source is CTIMERB3 OUT. */
CTIMER_CTRL2_TMRB2CLK_CTMRA4 = 23, /*!< CTMRA4 : Clock source is CTIMERA4 OUT. */
CTIMER_CTRL2_TMRB2CLK_CTMRB4 = 24, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */
CTIMER_CTRL2_TMRB2CLK_CTMRB0 = 25, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */
CTIMER_CTRL2_TMRB2CLK_CTMRB1 = 26, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */
CTIMER_CTRL2_TMRB2CLK_CTMRB5 = 27, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */
CTIMER_CTRL2_TMRB2CLK_CTMRB6 = 28, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */
CTIMER_CTRL2_TMRB2CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */
CTIMER_CTRL2_TMRB2CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */
CTIMER_CTRL2_TMRB2CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */
} CTIMER_CTRL2_TMRB2CLK_Enum;
/* ============================================= CTIMER CTRL2 TMRB2EN [16..16] ============================================= */
typedef enum { /*!< CTIMER_CTRL2_TMRB2EN */
CTIMER_CTRL2_TMRB2EN_DIS = 0, /*!< DIS : Counter/Timer B2 Disable. */
CTIMER_CTRL2_TMRB2EN_EN = 1, /*!< EN : Counter/Timer B2 Enable. */
} CTIMER_CTRL2_TMRB2EN_Enum;
/* ============================================ CTIMER CTRL2 TMRA2POL [12..12] ============================================= */
typedef enum { /*!< CTIMER_CTRL2_TMRA2POL */
CTIMER_CTRL2_TMRA2POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINA2 pin is the same as the
timer output. */
CTIMER_CTRL2_TMRA2POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINA2 pin is the inverse of
the timer output. */
} CTIMER_CTRL2_TMRA2POL_Enum;
/* ============================================ CTIMER CTRL2 TMRA2CLR [11..11] ============================================= */
typedef enum { /*!< CTIMER_CTRL2_TMRA2CLR */
CTIMER_CTRL2_TMRA2CLR_RUN = 0, /*!< RUN : Allow counter/timer A2 to run */
CTIMER_CTRL2_TMRA2CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer A2 at 0x0000. */
} CTIMER_CTRL2_TMRA2CLR_Enum;
/* ============================================ CTIMER CTRL2 TMRA2IE1 [10..10] ============================================= */
typedef enum { /*!< CTIMER_CTRL2_TMRA2IE1 */
CTIMER_CTRL2_TMRA2IE1_DIS = 0, /*!< DIS : Disable counter/timer A2 from generating an interrupt
based on COMPR1. */
CTIMER_CTRL2_TMRA2IE1_EN = 1, /*!< EN : Enable counter/timer A2 to generate an interrupt based
on COMPR1. */
} CTIMER_CTRL2_TMRA2IE1_Enum;
/* ============================================= CTIMER CTRL2 TMRA2IE0 [9..9] ============================================== */
typedef enum { /*!< CTIMER_CTRL2_TMRA2IE0 */
CTIMER_CTRL2_TMRA2IE0_DIS = 0, /*!< DIS : Disable counter/timer A2 from generating an interrupt
based on COMPR0. */
CTIMER_CTRL2_TMRA2IE0_EN = 1, /*!< EN : Enable counter/timer A2 to generate an interrupt based
on COMPR0. */
} CTIMER_CTRL2_TMRA2IE0_Enum;
/* ============================================== CTIMER CTRL2 TMRA2FN [6..8] ============================================== */
typedef enum { /*!< CTIMER_CTRL2_TMRA2FN */
CTIMER_CTRL2_TMRA2FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
to CMPR0A2, stop. */
CTIMER_CTRL2_TMRA2FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
pulses). Count to CMPR0A2, restart. */
CTIMER_CTRL2_TMRA2FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A2, assert,
count to CMPR1A2, deassert, stop. */
CTIMER_CTRL2_TMRA2FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0A2, assert, count
to CMPR1A2, deassert, restart. */
CTIMER_CTRL2_TMRA2FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */
CTIMER_CTRL2_TMRA2FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */
CTIMER_CTRL2_TMRA2FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */
CTIMER_CTRL2_TMRA2FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */
} CTIMER_CTRL2_TMRA2FN_Enum;
/* ============================================= CTIMER CTRL2 TMRA2CLK [1..5] ============================================== */
typedef enum { /*!< CTIMER_CTRL2_TMRA2CLK */
CTIMER_CTRL2_TMRA2CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINA. */
CTIMER_CTRL2_TMRA2CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */
CTIMER_CTRL2_TMRA2CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */
CTIMER_CTRL2_TMRA2CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */
CTIMER_CTRL2_TMRA2CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */
CTIMER_CTRL2_TMRA2CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */
CTIMER_CTRL2_TMRA2CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */
CTIMER_CTRL2_TMRA2CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */
CTIMER_CTRL2_TMRA2CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */
CTIMER_CTRL2_TMRA2CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */
CTIMER_CTRL2_TMRA2CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */
CTIMER_CTRL2_TMRA2CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */
CTIMER_CTRL2_TMRA2CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */
CTIMER_CTRL2_TMRA2CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */
CTIMER_CTRL2_TMRA2CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */
CTIMER_CTRL2_TMRA2CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
available when MCU is in active mode) */
CTIMER_CTRL2_TMRA2CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */
CTIMER_CTRL2_TMRA2CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */
CTIMER_CTRL2_TMRA2CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */
CTIMER_CTRL2_TMRA2CLK_CTMRB2 = 20, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */
CTIMER_CTRL2_TMRA2CLK_CTMRB3 = 21, /*!< CTMRB3 : Clock source is CTIMERA3 OUT. */
CTIMER_CTRL2_TMRA2CLK_CTMRA3 = 22, /*!< CTMRA3 : Clock source is CTIMERB3 OUT. */
CTIMER_CTRL2_TMRA2CLK_CTMRA4 = 23, /*!< CTMRA4 : Clock source is CTIMERA4 OUT. */
CTIMER_CTRL2_TMRA2CLK_CTMRB4 = 24, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */
CTIMER_CTRL2_TMRA2CLK_CTMRB0 = 25, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */
CTIMER_CTRL2_TMRA2CLK_CTMRB1 = 26, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */
CTIMER_CTRL2_TMRA2CLK_CTMRB5 = 27, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */
CTIMER_CTRL2_TMRA2CLK_CTMRB6 = 28, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */
CTIMER_CTRL2_TMRA2CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */
CTIMER_CTRL2_TMRA2CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */
CTIMER_CTRL2_TMRA2CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */
} CTIMER_CTRL2_TMRA2CLK_Enum;
/* ============================================== CTIMER CTRL2 TMRA2EN [0..0] ============================================== */
typedef enum { /*!< CTIMER_CTRL2_TMRA2EN */
CTIMER_CTRL2_TMRA2EN_DIS = 0, /*!< DIS : Counter/Timer A2 Disable. */
CTIMER_CTRL2_TMRA2EN_EN = 1, /*!< EN : Counter/Timer A2 Enable. */
} CTIMER_CTRL2_TMRA2EN_Enum;
/* ======================================================= CMPRAUXA2 ======================================================= */
/* ======================================================= CMPRAUXB2 ======================================================= */
/* ========================================================= AUX2 ========================================================== */
/* ============================================ CTIMER AUX2 TMRB2EN23 [30..30] ============================================= */
typedef enum { /*!< CTIMER_AUX2_TMRB2EN23 */
CTIMER_AUX2_TMRB2EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */
CTIMER_AUX2_TMRB2EN23_EN = 0, /*!< EN : Enable enhanced functions. */
} CTIMER_AUX2_TMRB2EN23_Enum;
/* ============================================ CTIMER AUX2 TMRB2POL23 [29..29] ============================================ */
typedef enum { /*!< CTIMER_AUX2_TMRB2POL23 */
CTIMER_AUX2_TMRB2POL23_NORM = 0, /*!< NORM : Upper output normal polarity */
CTIMER_AUX2_TMRB2POL23_INV = 1, /*!< INV : Upper output inverted polarity. */
} CTIMER_AUX2_TMRB2POL23_Enum;
/* ============================================ CTIMER AUX2 TMRB2TINV [28..28] ============================================= */
typedef enum { /*!< CTIMER_AUX2_TMRB2TINV */
CTIMER_AUX2_TMRB2TINV_DIS = 0, /*!< DIS : Disable invert on trigger */
CTIMER_AUX2_TMRB2TINV_EN = 1, /*!< EN : Enable invert on trigger */
} CTIMER_AUX2_TMRB2TINV_Enum;
/* =========================================== CTIMER AUX2 TMRB2NOSYNC [27..27] ============================================ */
typedef enum { /*!< CTIMER_AUX2_TMRB2NOSYNC */
CTIMER_AUX2_TMRB2NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */
CTIMER_AUX2_TMRB2NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */
} CTIMER_AUX2_TMRB2NOSYNC_Enum;
/* ============================================ CTIMER AUX2 TMRB2TRIG [23..26] ============================================= */
typedef enum { /*!< CTIMER_AUX2_TMRB2TRIG */
CTIMER_AUX2_TMRB2TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */
CTIMER_AUX2_TMRB2TRIG_A2OUT = 1, /*!< A2OUT : Trigger source is CTIMERA2 OUT. */
CTIMER_AUX2_TMRB2TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */
CTIMER_AUX2_TMRB2TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */
CTIMER_AUX2_TMRB2TRIG_A1OUT = 4, /*!< A1OUT : Trigger source is CTIMERA1 OUT. */
CTIMER_AUX2_TMRB2TRIG_B1OUT = 5, /*!< B1OUT : Trigger source is CTIMERB1 OUT. */
CTIMER_AUX2_TMRB2TRIG_A4OUT = 6, /*!< A4OUT : Trigger source is CTIMERA4 OUT. */
CTIMER_AUX2_TMRB2TRIG_B4OUT = 7, /*!< B4OUT : Trigger source is CTIMERB4 OUT. */
CTIMER_AUX2_TMRB2TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */
CTIMER_AUX2_TMRB2TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */
CTIMER_AUX2_TMRB2TRIG_A5OUT2 = 10, /*!< A5OUT2 : Trigger source is CTIMERA5 OUT2. */
CTIMER_AUX2_TMRB2TRIG_B5OUT2 = 11, /*!< B5OUT2 : Trigger source is CTIMERB5 OUT2. */
CTIMER_AUX2_TMRB2TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */
CTIMER_AUX2_TMRB2TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */
CTIMER_AUX2_TMRB2TRIG_B4OUT2DUAL = 14, /*!< B4OUT2DUAL : Trigger source is CTIMERB4 OUT2, dual edge. */
CTIMER_AUX2_TMRB2TRIG_A4OUT2DUAL = 15, /*!< A4OUT2DUAL : Trigger source is CTIMERA4 OUT2, dual edge. */
} CTIMER_AUX2_TMRB2TRIG_Enum;
/* ============================================ CTIMER AUX2 TMRA2EN23 [14..14] ============================================= */
typedef enum { /*!< CTIMER_AUX2_TMRA2EN23 */
CTIMER_AUX2_TMRA2EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */
CTIMER_AUX2_TMRA2EN23_EN = 0, /*!< EN : Enable enhanced functions. */
} CTIMER_AUX2_TMRA2EN23_Enum;
/* ============================================ CTIMER AUX2 TMRA2POL23 [13..13] ============================================ */
typedef enum { /*!< CTIMER_AUX2_TMRA2POL23 */
CTIMER_AUX2_TMRA2POL23_NORM = 0, /*!< NORM : Upper output normal polarity */
CTIMER_AUX2_TMRA2POL23_INV = 1, /*!< INV : Upper output inverted polarity. */
} CTIMER_AUX2_TMRA2POL23_Enum;
/* ============================================ CTIMER AUX2 TMRA2TINV [12..12] ============================================= */
typedef enum { /*!< CTIMER_AUX2_TMRA2TINV */
CTIMER_AUX2_TMRA2TINV_DIS = 0, /*!< DIS : Disable invert on trigger */
CTIMER_AUX2_TMRA2TINV_EN = 1, /*!< EN : Enable invert on trigger */
} CTIMER_AUX2_TMRA2TINV_Enum;
/* =========================================== CTIMER AUX2 TMRA2NOSYNC [11..11] ============================================ */
typedef enum { /*!< CTIMER_AUX2_TMRA2NOSYNC */
CTIMER_AUX2_TMRA2NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */
CTIMER_AUX2_TMRA2NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */
} CTIMER_AUX2_TMRA2NOSYNC_Enum;
/* ============================================= CTIMER AUX2 TMRA2TRIG [7..10] ============================================= */
typedef enum { /*!< CTIMER_AUX2_TMRA2TRIG */
CTIMER_AUX2_TMRA2TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */
CTIMER_AUX2_TMRA2TRIG_B2OUT = 1, /*!< B2OUT : Trigger source is CTIMERB2 OUT. */
CTIMER_AUX2_TMRA2TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */
CTIMER_AUX2_TMRA2TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */
CTIMER_AUX2_TMRA2TRIG_A0OUT = 4, /*!< A0OUT : Trigger source is CTIMERA0 OUT. */
CTIMER_AUX2_TMRA2TRIG_B0OUT = 5, /*!< B0OUT : Trigger source is CTIMERB0 OUT. */
CTIMER_AUX2_TMRA2TRIG_A4OUT = 6, /*!< A4OUT : Trigger source is CTIMERA4 OUT. */
CTIMER_AUX2_TMRA2TRIG_B4OUT = 7, /*!< B4OUT : Trigger source is CTIMERB4 OUT. */
CTIMER_AUX2_TMRA2TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */
CTIMER_AUX2_TMRA2TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */
CTIMER_AUX2_TMRA2TRIG_A5OUT2 = 10, /*!< A5OUT2 : Trigger source is CTIMERA5 OUT2. */
CTIMER_AUX2_TMRA2TRIG_B5OUT2 = 11, /*!< B5OUT2 : Trigger source is CTIMERB5 OUT2. */
CTIMER_AUX2_TMRA2TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */
CTIMER_AUX2_TMRA2TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */
CTIMER_AUX2_TMRA2TRIG_B4OUT2DUAL = 14, /*!< B4OUT2DUAL : Trigger source is CTIMERB4 OUT2, dual edge. */
CTIMER_AUX2_TMRA2TRIG_A4OUT2DUAL = 15, /*!< A4OUT2DUAL : Trigger source is CTIMERA4 OUT2, dual edge. */
} CTIMER_AUX2_TMRA2TRIG_Enum;
/* ========================================================= TMR3 ========================================================== */
/* ======================================================== CMPRA3 ========================================================= */
/* ======================================================== CMPRB3 ========================================================= */
/* ========================================================= CTRL3 ========================================================= */
/* ============================================= CTIMER CTRL3 CTLINK3 [31..31] ============================================= */
typedef enum { /*!< CTIMER_CTRL3_CTLINK3 */
CTIMER_CTRL3_CTLINK3_TWO_16BIT_TIMERS = 0, /*!< TWO_16BIT_TIMERS : Use A3/B3 timers as two independent 16-bit
timers (default). */
CTIMER_CTRL3_CTLINK3_32BIT_TIMER = 1, /*!< 32BIT_TIMER : Link A3/B3 timers into a single 32-bit timer. */
} CTIMER_CTRL3_CTLINK3_Enum;
/* ============================================ CTIMER CTRL3 TMRB3POL [28..28] ============================================= */
typedef enum { /*!< CTIMER_CTRL3_TMRB3POL */
CTIMER_CTRL3_TMRB3POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINB3 pin is the same as the
timer output. */
CTIMER_CTRL3_TMRB3POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINB3 pin is the inverse of
the timer output. */
} CTIMER_CTRL3_TMRB3POL_Enum;
/* ============================================ CTIMER CTRL3 TMRB3CLR [27..27] ============================================= */
typedef enum { /*!< CTIMER_CTRL3_TMRB3CLR */
CTIMER_CTRL3_TMRB3CLR_RUN = 0, /*!< RUN : Allow counter/timer B3 to run */
CTIMER_CTRL3_TMRB3CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer B3 at 0x0000. */
} CTIMER_CTRL3_TMRB3CLR_Enum;
/* ============================================ CTIMER CTRL3 TMRB3IE1 [26..26] ============================================= */
typedef enum { /*!< CTIMER_CTRL3_TMRB3IE1 */
CTIMER_CTRL3_TMRB3IE1_DIS = 0, /*!< DIS : Disable counter/timer B3 from generating an interrupt
based on COMPR1. */
CTIMER_CTRL3_TMRB3IE1_EN = 1, /*!< EN : Enable counter/timer B3 to generate an interrupt based
on COMPR1. */
} CTIMER_CTRL3_TMRB3IE1_Enum;
/* ============================================ CTIMER CTRL3 TMRB3IE0 [25..25] ============================================= */
typedef enum { /*!< CTIMER_CTRL3_TMRB3IE0 */
CTIMER_CTRL3_TMRB3IE0_DIS = 0, /*!< DIS : Disable counter/timer B3 from generating an interrupt
based on COMPR0. */
CTIMER_CTRL3_TMRB3IE0_EN = 1, /*!< EN : Enable counter/timer B3 to generate an interrupt based
on COMPR0 */
} CTIMER_CTRL3_TMRB3IE0_Enum;
/* ============================================= CTIMER CTRL3 TMRB3FN [22..24] ============================================= */
typedef enum { /*!< CTIMER_CTRL3_TMRB3FN */
CTIMER_CTRL3_TMRB3FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
to CMPR0B3, stop. */
CTIMER_CTRL3_TMRB3FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
pulses). Count to CMPR0B3, restart. */
CTIMER_CTRL3_TMRB3FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B3, assert,
count to CMPR1B3, deassert, stop. */
CTIMER_CTRL3_TMRB3FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0B3, assert, count
to CMPR1B3, deassert, restart. */
CTIMER_CTRL3_TMRB3FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */
CTIMER_CTRL3_TMRB3FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */
CTIMER_CTRL3_TMRB3FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */
CTIMER_CTRL3_TMRB3FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */
} CTIMER_CTRL3_TMRB3FN_Enum;
/* ============================================ CTIMER CTRL3 TMRB3CLK [17..21] ============================================= */
typedef enum { /*!< CTIMER_CTRL3_TMRB3CLK */
CTIMER_CTRL3_TMRB3CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINB. */
CTIMER_CTRL3_TMRB3CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */
CTIMER_CTRL3_TMRB3CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */
CTIMER_CTRL3_TMRB3CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */
CTIMER_CTRL3_TMRB3CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */
CTIMER_CTRL3_TMRB3CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */
CTIMER_CTRL3_TMRB3CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */
CTIMER_CTRL3_TMRB3CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */
CTIMER_CTRL3_TMRB3CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */
CTIMER_CTRL3_TMRB3CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */
CTIMER_CTRL3_TMRB3CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */
CTIMER_CTRL3_TMRB3CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */
CTIMER_CTRL3_TMRB3CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */
CTIMER_CTRL3_TMRB3CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */
CTIMER_CTRL3_TMRB3CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */
CTIMER_CTRL3_TMRB3CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
available when MCU is in active mode) */
CTIMER_CTRL3_TMRB3CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */
CTIMER_CTRL3_TMRB3CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */
CTIMER_CTRL3_TMRB3CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */
CTIMER_CTRL3_TMRB3CLK_CTMRA3 = 20, /*!< CTMRA3 : Clock source is CTIMERA3 OUT. */
CTIMER_CTRL3_TMRB3CLK_CTMRA2 = 21, /*!< CTMRA2 : Clock source is CTIMERA2 OUT. */
CTIMER_CTRL3_TMRB3CLK_CTMRB2 = 22, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */
CTIMER_CTRL3_TMRB3CLK_CTMRA4 = 23, /*!< CTMRA4 : Clock source is CTIMERA4 OUT. */
CTIMER_CTRL3_TMRB3CLK_CTMRB4 = 24, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */
CTIMER_CTRL3_TMRB3CLK_CTMRB0 = 25, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */
CTIMER_CTRL3_TMRB3CLK_CTMRB1 = 26, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */
CTIMER_CTRL3_TMRB3CLK_CTMRB5 = 27, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */
CTIMER_CTRL3_TMRB3CLK_CTMRB6 = 28, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */
CTIMER_CTRL3_TMRB3CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */
CTIMER_CTRL3_TMRB3CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */
CTIMER_CTRL3_TMRB3CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */
} CTIMER_CTRL3_TMRB3CLK_Enum;
/* ============================================= CTIMER CTRL3 TMRB3EN [16..16] ============================================= */
typedef enum { /*!< CTIMER_CTRL3_TMRB3EN */
CTIMER_CTRL3_TMRB3EN_DIS = 0, /*!< DIS : Counter/Timer B3 Disable. */
CTIMER_CTRL3_TMRB3EN_EN = 1, /*!< EN : Counter/Timer B3 Enable. */
} CTIMER_CTRL3_TMRB3EN_Enum;
/* ============================================ CTIMER CTRL3 TMRA3POL [12..12] ============================================= */
typedef enum { /*!< CTIMER_CTRL3_TMRA3POL */
CTIMER_CTRL3_TMRA3POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINA3 pin is the same as the
timer output. */
CTIMER_CTRL3_TMRA3POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINA3 pin is the inverse of
the timer output. */
} CTIMER_CTRL3_TMRA3POL_Enum;
/* ============================================ CTIMER CTRL3 TMRA3CLR [11..11] ============================================= */
typedef enum { /*!< CTIMER_CTRL3_TMRA3CLR */
CTIMER_CTRL3_TMRA3CLR_RUN = 0, /*!< RUN : Allow counter/timer A3 to run */
CTIMER_CTRL3_TMRA3CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer A3 at 0x0000. */
} CTIMER_CTRL3_TMRA3CLR_Enum;
/* ============================================ CTIMER CTRL3 TMRA3IE1 [10..10] ============================================= */
typedef enum { /*!< CTIMER_CTRL3_TMRA3IE1 */
CTIMER_CTRL3_TMRA3IE1_DIS = 0, /*!< DIS : Disable counter/timer A3 from generating an interrupt
based on COMPR1. */
CTIMER_CTRL3_TMRA3IE1_EN = 1, /*!< EN : Enable counter/timer A3 to generate an interrupt based
on COMPR1. */
} CTIMER_CTRL3_TMRA3IE1_Enum;
/* ============================================= CTIMER CTRL3 TMRA3IE0 [9..9] ============================================== */
typedef enum { /*!< CTIMER_CTRL3_TMRA3IE0 */
CTIMER_CTRL3_TMRA3IE0_DIS = 0, /*!< DIS : Disable counter/timer A3 from generating an interrupt
based on COMPR0. */
CTIMER_CTRL3_TMRA3IE0_EN = 1, /*!< EN : Enable counter/timer A3 to generate an interrupt based
on COMPR0. */
} CTIMER_CTRL3_TMRA3IE0_Enum;
/* ============================================== CTIMER CTRL3 TMRA3FN [6..8] ============================================== */
typedef enum { /*!< CTIMER_CTRL3_TMRA3FN */
CTIMER_CTRL3_TMRA3FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
to CMPR0A3, stop. */
CTIMER_CTRL3_TMRA3FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
pulses). Count to CMPR0A3, restart. */
CTIMER_CTRL3_TMRA3FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A3, assert,
count to CMPR1A3, deassert, stop. */
CTIMER_CTRL3_TMRA3FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0A3, assert, count
to CMPR1A3, deassert, restart. */
CTIMER_CTRL3_TMRA3FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */
CTIMER_CTRL3_TMRA3FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */
CTIMER_CTRL3_TMRA3FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */
CTIMER_CTRL3_TMRA3FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */
} CTIMER_CTRL3_TMRA3FN_Enum;
/* ============================================= CTIMER CTRL3 TMRA3CLK [1..5] ============================================== */
typedef enum { /*!< CTIMER_CTRL3_TMRA3CLK */
CTIMER_CTRL3_TMRA3CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINA. */
CTIMER_CTRL3_TMRA3CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */
CTIMER_CTRL3_TMRA3CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */
CTIMER_CTRL3_TMRA3CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */
CTIMER_CTRL3_TMRA3CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */
CTIMER_CTRL3_TMRA3CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */
CTIMER_CTRL3_TMRA3CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */
CTIMER_CTRL3_TMRA3CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */
CTIMER_CTRL3_TMRA3CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */
CTIMER_CTRL3_TMRA3CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */
CTIMER_CTRL3_TMRA3CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */
CTIMER_CTRL3_TMRA3CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */
CTIMER_CTRL3_TMRA3CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */
CTIMER_CTRL3_TMRA3CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */
CTIMER_CTRL3_TMRA3CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */
CTIMER_CTRL3_TMRA3CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
available when MCU is in active mode) */
CTIMER_CTRL3_TMRA3CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */
CTIMER_CTRL3_TMRA3CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */
CTIMER_CTRL3_TMRA3CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */
CTIMER_CTRL3_TMRA3CLK_CTMRB3 = 20, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */
CTIMER_CTRL3_TMRA3CLK_CTMRA2 = 21, /*!< CTMRA2 : Clock source is CTIMERA2 OUT. */
CTIMER_CTRL3_TMRA3CLK_CTMRB2 = 22, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */
CTIMER_CTRL3_TMRA3CLK_CTMRA4 = 23, /*!< CTMRA4 : Clock source is CTIMERA4 OUT. */
CTIMER_CTRL3_TMRA3CLK_CTMRB4 = 24, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */
CTIMER_CTRL3_TMRA3CLK_CTMRB0 = 25, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */
CTIMER_CTRL3_TMRA3CLK_CTMRB1 = 26, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */
CTIMER_CTRL3_TMRA3CLK_CTMRB5 = 27, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */
CTIMER_CTRL3_TMRA3CLK_CTMRB6 = 28, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */
CTIMER_CTRL3_TMRA3CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */
CTIMER_CTRL3_TMRA3CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */
CTIMER_CTRL3_TMRA3CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */
} CTIMER_CTRL3_TMRA3CLK_Enum;
/* ============================================== CTIMER CTRL3 TMRA3EN [0..0] ============================================== */
typedef enum { /*!< CTIMER_CTRL3_TMRA3EN */
CTIMER_CTRL3_TMRA3EN_DIS = 0, /*!< DIS : Counter/Timer A3 Disable. */
CTIMER_CTRL3_TMRA3EN_EN = 1, /*!< EN : Counter/Timer A3 Enable. */
} CTIMER_CTRL3_TMRA3EN_Enum;
/* ======================================================= CMPRAUXA3 ======================================================= */
/* ======================================================= CMPRAUXB3 ======================================================= */
/* ========================================================= AUX3 ========================================================== */
/* ============================================ CTIMER AUX3 TMRB3EN23 [30..30] ============================================= */
typedef enum { /*!< CTIMER_AUX3_TMRB3EN23 */
CTIMER_AUX3_TMRB3EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */
CTIMER_AUX3_TMRB3EN23_EN = 0, /*!< EN : Enable enhanced functions. */
} CTIMER_AUX3_TMRB3EN23_Enum;
/* ============================================ CTIMER AUX3 TMRB3POL23 [29..29] ============================================ */
typedef enum { /*!< CTIMER_AUX3_TMRB3POL23 */
CTIMER_AUX3_TMRB3POL23_NORM = 0, /*!< NORM : Upper output normal polarity */
CTIMER_AUX3_TMRB3POL23_INV = 1, /*!< INV : Upper output inverted polarity. */
} CTIMER_AUX3_TMRB3POL23_Enum;
/* ============================================ CTIMER AUX3 TMRB3TINV [28..28] ============================================= */
typedef enum { /*!< CTIMER_AUX3_TMRB3TINV */
CTIMER_AUX3_TMRB3TINV_DIS = 0, /*!< DIS : Disable invert on trigger */
CTIMER_AUX3_TMRB3TINV_EN = 1, /*!< EN : Enable invert on trigger */
} CTIMER_AUX3_TMRB3TINV_Enum;
/* =========================================== CTIMER AUX3 TMRB3NOSYNC [27..27] ============================================ */
typedef enum { /*!< CTIMER_AUX3_TMRB3NOSYNC */
CTIMER_AUX3_TMRB3NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */
CTIMER_AUX3_TMRB3NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */
} CTIMER_AUX3_TMRB3NOSYNC_Enum;
/* ============================================ CTIMER AUX3 TMRB3TRIG [23..26] ============================================= */
typedef enum { /*!< CTIMER_AUX3_TMRB3TRIG */
CTIMER_AUX3_TMRB3TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */
CTIMER_AUX3_TMRB3TRIG_A3OUT = 1, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */
CTIMER_AUX3_TMRB3TRIG_B2OUT = 2, /*!< B2OUT : Trigger source is CTIMERB2 OUT. */
CTIMER_AUX3_TMRB3TRIG_A2OUT = 3, /*!< A2OUT : Trigger source is CTIMERA2 OUT. */
CTIMER_AUX3_TMRB3TRIG_A4OUT = 4, /*!< A4OUT : Trigger source is CTIMERA4 OUT. */
CTIMER_AUX3_TMRB3TRIG_B4OUT = 5, /*!< B4OUT : Trigger source is CTIMERB4 OUT. */
CTIMER_AUX3_TMRB3TRIG_A6OUT = 6, /*!< A6OUT : Trigger source is CTIMERA6 OUT. */
CTIMER_AUX3_TMRB3TRIG_B6OUT = 7, /*!< B6OUT : Trigger source is CTIMERB6 OUT. */
CTIMER_AUX3_TMRB3TRIG_B5OUT2 = 8, /*!< B5OUT2 : Trigger source is CTIMERB5 OUT2. */
CTIMER_AUX3_TMRB3TRIG_A5OUT2 = 9, /*!< A5OUT2 : Trigger source is CTIMERA5 OUT2. */
CTIMER_AUX3_TMRB3TRIG_A1OUT2 = 10, /*!< A1OUT2 : Trigger source is CTIMERA1 OUT2. */
CTIMER_AUX3_TMRB3TRIG_B1OUT2 = 11, /*!< B1OUT2 : Trigger source is CTIMERB1 OUT2. */
CTIMER_AUX3_TMRB3TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */
CTIMER_AUX3_TMRB3TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */
CTIMER_AUX3_TMRB3TRIG_B2OUT2DUAL = 14, /*!< B2OUT2DUAL : Trigger source is CTIMERB2 OUT2, dual edge. */
CTIMER_AUX3_TMRB3TRIG_A2OUT2DUAL = 15, /*!< A2OUT2DUAL : Trigger source is CTIMERA2 OUT2, dual edge. */
} CTIMER_AUX3_TMRB3TRIG_Enum;
/* ============================================ CTIMER AUX3 TMRA3EN23 [14..14] ============================================= */
typedef enum { /*!< CTIMER_AUX3_TMRA3EN23 */
CTIMER_AUX3_TMRA3EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */
CTIMER_AUX3_TMRA3EN23_EN = 0, /*!< EN : Enable enhanced functions. */
} CTIMER_AUX3_TMRA3EN23_Enum;
/* ============================================ CTIMER AUX3 TMRA3POL23 [13..13] ============================================ */
typedef enum { /*!< CTIMER_AUX3_TMRA3POL23 */
CTIMER_AUX3_TMRA3POL23_NORM = 0, /*!< NORM : Upper output normal polarity */
CTIMER_AUX3_TMRA3POL23_INV = 1, /*!< INV : Upper output inverted polarity. */
} CTIMER_AUX3_TMRA3POL23_Enum;
/* ============================================ CTIMER AUX3 TMRA3TINV [12..12] ============================================= */
typedef enum { /*!< CTIMER_AUX3_TMRA3TINV */
CTIMER_AUX3_TMRA3TINV_DIS = 0, /*!< DIS : Disable invert on trigger */
CTIMER_AUX3_TMRA3TINV_EN = 1, /*!< EN : Enable invert on trigger */
} CTIMER_AUX3_TMRA3TINV_Enum;
/* =========================================== CTIMER AUX3 TMRA3NOSYNC [11..11] ============================================ */
typedef enum { /*!< CTIMER_AUX3_TMRA3NOSYNC */
CTIMER_AUX3_TMRA3NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */
CTIMER_AUX3_TMRA3NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */
} CTIMER_AUX3_TMRA3NOSYNC_Enum;
/* ============================================= CTIMER AUX3 TMRA3TRIG [7..10] ============================================= */
typedef enum { /*!< CTIMER_AUX3_TMRA3TRIG */
CTIMER_AUX3_TMRA3TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */
CTIMER_AUX3_TMRA3TRIG_B3OUT = 1, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */
CTIMER_AUX3_TMRA3TRIG_B2OUT = 2, /*!< B2OUT : Trigger source is CTIMERB2 OUT. */
CTIMER_AUX3_TMRA3TRIG_A2OUT = 3, /*!< A2OUT : Trigger source is CTIMERA2 OUT. */
CTIMER_AUX3_TMRA3TRIG_A4OUT = 4, /*!< A4OUT : Trigger source is CTIMERA4 OUT. */
CTIMER_AUX3_TMRA3TRIG_B4OUT = 5, /*!< B4OUT : Trigger source is CTIMERB4 OUT. */
CTIMER_AUX3_TMRA3TRIG_A7OUT = 6, /*!< A7OUT : Trigger source is CTIMERA7 OUT. */
CTIMER_AUX3_TMRA3TRIG_B7OUT = 7, /*!< B7OUT : Trigger source is CTIMERB7 OUT. */
CTIMER_AUX3_TMRA3TRIG_B5OUT2 = 8, /*!< B5OUT2 : Trigger source is CTIMERB5 OUT2. */
CTIMER_AUX3_TMRA3TRIG_A5OUT2 = 9, /*!< A5OUT2 : Trigger source is CTIMERA5 OUT2. */
CTIMER_AUX3_TMRA3TRIG_A1OUT2 = 10, /*!< A1OUT2 : Trigger source is CTIMERA1 OUT2. */
CTIMER_AUX3_TMRA3TRIG_B1OUT2 = 11, /*!< B1OUT2 : Trigger source is CTIMERB1 OUT2. */
CTIMER_AUX3_TMRA3TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */
CTIMER_AUX3_TMRA3TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */
CTIMER_AUX3_TMRA3TRIG_B2OUT2DUAL = 14, /*!< B2OUT2DUAL : Trigger source is CTIMERB2 OUT2, dual edge. */
CTIMER_AUX3_TMRA3TRIG_A2OUT2DUAL = 15, /*!< A2OUT2DUAL : Trigger source is CTIMERA2 OUT2, dual edge. */
} CTIMER_AUX3_TMRA3TRIG_Enum;
/* ========================================================= TMR4 ========================================================== */
/* ======================================================== CMPRA4 ========================================================= */
/* ======================================================== CMPRB4 ========================================================= */
/* ========================================================= CTRL4 ========================================================= */
/* ============================================= CTIMER CTRL4 CTLINK4 [31..31] ============================================= */
typedef enum { /*!< CTIMER_CTRL4_CTLINK4 */
CTIMER_CTRL4_CTLINK4_TWO_16BIT_TIMERS = 0, /*!< TWO_16BIT_TIMERS : Use A4/B4 timers as two independent 16-bit
timers (default). */
CTIMER_CTRL4_CTLINK4_32BIT_TIMER = 1, /*!< 32BIT_TIMER : Link A4/B4 timers into a single 32-bit timer. */
} CTIMER_CTRL4_CTLINK4_Enum;
/* ============================================ CTIMER CTRL4 TMRB4POL [28..28] ============================================= */
typedef enum { /*!< CTIMER_CTRL4_TMRB4POL */
CTIMER_CTRL4_TMRB4POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINB4 pin is the same as the
timer output. */
CTIMER_CTRL4_TMRB4POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINB4 pin is the inverse of
the timer output. */
} CTIMER_CTRL4_TMRB4POL_Enum;
/* ============================================ CTIMER CTRL4 TMRB4CLR [27..27] ============================================= */
typedef enum { /*!< CTIMER_CTRL4_TMRB4CLR */
CTIMER_CTRL4_TMRB4CLR_RUN = 0, /*!< RUN : Allow counter/timer B4 to run */
CTIMER_CTRL4_TMRB4CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer B4 at 0x0000. */
} CTIMER_CTRL4_TMRB4CLR_Enum;
/* ============================================ CTIMER CTRL4 TMRB4IE1 [26..26] ============================================= */
typedef enum { /*!< CTIMER_CTRL4_TMRB4IE1 */
CTIMER_CTRL4_TMRB4IE1_DIS = 0, /*!< DIS : Disable counter/timer B4 from generating an interrupt
based on COMPR1. */
CTIMER_CTRL4_TMRB4IE1_EN = 1, /*!< EN : Enable counter/timer B4 to generate an interrupt based
on COMPR1. */
} CTIMER_CTRL4_TMRB4IE1_Enum;
/* ============================================ CTIMER CTRL4 TMRB4IE0 [25..25] ============================================= */
typedef enum { /*!< CTIMER_CTRL4_TMRB4IE0 */
CTIMER_CTRL4_TMRB4IE0_DIS = 0, /*!< DIS : Disable counter/timer B4 from generating an interrupt
based on COMPR0. */
CTIMER_CTRL4_TMRB4IE0_EN = 1, /*!< EN : Enable counter/timer B4 to generate an interrupt based
on COMPR0 */
} CTIMER_CTRL4_TMRB4IE0_Enum;
/* ============================================= CTIMER CTRL4 TMRB4FN [22..24] ============================================= */
typedef enum { /*!< CTIMER_CTRL4_TMRB4FN */
CTIMER_CTRL4_TMRB4FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
to CMPR0B4, stop. */
CTIMER_CTRL4_TMRB4FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
pulses). Count to CMPR0B4, restart. */
CTIMER_CTRL4_TMRB4FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B4, assert,
count to CMPR1B4, deassert, stop. */
CTIMER_CTRL4_TMRB4FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0B4, assert, count
to CMPR1B4, deassert, restart. */
CTIMER_CTRL4_TMRB4FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */
CTIMER_CTRL4_TMRB4FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */
CTIMER_CTRL4_TMRB4FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */
CTIMER_CTRL4_TMRB4FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */
} CTIMER_CTRL4_TMRB4FN_Enum;
/* ============================================ CTIMER CTRL4 TMRB4CLK [17..21] ============================================= */
typedef enum { /*!< CTIMER_CTRL4_TMRB4CLK */
CTIMER_CTRL4_TMRB4CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINB. */
CTIMER_CTRL4_TMRB4CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */
CTIMER_CTRL4_TMRB4CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */
CTIMER_CTRL4_TMRB4CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */
CTIMER_CTRL4_TMRB4CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */
CTIMER_CTRL4_TMRB4CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */
CTIMER_CTRL4_TMRB4CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */
CTIMER_CTRL4_TMRB4CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */
CTIMER_CTRL4_TMRB4CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */
CTIMER_CTRL4_TMRB4CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */
CTIMER_CTRL4_TMRB4CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */
CTIMER_CTRL4_TMRB4CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */
CTIMER_CTRL4_TMRB4CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */
CTIMER_CTRL4_TMRB4CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */
CTIMER_CTRL4_TMRB4CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */
CTIMER_CTRL4_TMRB4CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
available when MCU is in active mode) */
CTIMER_CTRL4_TMRB4CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */
CTIMER_CTRL4_TMRB4CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */
CTIMER_CTRL4_TMRB4CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */
CTIMER_CTRL4_TMRB4CLK_CTMRA4 = 20, /*!< CTMRA4 : Clock source is CTIMERA4 OUT. */
CTIMER_CTRL4_TMRB4CLK_CTMRA1 = 21, /*!< CTMRA1 : Clock source is CTIMERA1 OUT. */
CTIMER_CTRL4_TMRB4CLK_CTMRB1 = 22, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */
CTIMER_CTRL4_TMRB4CLK_CTMRA5 = 23, /*!< CTMRA5 : Clock source is CTIMERA5 OUT. */
CTIMER_CTRL4_TMRB4CLK_CTMRB5 = 24, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */
CTIMER_CTRL4_TMRB4CLK_CTMRB0 = 25, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */
CTIMER_CTRL4_TMRB4CLK_CTMRB2 = 26, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */
CTIMER_CTRL4_TMRB4CLK_CTMRB3 = 27, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */
CTIMER_CTRL4_TMRB4CLK_CTMRB6 = 28, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */
CTIMER_CTRL4_TMRB4CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */
CTIMER_CTRL4_TMRB4CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */
CTIMER_CTRL4_TMRB4CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */
} CTIMER_CTRL4_TMRB4CLK_Enum;
/* ============================================= CTIMER CTRL4 TMRB4EN [16..16] ============================================= */
typedef enum { /*!< CTIMER_CTRL4_TMRB4EN */
CTIMER_CTRL4_TMRB4EN_DIS = 0, /*!< DIS : Counter/Timer B4 Disable. */
CTIMER_CTRL4_TMRB4EN_EN = 1, /*!< EN : Counter/Timer B4 Enable. */
} CTIMER_CTRL4_TMRB4EN_Enum;
/* ============================================ CTIMER CTRL4 TMRA4POL [12..12] ============================================= */
typedef enum { /*!< CTIMER_CTRL4_TMRA4POL */
CTIMER_CTRL4_TMRA4POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINA4 pin is the same as the
timer output. */
CTIMER_CTRL4_TMRA4POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINA4 pin is the inverse of
the timer output. */
} CTIMER_CTRL4_TMRA4POL_Enum;
/* ============================================ CTIMER CTRL4 TMRA4CLR [11..11] ============================================= */
typedef enum { /*!< CTIMER_CTRL4_TMRA4CLR */
CTIMER_CTRL4_TMRA4CLR_RUN = 0, /*!< RUN : Allow counter/timer A4 to run */
CTIMER_CTRL4_TMRA4CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer A4 at 0x0000. */
} CTIMER_CTRL4_TMRA4CLR_Enum;
/* ============================================ CTIMER CTRL4 TMRA4IE1 [10..10] ============================================= */
typedef enum { /*!< CTIMER_CTRL4_TMRA4IE1 */
CTIMER_CTRL4_TMRA4IE1_DIS = 0, /*!< DIS : Disable counter/timer A4 from generating an interrupt
based on COMPR1. */
CTIMER_CTRL4_TMRA4IE1_EN = 1, /*!< EN : Enable counter/timer A4 to generate an interrupt based
on COMPR1. */
} CTIMER_CTRL4_TMRA4IE1_Enum;
/* ============================================= CTIMER CTRL4 TMRA4IE0 [9..9] ============================================== */
typedef enum { /*!< CTIMER_CTRL4_TMRA4IE0 */
CTIMER_CTRL4_TMRA4IE0_DIS = 0, /*!< DIS : Disable counter/timer A4 from generating an interrupt
based on COMPR0. */
CTIMER_CTRL4_TMRA4IE0_EN = 1, /*!< EN : Enable counter/timer A4 to generate an interrupt based
on COMPR0. */
} CTIMER_CTRL4_TMRA4IE0_Enum;
/* ============================================== CTIMER CTRL4 TMRA4FN [6..8] ============================================== */
typedef enum { /*!< CTIMER_CTRL4_TMRA4FN */
CTIMER_CTRL4_TMRA4FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
to CMPR0A4, stop. */
CTIMER_CTRL4_TMRA4FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
pulses). Count to CMPR0A4, restart. */
CTIMER_CTRL4_TMRA4FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A4, assert,
count to CMPR1A4, deassert, stop. */
CTIMER_CTRL4_TMRA4FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0A4, assert, count
to CMPR1A4, deassert, restart. */
CTIMER_CTRL4_TMRA4FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */
CTIMER_CTRL4_TMRA4FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */
CTIMER_CTRL4_TMRA4FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */
CTIMER_CTRL4_TMRA4FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */
} CTIMER_CTRL4_TMRA4FN_Enum;
/* ============================================= CTIMER CTRL4 TMRA4CLK [1..5] ============================================== */
typedef enum { /*!< CTIMER_CTRL4_TMRA4CLK */
CTIMER_CTRL4_TMRA4CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINA. */
CTIMER_CTRL4_TMRA4CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */
CTIMER_CTRL4_TMRA4CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */
CTIMER_CTRL4_TMRA4CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */
CTIMER_CTRL4_TMRA4CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */
CTIMER_CTRL4_TMRA4CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */
CTIMER_CTRL4_TMRA4CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */
CTIMER_CTRL4_TMRA4CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */
CTIMER_CTRL4_TMRA4CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */
CTIMER_CTRL4_TMRA4CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */
CTIMER_CTRL4_TMRA4CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */
CTIMER_CTRL4_TMRA4CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */
CTIMER_CTRL4_TMRA4CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */
CTIMER_CTRL4_TMRA4CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */
CTIMER_CTRL4_TMRA4CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */
CTIMER_CTRL4_TMRA4CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4. (note: this clock is only
available when MCU is in active mode) */
CTIMER_CTRL4_TMRA4CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */
CTIMER_CTRL4_TMRA4CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */
CTIMER_CTRL4_TMRA4CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */
CTIMER_CTRL4_TMRA4CLK_CTMRB4 = 20, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */
CTIMER_CTRL4_TMRA4CLK_CTMRA1 = 21, /*!< CTMRA1 : Clock source is CTIMERA1 OUT. */
CTIMER_CTRL4_TMRA4CLK_CTMRB1 = 22, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */
CTIMER_CTRL4_TMRA4CLK_CTMRA5 = 23, /*!< CTMRA5 : Clock source is CTIMERA5 OUT. */
CTIMER_CTRL4_TMRA4CLK_CTMRB5 = 24, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */
CTIMER_CTRL4_TMRA4CLK_CTMRB0 = 25, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */
CTIMER_CTRL4_TMRA4CLK_CTMRB2 = 26, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */
CTIMER_CTRL4_TMRA4CLK_CTMRB3 = 27, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */
CTIMER_CTRL4_TMRA4CLK_CTMRB6 = 28, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */
CTIMER_CTRL4_TMRA4CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */
CTIMER_CTRL4_TMRA4CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */
CTIMER_CTRL4_TMRA4CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */
} CTIMER_CTRL4_TMRA4CLK_Enum;
/* ============================================== CTIMER CTRL4 TMRA4EN [0..0] ============================================== */
typedef enum { /*!< CTIMER_CTRL4_TMRA4EN */
CTIMER_CTRL4_TMRA4EN_DIS = 0, /*!< DIS : Counter/Timer A4 Disable. */
CTIMER_CTRL4_TMRA4EN_EN = 1, /*!< EN : Counter/Timer A4 Enable. */
} CTIMER_CTRL4_TMRA4EN_Enum;
/* ======================================================= CMPRAUXA4 ======================================================= */
/* ======================================================= CMPRAUXB4 ======================================================= */
/* ========================================================= AUX4 ========================================================== */
/* ============================================ CTIMER AUX4 TMRB4EN23 [30..30] ============================================= */
typedef enum { /*!< CTIMER_AUX4_TMRB4EN23 */
CTIMER_AUX4_TMRB4EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */
CTIMER_AUX4_TMRB4EN23_EN = 0, /*!< EN : Enable enhanced functions. */
} CTIMER_AUX4_TMRB4EN23_Enum;
/* ============================================ CTIMER AUX4 TMRB4POL23 [29..29] ============================================ */
typedef enum { /*!< CTIMER_AUX4_TMRB4POL23 */
CTIMER_AUX4_TMRB4POL23_NORM = 0, /*!< NORM : Upper output normal polarity */
CTIMER_AUX4_TMRB4POL23_INV = 1, /*!< INV : Upper output inverted polarity. */
} CTIMER_AUX4_TMRB4POL23_Enum;
/* ============================================ CTIMER AUX4 TMRB4TINV [28..28] ============================================= */
typedef enum { /*!< CTIMER_AUX4_TMRB4TINV */
CTIMER_AUX4_TMRB4TINV_DIS = 0, /*!< DIS : Disable invert on trigger */
CTIMER_AUX4_TMRB4TINV_EN = 1, /*!< EN : Enable invert on trigger */
} CTIMER_AUX4_TMRB4TINV_Enum;
/* =========================================== CTIMER AUX4 TMRB4NOSYNC [27..27] ============================================ */
typedef enum { /*!< CTIMER_AUX4_TMRB4NOSYNC */
CTIMER_AUX4_TMRB4NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */
CTIMER_AUX4_TMRB4NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */
} CTIMER_AUX4_TMRB4NOSYNC_Enum;
/* ============================================ CTIMER AUX4 TMRB4TRIG [23..26] ============================================= */
typedef enum { /*!< CTIMER_AUX4_TMRB4TRIG */
CTIMER_AUX4_TMRB4TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */
CTIMER_AUX4_TMRB4TRIG_A4OUT = 1, /*!< A4OUT : Trigger source is CTIMERA4 OUT. */
CTIMER_AUX4_TMRB4TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */
CTIMER_AUX4_TMRB4TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */
CTIMER_AUX4_TMRB4TRIG_A7OUT = 4, /*!< A7OUT : Trigger source is CTIMERA7 OUT. */
CTIMER_AUX4_TMRB4TRIG_B7OUT = 5, /*!< B7OUT : Trigger source is CTIMERB7 OUT. */
CTIMER_AUX4_TMRB4TRIG_A1OUT = 6, /*!< A1OUT : Trigger source is CTIMERA1 OUT. */
CTIMER_AUX4_TMRB4TRIG_B1OUT = 7, /*!< B1OUT : Trigger source is CTIMERB1 OUT. */
CTIMER_AUX4_TMRB4TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */
CTIMER_AUX4_TMRB4TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */
CTIMER_AUX4_TMRB4TRIG_A1OUT2 = 10, /*!< A1OUT2 : Trigger source is CTIMERA1 OUT2. */
CTIMER_AUX4_TMRB4TRIG_B1OUT2 = 11, /*!< B1OUT2 : Trigger source is CTIMERB1 OUT2. */
CTIMER_AUX4_TMRB4TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */
CTIMER_AUX4_TMRB4TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */
CTIMER_AUX4_TMRB4TRIG_B5OUT2DUAL = 14, /*!< B5OUT2DUAL : Trigger source is CTIMERB5 OUT2, dual edge. */
CTIMER_AUX4_TMRB4TRIG_A5OUT2DUAL = 15, /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge. */
} CTIMER_AUX4_TMRB4TRIG_Enum;
/* ============================================ CTIMER AUX4 TMRA4EN23 [14..14] ============================================= */
typedef enum { /*!< CTIMER_AUX4_TMRA4EN23 */
CTIMER_AUX4_TMRA4EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */
CTIMER_AUX4_TMRA4EN23_EN = 0, /*!< EN : Enable enhanced functions. */
} CTIMER_AUX4_TMRA4EN23_Enum;
/* ============================================ CTIMER AUX4 TMRA4POL23 [13..13] ============================================ */
typedef enum { /*!< CTIMER_AUX4_TMRA4POL23 */
CTIMER_AUX4_TMRA4POL23_NORM = 0, /*!< NORM : Upper output normal polarity */
CTIMER_AUX4_TMRA4POL23_INV = 1, /*!< INV : Upper output inverted polarity. */
} CTIMER_AUX4_TMRA4POL23_Enum;
/* ============================================ CTIMER AUX4 TMRA4TINV [12..12] ============================================= */
typedef enum { /*!< CTIMER_AUX4_TMRA4TINV */
CTIMER_AUX4_TMRA4TINV_DIS = 0, /*!< DIS : Disable invert on trigger */
CTIMER_AUX4_TMRA4TINV_EN = 1, /*!< EN : Enable invert on trigger */
} CTIMER_AUX4_TMRA4TINV_Enum;
/* =========================================== CTIMER AUX4 TMRA4NOSYNC [11..11] ============================================ */
typedef enum { /*!< CTIMER_AUX4_TMRA4NOSYNC */
CTIMER_AUX4_TMRA4NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */
CTIMER_AUX4_TMRA4NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */
} CTIMER_AUX4_TMRA4NOSYNC_Enum;
/* ============================================= CTIMER AUX4 TMRA4TRIG [7..10] ============================================= */
typedef enum { /*!< CTIMER_AUX4_TMRA4TRIG */
CTIMER_AUX4_TMRA4TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */
CTIMER_AUX4_TMRA4TRIG_STIMER = 1, /*!< STIMER : Trigger source is STimer Interrupt. Only Active When
CTLINK==1 and TMRB4TRIG!=0. TMRB4TRIG selects an STIMER
interrupt */
CTIMER_AUX4_TMRA4TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */
CTIMER_AUX4_TMRA4TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */
CTIMER_AUX4_TMRA4TRIG_A6OUT = 4, /*!< A6OUT : Trigger source is CTIMERA6 OUT. */
CTIMER_AUX4_TMRA4TRIG_B6OUT = 5, /*!< B6OUT : Trigger source is CTIMERB6 OUT. */
CTIMER_AUX4_TMRA4TRIG_A2OUT = 6, /*!< A2OUT : Trigger source is CTIMERA2 OUT. */
CTIMER_AUX4_TMRA4TRIG_B2OUT = 7, /*!< B2OUT : Trigger source is CTIMERB2 OUT. */
CTIMER_AUX4_TMRA4TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */
CTIMER_AUX4_TMRA4TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */
CTIMER_AUX4_TMRA4TRIG_A1OUT2 = 10, /*!< A1OUT2 : Trigger source is CTIMERA1 OUT2. */
CTIMER_AUX4_TMRA4TRIG_B1OUT2 = 11, /*!< B1OUT2 : Trigger source is CTIMERB1 OUT2. */
CTIMER_AUX4_TMRA4TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */
CTIMER_AUX4_TMRA4TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */
CTIMER_AUX4_TMRA4TRIG_B5OUT2DUAL = 14, /*!< B5OUT2DUAL : Trigger source is CTIMERB5 OUT2, dual edge. */
CTIMER_AUX4_TMRA4TRIG_A5OUT2DUAL = 15, /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge. */
} CTIMER_AUX4_TMRA4TRIG_Enum;
/* ========================================================= TMR5 ========================================================== */
/* ======================================================== CMPRA5 ========================================================= */
/* ======================================================== CMPRB5 ========================================================= */
/* ========================================================= CTRL5 ========================================================= */
/* ============================================= CTIMER CTRL5 CTLINK5 [31..31] ============================================= */
typedef enum { /*!< CTIMER_CTRL5_CTLINK5 */
CTIMER_CTRL5_CTLINK5_TWO_16BIT_TIMERS = 0, /*!< TWO_16BIT_TIMERS : Use A5/B5 timers as two independent 16-bit
timers (default). */
CTIMER_CTRL5_CTLINK5_32BIT_TIMER = 1, /*!< 32BIT_TIMER : Link A5/B5 timers into a single 32-bit timer. */
} CTIMER_CTRL5_CTLINK5_Enum;
/* ============================================ CTIMER CTRL5 TMRB5POL [28..28] ============================================= */
typedef enum { /*!< CTIMER_CTRL5_TMRB5POL */
CTIMER_CTRL5_TMRB5POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINB5 pin is the same as the
timer output. */
CTIMER_CTRL5_TMRB5POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINB5 pin is the inverse of
the timer output. */
} CTIMER_CTRL5_TMRB5POL_Enum;
/* ============================================ CTIMER CTRL5 TMRB5CLR [27..27] ============================================= */
typedef enum { /*!< CTIMER_CTRL5_TMRB5CLR */
CTIMER_CTRL5_TMRB5CLR_RUN = 0, /*!< RUN : Allow counter/timer B5 to run */
CTIMER_CTRL5_TMRB5CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer B5 at 0x0000. */
} CTIMER_CTRL5_TMRB5CLR_Enum;
/* ============================================ CTIMER CTRL5 TMRB5IE1 [26..26] ============================================= */
typedef enum { /*!< CTIMER_CTRL5_TMRB5IE1 */
CTIMER_CTRL5_TMRB5IE1_DIS = 0, /*!< DIS : Disable counter/timer B5 from generating an interrupt
based on COMPR1. */
CTIMER_CTRL5_TMRB5IE1_EN = 1, /*!< EN : Enable counter/timer B5 to generate an interrupt based
on COMPR1. */
} CTIMER_CTRL5_TMRB5IE1_Enum;
/* ============================================ CTIMER CTRL5 TMRB5IE0 [25..25] ============================================= */
typedef enum { /*!< CTIMER_CTRL5_TMRB5IE0 */
CTIMER_CTRL5_TMRB5IE0_DIS = 0, /*!< DIS : Disable counter/timer B5 from generating an interrupt
based on COMPR0. */
CTIMER_CTRL5_TMRB5IE0_EN = 1, /*!< EN : Enable counter/timer B5 to generate an interrupt based
on COMPR0 */
} CTIMER_CTRL5_TMRB5IE0_Enum;
/* ============================================= CTIMER CTRL5 TMRB5FN [22..24] ============================================= */
typedef enum { /*!< CTIMER_CTRL5_TMRB5FN */
CTIMER_CTRL5_TMRB5FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
to CMPR0B5, stop. */
CTIMER_CTRL5_TMRB5FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
pulses). Count to CMPR0B5, restart. */
CTIMER_CTRL5_TMRB5FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B5, assert,
count to CMPR1B5, deassert, stop. */
CTIMER_CTRL5_TMRB5FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0B5, assert, count
to CMPR1B5, deassert, restart. */
CTIMER_CTRL5_TMRB5FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */
CTIMER_CTRL5_TMRB5FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */
CTIMER_CTRL5_TMRB5FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */
CTIMER_CTRL5_TMRB5FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */
} CTIMER_CTRL5_TMRB5FN_Enum;
/* ============================================ CTIMER CTRL5 TMRB5CLK [17..21] ============================================= */
typedef enum { /*!< CTIMER_CTRL5_TMRB5CLK */
CTIMER_CTRL5_TMRB5CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINB. */
CTIMER_CTRL5_TMRB5CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */
CTIMER_CTRL5_TMRB5CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */
CTIMER_CTRL5_TMRB5CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */
CTIMER_CTRL5_TMRB5CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */
CTIMER_CTRL5_TMRB5CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */
CTIMER_CTRL5_TMRB5CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */
CTIMER_CTRL5_TMRB5CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */
CTIMER_CTRL5_TMRB5CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */
CTIMER_CTRL5_TMRB5CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */
CTIMER_CTRL5_TMRB5CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */
CTIMER_CTRL5_TMRB5CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */
CTIMER_CTRL5_TMRB5CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */
CTIMER_CTRL5_TMRB5CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */
CTIMER_CTRL5_TMRB5CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */
CTIMER_CTRL5_TMRB5CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
available when MCU is in active mode) */
CTIMER_CTRL5_TMRB5CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */
CTIMER_CTRL5_TMRB5CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */
CTIMER_CTRL5_TMRB5CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */
CTIMER_CTRL5_TMRB5CLK_CTMRA5 = 20, /*!< CTMRA5 : Clock source is CTIMERA5 OUT. */
CTIMER_CTRL5_TMRB5CLK_CTMRA0 = 21, /*!< CTMRA0 : Clock source is CTIMERA0 OUT. */
CTIMER_CTRL5_TMRB5CLK_CTMRB0 = 22, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */
CTIMER_CTRL5_TMRB5CLK_CTMRA6 = 23, /*!< CTMRA6 : Clock source is CTIMERA6 OUT. */
CTIMER_CTRL5_TMRB5CLK_CTMRB6 = 24, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */
CTIMER_CTRL5_TMRB5CLK_CTMRB1 = 25, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */
CTIMER_CTRL5_TMRB5CLK_CTMRB2 = 26, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */
CTIMER_CTRL5_TMRB5CLK_CTMRB3 = 27, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */
CTIMER_CTRL5_TMRB5CLK_CTMRB4 = 28, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */
CTIMER_CTRL5_TMRB5CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */
CTIMER_CTRL5_TMRB5CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */
CTIMER_CTRL5_TMRB5CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */
} CTIMER_CTRL5_TMRB5CLK_Enum;
/* ============================================= CTIMER CTRL5 TMRB5EN [16..16] ============================================= */
typedef enum { /*!< CTIMER_CTRL5_TMRB5EN */
CTIMER_CTRL5_TMRB5EN_DIS = 0, /*!< DIS : Counter/Timer B5 Disable. */
CTIMER_CTRL5_TMRB5EN_EN = 1, /*!< EN : Counter/Timer B5 Enable. */
} CTIMER_CTRL5_TMRB5EN_Enum;
/* ============================================ CTIMER CTRL5 TMRA5POL [12..12] ============================================= */
typedef enum { /*!< CTIMER_CTRL5_TMRA5POL */
CTIMER_CTRL5_TMRA5POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINA5 pin is the same as the
timer output. */
CTIMER_CTRL5_TMRA5POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINA5 pin is the inverse of
the timer output. */
} CTIMER_CTRL5_TMRA5POL_Enum;
/* ============================================ CTIMER CTRL5 TMRA5CLR [11..11] ============================================= */
typedef enum { /*!< CTIMER_CTRL5_TMRA5CLR */
CTIMER_CTRL5_TMRA5CLR_RUN = 0, /*!< RUN : Allow counter/timer A5 to run */
CTIMER_CTRL5_TMRA5CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer A5 at 0x0000. */
} CTIMER_CTRL5_TMRA5CLR_Enum;
/* ============================================ CTIMER CTRL5 TMRA5IE1 [10..10] ============================================= */
typedef enum { /*!< CTIMER_CTRL5_TMRA5IE1 */
CTIMER_CTRL5_TMRA5IE1_DIS = 0, /*!< DIS : Disable counter/timer A5 from generating an interrupt
based on COMPR1. */
CTIMER_CTRL5_TMRA5IE1_EN = 1, /*!< EN : Enable counter/timer A5 to generate an interrupt based
on COMPR1. */
} CTIMER_CTRL5_TMRA5IE1_Enum;
/* ============================================= CTIMER CTRL5 TMRA5IE0 [9..9] ============================================== */
typedef enum { /*!< CTIMER_CTRL5_TMRA5IE0 */
CTIMER_CTRL5_TMRA5IE0_DIS = 0, /*!< DIS : Disable counter/timer A5 from generating an interrupt
based on COMPR0. */
CTIMER_CTRL5_TMRA5IE0_EN = 1, /*!< EN : Enable counter/timer A5 to generate an interrupt based
on COMPR0. */
} CTIMER_CTRL5_TMRA5IE0_Enum;
/* ============================================== CTIMER CTRL5 TMRA5FN [6..8] ============================================== */
typedef enum { /*!< CTIMER_CTRL5_TMRA5FN */
CTIMER_CTRL5_TMRA5FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
to CMPR0A5, stop. */
CTIMER_CTRL5_TMRA5FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
pulses). Count to CMPR0A5, restart. */
CTIMER_CTRL5_TMRA5FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A5, assert,
count to CMPR1A5, deassert, stop. */
CTIMER_CTRL5_TMRA5FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0A5, assert, count
to CMPR1A5, deassert, restart. */
CTIMER_CTRL5_TMRA5FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */
CTIMER_CTRL5_TMRA5FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */
CTIMER_CTRL5_TMRA5FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */
CTIMER_CTRL5_TMRA5FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */
} CTIMER_CTRL5_TMRA5FN_Enum;
/* ============================================= CTIMER CTRL5 TMRA5CLK [1..5] ============================================== */
typedef enum { /*!< CTIMER_CTRL5_TMRA5CLK */
CTIMER_CTRL5_TMRA5CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINA. */
CTIMER_CTRL5_TMRA5CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */
CTIMER_CTRL5_TMRA5CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */
CTIMER_CTRL5_TMRA5CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */
CTIMER_CTRL5_TMRA5CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */
CTIMER_CTRL5_TMRA5CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */
CTIMER_CTRL5_TMRA5CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */
CTIMER_CTRL5_TMRA5CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */
CTIMER_CTRL5_TMRA5CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */
CTIMER_CTRL5_TMRA5CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */
CTIMER_CTRL5_TMRA5CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */
CTIMER_CTRL5_TMRA5CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */
CTIMER_CTRL5_TMRA5CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */
CTIMER_CTRL5_TMRA5CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */
CTIMER_CTRL5_TMRA5CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */
CTIMER_CTRL5_TMRA5CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
available when MCU is in active mode) */
CTIMER_CTRL5_TMRA5CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */
CTIMER_CTRL5_TMRA5CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */
CTIMER_CTRL5_TMRA5CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */
CTIMER_CTRL5_TMRA5CLK_CTMRB5 = 20, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */
CTIMER_CTRL5_TMRA5CLK_CTMRA0 = 21, /*!< CTMRA0 : Clock source is CTIMERA0 OUT. */
CTIMER_CTRL5_TMRA5CLK_CTMRB0 = 22, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */
CTIMER_CTRL5_TMRA5CLK_CTMRA6 = 23, /*!< CTMRA6 : Clock source is CTIMERA6 OUT. */
CTIMER_CTRL5_TMRA5CLK_CTMRB6 = 24, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */
CTIMER_CTRL5_TMRA5CLK_CTMRB1 = 25, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */
CTIMER_CTRL5_TMRA5CLK_CTMRB2 = 26, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */
CTIMER_CTRL5_TMRA5CLK_CTMRB3 = 27, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */
CTIMER_CTRL5_TMRA5CLK_CTMRB4 = 28, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */
CTIMER_CTRL5_TMRA5CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */
CTIMER_CTRL5_TMRA5CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */
CTIMER_CTRL5_TMRA5CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */
} CTIMER_CTRL5_TMRA5CLK_Enum;
/* ============================================== CTIMER CTRL5 TMRA5EN [0..0] ============================================== */
typedef enum { /*!< CTIMER_CTRL5_TMRA5EN */
CTIMER_CTRL5_TMRA5EN_DIS = 0, /*!< DIS : Counter/Timer A5 Disable. */
CTIMER_CTRL5_TMRA5EN_EN = 1, /*!< EN : Counter/Timer A5 Enable. */
} CTIMER_CTRL5_TMRA5EN_Enum;
/* ======================================================= CMPRAUXA5 ======================================================= */
/* ======================================================= CMPRAUXB5 ======================================================= */
/* ========================================================= AUX5 ========================================================== */
/* ============================================ CTIMER AUX5 TMRB5EN23 [30..30] ============================================= */
typedef enum { /*!< CTIMER_AUX5_TMRB5EN23 */
CTIMER_AUX5_TMRB5EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */
CTIMER_AUX5_TMRB5EN23_EN = 0, /*!< EN : Enable enhanced functions. */
} CTIMER_AUX5_TMRB5EN23_Enum;
/* ============================================ CTIMER AUX5 TMRB5POL23 [29..29] ============================================ */
typedef enum { /*!< CTIMER_AUX5_TMRB5POL23 */
CTIMER_AUX5_TMRB5POL23_NORM = 0, /*!< NORM : Upper output normal polarity */
CTIMER_AUX5_TMRB5POL23_INV = 1, /*!< INV : Upper output inverted polarity. */
} CTIMER_AUX5_TMRB5POL23_Enum;
/* ============================================ CTIMER AUX5 TMRB5TINV [28..28] ============================================= */
typedef enum { /*!< CTIMER_AUX5_TMRB5TINV */
CTIMER_AUX5_TMRB5TINV_DIS = 0, /*!< DIS : Disable invert on trigger */
CTIMER_AUX5_TMRB5TINV_EN = 1, /*!< EN : Enable invert on trigger */
} CTIMER_AUX5_TMRB5TINV_Enum;
/* =========================================== CTIMER AUX5 TMRB5NOSYNC [27..27] ============================================ */
typedef enum { /*!< CTIMER_AUX5_TMRB5NOSYNC */
CTIMER_AUX5_TMRB5NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */
CTIMER_AUX5_TMRB5NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */
} CTIMER_AUX5_TMRB5NOSYNC_Enum;
/* ============================================ CTIMER AUX5 TMRB5TRIG [23..26] ============================================= */
typedef enum { /*!< CTIMER_AUX5_TMRB5TRIG */
CTIMER_AUX5_TMRB5TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */
CTIMER_AUX5_TMRB5TRIG_A5OUT = 1, /*!< A5OUT : Trigger source is CTIMERA5 OUT. */
CTIMER_AUX5_TMRB5TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */
CTIMER_AUX5_TMRB5TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */
CTIMER_AUX5_TMRB5TRIG_A6OUT = 4, /*!< A6OUT : Trigger source is CTIMERA6 OUT. */
CTIMER_AUX5_TMRB5TRIG_B6OUT = 5, /*!< B6OUT : Trigger source is CTIMERB6 OUT. */
CTIMER_AUX5_TMRB5TRIG_A1OUT = 6, /*!< A1OUT : Trigger source is CTIMERA1 OUT. */
CTIMER_AUX5_TMRB5TRIG_B1OUT = 7, /*!< B1OUT : Trigger source is CTIMERB1 OUT. */
CTIMER_AUX5_TMRB5TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */
CTIMER_AUX5_TMRB5TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */
CTIMER_AUX5_TMRB5TRIG_A0OUT2 = 10, /*!< A0OUT2 : Trigger source is CTIMERA0 OUT2. */
CTIMER_AUX5_TMRB5TRIG_B0OUT2 = 11, /*!< B0OUT2 : Trigger source is CTIMERB0 OUT2. */
CTIMER_AUX5_TMRB5TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */
CTIMER_AUX5_TMRB5TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */
CTIMER_AUX5_TMRB5TRIG_B4OUT2DUAL = 14, /*!< B4OUT2DUAL : Trigger source is CTIMERB4 OUT2, dual edge. */
CTIMER_AUX5_TMRB5TRIG_A4OUT2DUAL = 15, /*!< A4OUT2DUAL : Trigger source is CTIMERA4 OUT2, dual edge. */
} CTIMER_AUX5_TMRB5TRIG_Enum;
/* ============================================ CTIMER AUX5 TMRA5EN23 [14..14] ============================================= */
typedef enum { /*!< CTIMER_AUX5_TMRA5EN23 */
CTIMER_AUX5_TMRA5EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */
CTIMER_AUX5_TMRA5EN23_EN = 0, /*!< EN : Enable enhanced functions. */
} CTIMER_AUX5_TMRA5EN23_Enum;
/* ============================================ CTIMER AUX5 TMRA5POL23 [13..13] ============================================ */
typedef enum { /*!< CTIMER_AUX5_TMRA5POL23 */
CTIMER_AUX5_TMRA5POL23_NORMAL = 0, /*!< NORMAL : Upper output normal polarity */
CTIMER_AUX5_TMRA5POL23_INV = 1, /*!< INV : Upper output inverted polarity. */
} CTIMER_AUX5_TMRA5POL23_Enum;
/* ============================================ CTIMER AUX5 TMRA5TINV [12..12] ============================================= */
typedef enum { /*!< CTIMER_AUX5_TMRA5TINV */
CTIMER_AUX5_TMRA5TINV_DIS = 0, /*!< DIS : Disable invert on trigger */
CTIMER_AUX5_TMRA5TINV_EN = 1, /*!< EN : Enable invert on trigger */
} CTIMER_AUX5_TMRA5TINV_Enum;
/* =========================================== CTIMER AUX5 TMRA5NOSYNC [11..11] ============================================ */
typedef enum { /*!< CTIMER_AUX5_TMRA5NOSYNC */
CTIMER_AUX5_TMRA5NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */
CTIMER_AUX5_TMRA5NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */
} CTIMER_AUX5_TMRA5NOSYNC_Enum;
/* ============================================= CTIMER AUX5 TMRA5TRIG [7..10] ============================================= */
typedef enum { /*!< CTIMER_AUX5_TMRA5TRIG */
CTIMER_AUX5_TMRA5TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */
CTIMER_AUX5_TMRA5TRIG_STIMER = 1, /*!< STIMER : Trigger source is STimer Interrupt. Only Active When
CTLINK==1 and TMRB5TRIG!=0. TMRB5TRIG selects an STIMER
interrupt */
CTIMER_AUX5_TMRA5TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */
CTIMER_AUX5_TMRA5TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */
CTIMER_AUX5_TMRA5TRIG_A4OUT = 4, /*!< A4OUT : Trigger source is CTIMERA4 OUT. */
CTIMER_AUX5_TMRA5TRIG_B4OUT = 5, /*!< B4OUT : Trigger source is CTIMERB4 OUT. */
CTIMER_AUX5_TMRA5TRIG_A2OUT = 6, /*!< A2OUT : Trigger source is CTIMERA2 OUT. */
CTIMER_AUX5_TMRA5TRIG_B2OUT = 7, /*!< B2OUT : Trigger source is CTIMERB2 OUT. */
CTIMER_AUX5_TMRA5TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */
CTIMER_AUX5_TMRA5TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */
CTIMER_AUX5_TMRA5TRIG_A0OUT2 = 10, /*!< A0OUT2 : Trigger source is CTIMERA0 OUT2. */
CTIMER_AUX5_TMRA5TRIG_B0OUT2 = 11, /*!< B0OUT2 : Trigger source is CTIMERB0 OUT2. */
CTIMER_AUX5_TMRA5TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */
CTIMER_AUX5_TMRA5TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */
CTIMER_AUX5_TMRA5TRIG_B4OUT2DUAL = 14, /*!< B4OUT2DUAL : Trigger source is CTIMERB4 OUT2, dual edge. */
CTIMER_AUX5_TMRA5TRIG_A4OUT2DUAL = 15, /*!< A4OUT2DUAL : Trigger source is CTIMERA4 OUT2, dual edge. */
} CTIMER_AUX5_TMRA5TRIG_Enum;
/* ========================================================= TMR6 ========================================================== */
/* ======================================================== CMPRA6 ========================================================= */
/* ======================================================== CMPRB6 ========================================================= */
/* ========================================================= CTRL6 ========================================================= */
/* ============================================= CTIMER CTRL6 CTLINK6 [31..31] ============================================= */
typedef enum { /*!< CTIMER_CTRL6_CTLINK6 */
CTIMER_CTRL6_CTLINK6_TWO_16BIT_TIMERS = 0, /*!< TWO_16BIT_TIMERS : Use A6/B6 timers as two independent 16-bit
timers (default). */
CTIMER_CTRL6_CTLINK6_32BIT_TIMER = 1, /*!< 32BIT_TIMER : Link A6/B6 timers into a single 32-bit timer. */
} CTIMER_CTRL6_CTLINK6_Enum;
/* ============================================ CTIMER CTRL6 TMRB6POL [28..28] ============================================= */
typedef enum { /*!< CTIMER_CTRL6_TMRB6POL */
CTIMER_CTRL6_TMRB6POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINB6 pin is the same as the
timer output. */
CTIMER_CTRL6_TMRB6POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINB6 pin is the inverse of
the timer output. */
} CTIMER_CTRL6_TMRB6POL_Enum;
/* ============================================ CTIMER CTRL6 TMRB6CLR [27..27] ============================================= */
typedef enum { /*!< CTIMER_CTRL6_TMRB6CLR */
CTIMER_CTRL6_TMRB6CLR_RUN = 0, /*!< RUN : Allow counter/timer B6 to run */
CTIMER_CTRL6_TMRB6CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer B6 at 0x0000. */
} CTIMER_CTRL6_TMRB6CLR_Enum;
/* ============================================ CTIMER CTRL6 TMRB6IE1 [26..26] ============================================= */
typedef enum { /*!< CTIMER_CTRL6_TMRB6IE1 */
CTIMER_CTRL6_TMRB6IE1_DIS = 0, /*!< DIS : Disable counter/timer B6 from generating an interrupt
based on COMPR1. */
CTIMER_CTRL6_TMRB6IE1_EN = 1, /*!< EN : Enable counter/timer B6 to generate an interrupt based
on COMPR1. */
} CTIMER_CTRL6_TMRB6IE1_Enum;
/* ============================================ CTIMER CTRL6 TMRB6IE0 [25..25] ============================================= */
typedef enum { /*!< CTIMER_CTRL6_TMRB6IE0 */
CTIMER_CTRL6_TMRB6IE0_DIS = 0, /*!< DIS : Disable counter/timer B6 from generating an interrupt
based on COMPR0. */
CTIMER_CTRL6_TMRB6IE0_EN = 1, /*!< EN : Enable counter/timer B6 to generate an interrupt based
on COMPR0 */
} CTIMER_CTRL6_TMRB6IE0_Enum;
/* ============================================= CTIMER CTRL6 TMRB6FN [22..24] ============================================= */
typedef enum { /*!< CTIMER_CTRL6_TMRB6FN */
CTIMER_CTRL6_TMRB6FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
to CMPR0B6, stop. */
CTIMER_CTRL6_TMRB6FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
pulses). Count to CMPR0B6, restart. */
CTIMER_CTRL6_TMRB6FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B6, assert,
count to CMPR1B6, deassert, stop. */
CTIMER_CTRL6_TMRB6FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0B6, assert, count
to CMPR1B6, deassert, restart. */
CTIMER_CTRL6_TMRB6FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */
CTIMER_CTRL6_TMRB6FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */
CTIMER_CTRL6_TMRB6FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */
CTIMER_CTRL6_TMRB6FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */
} CTIMER_CTRL6_TMRB6FN_Enum;
/* ============================================ CTIMER CTRL6 TMRB6CLK [17..21] ============================================= */
typedef enum { /*!< CTIMER_CTRL6_TMRB6CLK */
CTIMER_CTRL6_TMRB6CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINB. */
CTIMER_CTRL6_TMRB6CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */
CTIMER_CTRL6_TMRB6CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */
CTIMER_CTRL6_TMRB6CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */
CTIMER_CTRL6_TMRB6CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */
CTIMER_CTRL6_TMRB6CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */
CTIMER_CTRL6_TMRB6CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */
CTIMER_CTRL6_TMRB6CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */
CTIMER_CTRL6_TMRB6CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */
CTIMER_CTRL6_TMRB6CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */
CTIMER_CTRL6_TMRB6CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */
CTIMER_CTRL6_TMRB6CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */
CTIMER_CTRL6_TMRB6CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */
CTIMER_CTRL6_TMRB6CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */
CTIMER_CTRL6_TMRB6CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */
CTIMER_CTRL6_TMRB6CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
available when MCU is in active mode) */
CTIMER_CTRL6_TMRB6CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */
CTIMER_CTRL6_TMRB6CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */
CTIMER_CTRL6_TMRB6CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */
CTIMER_CTRL6_TMRB6CLK_CTMRA6 = 20, /*!< CTMRA6 : Clock source is CTIMERA6 OUT. */
CTIMER_CTRL6_TMRB6CLK_CTMRA3 = 21, /*!< CTMRA3 : Clock source is CTIMERA3 OUT. */
CTIMER_CTRL6_TMRB6CLK_CTMRB3 = 22, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */
CTIMER_CTRL6_TMRB6CLK_CTMRA7 = 23, /*!< CTMRA7 : Clock source is CTIMERA7 OUT. */
CTIMER_CTRL6_TMRB6CLK_CTMRB7 = 24, /*!< CTMRB7 : Clock source is CTIMERB7 OUT. */
CTIMER_CTRL6_TMRB6CLK_CTMRB0 = 25, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */
CTIMER_CTRL6_TMRB6CLK_CTMRB1 = 26, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */
CTIMER_CTRL6_TMRB6CLK_CTMRB2 = 27, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */
CTIMER_CTRL6_TMRB6CLK_CTMRB4 = 28, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */
CTIMER_CTRL6_TMRB6CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */
CTIMER_CTRL6_TMRB6CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */
CTIMER_CTRL6_TMRB6CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */
} CTIMER_CTRL6_TMRB6CLK_Enum;
/* ============================================= CTIMER CTRL6 TMRB6EN [16..16] ============================================= */
typedef enum { /*!< CTIMER_CTRL6_TMRB6EN */
CTIMER_CTRL6_TMRB6EN_DIS = 0, /*!< DIS : Counter/Timer B6 Disable. */
CTIMER_CTRL6_TMRB6EN_EN = 1, /*!< EN : Counter/Timer B6 Enable. */
} CTIMER_CTRL6_TMRB6EN_Enum;
/* ============================================ CTIMER CTRL6 TMRA6POL [12..12] ============================================= */
typedef enum { /*!< CTIMER_CTRL6_TMRA6POL */
CTIMER_CTRL6_TMRA6POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINA6 pin is the same as the
timer output. */
CTIMER_CTRL6_TMRA6POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINA6 pin is the inverse of
the timer output. */
} CTIMER_CTRL6_TMRA6POL_Enum;
/* ============================================ CTIMER CTRL6 TMRA6CLR [11..11] ============================================= */
typedef enum { /*!< CTIMER_CTRL6_TMRA6CLR */
CTIMER_CTRL6_TMRA6CLR_RUN = 0, /*!< RUN : Allow counter/timer A6 to run */
CTIMER_CTRL6_TMRA6CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer A6 at 0x0000. */
} CTIMER_CTRL6_TMRA6CLR_Enum;
/* ============================================ CTIMER CTRL6 TMRA6IE1 [10..10] ============================================= */
typedef enum { /*!< CTIMER_CTRL6_TMRA6IE1 */
CTIMER_CTRL6_TMRA6IE1_DIS = 0, /*!< DIS : Disable counter/timer A6 from generating an interrupt
based on COMPR1. */
CTIMER_CTRL6_TMRA6IE1_EN = 1, /*!< EN : Enable counter/timer A6 to generate an interrupt based
on COMPR1. */
} CTIMER_CTRL6_TMRA6IE1_Enum;
/* ============================================= CTIMER CTRL6 TMRA6IE0 [9..9] ============================================== */
typedef enum { /*!< CTIMER_CTRL6_TMRA6IE0 */
CTIMER_CTRL6_TMRA6IE0_DIS = 0, /*!< DIS : Disable counter/timer A6 from generating an interrupt
based on COMPR0. */
CTIMER_CTRL6_TMRA6IE0_EN = 1, /*!< EN : Enable counter/timer A6 to generate an interrupt based
on COMPR0. */
} CTIMER_CTRL6_TMRA6IE0_Enum;
/* ============================================== CTIMER CTRL6 TMRA6FN [6..8] ============================================== */
typedef enum { /*!< CTIMER_CTRL6_TMRA6FN */
CTIMER_CTRL6_TMRA6FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
to CMPR0A6, stop. */
CTIMER_CTRL6_TMRA6FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
pulses). Count to CMPR0A6, restart. */
CTIMER_CTRL6_TMRA6FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A6, assert,
count to CMPR1A6, deassert, stop. */
CTIMER_CTRL6_TMRA6FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0A6, assert, count
to CMPR1A6, deassert, restart. */
CTIMER_CTRL6_TMRA6FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */
CTIMER_CTRL6_TMRA6FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */
CTIMER_CTRL6_TMRA6FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */
CTIMER_CTRL6_TMRA6FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */
} CTIMER_CTRL6_TMRA6FN_Enum;
/* ============================================= CTIMER CTRL6 TMRA6CLK [1..5] ============================================== */
typedef enum { /*!< CTIMER_CTRL6_TMRA6CLK */
CTIMER_CTRL6_TMRA6CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINA. */
CTIMER_CTRL6_TMRA6CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */
CTIMER_CTRL6_TMRA6CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */
CTIMER_CTRL6_TMRA6CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */
CTIMER_CTRL6_TMRA6CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */
CTIMER_CTRL6_TMRA6CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */
CTIMER_CTRL6_TMRA6CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */
CTIMER_CTRL6_TMRA6CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */
CTIMER_CTRL6_TMRA6CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */
CTIMER_CTRL6_TMRA6CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */
CTIMER_CTRL6_TMRA6CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */
CTIMER_CTRL6_TMRA6CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */
CTIMER_CTRL6_TMRA6CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */
CTIMER_CTRL6_TMRA6CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */
CTIMER_CTRL6_TMRA6CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */
CTIMER_CTRL6_TMRA6CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
available when MCU is in active mode) */
CTIMER_CTRL6_TMRA6CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */
CTIMER_CTRL6_TMRA6CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */
CTIMER_CTRL6_TMRA6CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */
CTIMER_CTRL6_TMRA6CLK_CTMRB6 = 20, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */
CTIMER_CTRL6_TMRA6CLK_CTMRA3 = 21, /*!< CTMRA3 : Clock source is CTIMERA3 OUT. */
CTIMER_CTRL6_TMRA6CLK_CTMRB3 = 22, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */
CTIMER_CTRL6_TMRA6CLK_CTMRA7 = 23, /*!< CTMRA7 : Clock source is CTIMERA7 OUT. */
CTIMER_CTRL6_TMRA6CLK_CTMRB7 = 24, /*!< CTMRB7 : Clock source is CTIMERB7 OUT. */
CTIMER_CTRL6_TMRA6CLK_CTMRB0 = 25, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */
CTIMER_CTRL6_TMRA6CLK_CTMRB1 = 26, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */
CTIMER_CTRL6_TMRA6CLK_CTMRB2 = 27, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */
CTIMER_CTRL6_TMRA6CLK_CTMRB4 = 28, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */
CTIMER_CTRL6_TMRA6CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */
CTIMER_CTRL6_TMRA6CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */
CTIMER_CTRL6_TMRA6CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */
} CTIMER_CTRL6_TMRA6CLK_Enum;
/* ============================================== CTIMER CTRL6 TMRA6EN [0..0] ============================================== */
typedef enum { /*!< CTIMER_CTRL6_TMRA6EN */
CTIMER_CTRL6_TMRA6EN_DIS = 0, /*!< DIS : Counter/Timer A6 Disable. */
CTIMER_CTRL6_TMRA6EN_EN = 1, /*!< EN : Counter/Timer A6 Enable. */
} CTIMER_CTRL6_TMRA6EN_Enum;
/* ======================================================= CMPRAUXA6 ======================================================= */
/* ======================================================= CMPRAUXB6 ======================================================= */
/* ========================================================= AUX6 ========================================================== */
/* ============================================ CTIMER AUX6 TMRB6EN23 [30..30] ============================================= */
typedef enum { /*!< CTIMER_AUX6_TMRB6EN23 */
CTIMER_AUX6_TMRB6EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */
CTIMER_AUX6_TMRB6EN23_EN = 0, /*!< EN : Enable enhanced functions. */
} CTIMER_AUX6_TMRB6EN23_Enum;
/* ============================================ CTIMER AUX6 TMRB6POL23 [29..29] ============================================ */
typedef enum { /*!< CTIMER_AUX6_TMRB6POL23 */
CTIMER_AUX6_TMRB6POL23_NORM = 0, /*!< NORM : Upper output normal polarity */
CTIMER_AUX6_TMRB6POL23_INV = 1, /*!< INV : Upper output inverted polarity. */
} CTIMER_AUX6_TMRB6POL23_Enum;
/* ============================================ CTIMER AUX6 TMRB6TINV [28..28] ============================================= */
typedef enum { /*!< CTIMER_AUX6_TMRB6TINV */
CTIMER_AUX6_TMRB6TINV_DIS = 0, /*!< DIS : Disable invert on trigger */
CTIMER_AUX6_TMRB6TINV_EN = 1, /*!< EN : Enable invert on trigger */
} CTIMER_AUX6_TMRB6TINV_Enum;
/* =========================================== CTIMER AUX6 TMRB6NOSYNC [27..27] ============================================ */
typedef enum { /*!< CTIMER_AUX6_TMRB6NOSYNC */
CTIMER_AUX6_TMRB6NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */
CTIMER_AUX6_TMRB6NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */
} CTIMER_AUX6_TMRB6NOSYNC_Enum;
/* ============================================ CTIMER AUX6 TMRB6TRIG [23..26] ============================================= */
typedef enum { /*!< CTIMER_AUX6_TMRB6TRIG */
CTIMER_AUX6_TMRB6TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */
CTIMER_AUX6_TMRB6TRIG_A6OUT = 1, /*!< A6OUT : Trigger source is CTIMERA6 OUT. */
CTIMER_AUX6_TMRB6TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */
CTIMER_AUX6_TMRB6TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */
CTIMER_AUX6_TMRB6TRIG_A4OUT = 4, /*!< A4OUT : Trigger source is CTIMERA4 OUT. */
CTIMER_AUX6_TMRB6TRIG_B4OUT = 5, /*!< B4OUT : Trigger source is CTIMERB4 OUT. */
CTIMER_AUX6_TMRB6TRIG_A1OUT = 6, /*!< A1OUT : Trigger source is CTIMERA1 OUT. */
CTIMER_AUX6_TMRB6TRIG_B1OUT = 7, /*!< B1OUT : Trigger source is CTIMERB1 OUT. */
CTIMER_AUX6_TMRB6TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */
CTIMER_AUX6_TMRB6TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */
CTIMER_AUX6_TMRB6TRIG_A2OUT2 = 10, /*!< A2OUT2 : Trigger source is CTIMERA2 OUT2. */
CTIMER_AUX6_TMRB6TRIG_B2OUT2 = 11, /*!< B2OUT2 : Trigger source is CTIMERB2 OUT2. */
CTIMER_AUX6_TMRB6TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */
CTIMER_AUX6_TMRB6TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */
CTIMER_AUX6_TMRB6TRIG_B0OUT2DUAL = 14, /*!< B0OUT2DUAL : Trigger source is CTIMERB0 OUT2, dual edge. */
CTIMER_AUX6_TMRB6TRIG_A0OUT2DUAL = 15, /*!< A0OUT2DUAL : Trigger source is CTIMERA0 OUT2, dual edge. */
} CTIMER_AUX6_TMRB6TRIG_Enum;
/* ============================================ CTIMER AUX6 TMRA6EN23 [14..14] ============================================= */
typedef enum { /*!< CTIMER_AUX6_TMRA6EN23 */
CTIMER_AUX6_TMRA6EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */
CTIMER_AUX6_TMRA6EN23_EN = 0, /*!< EN : Enable enhanced functions. */
} CTIMER_AUX6_TMRA6EN23_Enum;
/* ============================================ CTIMER AUX6 TMRA6POL23 [13..13] ============================================ */
typedef enum { /*!< CTIMER_AUX6_TMRA6POL23 */
CTIMER_AUX6_TMRA6POL23_NORM = 0, /*!< NORM : Upper output normal polarity */
CTIMER_AUX6_TMRA6POL23_INV = 1, /*!< INV : Upper output inverted polarity. */
} CTIMER_AUX6_TMRA6POL23_Enum;
/* ============================================ CTIMER AUX6 TMRA6TINV [12..12] ============================================= */
typedef enum { /*!< CTIMER_AUX6_TMRA6TINV */
CTIMER_AUX6_TMRA6TINV_DIS = 0, /*!< DIS : Disable invert on trigger */
CTIMER_AUX6_TMRA6TINV_EN = 1, /*!< EN : Enable invert on trigger */
} CTIMER_AUX6_TMRA6TINV_Enum;
/* =========================================== CTIMER AUX6 TMRA6NOSYNC [11..11] ============================================ */
typedef enum { /*!< CTIMER_AUX6_TMRA6NOSYNC */
CTIMER_AUX6_TMRA6NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */
CTIMER_AUX6_TMRA6NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */
} CTIMER_AUX6_TMRA6NOSYNC_Enum;
/* ============================================= CTIMER AUX6 TMRA6TRIG [7..10] ============================================= */
typedef enum { /*!< CTIMER_AUX6_TMRA6TRIG */
CTIMER_AUX6_TMRA6TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */
CTIMER_AUX6_TMRA6TRIG_B6OUT = 1, /*!< B6OUT : Trigger source is CTIMERB6 OUT. */
CTIMER_AUX6_TMRA6TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */
CTIMER_AUX6_TMRA6TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */
CTIMER_AUX6_TMRA6TRIG_A5OUT = 4, /*!< A5OUT : Trigger source is CTIMERA5 OUT. */
CTIMER_AUX6_TMRA6TRIG_B5OUT = 5, /*!< B5OUT : Trigger source is CTIMERB5 OUT. */
CTIMER_AUX6_TMRA6TRIG_A1OUT = 6, /*!< A1OUT : Trigger source is CTIMERA1 OUT. */
CTIMER_AUX6_TMRA6TRIG_B1OUT = 7, /*!< B1OUT : Trigger source is CTIMERB1 OUT. */
CTIMER_AUX6_TMRA6TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */
CTIMER_AUX6_TMRA6TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */
CTIMER_AUX6_TMRA6TRIG_A2OUT2 = 10, /*!< A2OUT2 : Trigger source is CTIMERA2 OUT2. */
CTIMER_AUX6_TMRA6TRIG_B2OUT2 = 11, /*!< B2OUT2 : Trigger source is CTIMERBb OUT2. */
CTIMER_AUX6_TMRA6TRIG_A5OUT2DUAL = 12, /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge. */
CTIMER_AUX6_TMRA6TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */
CTIMER_AUX6_TMRA6TRIG_B0OUT2DUAL = 14, /*!< B0OUT2DUAL : Trigger source is CTIMERB0 OUT2, dual edge. */
CTIMER_AUX6_TMRA6TRIG_A0OUT2DUAL = 15, /*!< A0OUT2DUAL : Trigger source is CTIMERA0 OUT2, dual edge. */
} CTIMER_AUX6_TMRA6TRIG_Enum;
/* ========================================================= TMR7 ========================================================== */
/* ======================================================== CMPRA7 ========================================================= */
/* ======================================================== CMPRB7 ========================================================= */
/* ========================================================= CTRL7 ========================================================= */
/* ============================================= CTIMER CTRL7 CTLINK7 [31..31] ============================================= */
typedef enum { /*!< CTIMER_CTRL7_CTLINK7 */
CTIMER_CTRL7_CTLINK7_TWO_16BIT_TIMERS = 0, /*!< TWO_16BIT_TIMERS : Use A7/B7 timers as two independent 16-bit
timers (default). */
CTIMER_CTRL7_CTLINK7_32BIT_TIMER = 1, /*!< 32BIT_TIMER : Link A7/B7 timers into a single 32-bit timer. */
} CTIMER_CTRL7_CTLINK7_Enum;
/* ============================================ CTIMER CTRL7 TMRB7POL [28..28] ============================================= */
typedef enum { /*!< CTIMER_CTRL7_TMRB7POL */
CTIMER_CTRL7_TMRB7POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINB7 pin is the same as the
timer output. */
CTIMER_CTRL7_TMRB7POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINB7 pin is the inverse of
the timer output. */
} CTIMER_CTRL7_TMRB7POL_Enum;
/* ============================================ CTIMER CTRL7 TMRB7CLR [27..27] ============================================= */
typedef enum { /*!< CTIMER_CTRL7_TMRB7CLR */
CTIMER_CTRL7_TMRB7CLR_RUN = 0, /*!< RUN : Allow counter/timer B7 to run */
CTIMER_CTRL7_TMRB7CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer B7 at 0x0000. */
} CTIMER_CTRL7_TMRB7CLR_Enum;
/* ============================================ CTIMER CTRL7 TMRB7IE1 [26..26] ============================================= */
typedef enum { /*!< CTIMER_CTRL7_TMRB7IE1 */
CTIMER_CTRL7_TMRB7IE1_DIS = 0, /*!< DIS : Disable counter/timer B7 from generating an interrupt
based on COMPR1. */
CTIMER_CTRL7_TMRB7IE1_EN = 1, /*!< EN : Enable counter/timer B7 to generate an interrupt based
on COMPR1. */
} CTIMER_CTRL7_TMRB7IE1_Enum;
/* ============================================ CTIMER CTRL7 TMRB7IE0 [25..25] ============================================= */
typedef enum { /*!< CTIMER_CTRL7_TMRB7IE0 */
CTIMER_CTRL7_TMRB7IE0_DIS = 0, /*!< DIS : Disable counter/timer B7 from generating an interrupt
based on COMPR0. */
CTIMER_CTRL7_TMRB7IE0_EN = 1, /*!< EN : Enable counter/timer B7 to generate an interrupt based
on COMPR0 */
} CTIMER_CTRL7_TMRB7IE0_Enum;
/* ============================================= CTIMER CTRL7 TMRB7FN [22..24] ============================================= */
typedef enum { /*!< CTIMER_CTRL7_TMRB7FN */
CTIMER_CTRL7_TMRB7FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
to CMPR0B7, stop. */
CTIMER_CTRL7_TMRB7FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
pulses). Count to CMPR0B7, restart. */
CTIMER_CTRL7_TMRB7FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B7, assert,
count to CMPR1B7, deassert, stop. */
CTIMER_CTRL7_TMRB7FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0B7, assert, count
to CMPR1B7, deassert, restart. */
CTIMER_CTRL7_TMRB7FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */
CTIMER_CTRL7_TMRB7FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */
CTIMER_CTRL7_TMRB7FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */
CTIMER_CTRL7_TMRB7FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */
} CTIMER_CTRL7_TMRB7FN_Enum;
/* ============================================ CTIMER CTRL7 TMRB7CLK [17..21] ============================================= */
typedef enum { /*!< CTIMER_CTRL7_TMRB7CLK */
CTIMER_CTRL7_TMRB7CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINB. */
CTIMER_CTRL7_TMRB7CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */
CTIMER_CTRL7_TMRB7CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */
CTIMER_CTRL7_TMRB7CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */
CTIMER_CTRL7_TMRB7CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */
CTIMER_CTRL7_TMRB7CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */
CTIMER_CTRL7_TMRB7CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */
CTIMER_CTRL7_TMRB7CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */
CTIMER_CTRL7_TMRB7CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */
CTIMER_CTRL7_TMRB7CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */
CTIMER_CTRL7_TMRB7CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */
CTIMER_CTRL7_TMRB7CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */
CTIMER_CTRL7_TMRB7CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */
CTIMER_CTRL7_TMRB7CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */
CTIMER_CTRL7_TMRB7CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */
CTIMER_CTRL7_TMRB7CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
available when MCU is in active mode) */
CTIMER_CTRL7_TMRB7CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */
CTIMER_CTRL7_TMRB7CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */
CTIMER_CTRL7_TMRB7CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */
CTIMER_CTRL7_TMRB7CLK_CTMRA7 = 20, /*!< CTMRA7 : Clock source is CTIMERA7 OUT. */
CTIMER_CTRL7_TMRB7CLK_CTMRA2 = 21, /*!< CTMRA2 : Clock source is CTIMERA2 OUT. */
CTIMER_CTRL7_TMRB7CLK_CTMRB2 = 22, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */
CTIMER_CTRL7_TMRB7CLK_CTMRA0 = 23, /*!< CTMRA0 : Clock source is CTIMERA0 OUT. */
CTIMER_CTRL7_TMRB7CLK_CTMRB0 = 24, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */
CTIMER_CTRL7_TMRB7CLK_CTMRB1 = 25, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */
CTIMER_CTRL7_TMRB7CLK_CTMRB3 = 26, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */
CTIMER_CTRL7_TMRB7CLK_CTMRB4 = 27, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */
CTIMER_CTRL7_TMRB7CLK_CTMRB5 = 28, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */
CTIMER_CTRL7_TMRB7CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */
CTIMER_CTRL7_TMRB7CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */
CTIMER_CTRL7_TMRB7CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */
} CTIMER_CTRL7_TMRB7CLK_Enum;
/* ============================================= CTIMER CTRL7 TMRB7EN [16..16] ============================================= */
typedef enum { /*!< CTIMER_CTRL7_TMRB7EN */
CTIMER_CTRL7_TMRB7EN_DIS = 0, /*!< DIS : Counter/Timer B7 Disable. */
CTIMER_CTRL7_TMRB7EN_EN = 1, /*!< EN : Counter/Timer B7 Enable. */
} CTIMER_CTRL7_TMRB7EN_Enum;
/* ============================================ CTIMER CTRL7 TMRA7POL [12..12] ============================================= */
typedef enum { /*!< CTIMER_CTRL7_TMRA7POL */
CTIMER_CTRL7_TMRA7POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINA7 pin is the same as the
timer output. */
CTIMER_CTRL7_TMRA7POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINA7 pin is the inverse of
the timer output. */
} CTIMER_CTRL7_TMRA7POL_Enum;
/* ============================================ CTIMER CTRL7 TMRA7CLR [11..11] ============================================= */
typedef enum { /*!< CTIMER_CTRL7_TMRA7CLR */
CTIMER_CTRL7_TMRA7CLR_RUN = 0, /*!< RUN : Allow counter/timer A7 to run */
CTIMER_CTRL7_TMRA7CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer A7 at 0x0000. */
} CTIMER_CTRL7_TMRA7CLR_Enum;
/* ============================================ CTIMER CTRL7 TMRA7IE1 [10..10] ============================================= */
typedef enum { /*!< CTIMER_CTRL7_TMRA7IE1 */
CTIMER_CTRL7_TMRA7IE1_DIS = 0, /*!< DIS : Disable counter/timer A7 from generating an interrupt
based on COMPR1. */
CTIMER_CTRL7_TMRA7IE1_EN = 1, /*!< EN : Enable counter/timer A7 to generate an interrupt based
on COMPR1. */
} CTIMER_CTRL7_TMRA7IE1_Enum;
/* ============================================= CTIMER CTRL7 TMRA7IE0 [9..9] ============================================== */
typedef enum { /*!< CTIMER_CTRL7_TMRA7IE0 */
CTIMER_CTRL7_TMRA7IE0_DIS = 0, /*!< DIS : Disable counter/timer A7 from generating an interrupt
based on COMPR0. */
CTIMER_CTRL7_TMRA7IE0_EN = 1, /*!< EN : Enable counter/timer A7 to generate an interrupt based
on COMPR0. */
} CTIMER_CTRL7_TMRA7IE0_Enum;
/* ============================================== CTIMER CTRL7 TMRA7FN [6..8] ============================================== */
typedef enum { /*!< CTIMER_CTRL7_TMRA7FN */
CTIMER_CTRL7_TMRA7FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
to CMPR0A7, stop. */
CTIMER_CTRL7_TMRA7FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
pulses). Count to CMPR0A7, restart. */
CTIMER_CTRL7_TMRA7FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A7, assert,
count to CMPR1A7, deassert, stop. */
CTIMER_CTRL7_TMRA7FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0A7, assert, count
to CMPR1A7, deassert, restart. */
CTIMER_CTRL7_TMRA7FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */
CTIMER_CTRL7_TMRA7FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */
CTIMER_CTRL7_TMRA7FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */
CTIMER_CTRL7_TMRA7FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */
} CTIMER_CTRL7_TMRA7FN_Enum;
/* ============================================= CTIMER CTRL7 TMRA7CLK [1..5] ============================================== */
typedef enum { /*!< CTIMER_CTRL7_TMRA7CLK */
CTIMER_CTRL7_TMRA7CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINA. */
CTIMER_CTRL7_TMRA7CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */
CTIMER_CTRL7_TMRA7CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */
CTIMER_CTRL7_TMRA7CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */
CTIMER_CTRL7_TMRA7CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */
CTIMER_CTRL7_TMRA7CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */
CTIMER_CTRL7_TMRA7CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */
CTIMER_CTRL7_TMRA7CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */
CTIMER_CTRL7_TMRA7CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */
CTIMER_CTRL7_TMRA7CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */
CTIMER_CTRL7_TMRA7CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */
CTIMER_CTRL7_TMRA7CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */
CTIMER_CTRL7_TMRA7CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */
CTIMER_CTRL7_TMRA7CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */
CTIMER_CTRL7_TMRA7CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */
CTIMER_CTRL7_TMRA7CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
available when MCU is in active mode) */
CTIMER_CTRL7_TMRA7CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */
CTIMER_CTRL7_TMRA7CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */
CTIMER_CTRL7_TMRA7CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */
CTIMER_CTRL7_TMRA7CLK_CTMRB7 = 20, /*!< CTMRB7 : Clock source is CTIMERB7 OUT. */
CTIMER_CTRL7_TMRA7CLK_CTMRA2 = 21, /*!< CTMRA2 : Clock source is CTIMERA2 OUT. */
CTIMER_CTRL7_TMRA7CLK_CTMRB2 = 22, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */
CTIMER_CTRL7_TMRA7CLK_CTMRA0 = 23, /*!< CTMRA0 : Clock source is CTIMERA0 OUT. */
CTIMER_CTRL7_TMRA7CLK_CTMRB0 = 24, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */
CTIMER_CTRL7_TMRA7CLK_CTMRB1 = 25, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */
CTIMER_CTRL7_TMRA7CLK_CTMRB3 = 26, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */
CTIMER_CTRL7_TMRA7CLK_CTMRB4 = 27, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */
CTIMER_CTRL7_TMRA7CLK_CTMRB5 = 28, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */
CTIMER_CTRL7_TMRA7CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */
CTIMER_CTRL7_TMRA7CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */
CTIMER_CTRL7_TMRA7CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */
} CTIMER_CTRL7_TMRA7CLK_Enum;
/* ============================================== CTIMER CTRL7 TMRA7EN [0..0] ============================================== */
typedef enum { /*!< CTIMER_CTRL7_TMRA7EN */
CTIMER_CTRL7_TMRA7EN_DIS = 0, /*!< DIS : Counter/Timer A7 Disable. */
CTIMER_CTRL7_TMRA7EN_EN = 1, /*!< EN : Counter/Timer A7 Enable. */
} CTIMER_CTRL7_TMRA7EN_Enum;
/* ======================================================= CMPRAUXA7 ======================================================= */
/* ======================================================= CMPRAUXB7 ======================================================= */
/* ========================================================= AUX7 ========================================================== */
/* ============================================ CTIMER AUX7 TMRB7EN23 [30..30] ============================================= */
typedef enum { /*!< CTIMER_AUX7_TMRB7EN23 */
CTIMER_AUX7_TMRB7EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */
CTIMER_AUX7_TMRB7EN23_EN = 0, /*!< EN : Enable enhanced functions. */
} CTIMER_AUX7_TMRB7EN23_Enum;
/* ============================================ CTIMER AUX7 TMRB7POL23 [29..29] ============================================ */
typedef enum { /*!< CTIMER_AUX7_TMRB7POL23 */
CTIMER_AUX7_TMRB7POL23_NORM = 0, /*!< NORM : Upper output normal polarity */
CTIMER_AUX7_TMRB7POL23_INV = 1, /*!< INV : Upper output inverted polarity. */
} CTIMER_AUX7_TMRB7POL23_Enum;
/* ============================================ CTIMER AUX7 TMRB7TINV [28..28] ============================================= */
typedef enum { /*!< CTIMER_AUX7_TMRB7TINV */
CTIMER_AUX7_TMRB7TINV_DIS = 0, /*!< DIS : Disable invert on trigger */
CTIMER_AUX7_TMRB7TINV_EN = 1, /*!< EN : Enable invert on trigger */
} CTIMER_AUX7_TMRB7TINV_Enum;
/* =========================================== CTIMER AUX7 TMRB7NOSYNC [27..27] ============================================ */
typedef enum { /*!< CTIMER_AUX7_TMRB7NOSYNC */
CTIMER_AUX7_TMRB7NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */
CTIMER_AUX7_TMRB7NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */
} CTIMER_AUX7_TMRB7NOSYNC_Enum;
/* ============================================ CTIMER AUX7 TMRB7TRIG [23..26] ============================================= */
typedef enum { /*!< CTIMER_AUX7_TMRB7TRIG */
CTIMER_AUX7_TMRB7TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */
CTIMER_AUX7_TMRB7TRIG_A7OUT = 1, /*!< A7OUT : Trigger source is CTIMERA7 OUT. */
CTIMER_AUX7_TMRB7TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */
CTIMER_AUX7_TMRB7TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */
CTIMER_AUX7_TMRB7TRIG_A5OUT = 4, /*!< A5OUT : Trigger source is CTIMERA5 OUT. */
CTIMER_AUX7_TMRB7TRIG_B5OUT = 5, /*!< B5OUT : Trigger source is CTIMERB5 OUT. */
CTIMER_AUX7_TMRB7TRIG_A2OUT = 6, /*!< A2OUT : Trigger source is CTIMERA2 OUT. */
CTIMER_AUX7_TMRB7TRIG_B2OUT = 7, /*!< B2OUT : Trigger source is CTIMERB2 OUT. */
CTIMER_AUX7_TMRB7TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */
CTIMER_AUX7_TMRB7TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */
CTIMER_AUX7_TMRB7TRIG_A2OUT2 = 10, /*!< A2OUT2 : Trigger source is CTIMERA2 OUT2. */
CTIMER_AUX7_TMRB7TRIG_B2OUT2 = 11, /*!< B2OUT2 : Trigger source is CTIMERB2 OUT2. */
CTIMER_AUX7_TMRB7TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */
CTIMER_AUX7_TMRB7TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */
CTIMER_AUX7_TMRB7TRIG_B1OUT2DUAL = 14, /*!< B1OUT2DUAL : Trigger source is CTIMERB1 OUT2, dual edge. */
CTIMER_AUX7_TMRB7TRIG_A1OUT2DUAL = 15, /*!< A1OUT2DUAL : Trigger source is CTIMERA1 OUT2, dual edge. */
} CTIMER_AUX7_TMRB7TRIG_Enum;
/* ============================================ CTIMER AUX7 TMRA7EN23 [14..14] ============================================= */
typedef enum { /*!< CTIMER_AUX7_TMRA7EN23 */
CTIMER_AUX7_TMRA7EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */
CTIMER_AUX7_TMRA7EN23_EN = 0, /*!< EN : Enable enhanced functions. */
} CTIMER_AUX7_TMRA7EN23_Enum;
/* ============================================ CTIMER AUX7 TMRA7POL23 [13..13] ============================================ */
typedef enum { /*!< CTIMER_AUX7_TMRA7POL23 */
CTIMER_AUX7_TMRA7POL23_NORM = 0, /*!< NORM : Upper output normal polarity */
CTIMER_AUX7_TMRA7POL23_INV = 1, /*!< INV : Upper output inverted polarity. */
} CTIMER_AUX7_TMRA7POL23_Enum;
/* ============================================ CTIMER AUX7 TMRA7TINV [12..12] ============================================= */
typedef enum { /*!< CTIMER_AUX7_TMRA7TINV */
CTIMER_AUX7_TMRA7TINV_DIS = 0, /*!< DIS : Disable invert on trigger */
CTIMER_AUX7_TMRA7TINV_EN = 1, /*!< EN : Enable invert on trigger */
} CTIMER_AUX7_TMRA7TINV_Enum;
/* =========================================== CTIMER AUX7 TMRA7NOSYNC [11..11] ============================================ */
typedef enum { /*!< CTIMER_AUX7_TMRA7NOSYNC */
CTIMER_AUX7_TMRA7NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */
CTIMER_AUX7_TMRA7NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */
} CTIMER_AUX7_TMRA7NOSYNC_Enum;
/* ============================================= CTIMER AUX7 TMRA7TRIG [7..10] ============================================= */
typedef enum { /*!< CTIMER_AUX7_TMRA7TRIG */
CTIMER_AUX7_TMRA7TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */
CTIMER_AUX7_TMRA7TRIG_B7OUT = 1, /*!< B7OUT : Trigger source is CTIMERB7 OUT. */
CTIMER_AUX7_TMRA7TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */
CTIMER_AUX7_TMRA7TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */
CTIMER_AUX7_TMRA7TRIG_A1OUT = 4, /*!< A1OUT : Trigger source is CTIMERA1 OUT. */
CTIMER_AUX7_TMRA7TRIG_B1OUT = 5, /*!< B1OUT : Trigger source is CTIMERB1 OUT. */
CTIMER_AUX7_TMRA7TRIG_A4OUT = 6, /*!< A4OUT : Trigger source is CTIMERA4 OUT. */
CTIMER_AUX7_TMRA7TRIG_B4OUT = 7, /*!< B4OUT : Trigger source is CTIMERB4 OUT. */
CTIMER_AUX7_TMRA7TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */
CTIMER_AUX7_TMRA7TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */
CTIMER_AUX7_TMRA7TRIG_A2OUT2 = 10, /*!< A2OUT2 : Trigger source is CTIMERA2 OUT2. */
CTIMER_AUX7_TMRA7TRIG_B2OUT2 = 11, /*!< B2OUT2 : Trigger source is CTIMERB2 OUT2. */
CTIMER_AUX7_TMRA7TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */
CTIMER_AUX7_TMRA7TRIG_A5OUT2DUAL = 13, /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge. */
CTIMER_AUX7_TMRA7TRIG_B4OUT2DUAL = 14, /*!< B4OUT2DUAL : Trigger source is CTIMERB4 OUT2, dual edge. */
CTIMER_AUX7_TMRA7TRIG_A4OUT2DUAL = 15, /*!< A4OUT2DUAL : Trigger source is CTIMERA4 OUT2, dual edge. */
} CTIMER_AUX7_TMRA7TRIG_Enum;
/* ======================================================== GLOBEN ========================================================= */
/* ============================================== CTIMER GLOBEN ENB7 [15..15] ============================================== */
typedef enum { /*!< CTIMER_GLOBEN_ENB7 */
CTIMER_GLOBEN_ENB7_LCO = 1, /*!< LCO : Use local enable. */
CTIMER_GLOBEN_ENB7_DIS = 0, /*!< DIS : Disable CTIMER. */
} CTIMER_GLOBEN_ENB7_Enum;
/* ============================================== CTIMER GLOBEN ENA7 [14..14] ============================================== */
typedef enum { /*!< CTIMER_GLOBEN_ENA7 */
CTIMER_GLOBEN_ENA7_LCO = 1, /*!< LCO : Use local enable. */
CTIMER_GLOBEN_ENA7_DIS = 0, /*!< DIS : Disable CTIMER. */
} CTIMER_GLOBEN_ENA7_Enum;
/* ============================================== CTIMER GLOBEN ENB6 [13..13] ============================================== */
typedef enum { /*!< CTIMER_GLOBEN_ENB6 */
CTIMER_GLOBEN_ENB6_LCO = 1, /*!< LCO : Use local enable. */
CTIMER_GLOBEN_ENB6_DIS = 0, /*!< DIS : Disable CTIMER. */
} CTIMER_GLOBEN_ENB6_Enum;
/* ============================================== CTIMER GLOBEN ENA6 [12..12] ============================================== */
typedef enum { /*!< CTIMER_GLOBEN_ENA6 */
CTIMER_GLOBEN_ENA6_LCO = 1, /*!< LCO : Use local enable. */
CTIMER_GLOBEN_ENA6_DIS = 0, /*!< DIS : Disable CTIMER. */
} CTIMER_GLOBEN_ENA6_Enum;
/* ============================================== CTIMER GLOBEN ENB5 [11..11] ============================================== */
typedef enum { /*!< CTIMER_GLOBEN_ENB5 */
CTIMER_GLOBEN_ENB5_LCO = 1, /*!< LCO : Use local enable. */
CTIMER_GLOBEN_ENB5_DIS = 0, /*!< DIS : Disable CTIMER. */
} CTIMER_GLOBEN_ENB5_Enum;
/* ============================================== CTIMER GLOBEN ENA5 [10..10] ============================================== */
typedef enum { /*!< CTIMER_GLOBEN_ENA5 */
CTIMER_GLOBEN_ENA5_LCO = 1, /*!< LCO : Use local enable. */
CTIMER_GLOBEN_ENA5_DIS = 0, /*!< DIS : Disable CTIMER. */
} CTIMER_GLOBEN_ENA5_Enum;
/* =============================================== CTIMER GLOBEN ENB4 [9..9] =============================================== */
typedef enum { /*!< CTIMER_GLOBEN_ENB4 */
CTIMER_GLOBEN_ENB4_LCO = 1, /*!< LCO : Use local enable. */
CTIMER_GLOBEN_ENB4_DIS = 0, /*!< DIS : Disable CTIMER. */
} CTIMER_GLOBEN_ENB4_Enum;
/* =============================================== CTIMER GLOBEN ENA4 [8..8] =============================================== */
typedef enum { /*!< CTIMER_GLOBEN_ENA4 */
CTIMER_GLOBEN_ENA4_LCO = 1, /*!< LCO : Use local enable. */
CTIMER_GLOBEN_ENA4_DIS = 0, /*!< DIS : Disable CTIMER. */
} CTIMER_GLOBEN_ENA4_Enum;
/* =============================================== CTIMER GLOBEN ENB3 [7..7] =============================================== */
typedef enum { /*!< CTIMER_GLOBEN_ENB3 */
CTIMER_GLOBEN_ENB3_LCO = 1, /*!< LCO : Use local enable. */
CTIMER_GLOBEN_ENB3_DIS = 0, /*!< DIS : Disable CTIMER. */
} CTIMER_GLOBEN_ENB3_Enum;
/* =============================================== CTIMER GLOBEN ENA3 [6..6] =============================================== */
typedef enum { /*!< CTIMER_GLOBEN_ENA3 */
CTIMER_GLOBEN_ENA3_LCO = 1, /*!< LCO : Use local enable. */
CTIMER_GLOBEN_ENA3_DIS = 0, /*!< DIS : Disable CTIMER. */
} CTIMER_GLOBEN_ENA3_Enum;
/* =============================================== CTIMER GLOBEN ENB2 [5..5] =============================================== */
typedef enum { /*!< CTIMER_GLOBEN_ENB2 */
CTIMER_GLOBEN_ENB2_LCO = 1, /*!< LCO : Use local enable. */
CTIMER_GLOBEN_ENB2_DIS = 0, /*!< DIS : Disable CTIMER. */
} CTIMER_GLOBEN_ENB2_Enum;
/* =============================================== CTIMER GLOBEN ENA2 [4..4] =============================================== */
typedef enum { /*!< CTIMER_GLOBEN_ENA2 */
CTIMER_GLOBEN_ENA2_LCO = 1, /*!< LCO : Use local enable. */
CTIMER_GLOBEN_ENA2_DIS = 0, /*!< DIS : Disable CTIMER. */
} CTIMER_GLOBEN_ENA2_Enum;
/* =============================================== CTIMER GLOBEN ENB1 [3..3] =============================================== */
typedef enum { /*!< CTIMER_GLOBEN_ENB1 */
CTIMER_GLOBEN_ENB1_LCO = 1, /*!< LCO : Use local enable. */
CTIMER_GLOBEN_ENB1_DIS = 0, /*!< DIS : Disable CTIMER. */
} CTIMER_GLOBEN_ENB1_Enum;
/* =============================================== CTIMER GLOBEN ENA1 [2..2] =============================================== */
typedef enum { /*!< CTIMER_GLOBEN_ENA1 */
CTIMER_GLOBEN_ENA1_LCO = 1, /*!< LCO : Use local enable. */
CTIMER_GLOBEN_ENA1_DIS = 0, /*!< DIS : Disable CTIMER. */
} CTIMER_GLOBEN_ENA1_Enum;
/* =============================================== CTIMER GLOBEN ENB0 [1..1] =============================================== */
typedef enum { /*!< CTIMER_GLOBEN_ENB0 */
CTIMER_GLOBEN_ENB0_LCO = 1, /*!< LCO : Use local enable. */
CTIMER_GLOBEN_ENB0_DIS = 0, /*!< DIS : Disable CTIMER. */
} CTIMER_GLOBEN_ENB0_Enum;
/* =============================================== CTIMER GLOBEN ENA0 [0..0] =============================================== */
typedef enum { /*!< CTIMER_GLOBEN_ENA0 */
CTIMER_GLOBEN_ENA0_LCO = 1, /*!< LCO : Use local enable. */
CTIMER_GLOBEN_ENA0_DIS = 0, /*!< DIS : Disable CTIMER. */
} CTIMER_GLOBEN_ENA0_Enum;
/* ======================================================== OUTCFG0 ======================================================== */
/* ============================================= CTIMER OUTCFG0 CFG9 [28..30] ============================================== */
typedef enum { /*!< CTIMER_OUTCFG0_CFG9 */
CTIMER_OUTCFG0_CFG9_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */
CTIMER_OUTCFG0_CFG9_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */
CTIMER_OUTCFG0_CFG9_B0OUT = 5, /*!< B0OUT : Output is B0OUT. */
CTIMER_OUTCFG0_CFG9_A4OUT = 4, /*!< A4OUT : Output is A4OUT. */
CTIMER_OUTCFG0_CFG9_A2OUT = 3, /*!< A2OUT : Output is A2OUT. */
CTIMER_OUTCFG0_CFG9_A2OUT2 = 2, /*!< A2OUT2 : Output is A2OUT2 */
CTIMER_OUTCFG0_CFG9_ONE = 1, /*!< ONE : Force output to 1. */
CTIMER_OUTCFG0_CFG9_ZERO = 0, /*!< ZERO : Force output to 0 */
} CTIMER_OUTCFG0_CFG9_Enum;
/* ============================================= CTIMER OUTCFG0 CFG8 [25..27] ============================================== */
typedef enum { /*!< CTIMER_OUTCFG0_CFG8 */
CTIMER_OUTCFG0_CFG8_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */
CTIMER_OUTCFG0_CFG8_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */
CTIMER_OUTCFG0_CFG8_B6OUT = 5, /*!< B6OUT : Output is B6OUT. */
CTIMER_OUTCFG0_CFG8_A4OUT2 = 4, /*!< A4OUT2 : Output is A4OUT2. */
CTIMER_OUTCFG0_CFG8_A3OUT2 = 3, /*!< A3OUT2 : Output is A3OUT. */
CTIMER_OUTCFG0_CFG8_A2OUT = 2, /*!< A2OUT : Output is A2OUT */
CTIMER_OUTCFG0_CFG8_ONE = 1, /*!< ONE : Force output to 1. */
CTIMER_OUTCFG0_CFG8_ZERO = 0, /*!< ZERO : Force output to 0 */
} CTIMER_OUTCFG0_CFG8_Enum;
/* ============================================= CTIMER OUTCFG0 CFG7 [22..24] ============================================== */
typedef enum { /*!< CTIMER_OUTCFG0_CFG7 */
CTIMER_OUTCFG0_CFG7_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */
CTIMER_OUTCFG0_CFG7_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */
CTIMER_OUTCFG0_CFG7_A7OUT = 5, /*!< A7OUT : Output is A7OUT. */
CTIMER_OUTCFG0_CFG7_B5OUT = 4, /*!< B5OUT : Output is B5OUT. */
CTIMER_OUTCFG0_CFG7_B1OUT = 3, /*!< B1OUT : Output is B1OUT. */
CTIMER_OUTCFG0_CFG7_B1OUT2 = 2, /*!< B1OUT2 : Output is B1OUT2 */
CTIMER_OUTCFG0_CFG7_ONE = 1, /*!< ONE : Force output to 1. */
CTIMER_OUTCFG0_CFG7_ZERO = 0, /*!< ZERO : Force output to 0 */
} CTIMER_OUTCFG0_CFG7_Enum;
/* ============================================= CTIMER OUTCFG0 CFG6 [19..21] ============================================== */
typedef enum { /*!< CTIMER_OUTCFG0_CFG6 */
CTIMER_OUTCFG0_CFG6_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */
CTIMER_OUTCFG0_CFG6_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */
CTIMER_OUTCFG0_CFG6_B7OUT = 5, /*!< B7OUT : Output is B7OUT. */
CTIMER_OUTCFG0_CFG6_B5OUT2 = 4, /*!< B5OUT2 : Output is B5OUT2. */
CTIMER_OUTCFG0_CFG6_A1OUT = 3, /*!< A1OUT : Output is A1OUT. */
CTIMER_OUTCFG0_CFG6_B1OUT = 2, /*!< B1OUT : Output is B1OUT */
CTIMER_OUTCFG0_CFG6_ONE = 1, /*!< ONE : Force output to 1. */
CTIMER_OUTCFG0_CFG6_ZERO = 0, /*!< ZERO : Force output to 0 */
} CTIMER_OUTCFG0_CFG6_Enum;
/* ============================================= CTIMER OUTCFG0 CFG5 [16..18] ============================================== */
typedef enum { /*!< CTIMER_OUTCFG0_CFG5 */
CTIMER_OUTCFG0_CFG5_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */
CTIMER_OUTCFG0_CFG5_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */
CTIMER_OUTCFG0_CFG5_A7OUT = 5, /*!< A7OUT : Output is A7OUT. */
CTIMER_OUTCFG0_CFG5_B6OUT = 4, /*!< B6OUT : Output is A5OUT. */
CTIMER_OUTCFG0_CFG5_A1OUT = 3, /*!< A1OUT : Output is A1OUT. */
CTIMER_OUTCFG0_CFG5_A1OUT2 = 2, /*!< A1OUT2 : Output is A1OUT2 */
CTIMER_OUTCFG0_CFG5_ONE = 1, /*!< ONE : Force output to 1. */
CTIMER_OUTCFG0_CFG5_ZERO = 0, /*!< ZERO : Force output to 0 */
} CTIMER_OUTCFG0_CFG5_Enum;
/* ============================================= CTIMER OUTCFG0 CFG4 [12..14] ============================================== */
typedef enum { /*!< CTIMER_OUTCFG0_CFG4 */
CTIMER_OUTCFG0_CFG4_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */
CTIMER_OUTCFG0_CFG4_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */
CTIMER_OUTCFG0_CFG4_B5OUT = 5, /*!< B5OUT : Output is B5OUT. */
CTIMER_OUTCFG0_CFG4_A5OUT2 = 4, /*!< A5OUT2 : Output is A5OUT2. */
CTIMER_OUTCFG0_CFG4_A2OUT2 = 3, /*!< A2OUT2 : Output is A2OUT2. */
CTIMER_OUTCFG0_CFG4_A1OUT = 2, /*!< A1OUT : Output is A1OUT */
CTIMER_OUTCFG0_CFG4_ONE = 1, /*!< ONE : Force output to 1. */
CTIMER_OUTCFG0_CFG4_ZERO = 0, /*!< ZERO : Force output to 0 */
} CTIMER_OUTCFG0_CFG4_Enum;
/* ============================================== CTIMER OUTCFG0 CFG3 [9..11] ============================================== */
typedef enum { /*!< CTIMER_OUTCFG0_CFG3 */
CTIMER_OUTCFG0_CFG3_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */
CTIMER_OUTCFG0_CFG3_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */
CTIMER_OUTCFG0_CFG3_A6OUT = 5, /*!< A6OUT : Output is A6OUT. */
CTIMER_OUTCFG0_CFG3_A1OUT = 4, /*!< A1OUT : Output is A1OUT. */
CTIMER_OUTCFG0_CFG3_B0OUT = 3, /*!< B0OUT : Output is B0OUT. */
CTIMER_OUTCFG0_CFG3_B0OUT2 = 2, /*!< B0OUT2 : Output is B0OUT2 */
CTIMER_OUTCFG0_CFG3_ONE = 1, /*!< ONE : Force output to 1. */
CTIMER_OUTCFG0_CFG3_ZERO = 0, /*!< ZERO : Force output to 0 */
} CTIMER_OUTCFG0_CFG3_Enum;
/* ============================================== CTIMER OUTCFG0 CFG2 [6..8] =============================================== */
typedef enum { /*!< CTIMER_OUTCFG0_CFG2 */
CTIMER_OUTCFG0_CFG2_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */
CTIMER_OUTCFG0_CFG2_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */
CTIMER_OUTCFG0_CFG2_A7OUT = 5, /*!< A7OUT : Output is A7OUT. */
CTIMER_OUTCFG0_CFG2_B6OUT2 = 4, /*!< B6OUT2 : Output is B6OUT2. */
CTIMER_OUTCFG0_CFG2_B1OUT2 = 3, /*!< B1OUT2 : Output is B1OUT2. */
CTIMER_OUTCFG0_CFG2_B0OUT = 2, /*!< B0OUT : Output is B0OUT */
CTIMER_OUTCFG0_CFG2_ONE = 1, /*!< ONE : Force output to 1. */
CTIMER_OUTCFG0_CFG2_ZERO = 0, /*!< ZERO : Force output to 0 */
} CTIMER_OUTCFG0_CFG2_Enum;
/* ============================================== CTIMER OUTCFG0 CFG1 [3..5] =============================================== */
typedef enum { /*!< CTIMER_OUTCFG0_CFG1 */
CTIMER_OUTCFG0_CFG1_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */
CTIMER_OUTCFG0_CFG1_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */
CTIMER_OUTCFG0_CFG1_B7OUT2 = 5, /*!< B7OUT2 : Output is B7OUT2. */
CTIMER_OUTCFG0_CFG1_A5OUT = 4, /*!< A5OUT : Output is A5OUT. */
CTIMER_OUTCFG0_CFG1_A0OUT = 3, /*!< A0OUT : Output is A0OUT. */
CTIMER_OUTCFG0_CFG1_A0OUT2 = 2, /*!< A0OUT2 : Output is A0OUT2 */
CTIMER_OUTCFG0_CFG1_ONE = 1, /*!< ONE : Force output to 1. */
CTIMER_OUTCFG0_CFG1_ZERO = 0, /*!< ZERO : Force output to 0 */
} CTIMER_OUTCFG0_CFG1_Enum;
/* ============================================== CTIMER OUTCFG0 CFG0 [0..2] =============================================== */
typedef enum { /*!< CTIMER_OUTCFG0_CFG0 */
CTIMER_OUTCFG0_CFG0_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */
CTIMER_OUTCFG0_CFG0_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */
CTIMER_OUTCFG0_CFG0_A6OUT = 5, /*!< A6OUT : Output is A6OUT. */
CTIMER_OUTCFG0_CFG0_A5OUT2 = 4, /*!< A5OUT2 : Output is A5OUT2. */
CTIMER_OUTCFG0_CFG0_B2OUT2 = 3, /*!< B2OUT2 : Output is B2OUT2. */
CTIMER_OUTCFG0_CFG0_A0OUT = 2, /*!< A0OUT : Output is A0OUT */
CTIMER_OUTCFG0_CFG0_ONE = 1, /*!< ONE : Force output to 1. */
CTIMER_OUTCFG0_CFG0_ZERO = 0, /*!< ZERO : Force output to 0 */
} CTIMER_OUTCFG0_CFG0_Enum;
/* ======================================================== OUTCFG1 ======================================================== */
/* ============================================= CTIMER OUTCFG1 CFG19 [28..30] ============================================= */
typedef enum { /*!< CTIMER_OUTCFG1_CFG19 */
CTIMER_OUTCFG1_CFG19_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */
CTIMER_OUTCFG1_CFG19_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */
CTIMER_OUTCFG1_CFG19_B1OUT2 = 5, /*!< B1OUT2 : Output is B1OUT2. */
CTIMER_OUTCFG1_CFG19_B4OUT = 4, /*!< B4OUT : Output is B4OUT. */
CTIMER_OUTCFG1_CFG19_A2OUT = 3, /*!< A2OUT : Output is A2OUT. */
CTIMER_OUTCFG1_CFG19_B4OUT2 = 2, /*!< B4OUT2 : Output is B4OUT2 */
CTIMER_OUTCFG1_CFG19_ONE = 1, /*!< ONE : Force output to 1. */
CTIMER_OUTCFG1_CFG19_ZERO = 0, /*!< ZERO : Force output to 0 */
} CTIMER_OUTCFG1_CFG19_Enum;
/* ============================================= CTIMER OUTCFG1 CFG18 [25..27] ============================================= */
typedef enum { /*!< CTIMER_OUTCFG1_CFG18 */
CTIMER_OUTCFG1_CFG18_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */
CTIMER_OUTCFG1_CFG18_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */
CTIMER_OUTCFG1_CFG18_A3OUT2 = 5, /*!< A3OUT2 : Output is A3OUT2. */
CTIMER_OUTCFG1_CFG18_A0OUT = 4, /*!< A0OUT : Output is A0OUT. */
CTIMER_OUTCFG1_CFG18_B0OUT = 3, /*!< B0OUT : Output is B0OUT. */
CTIMER_OUTCFG1_CFG18_B4OUT = 2, /*!< B4OUT : Output is B4OUT */
CTIMER_OUTCFG1_CFG18_ONE = 1, /*!< ONE : Force output to 1. */
CTIMER_OUTCFG1_CFG18_ZERO = 0, /*!< ZERO : Force output to 0 */
} CTIMER_OUTCFG1_CFG18_Enum;
/* ============================================= CTIMER OUTCFG1 CFG17 [22..24] ============================================= */
typedef enum { /*!< CTIMER_OUTCFG1_CFG17 */
CTIMER_OUTCFG1_CFG17_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */
CTIMER_OUTCFG1_CFG17_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */
CTIMER_OUTCFG1_CFG17_A1OUT2 = 5, /*!< A1OUT2 : Output is A1OUT2. */
CTIMER_OUTCFG1_CFG17_A4OUT = 4, /*!< A4OUT : Output is A4OUT. */
CTIMER_OUTCFG1_CFG17_B7OUT = 3, /*!< B7OUT : Output is B7OUT. */
CTIMER_OUTCFG1_CFG17_A4OUT2 = 2, /*!< A4OUT2 : Output is A4OUT2 */
CTIMER_OUTCFG1_CFG17_ONE = 1, /*!< ONE : Force output to 1. */
CTIMER_OUTCFG1_CFG17_ZERO = 0, /*!< ZERO : Force output to 0 */
} CTIMER_OUTCFG1_CFG17_Enum;
/* ============================================= CTIMER OUTCFG1 CFG16 [19..21] ============================================= */
typedef enum { /*!< CTIMER_OUTCFG1_CFG16 */
CTIMER_OUTCFG1_CFG16_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */
CTIMER_OUTCFG1_CFG16_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */
CTIMER_OUTCFG1_CFG16_B3OUT2 = 5, /*!< B3OUT2 : Output is B3OUT2. */
CTIMER_OUTCFG1_CFG16_A0OUT2 = 4, /*!< A0OUT2 : Output is A0OUT2. */
CTIMER_OUTCFG1_CFG16_A0OUT = 3, /*!< A0OUT : Output is A0OUT. */
CTIMER_OUTCFG1_CFG16_A4OUT = 2, /*!< A4OUT : Output is A4OUT */
CTIMER_OUTCFG1_CFG16_ONE = 1, /*!< ONE : Force output to 1. */
CTIMER_OUTCFG1_CFG16_ZERO = 0, /*!< ZERO : Force output to 0 */
} CTIMER_OUTCFG1_CFG16_Enum;
/* ============================================= CTIMER OUTCFG1 CFG15 [16..18] ============================================= */
typedef enum { /*!< CTIMER_OUTCFG1_CFG15 */
CTIMER_OUTCFG1_CFG15_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */
CTIMER_OUTCFG1_CFG15_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */
CTIMER_OUTCFG1_CFG15_A4OUT2 = 5, /*!< A4OUT2 : Output is A4OUT2. */
CTIMER_OUTCFG1_CFG15_A7OUT = 4, /*!< A7OUT : Output is A7OUT. */
CTIMER_OUTCFG1_CFG15_B3OUT = 3, /*!< B3OUT : Output is B3OUT. */
CTIMER_OUTCFG1_CFG15_B3OUT2 = 2, /*!< B3OUT2 : Output is B3OUT2 */
CTIMER_OUTCFG1_CFG15_ONE = 1, /*!< ONE : Force output to 1. */
CTIMER_OUTCFG1_CFG15_ZERO = 0, /*!< ZERO : Force output to 0 */
} CTIMER_OUTCFG1_CFG15_Enum;
/* ============================================= CTIMER OUTCFG1 CFG14 [12..14] ============================================= */
typedef enum { /*!< CTIMER_OUTCFG1_CFG14 */
CTIMER_OUTCFG1_CFG14_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */
CTIMER_OUTCFG1_CFG14_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */
CTIMER_OUTCFG1_CFG14_A7OUT = 5, /*!< A7OUT : Output is A7OUT. */
CTIMER_OUTCFG1_CFG14_B7OUT2 = 4, /*!< B7OUT2 : Output is B7OUT2. */
CTIMER_OUTCFG1_CFG14_B1OUT = 3, /*!< B1OUT : Output is B1OUT. */
CTIMER_OUTCFG1_CFG14_B3OUT = 2, /*!< B3OUT : Output is B3OUT */
CTIMER_OUTCFG1_CFG14_ONE = 1, /*!< ONE : Force output to 1. */
CTIMER_OUTCFG1_CFG14_ZERO = 0, /*!< ZERO : Force output to 0 */
} CTIMER_OUTCFG1_CFG14_Enum;
/* ============================================= CTIMER OUTCFG1 CFG13 [9..11] ============================================== */
typedef enum { /*!< CTIMER_OUTCFG1_CFG13 */
CTIMER_OUTCFG1_CFG13_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */
CTIMER_OUTCFG1_CFG13_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */
CTIMER_OUTCFG1_CFG13_B4OUT2 = 5, /*!< B4OUT2 : Output is B4OUT2. */
CTIMER_OUTCFG1_CFG13_A6OUT = 4, /*!< A6OUT : Output is A6OUT. */
CTIMER_OUTCFG1_CFG13_A3OUT = 3, /*!< A3OUT : Output is A3OUT. */
CTIMER_OUTCFG1_CFG13_A3OUT2 = 2, /*!< A3OUT2 : Output is A3OUT2 */
CTIMER_OUTCFG1_CFG13_ONE = 1, /*!< ONE : Force output to 1. */
CTIMER_OUTCFG1_CFG13_ZERO = 0, /*!< ZERO : Force output to 0 */
} CTIMER_OUTCFG1_CFG13_Enum;
/* ============================================== CTIMER OUTCFG1 CFG12 [6..8] ============================================== */
typedef enum { /*!< CTIMER_OUTCFG1_CFG12 */
CTIMER_OUTCFG1_CFG12_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */
CTIMER_OUTCFG1_CFG12_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */
CTIMER_OUTCFG1_CFG12_B6OUT2 = 5, /*!< B6OUT2 : Output is B6OUT2. */
CTIMER_OUTCFG1_CFG12_B0OUT2 = 4, /*!< B0OUT2 : Output is B0OUT2. */
CTIMER_OUTCFG1_CFG12_B1OUT = 3, /*!< B1OUT : Output is B1OUT. */
CTIMER_OUTCFG1_CFG12_A3OUT = 2, /*!< A3OUT : Output is A3OUT */
CTIMER_OUTCFG1_CFG12_ONE = 1, /*!< ONE : Force output to 1. */
CTIMER_OUTCFG1_CFG12_ZERO = 0, /*!< ZERO : Force output to 0 */
} CTIMER_OUTCFG1_CFG12_Enum;
/* ============================================== CTIMER OUTCFG1 CFG11 [3..5] ============================================== */
typedef enum { /*!< CTIMER_OUTCFG1_CFG11 */
CTIMER_OUTCFG1_CFG11_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */
CTIMER_OUTCFG1_CFG11_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */
CTIMER_OUTCFG1_CFG11_B5OUT2 = 5, /*!< B5OUT2 : Output is B5OUT2. */
CTIMER_OUTCFG1_CFG11_B4OUT = 4, /*!< B4OUT : Output is B4OUT. */
CTIMER_OUTCFG1_CFG11_B2OUT = 3, /*!< B2OUT : Output is B2OUT. */
CTIMER_OUTCFG1_CFG11_B2OUT2 = 2, /*!< B2OUT2 : Output is B2OUT2 */
CTIMER_OUTCFG1_CFG11_ONE = 1, /*!< ONE : Force output to 1. */
CTIMER_OUTCFG1_CFG11_ZERO = 0, /*!< ZERO : Force output to 0 */
} CTIMER_OUTCFG1_CFG11_Enum;
/* ============================================== CTIMER OUTCFG1 CFG10 [0..2] ============================================== */
typedef enum { /*!< CTIMER_OUTCFG1_CFG10 */
CTIMER_OUTCFG1_CFG10_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */
CTIMER_OUTCFG1_CFG10_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */
CTIMER_OUTCFG1_CFG10_A6OUT = 5, /*!< A6OUT : Output is A6OUT. */
CTIMER_OUTCFG1_CFG10_B4OUT2 = 4, /*!< B4OUT2 : Output is B4OUT2. */
CTIMER_OUTCFG1_CFG10_B3OUT2 = 3, /*!< B3OUT2 : Output is B3OUT2. */
CTIMER_OUTCFG1_CFG10_B2OUT = 2, /*!< B2OUT : Output is B2OUT */
CTIMER_OUTCFG1_CFG10_ONE = 1, /*!< ONE : Force output to 1. */
CTIMER_OUTCFG1_CFG10_ZERO = 0, /*!< ZERO : Force output to 0 */
} CTIMER_OUTCFG1_CFG10_Enum;
/* ======================================================== OUTCFG2 ======================================================== */
/* ============================================= CTIMER OUTCFG2 CFG29 [28..30] ============================================= */
typedef enum { /*!< CTIMER_OUTCFG2_CFG29 */
CTIMER_OUTCFG2_CFG29_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */
CTIMER_OUTCFG2_CFG29_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */
CTIMER_OUTCFG2_CFG29_A3OUT2 = 5, /*!< A3OUT2 : Output is A3OUT2. */
CTIMER_OUTCFG2_CFG29_A7OUT = 4, /*!< A7OUT : Output is A7OUT. */
CTIMER_OUTCFG2_CFG29_A1OUT = 3, /*!< A1OUT : Output is A1OUT. */
CTIMER_OUTCFG2_CFG29_B5OUT2 = 2, /*!< B5OUT2 : Output is B5OUT2 */
CTIMER_OUTCFG2_CFG29_ONE = 1, /*!< ONE : Force output to 1. */
CTIMER_OUTCFG2_CFG29_ZERO = 0, /*!< ZERO : Force output to 0 */
} CTIMER_OUTCFG2_CFG29_Enum;
/* ============================================= CTIMER OUTCFG2 CFG28 [25..27] ============================================= */
typedef enum { /*!< CTIMER_OUTCFG2_CFG28 */
CTIMER_OUTCFG2_CFG28_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */
CTIMER_OUTCFG2_CFG28_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */
CTIMER_OUTCFG2_CFG28_B0OUT2 = 5, /*!< B0OUT2 : Output is B0OUT2. */
CTIMER_OUTCFG2_CFG28_A5OUT2 = 4, /*!< A5OUT2 : Output is A5OUT2. */
CTIMER_OUTCFG2_CFG28_A3OUT = 3, /*!< A3OUT : Output is A3OUT. */
CTIMER_OUTCFG2_CFG28_A7OUT = 2, /*!< A7OUT : Output is A7OUT */
CTIMER_OUTCFG2_CFG28_ONE = 1, /*!< ONE : Force output to 1. */
CTIMER_OUTCFG2_CFG28_ZERO = 0, /*!< ZERO : Force output to 0 */
} CTIMER_OUTCFG2_CFG28_Enum;
/* ============================================= CTIMER OUTCFG2 CFG27 [22..24] ============================================= */
typedef enum { /*!< CTIMER_OUTCFG2_CFG27 */
CTIMER_OUTCFG2_CFG27_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */
CTIMER_OUTCFG2_CFG27_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */
CTIMER_OUTCFG2_CFG27_B2OUT2 = 5, /*!< B2OUT2 : Output is B2OUT2. */
CTIMER_OUTCFG2_CFG27_B6OUT = 4, /*!< B6OUT : Output is B6OUT. */
CTIMER_OUTCFG2_CFG27_A1OUT = 3, /*!< A1OUT : Output is A1OUT. */
CTIMER_OUTCFG2_CFG27_B6OUT2 = 2, /*!< B6OUT2 : Output is B6OUT2 */
CTIMER_OUTCFG2_CFG27_ONE = 1, /*!< ONE : Force output to 1. */
CTIMER_OUTCFG2_CFG27_ZERO = 0, /*!< ZERO : Force output to 0 */
} CTIMER_OUTCFG2_CFG27_Enum;
/* ============================================= CTIMER OUTCFG2 CFG26 [19..21] ============================================= */
typedef enum { /*!< CTIMER_OUTCFG2_CFG26 */
CTIMER_OUTCFG2_CFG26_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */
CTIMER_OUTCFG2_CFG26_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */
CTIMER_OUTCFG2_CFG26_A1OUT2 = 5, /*!< A1OUT2 : Output is A1OUT2. */
CTIMER_OUTCFG2_CFG26_A5OUT = 4, /*!< A5OUT : Output is A5OUT. */
CTIMER_OUTCFG2_CFG26_B2OUT = 3, /*!< B2OUT : Output is B2OUT. */
CTIMER_OUTCFG2_CFG26_B6OUT = 2, /*!< B6OUT : Output is B6OUT */
CTIMER_OUTCFG2_CFG26_ONE = 1, /*!< ONE : Force output to 1. */
CTIMER_OUTCFG2_CFG26_ZERO = 0, /*!< ZERO : Force output to 0 */
} CTIMER_OUTCFG2_CFG26_Enum;
/* ============================================= CTIMER OUTCFG2 CFG25 [16..18] ============================================= */
typedef enum { /*!< CTIMER_OUTCFG2_CFG25 */
CTIMER_OUTCFG2_CFG25_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */
CTIMER_OUTCFG2_CFG25_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */
CTIMER_OUTCFG2_CFG25_A2OUT2 = 5, /*!< A2OUT2 : Output is A2OUT2. */
CTIMER_OUTCFG2_CFG25_A6OUT = 4, /*!< A6OUT : Output is A6OUT. */
CTIMER_OUTCFG2_CFG25_B2OUT = 3, /*!< B2OUT : Output is B2OUT. */
CTIMER_OUTCFG2_CFG25_B4OUT2 = 2, /*!< B4OUT2 : Output is B4OUT2 */
CTIMER_OUTCFG2_CFG25_ONE = 1, /*!< ONE : Force output to 1. */
CTIMER_OUTCFG2_CFG25_ZERO = 0, /*!< ZERO : Force output to 0 */
} CTIMER_OUTCFG2_CFG25_Enum;
/* ============================================= CTIMER OUTCFG2 CFG24 [12..14] ============================================= */
typedef enum { /*!< CTIMER_OUTCFG2_CFG24 */
CTIMER_OUTCFG2_CFG24_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */
CTIMER_OUTCFG2_CFG24_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */
CTIMER_OUTCFG2_CFG24_B1OUT2 = 5, /*!< B1OUT2 : Output is B1OUT2. */
CTIMER_OUTCFG2_CFG24_A1OUT = 4, /*!< A1OUT : Output is A1OUT. */
CTIMER_OUTCFG2_CFG24_A2OUT = 3, /*!< A2OUT : Output is A2OUT. */
CTIMER_OUTCFG2_CFG24_A6OUT = 2, /*!< A6OUT : Output is A6OUT */
CTIMER_OUTCFG2_CFG24_ONE = 1, /*!< ONE : Force output to 1. */
CTIMER_OUTCFG2_CFG24_ZERO = 0, /*!< ZERO : Force output to 0 */
} CTIMER_OUTCFG2_CFG24_Enum;
/* ============================================= CTIMER OUTCFG2 CFG23 [9..11] ============================================== */
typedef enum { /*!< CTIMER_OUTCFG2_CFG23 */
CTIMER_OUTCFG2_CFG23_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */
CTIMER_OUTCFG2_CFG23_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */
CTIMER_OUTCFG2_CFG23_B0OUT2 = 5, /*!< B0OUT2 : Output is B0OUT2. */
CTIMER_OUTCFG2_CFG23_A5OUT = 4, /*!< A5OUT : Output is A5OUT. */
CTIMER_OUTCFG2_CFG23_A7OUT = 3, /*!< A7OUT : Output is A7OUT. */
CTIMER_OUTCFG2_CFG23_B5OUT2 = 2, /*!< B5OUT2 : Output is B5OUT2 */
CTIMER_OUTCFG2_CFG23_ONE = 1, /*!< ONE : Force output to 1. */
CTIMER_OUTCFG2_CFG23_ZERO = 0, /*!< ZERO : Force output to 0 */
} CTIMER_OUTCFG2_CFG23_Enum;
/* ============================================== CTIMER OUTCFG2 CFG22 [6..8] ============================================== */
typedef enum { /*!< CTIMER_OUTCFG2_CFG22 */
CTIMER_OUTCFG2_CFG22_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */
CTIMER_OUTCFG2_CFG22_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */
CTIMER_OUTCFG2_CFG22_A2OUT2 = 5, /*!< A2OUT2 : Output is A2OUT2. */
CTIMER_OUTCFG2_CFG22_A1OUT = 4, /*!< A1OUT : Output is A1OUT. */
CTIMER_OUTCFG2_CFG22_A6OUT = 3, /*!< A6OUT : Output is A6OUT. */
CTIMER_OUTCFG2_CFG22_B5OUT = 2, /*!< B5OUT : Output is B5OUT */
CTIMER_OUTCFG2_CFG22_ONE = 1, /*!< ONE : Force output to 1. */
CTIMER_OUTCFG2_CFG22_ZERO = 0, /*!< ZERO : Force output to 0 */
} CTIMER_OUTCFG2_CFG22_Enum;
/* ============================================== CTIMER OUTCFG2 CFG21 [3..5] ============================================== */
typedef enum { /*!< CTIMER_OUTCFG2_CFG21 */
CTIMER_OUTCFG2_CFG21_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */
CTIMER_OUTCFG2_CFG21_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */
CTIMER_OUTCFG2_CFG21_A0OUT2 = 5, /*!< A0OUT2 : Output is A0OUT2. */
CTIMER_OUTCFG2_CFG21_B5OUT = 4, /*!< B5OUT : Output is B5OUT. */
CTIMER_OUTCFG2_CFG21_A1OUT = 3, /*!< A1OUT : Output is A1OUT. */
CTIMER_OUTCFG2_CFG21_A5OUT2 = 2, /*!< A5OUT2 : Output is A5OUT2 */
CTIMER_OUTCFG2_CFG21_ONE = 1, /*!< ONE : Force output to 1. */
CTIMER_OUTCFG2_CFG21_ZERO = 0, /*!< ZERO : Force output to 0 */
} CTIMER_OUTCFG2_CFG21_Enum;
/* ============================================== CTIMER OUTCFG2 CFG20 [0..2] ============================================== */
typedef enum { /*!< CTIMER_OUTCFG2_CFG20 */
CTIMER_OUTCFG2_CFG20_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */
CTIMER_OUTCFG2_CFG20_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */
CTIMER_OUTCFG2_CFG20_B2OUT2 = 5, /*!< B2OUT2 : Output is B2OUT2. */
CTIMER_OUTCFG2_CFG20_A1OUT2 = 4, /*!< A1OUT2 : Output is A1OUT2. */
CTIMER_OUTCFG2_CFG20_A1OUT = 3, /*!< A1OUT : Output is A1OUT. */
CTIMER_OUTCFG2_CFG20_A5OUT = 2, /*!< A5OUT : Output is A5OUT */
CTIMER_OUTCFG2_CFG20_ONE = 1, /*!< ONE : Force output to 1. */
CTIMER_OUTCFG2_CFG20_ZERO = 0, /*!< ZERO : Force output to 0 */
} CTIMER_OUTCFG2_CFG20_Enum;
/* ======================================================== OUTCFG3 ======================================================== */
/* ============================================== CTIMER OUTCFG3 CFG31 [3..5] ============================================== */
typedef enum { /*!< CTIMER_OUTCFG3_CFG31 */
CTIMER_OUTCFG3_CFG31_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */
CTIMER_OUTCFG3_CFG31_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */
CTIMER_OUTCFG3_CFG31_B3OUT2 = 5, /*!< B3OUT2 : Output is B3OUT2. */
CTIMER_OUTCFG3_CFG31_B7OUT = 4, /*!< B7OUT : Output is B7OUT. */
CTIMER_OUTCFG3_CFG31_A6OUT = 3, /*!< A6OUT : Output is A6OUT. */
CTIMER_OUTCFG3_CFG31_B7OUT2 = 2, /*!< B7OUT2 : Output is B7OUT2 */
CTIMER_OUTCFG3_CFG31_ONE = 1, /*!< ONE : Force output to 1. */
CTIMER_OUTCFG3_CFG31_ZERO = 0, /*!< ZERO : Force output to 0 */
} CTIMER_OUTCFG3_CFG31_Enum;
/* ============================================== CTIMER OUTCFG3 CFG30 [0..2] ============================================== */
typedef enum { /*!< CTIMER_OUTCFG3_CFG30 */
CTIMER_OUTCFG3_CFG30_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */
CTIMER_OUTCFG3_CFG30_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */
CTIMER_OUTCFG3_CFG30_A0OUT2 = 5, /*!< A0OUT2 : Output is A0OUT2. */
CTIMER_OUTCFG3_CFG30_A4OUT2 = 4, /*!< A4OUT2 : Output is A4OUT2. */
CTIMER_OUTCFG3_CFG30_B3OUT = 3, /*!< B3OUT : Output is B3OUT. */
CTIMER_OUTCFG3_CFG30_B7OUT = 2, /*!< B7OUT : Output is B7OUT */
CTIMER_OUTCFG3_CFG30_ONE = 1, /*!< ONE : Force output to 1. */
CTIMER_OUTCFG3_CFG30_ZERO = 0, /*!< ZERO : Force output to 0 */
} CTIMER_OUTCFG3_CFG30_Enum;
/* ========================================================= INCFG ========================================================= */
/* ============================================== CTIMER INCFG CFGB7 [15..15] ============================================== */
typedef enum { /*!< CTIMER_INCFG_CFGB7 */
CTIMER_INCFG_CFGB7_CT31 = 1, /*!< CT31 : Input is CT31 */
CTIMER_INCFG_CFGB7_CT30 = 0, /*!< CT30 : Input is CT30 */
} CTIMER_INCFG_CFGB7_Enum;
/* ============================================== CTIMER INCFG CFGA7 [14..14] ============================================== */
typedef enum { /*!< CTIMER_INCFG_CFGA7 */
CTIMER_INCFG_CFGA7_CT29 = 1, /*!< CT29 : Input is CT29 */
CTIMER_INCFG_CFGA7_CT28 = 0, /*!< CT28 : Input is CT28 */
} CTIMER_INCFG_CFGA7_Enum;
/* ============================================== CTIMER INCFG CFGB6 [13..13] ============================================== */
typedef enum { /*!< CTIMER_INCFG_CFGB6 */
CTIMER_INCFG_CFGB6_CT27 = 1, /*!< CT27 : Input is CT27 */
CTIMER_INCFG_CFGB6_CT26 = 0, /*!< CT26 : Input is CT26 */
} CTIMER_INCFG_CFGB6_Enum;
/* ============================================== CTIMER INCFG CFGA6 [12..12] ============================================== */
typedef enum { /*!< CTIMER_INCFG_CFGA6 */
CTIMER_INCFG_CFGA6_CT25 = 1, /*!< CT25 : Input is CT25 */
CTIMER_INCFG_CFGA6_CT24 = 0, /*!< CT24 : Input is CT24 */
} CTIMER_INCFG_CFGA6_Enum;
/* ============================================== CTIMER INCFG CFGB5 [11..11] ============================================== */
typedef enum { /*!< CTIMER_INCFG_CFGB5 */
CTIMER_INCFG_CFGB5_CT23 = 1, /*!< CT23 : Input is CT23 */
CTIMER_INCFG_CFGB5_CT22 = 0, /*!< CT22 : Input is CT22 */
} CTIMER_INCFG_CFGB5_Enum;
/* ============================================== CTIMER INCFG CFGA5 [10..10] ============================================== */
typedef enum { /*!< CTIMER_INCFG_CFGA5 */
CTIMER_INCFG_CFGA5_CT21 = 1, /*!< CT21 : Input is CT21 */
CTIMER_INCFG_CFGA5_CT20 = 0, /*!< CT20 : Input is CT20 */
} CTIMER_INCFG_CFGA5_Enum;
/* =============================================== CTIMER INCFG CFGB4 [9..9] =============================================== */
typedef enum { /*!< CTIMER_INCFG_CFGB4 */
CTIMER_INCFG_CFGB4_CT19 = 1, /*!< CT19 : Input is CT19 */
CTIMER_INCFG_CFGB4_CT18 = 0, /*!< CT18 : Input is CT18 */
} CTIMER_INCFG_CFGB4_Enum;
/* =============================================== CTIMER INCFG CFGA4 [8..8] =============================================== */
typedef enum { /*!< CTIMER_INCFG_CFGA4 */
CTIMER_INCFG_CFGA4_CT17 = 1, /*!< CT17 : Input is CT17 */
CTIMER_INCFG_CFGA4_CT16 = 0, /*!< CT16 : Input is CT16 */
} CTIMER_INCFG_CFGA4_Enum;
/* =============================================== CTIMER INCFG CFGB3 [7..7] =============================================== */
typedef enum { /*!< CTIMER_INCFG_CFGB3 */
CTIMER_INCFG_CFGB3_CT15 = 1, /*!< CT15 : Input is CT15 */
CTIMER_INCFG_CFGB3_CT14 = 0, /*!< CT14 : Input is CT14 */
} CTIMER_INCFG_CFGB3_Enum;
/* =============================================== CTIMER INCFG CFGA3 [6..6] =============================================== */
typedef enum { /*!< CTIMER_INCFG_CFGA3 */
CTIMER_INCFG_CFGA3_CT13 = 1, /*!< CT13 : Input is CT13 */
CTIMER_INCFG_CFGA3_CT12 = 0, /*!< CT12 : Input is CT12 */
} CTIMER_INCFG_CFGA3_Enum;
/* =============================================== CTIMER INCFG CFGB2 [5..5] =============================================== */
typedef enum { /*!< CTIMER_INCFG_CFGB2 */
CTIMER_INCFG_CFGB2_CT11 = 1, /*!< CT11 : Input is CT11 */
CTIMER_INCFG_CFGB2_CT10 = 0, /*!< CT10 : Input is CT10 */
} CTIMER_INCFG_CFGB2_Enum;
/* =============================================== CTIMER INCFG CFGA2 [4..4] =============================================== */
typedef enum { /*!< CTIMER_INCFG_CFGA2 */
CTIMER_INCFG_CFGA2_CT9 = 1, /*!< CT9 : Input is CT9 */
CTIMER_INCFG_CFGA2_CT8 = 0, /*!< CT8 : Input is CT8 */
} CTIMER_INCFG_CFGA2_Enum;
/* =============================================== CTIMER INCFG CFGB1 [3..3] =============================================== */
typedef enum { /*!< CTIMER_INCFG_CFGB1 */
CTIMER_INCFG_CFGB1_CT7 = 1, /*!< CT7 : Input is CT7 */
CTIMER_INCFG_CFGB1_CT6 = 0, /*!< CT6 : Input is CT6 */
} CTIMER_INCFG_CFGB1_Enum;
/* =============================================== CTIMER INCFG CFGA1 [2..2] =============================================== */
typedef enum { /*!< CTIMER_INCFG_CFGA1 */
CTIMER_INCFG_CFGA1_CT5 = 1, /*!< CT5 : Input is CT5 */
CTIMER_INCFG_CFGA1_CT4 = 0, /*!< CT4 : Input is CT4 */
} CTIMER_INCFG_CFGA1_Enum;
/* =============================================== CTIMER INCFG CFGB0 [1..1] =============================================== */
typedef enum { /*!< CTIMER_INCFG_CFGB0 */
CTIMER_INCFG_CFGB0_CT3 = 1, /*!< CT3 : Input is CT3 */
CTIMER_INCFG_CFGB0_CT2 = 0, /*!< CT2 : Input is CT2 */
} CTIMER_INCFG_CFGB0_Enum;
/* =============================================== CTIMER INCFG CFGA0 [0..0] =============================================== */
typedef enum { /*!< CTIMER_INCFG_CFGA0 */
CTIMER_INCFG_CFGA0_CT1 = 1, /*!< CT1 : Input is CT1 */
CTIMER_INCFG_CFGA0_CT0 = 0, /*!< CT0 : Input is CT0 */
} CTIMER_INCFG_CFGA0_Enum;
/* ========================================================= STCFG ========================================================= */
/* ============================================= CTIMER STCFG FREEZE [31..31] ============================================== */
typedef enum { /*!< CTIMER_STCFG_FREEZE */
CTIMER_STCFG_FREEZE_THAW = 0, /*!< THAW : Let the COUNTER register run on its input clock. */
CTIMER_STCFG_FREEZE_FREEZE = 1, /*!< FREEZE : Stop the COUNTER register for loading. */
} CTIMER_STCFG_FREEZE_Enum;
/* ============================================== CTIMER STCFG CLEAR [30..30] ============================================== */
typedef enum { /*!< CTIMER_STCFG_CLEAR */
CTIMER_STCFG_CLEAR_RUN = 0, /*!< RUN : Let the COUNTER register run on its input clock. */
CTIMER_STCFG_CLEAR_CLEAR = 1, /*!< CLEAR : Stop the COUNTER register for loading. */
} CTIMER_STCFG_CLEAR_Enum;
/* ========================================== CTIMER STCFG COMPARE_H_EN [15..15] =========================================== */
typedef enum { /*!< CTIMER_STCFG_COMPARE_H_EN */
CTIMER_STCFG_COMPARE_H_EN_DISABLE = 0, /*!< DISABLE : Compare H disabled. */
CTIMER_STCFG_COMPARE_H_EN_ENABLE = 1, /*!< ENABLE : Compare H enabled. */
} CTIMER_STCFG_COMPARE_H_EN_Enum;
/* ========================================== CTIMER STCFG COMPARE_G_EN [14..14] =========================================== */
typedef enum { /*!< CTIMER_STCFG_COMPARE_G_EN */
CTIMER_STCFG_COMPARE_G_EN_DISABLE = 0, /*!< DISABLE : Compare G disabled. */
CTIMER_STCFG_COMPARE_G_EN_ENABLE = 1, /*!< ENABLE : Compare G enabled. */
} CTIMER_STCFG_COMPARE_G_EN_Enum;
/* ========================================== CTIMER STCFG COMPARE_F_EN [13..13] =========================================== */
typedef enum { /*!< CTIMER_STCFG_COMPARE_F_EN */
CTIMER_STCFG_COMPARE_F_EN_DISABLE = 0, /*!< DISABLE : Compare F disabled. */
CTIMER_STCFG_COMPARE_F_EN_ENABLE = 1, /*!< ENABLE : Compare F enabled. */
} CTIMER_STCFG_COMPARE_F_EN_Enum;
/* ========================================== CTIMER STCFG COMPARE_E_EN [12..12] =========================================== */
typedef enum { /*!< CTIMER_STCFG_COMPARE_E_EN */
CTIMER_STCFG_COMPARE_E_EN_DISABLE = 0, /*!< DISABLE : Compare E disabled. */
CTIMER_STCFG_COMPARE_E_EN_ENABLE = 1, /*!< ENABLE : Compare E enabled. */
} CTIMER_STCFG_COMPARE_E_EN_Enum;
/* ========================================== CTIMER STCFG COMPARE_D_EN [11..11] =========================================== */
typedef enum { /*!< CTIMER_STCFG_COMPARE_D_EN */
CTIMER_STCFG_COMPARE_D_EN_DISABLE = 0, /*!< DISABLE : Compare D disabled. */
CTIMER_STCFG_COMPARE_D_EN_ENABLE = 1, /*!< ENABLE : Compare D enabled. */
} CTIMER_STCFG_COMPARE_D_EN_Enum;
/* ========================================== CTIMER STCFG COMPARE_C_EN [10..10] =========================================== */
typedef enum { /*!< CTIMER_STCFG_COMPARE_C_EN */
CTIMER_STCFG_COMPARE_C_EN_DISABLE = 0, /*!< DISABLE : Compare C disabled. */
CTIMER_STCFG_COMPARE_C_EN_ENABLE = 1, /*!< ENABLE : Compare C enabled. */
} CTIMER_STCFG_COMPARE_C_EN_Enum;
/* =========================================== CTIMER STCFG COMPARE_B_EN [9..9] ============================================ */
typedef enum { /*!< CTIMER_STCFG_COMPARE_B_EN */
CTIMER_STCFG_COMPARE_B_EN_DISABLE = 0, /*!< DISABLE : Compare B disabled. */
CTIMER_STCFG_COMPARE_B_EN_ENABLE = 1, /*!< ENABLE : Compare B enabled. */
} CTIMER_STCFG_COMPARE_B_EN_Enum;
/* =========================================== CTIMER STCFG COMPARE_A_EN [8..8] ============================================ */
typedef enum { /*!< CTIMER_STCFG_COMPARE_A_EN */
CTIMER_STCFG_COMPARE_A_EN_DISABLE = 0, /*!< DISABLE : Compare A disabled. */
CTIMER_STCFG_COMPARE_A_EN_ENABLE = 1, /*!< ENABLE : Compare A enabled. */
} CTIMER_STCFG_COMPARE_A_EN_Enum;
/* ============================================== CTIMER STCFG CLKSEL [0..3] =============================================== */
typedef enum { /*!< CTIMER_STCFG_CLKSEL */
CTIMER_STCFG_CLKSEL_NOCLK = 0, /*!< NOCLK : No clock enabled. */
CTIMER_STCFG_CLKSEL_HFRC_DIV16 = 1, /*!< HFRC_DIV16 : 3MHz from the HFRC clock divider. */
CTIMER_STCFG_CLKSEL_HFRC_DIV256 = 2, /*!< HFRC_DIV256 : 187.5KHz from the HFRC clock divider. */
CTIMER_STCFG_CLKSEL_XTAL_DIV1 = 3, /*!< XTAL_DIV1 : 32768Hz from the crystal oscillator. */
CTIMER_STCFG_CLKSEL_XTAL_DIV2 = 4, /*!< XTAL_DIV2 : 16384Hz from the crystal oscillator. */
CTIMER_STCFG_CLKSEL_XTAL_DIV32 = 5, /*!< XTAL_DIV32 : 1024Hz from the crystal oscillator. */
CTIMER_STCFG_CLKSEL_LFRC_DIV1 = 6, /*!< LFRC_DIV1 : Approximately 1KHz from the LFRC oscillator (uncalibrated). */
CTIMER_STCFG_CLKSEL_CTIMER0A = 7, /*!< CTIMER0A : Use CTIMER 0 section A as a prescaler for the clock
source. */
CTIMER_STCFG_CLKSEL_CTIMER0B = 8, /*!< CTIMER0B : Use CTIMER 0 section B (or A and B linked together)
as a prescaler for the clock source. */
} CTIMER_STCFG_CLKSEL_Enum;
/* ========================================================= STTMR ========================================================= */
/* ==================================================== CAPTURECONTROL ===================================================== */
/* ========================================= CTIMER CAPTURECONTROL CAPTURE3 [3..3] ========================================= */
typedef enum { /*!< CTIMER_CAPTURECONTROL_CAPTURE3 */
CTIMER_CAPTURECONTROL_CAPTURE3_DISABLE = 0, /*!< DISABLE : Capture function disabled. */
CTIMER_CAPTURECONTROL_CAPTURE3_ENABLE = 1, /*!< ENABLE : Capture function enabled. */
} CTIMER_CAPTURECONTROL_CAPTURE3_Enum;
/* ========================================= CTIMER CAPTURECONTROL CAPTURE2 [2..2] ========================================= */
typedef enum { /*!< CTIMER_CAPTURECONTROL_CAPTURE2 */
CTIMER_CAPTURECONTROL_CAPTURE2_DISABLE = 0, /*!< DISABLE : Capture function disabled. */
CTIMER_CAPTURECONTROL_CAPTURE2_ENABLE = 1, /*!< ENABLE : Capture function enabled. */
} CTIMER_CAPTURECONTROL_CAPTURE2_Enum;
/* ========================================= CTIMER CAPTURECONTROL CAPTURE1 [1..1] ========================================= */
typedef enum { /*!< CTIMER_CAPTURECONTROL_CAPTURE1 */
CTIMER_CAPTURECONTROL_CAPTURE1_DISABLE = 0, /*!< DISABLE : Capture function disabled. */
CTIMER_CAPTURECONTROL_CAPTURE1_ENABLE = 1, /*!< ENABLE : Capture function enabled. */
} CTIMER_CAPTURECONTROL_CAPTURE1_Enum;
/* ========================================= CTIMER CAPTURECONTROL CAPTURE0 [0..0] ========================================= */
typedef enum { /*!< CTIMER_CAPTURECONTROL_CAPTURE0 */
CTIMER_CAPTURECONTROL_CAPTURE0_DISABLE = 0, /*!< DISABLE : Capture function disabled. */
CTIMER_CAPTURECONTROL_CAPTURE0_ENABLE = 1, /*!< ENABLE : Capture function enabled. */
} CTIMER_CAPTURECONTROL_CAPTURE0_Enum;
/* ======================================================== SCMPR0 ========================================================= */
/* ======================================================== SCMPR1 ========================================================= */
/* ======================================================== SCMPR2 ========================================================= */
/* ======================================================== SCMPR3 ========================================================= */
/* ======================================================== SCMPR4 ========================================================= */
/* ======================================================== SCMPR5 ========================================================= */
/* ======================================================== SCMPR6 ========================================================= */
/* ======================================================== SCMPR7 ========================================================= */
/* ======================================================== SCAPT0 ========================================================= */
/* ======================================================== SCAPT1 ========================================================= */
/* ======================================================== SCAPT2 ========================================================= */
/* ======================================================== SCAPT3 ========================================================= */
/* ========================================================= SNVR0 ========================================================= */
/* ========================================================= SNVR1 ========================================================= */
/* ========================================================= SNVR2 ========================================================= */
/* ========================================================= SNVR3 ========================================================= */
/* ========================================================= INTEN ========================================================= */
/* ======================================================== INTSTAT ======================================================== */
/* ======================================================== INTCLR ========================================================= */
/* ======================================================== INTSET ========================================================= */
/* ======================================================= STMINTEN ======================================================== */
/* =========================================== CTIMER STMINTEN CAPTURED [12..12] =========================================== */
typedef enum { /*!< CTIMER_STMINTEN_CAPTURED */
CTIMER_STMINTEN_CAPTURED_CAPD_INT = 1, /*!< CAPD_INT : Capture D interrupt status bit was set. */
} CTIMER_STMINTEN_CAPTURED_Enum;
/* =========================================== CTIMER STMINTEN CAPTUREC [11..11] =========================================== */
typedef enum { /*!< CTIMER_STMINTEN_CAPTUREC */
CTIMER_STMINTEN_CAPTUREC_CAPC_INT = 1, /*!< CAPC_INT : CAPTURE C interrupt status bit was set. */
} CTIMER_STMINTEN_CAPTUREC_Enum;
/* =========================================== CTIMER STMINTEN CAPTUREB [10..10] =========================================== */
typedef enum { /*!< CTIMER_STMINTEN_CAPTUREB */
CTIMER_STMINTEN_CAPTUREB_CAPB_INT = 1, /*!< CAPB_INT : CAPTURE B interrupt status bit was set. */
} CTIMER_STMINTEN_CAPTUREB_Enum;
/* ============================================ CTIMER STMINTEN CAPTUREA [9..9] ============================================ */
typedef enum { /*!< CTIMER_STMINTEN_CAPTUREA */
CTIMER_STMINTEN_CAPTUREA_CAPA_INT = 1, /*!< CAPA_INT : CAPTURE A interrupt status bit was set. */
} CTIMER_STMINTEN_CAPTUREA_Enum;
/* ============================================ CTIMER STMINTEN OVERFLOW [8..8] ============================================ */
typedef enum { /*!< CTIMER_STMINTEN_OVERFLOW */
CTIMER_STMINTEN_OVERFLOW_OFLOW_INT = 1, /*!< OFLOW_INT : Overflow interrupt status bit was set. */
} CTIMER_STMINTEN_OVERFLOW_Enum;
/* ============================================ CTIMER STMINTEN COMPAREH [7..7] ============================================ */
typedef enum { /*!< CTIMER_STMINTEN_COMPAREH */
CTIMER_STMINTEN_COMPAREH_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */
} CTIMER_STMINTEN_COMPAREH_Enum;
/* ============================================ CTIMER STMINTEN COMPAREG [6..6] ============================================ */
typedef enum { /*!< CTIMER_STMINTEN_COMPAREG */
CTIMER_STMINTEN_COMPAREG_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */
} CTIMER_STMINTEN_COMPAREG_Enum;
/* ============================================ CTIMER STMINTEN COMPAREF [5..5] ============================================ */
typedef enum { /*!< CTIMER_STMINTEN_COMPAREF */
CTIMER_STMINTEN_COMPAREF_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */
} CTIMER_STMINTEN_COMPAREF_Enum;
/* ============================================ CTIMER STMINTEN COMPAREE [4..4] ============================================ */
typedef enum { /*!< CTIMER_STMINTEN_COMPAREE */
CTIMER_STMINTEN_COMPAREE_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */
} CTIMER_STMINTEN_COMPAREE_Enum;
/* ============================================ CTIMER STMINTEN COMPARED [3..3] ============================================ */
typedef enum { /*!< CTIMER_STMINTEN_COMPARED */
CTIMER_STMINTEN_COMPARED_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */
} CTIMER_STMINTEN_COMPARED_Enum;
/* ============================================ CTIMER STMINTEN COMPAREC [2..2] ============================================ */
typedef enum { /*!< CTIMER_STMINTEN_COMPAREC */
CTIMER_STMINTEN_COMPAREC_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */
} CTIMER_STMINTEN_COMPAREC_Enum;
/* ============================================ CTIMER STMINTEN COMPAREB [1..1] ============================================ */
typedef enum { /*!< CTIMER_STMINTEN_COMPAREB */
CTIMER_STMINTEN_COMPAREB_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */
} CTIMER_STMINTEN_COMPAREB_Enum;
/* ============================================ CTIMER STMINTEN COMPAREA [0..0] ============================================ */
typedef enum { /*!< CTIMER_STMINTEN_COMPAREA */
CTIMER_STMINTEN_COMPAREA_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */
} CTIMER_STMINTEN_COMPAREA_Enum;
/* ====================================================== STMINTSTAT ======================================================= */
/* ========================================== CTIMER STMINTSTAT CAPTURED [12..12] ========================================== */
typedef enum { /*!< CTIMER_STMINTSTAT_CAPTURED */
CTIMER_STMINTSTAT_CAPTURED_CAPD_INT = 1, /*!< CAPD_INT : Capture D interrupt status bit was set. */
} CTIMER_STMINTSTAT_CAPTURED_Enum;
/* ========================================== CTIMER STMINTSTAT CAPTUREC [11..11] ========================================== */
typedef enum { /*!< CTIMER_STMINTSTAT_CAPTUREC */
CTIMER_STMINTSTAT_CAPTUREC_CAPC_INT = 1, /*!< CAPC_INT : CAPTURE C interrupt status bit was set. */
} CTIMER_STMINTSTAT_CAPTUREC_Enum;
/* ========================================== CTIMER STMINTSTAT CAPTUREB [10..10] ========================================== */
typedef enum { /*!< CTIMER_STMINTSTAT_CAPTUREB */
CTIMER_STMINTSTAT_CAPTUREB_CAPB_INT = 1, /*!< CAPB_INT : CAPTURE B interrupt status bit was set. */
} CTIMER_STMINTSTAT_CAPTUREB_Enum;
/* =========================================== CTIMER STMINTSTAT CAPTUREA [9..9] =========================================== */
typedef enum { /*!< CTIMER_STMINTSTAT_CAPTUREA */
CTIMER_STMINTSTAT_CAPTUREA_CAPA_INT = 1, /*!< CAPA_INT : CAPTURE A interrupt status bit was set. */
} CTIMER_STMINTSTAT_CAPTUREA_Enum;
/* =========================================== CTIMER STMINTSTAT OVERFLOW [8..8] =========================================== */
typedef enum { /*!< CTIMER_STMINTSTAT_OVERFLOW */
CTIMER_STMINTSTAT_OVERFLOW_OFLOW_INT = 1, /*!< OFLOW_INT : Overflow interrupt status bit was set. */
} CTIMER_STMINTSTAT_OVERFLOW_Enum;
/* =========================================== CTIMER STMINTSTAT COMPAREH [7..7] =========================================== */
typedef enum { /*!< CTIMER_STMINTSTAT_COMPAREH */
CTIMER_STMINTSTAT_COMPAREH_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */
} CTIMER_STMINTSTAT_COMPAREH_Enum;
/* =========================================== CTIMER STMINTSTAT COMPAREG [6..6] =========================================== */
typedef enum { /*!< CTIMER_STMINTSTAT_COMPAREG */
CTIMER_STMINTSTAT_COMPAREG_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */
} CTIMER_STMINTSTAT_COMPAREG_Enum;
/* =========================================== CTIMER STMINTSTAT COMPAREF [5..5] =========================================== */
typedef enum { /*!< CTIMER_STMINTSTAT_COMPAREF */
CTIMER_STMINTSTAT_COMPAREF_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */
} CTIMER_STMINTSTAT_COMPAREF_Enum;
/* =========================================== CTIMER STMINTSTAT COMPAREE [4..4] =========================================== */
typedef enum { /*!< CTIMER_STMINTSTAT_COMPAREE */
CTIMER_STMINTSTAT_COMPAREE_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */
} CTIMER_STMINTSTAT_COMPAREE_Enum;
/* =========================================== CTIMER STMINTSTAT COMPARED [3..3] =========================================== */
typedef enum { /*!< CTIMER_STMINTSTAT_COMPARED */
CTIMER_STMINTSTAT_COMPARED_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */
} CTIMER_STMINTSTAT_COMPARED_Enum;
/* =========================================== CTIMER STMINTSTAT COMPAREC [2..2] =========================================== */
typedef enum { /*!< CTIMER_STMINTSTAT_COMPAREC */
CTIMER_STMINTSTAT_COMPAREC_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */
} CTIMER_STMINTSTAT_COMPAREC_Enum;
/* =========================================== CTIMER STMINTSTAT COMPAREB [1..1] =========================================== */
typedef enum { /*!< CTIMER_STMINTSTAT_COMPAREB */
CTIMER_STMINTSTAT_COMPAREB_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */
} CTIMER_STMINTSTAT_COMPAREB_Enum;
/* =========================================== CTIMER STMINTSTAT COMPAREA [0..0] =========================================== */
typedef enum { /*!< CTIMER_STMINTSTAT_COMPAREA */
CTIMER_STMINTSTAT_COMPAREA_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */
} CTIMER_STMINTSTAT_COMPAREA_Enum;
/* ======================================================= STMINTCLR ======================================================= */
/* ========================================== CTIMER STMINTCLR CAPTURED [12..12] =========================================== */
typedef enum { /*!< CTIMER_STMINTCLR_CAPTURED */
CTIMER_STMINTCLR_CAPTURED_CAPD_INT = 1, /*!< CAPD_INT : Capture D interrupt status bit was set. */
} CTIMER_STMINTCLR_CAPTURED_Enum;
/* ========================================== CTIMER STMINTCLR CAPTUREC [11..11] =========================================== */
typedef enum { /*!< CTIMER_STMINTCLR_CAPTUREC */
CTIMER_STMINTCLR_CAPTUREC_CAPC_INT = 1, /*!< CAPC_INT : CAPTURE C interrupt status bit was set. */
} CTIMER_STMINTCLR_CAPTUREC_Enum;
/* ========================================== CTIMER STMINTCLR CAPTUREB [10..10] =========================================== */
typedef enum { /*!< CTIMER_STMINTCLR_CAPTUREB */
CTIMER_STMINTCLR_CAPTUREB_CAPB_INT = 1, /*!< CAPB_INT : CAPTURE B interrupt status bit was set. */
} CTIMER_STMINTCLR_CAPTUREB_Enum;
/* =========================================== CTIMER STMINTCLR CAPTUREA [9..9] ============================================ */
typedef enum { /*!< CTIMER_STMINTCLR_CAPTUREA */
CTIMER_STMINTCLR_CAPTUREA_CAPA_INT = 1, /*!< CAPA_INT : CAPTURE A interrupt status bit was set. */
} CTIMER_STMINTCLR_CAPTUREA_Enum;
/* =========================================== CTIMER STMINTCLR OVERFLOW [8..8] ============================================ */
typedef enum { /*!< CTIMER_STMINTCLR_OVERFLOW */
CTIMER_STMINTCLR_OVERFLOW_OFLOW_INT = 1, /*!< OFLOW_INT : Overflow interrupt status bit was set. */
} CTIMER_STMINTCLR_OVERFLOW_Enum;
/* =========================================== CTIMER STMINTCLR COMPAREH [7..7] ============================================ */
typedef enum { /*!< CTIMER_STMINTCLR_COMPAREH */
CTIMER_STMINTCLR_COMPAREH_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */
} CTIMER_STMINTCLR_COMPAREH_Enum;
/* =========================================== CTIMER STMINTCLR COMPAREG [6..6] ============================================ */
typedef enum { /*!< CTIMER_STMINTCLR_COMPAREG */
CTIMER_STMINTCLR_COMPAREG_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */
} CTIMER_STMINTCLR_COMPAREG_Enum;
/* =========================================== CTIMER STMINTCLR COMPAREF [5..5] ============================================ */
typedef enum { /*!< CTIMER_STMINTCLR_COMPAREF */
CTIMER_STMINTCLR_COMPAREF_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */
} CTIMER_STMINTCLR_COMPAREF_Enum;
/* =========================================== CTIMER STMINTCLR COMPAREE [4..4] ============================================ */
typedef enum { /*!< CTIMER_STMINTCLR_COMPAREE */
CTIMER_STMINTCLR_COMPAREE_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */
} CTIMER_STMINTCLR_COMPAREE_Enum;
/* =========================================== CTIMER STMINTCLR COMPARED [3..3] ============================================ */
typedef enum { /*!< CTIMER_STMINTCLR_COMPARED */
CTIMER_STMINTCLR_COMPARED_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */
} CTIMER_STMINTCLR_COMPARED_Enum;
/* =========================================== CTIMER STMINTCLR COMPAREC [2..2] ============================================ */
typedef enum { /*!< CTIMER_STMINTCLR_COMPAREC */
CTIMER_STMINTCLR_COMPAREC_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */
} CTIMER_STMINTCLR_COMPAREC_Enum;
/* =========================================== CTIMER STMINTCLR COMPAREB [1..1] ============================================ */
typedef enum { /*!< CTIMER_STMINTCLR_COMPAREB */
CTIMER_STMINTCLR_COMPAREB_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */
} CTIMER_STMINTCLR_COMPAREB_Enum;
/* =========================================== CTIMER STMINTCLR COMPAREA [0..0] ============================================ */
typedef enum { /*!< CTIMER_STMINTCLR_COMPAREA */
CTIMER_STMINTCLR_COMPAREA_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */
} CTIMER_STMINTCLR_COMPAREA_Enum;
/* ======================================================= STMINTSET ======================================================= */
/* ========================================== CTIMER STMINTSET CAPTURED [12..12] =========================================== */
typedef enum { /*!< CTIMER_STMINTSET_CAPTURED */
CTIMER_STMINTSET_CAPTURED_CAPD_INT = 1, /*!< CAPD_INT : Capture D interrupt status bit was set. */
} CTIMER_STMINTSET_CAPTURED_Enum;
/* ========================================== CTIMER STMINTSET CAPTUREC [11..11] =========================================== */
typedef enum { /*!< CTIMER_STMINTSET_CAPTUREC */
CTIMER_STMINTSET_CAPTUREC_CAPC_INT = 1, /*!< CAPC_INT : CAPTURE C interrupt status bit was set. */
} CTIMER_STMINTSET_CAPTUREC_Enum;
/* ========================================== CTIMER STMINTSET CAPTUREB [10..10] =========================================== */
typedef enum { /*!< CTIMER_STMINTSET_CAPTUREB */
CTIMER_STMINTSET_CAPTUREB_CAPB_INT = 1, /*!< CAPB_INT : CAPTURE B interrupt status bit was set. */
} CTIMER_STMINTSET_CAPTUREB_Enum;
/* =========================================== CTIMER STMINTSET CAPTUREA [9..9] ============================================ */
typedef enum { /*!< CTIMER_STMINTSET_CAPTUREA */
CTIMER_STMINTSET_CAPTUREA_CAPA_INT = 1, /*!< CAPA_INT : CAPTURE A interrupt status bit was set. */
} CTIMER_STMINTSET_CAPTUREA_Enum;
/* =========================================== CTIMER STMINTSET OVERFLOW [8..8] ============================================ */
typedef enum { /*!< CTIMER_STMINTSET_OVERFLOW */
CTIMER_STMINTSET_OVERFLOW_OFLOW_INT = 1, /*!< OFLOW_INT : Overflow interrupt status bit was set. */
} CTIMER_STMINTSET_OVERFLOW_Enum;
/* =========================================== CTIMER STMINTSET COMPAREH [7..7] ============================================ */
typedef enum { /*!< CTIMER_STMINTSET_COMPAREH */
CTIMER_STMINTSET_COMPAREH_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */
} CTIMER_STMINTSET_COMPAREH_Enum;
/* =========================================== CTIMER STMINTSET COMPAREG [6..6] ============================================ */
typedef enum { /*!< CTIMER_STMINTSET_COMPAREG */
CTIMER_STMINTSET_COMPAREG_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */
} CTIMER_STMINTSET_COMPAREG_Enum;
/* =========================================== CTIMER STMINTSET COMPAREF [5..5] ============================================ */
typedef enum { /*!< CTIMER_STMINTSET_COMPAREF */
CTIMER_STMINTSET_COMPAREF_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */
} CTIMER_STMINTSET_COMPAREF_Enum;
/* =========================================== CTIMER STMINTSET COMPAREE [4..4] ============================================ */
typedef enum { /*!< CTIMER_STMINTSET_COMPAREE */
CTIMER_STMINTSET_COMPAREE_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */
} CTIMER_STMINTSET_COMPAREE_Enum;
/* =========================================== CTIMER STMINTSET COMPARED [3..3] ============================================ */
typedef enum { /*!< CTIMER_STMINTSET_COMPARED */
CTIMER_STMINTSET_COMPARED_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */
} CTIMER_STMINTSET_COMPARED_Enum;
/* =========================================== CTIMER STMINTSET COMPAREC [2..2] ============================================ */
typedef enum { /*!< CTIMER_STMINTSET_COMPAREC */
CTIMER_STMINTSET_COMPAREC_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */
} CTIMER_STMINTSET_COMPAREC_Enum;
/* =========================================== CTIMER STMINTSET COMPAREB [1..1] ============================================ */
typedef enum { /*!< CTIMER_STMINTSET_COMPAREB */
CTIMER_STMINTSET_COMPAREB_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */
} CTIMER_STMINTSET_COMPAREB_Enum;
/* =========================================== CTIMER STMINTSET COMPAREA [0..0] ============================================ */
typedef enum { /*!< CTIMER_STMINTSET_COMPAREA */
CTIMER_STMINTSET_COMPAREA_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */
} CTIMER_STMINTSET_COMPAREA_Enum;
/* =========================================================================================================================== */
/* ================ GPIO ================ */
/* =========================================================================================================================== */
/* ======================================================== PADREGA ======================================================== */
/* ============================================ GPIO PADREGA PAD3PWRUP [30..30] ============================================ */
typedef enum { /*!< GPIO_PADREGA_PAD3PWRUP */
GPIO_PADREGA_PAD3PWRUP_DIS = 0, /*!< DIS : Power switch disabled */
GPIO_PADREGA_PAD3PWRUP_EN = 1, /*!< EN : Power switch enabled (switched to VDD) */
} GPIO_PADREGA_PAD3PWRUP_Enum;
/* =========================================== GPIO PADREGA PAD3FNCSEL [27..29] ============================================ */
typedef enum { /*!< GPIO_PADREGA_PAD3FNCSEL */
GPIO_PADREGA_PAD3FNCSEL_UA0RTS = 0, /*!< UA0RTS : Configure as the UART0 RTS output */
GPIO_PADREGA_PAD3FNCSEL_SLnCE = 1, /*!< SLnCE : Configure as the IOSLAVE SPI nCE signal */
GPIO_PADREGA_PAD3FNCSEL_NCE3 = 2, /*!< NCE3 : IOM/MSPI nCE group 3 */
GPIO_PADREGA_PAD3FNCSEL_GPIO3 = 3, /*!< GPIO3 : Configure as GPIO3 */
GPIO_PADREGA_PAD3FNCSEL_MSPI7 = 5, /*!< MSPI7 : MSPI data connection 7 */
GPIO_PADREGA_PAD3FNCSEL_TRIG1 = 6, /*!< TRIG1 : Configure as the ADC Trigger 1 signal */
GPIO_PADREGA_PAD3FNCSEL_I2S_WCLK = 7, /*!< I2S_WCLK : Configure as the PDM I2S Word Clock input */
} GPIO_PADREGA_PAD3FNCSEL_Enum;
/* ============================================ GPIO PADREGA PAD3STRNG [26..26] ============================================ */
typedef enum { /*!< GPIO_PADREGA_PAD3STRNG */
GPIO_PADREGA_PAD3STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGA_PAD3STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGA_PAD3STRNG_Enum;
/* ============================================ GPIO PADREGA PAD3INPEN [25..25] ============================================ */
typedef enum { /*!< GPIO_PADREGA_PAD3INPEN */
GPIO_PADREGA_PAD3INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGA_PAD3INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGA_PAD3INPEN_Enum;
/* ============================================ GPIO PADREGA PAD3PULL [24..24] ============================================= */
typedef enum { /*!< GPIO_PADREGA_PAD3PULL */
GPIO_PADREGA_PAD3PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGA_PAD3PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGA_PAD3PULL_Enum;
/* =========================================== GPIO PADREGA PAD2FNCSEL [19..21] ============================================ */
typedef enum { /*!< GPIO_PADREGA_PAD2FNCSEL */
GPIO_PADREGA_PAD2FNCSEL_UART1RX = 0, /*!< UART1RX : Configure as the UART1 RX input. */
GPIO_PADREGA_PAD2FNCSEL_SLMISO = 1, /*!< SLMISO : Configure as the IOSLAVE SPI MISO signal. */
GPIO_PADREGA_PAD2FNCSEL_UART0RX = 2, /*!< UART0RX : Configure as the UART0 RX input. */
GPIO_PADREGA_PAD2FNCSEL_GPIO2 = 3, /*!< GPIO2 : Configure as GPIO2. */
GPIO_PADREGA_PAD2FNCSEL_MSPI6 = 5, /*!< MSPI6 : MSPI data connection 6. */
GPIO_PADREGA_PAD2FNCSEL_NCE2 = 7, /*!< NCE2 : IOM/MSPI nCE group 2 */
} GPIO_PADREGA_PAD2FNCSEL_Enum;
/* ============================================ GPIO PADREGA PAD2STRNG [18..18] ============================================ */
typedef enum { /*!< GPIO_PADREGA_PAD2STRNG */
GPIO_PADREGA_PAD2STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGA_PAD2STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGA_PAD2STRNG_Enum;
/* ============================================ GPIO PADREGA PAD2INPEN [17..17] ============================================ */
typedef enum { /*!< GPIO_PADREGA_PAD2INPEN */
GPIO_PADREGA_PAD2INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGA_PAD2INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGA_PAD2INPEN_Enum;
/* ============================================ GPIO PADREGA PAD2PULL [16..16] ============================================= */
typedef enum { /*!< GPIO_PADREGA_PAD2PULL */
GPIO_PADREGA_PAD2PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGA_PAD2PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGA_PAD2PULL_Enum;
/* ============================================ GPIO PADREGA PAD1RSEL [14..15] ============================================= */
typedef enum { /*!< GPIO_PADREGA_PAD1RSEL */
GPIO_PADREGA_PAD1RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */
GPIO_PADREGA_PAD1RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */
GPIO_PADREGA_PAD1RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */
GPIO_PADREGA_PAD1RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */
} GPIO_PADREGA_PAD1RSEL_Enum;
/* =========================================== GPIO PADREGA PAD1FNCSEL [11..13] ============================================ */
typedef enum { /*!< GPIO_PADREGA_PAD1FNCSEL */
GPIO_PADREGA_PAD1FNCSEL_SLSDAWIR3 = 0, /*!< SLSDAWIR3 : Configure as the IOSLAVE I2C SDA or SPI WIR3 signal */
GPIO_PADREGA_PAD1FNCSEL_SLMOSI = 1, /*!< SLMOSI : Configure as the IOSLAVE SPI MOSI signal */
GPIO_PADREGA_PAD1FNCSEL_UART0TX = 2, /*!< UART0TX : Configure as the UART0 TX output signal */
GPIO_PADREGA_PAD1FNCSEL_GPIO1 = 3, /*!< GPIO1 : Configure as GPIO1 */
GPIO_PADREGA_PAD1FNCSEL_MSPI5 = 5, /*!< MSPI5 : MSPI data connection 5 */
GPIO_PADREGA_PAD1FNCSEL_NCE1 = 7, /*!< NCE1 : IOM/MSPI nCE group 1 */
} GPIO_PADREGA_PAD1FNCSEL_Enum;
/* ============================================ GPIO PADREGA PAD1STRNG [10..10] ============================================ */
typedef enum { /*!< GPIO_PADREGA_PAD1STRNG */
GPIO_PADREGA_PAD1STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGA_PAD1STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGA_PAD1STRNG_Enum;
/* ============================================= GPIO PADREGA PAD1INPEN [9..9] ============================================= */
typedef enum { /*!< GPIO_PADREGA_PAD1INPEN */
GPIO_PADREGA_PAD1INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGA_PAD1INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGA_PAD1INPEN_Enum;
/* ============================================= GPIO PADREGA PAD1PULL [8..8] ============================================== */
typedef enum { /*!< GPIO_PADREGA_PAD1PULL */
GPIO_PADREGA_PAD1PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGA_PAD1PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGA_PAD1PULL_Enum;
/* ============================================= GPIO PADREGA PAD0RSEL [6..7] ============================================== */
typedef enum { /*!< GPIO_PADREGA_PAD0RSEL */
GPIO_PADREGA_PAD0RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */
GPIO_PADREGA_PAD0RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */
GPIO_PADREGA_PAD0RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */
GPIO_PADREGA_PAD0RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */
} GPIO_PADREGA_PAD0RSEL_Enum;
/* ============================================ GPIO PADREGA PAD0FNCSEL [3..5] ============================================= */
typedef enum { /*!< GPIO_PADREGA_PAD0FNCSEL */
GPIO_PADREGA_PAD0FNCSEL_SLSCL = 0, /*!< SLSCL : Configure as the IOSLAVE I2C SCL signal */
GPIO_PADREGA_PAD0FNCSEL_SLSCK = 1, /*!< SLSCK : Configure as the IOSLAVE SPI SCK signal */
GPIO_PADREGA_PAD0FNCSEL_CLKOUT = 2, /*!< CLKOUT : Configure as the CLKOUT signal */
GPIO_PADREGA_PAD0FNCSEL_GPIO0 = 3, /*!< GPIO0 : Configure as GPIO0 */
GPIO_PADREGA_PAD0FNCSEL_MSPI4 = 5, /*!< MSPI4 : MSPI data connection 4 */
GPIO_PADREGA_PAD0FNCSEL_NCE0 = 7, /*!< NCE0 : IOM/MSPI nCE group 0 */
} GPIO_PADREGA_PAD0FNCSEL_Enum;
/* ============================================= GPIO PADREGA PAD0STRNG [2..2] ============================================= */
typedef enum { /*!< GPIO_PADREGA_PAD0STRNG */
GPIO_PADREGA_PAD0STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGA_PAD0STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGA_PAD0STRNG_Enum;
/* ============================================= GPIO PADREGA PAD0INPEN [1..1] ============================================= */
typedef enum { /*!< GPIO_PADREGA_PAD0INPEN */
GPIO_PADREGA_PAD0INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGA_PAD0INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGA_PAD0INPEN_Enum;
/* ============================================= GPIO PADREGA PAD0PULL [0..0] ============================================== */
typedef enum { /*!< GPIO_PADREGA_PAD0PULL */
GPIO_PADREGA_PAD0PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGA_PAD0PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGA_PAD0PULL_Enum;
/* ======================================================== PADREGB ======================================================== */
/* =========================================== GPIO PADREGB PAD7FNCSEL [27..29] ============================================ */
typedef enum { /*!< GPIO_PADREGB_PAD7FNCSEL */
GPIO_PADREGB_PAD7FNCSEL_NCE7 = 0, /*!< NCE7 : IOM/MSPI nCE group 7 */
GPIO_PADREGB_PAD7FNCSEL_M0MOSI = 1, /*!< M0MOSI : Configure as the IOMSTR0 SPI MOSI signal */
GPIO_PADREGB_PAD7FNCSEL_CLKOUT = 2, /*!< CLKOUT : Configure as the CLKOUT signal */
GPIO_PADREGB_PAD7FNCSEL_GPIO7 = 3, /*!< GPIO7 : Configure as GPIO7 */
GPIO_PADREGB_PAD7FNCSEL_TRIG0 = 4, /*!< TRIG0 : Configure as the ADC Trigger 0 signal */
GPIO_PADREGB_PAD7FNCSEL_UART0TX = 5, /*!< UART0TX : Configure as the UART0 TX output signal */
GPIO_PADREGB_PAD7FNCSEL_CT19 = 7, /*!< CT19 : CTIMER connection 19 */
} GPIO_PADREGB_PAD7FNCSEL_Enum;
/* ============================================ GPIO PADREGB PAD7STRNG [26..26] ============================================ */
typedef enum { /*!< GPIO_PADREGB_PAD7STRNG */
GPIO_PADREGB_PAD7STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGB_PAD7STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGB_PAD7STRNG_Enum;
/* ============================================ GPIO PADREGB PAD7INPEN [25..25] ============================================ */
typedef enum { /*!< GPIO_PADREGB_PAD7INPEN */
GPIO_PADREGB_PAD7INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGB_PAD7INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGB_PAD7INPEN_Enum;
/* ============================================ GPIO PADREGB PAD7PULL [24..24] ============================================= */
typedef enum { /*!< GPIO_PADREGB_PAD7PULL */
GPIO_PADREGB_PAD7PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGB_PAD7PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGB_PAD7PULL_Enum;
/* ============================================ GPIO PADREGB PAD6RSEL [22..23] ============================================= */
typedef enum { /*!< GPIO_PADREGB_PAD6RSEL */
GPIO_PADREGB_PAD6RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */
GPIO_PADREGB_PAD6RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */
GPIO_PADREGB_PAD6RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */
GPIO_PADREGB_PAD6RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */
} GPIO_PADREGB_PAD6RSEL_Enum;
/* =========================================== GPIO PADREGB PAD6FNCSEL [19..21] ============================================ */
typedef enum { /*!< GPIO_PADREGB_PAD6FNCSEL */
GPIO_PADREGB_PAD6FNCSEL_M0SDAWIR3 = 0, /*!< M0SDAWIR3 : Configure as the IOMSTR0 I2C SDA or SPI WIR3 signal */
GPIO_PADREGB_PAD6FNCSEL_M0MISO = 1, /*!< M0MISO : Configure as the IOMSTR0 SPI MISO signal */
GPIO_PADREGB_PAD6FNCSEL_UA0CTS = 2, /*!< UA0CTS : Configure as the UART0 CTS input signal */
GPIO_PADREGB_PAD6FNCSEL_GPIO6 = 3, /*!< GPIO6 : Configure as GPIO6 */
GPIO_PADREGB_PAD6FNCSEL_CT10 = 5, /*!< CT10 : CTIMER connection 10 */
GPIO_PADREGB_PAD6FNCSEL_I2S_DAT = 7, /*!< I2S_DAT : Configure as the PDM I2S Data output signal */
} GPIO_PADREGB_PAD6FNCSEL_Enum;
/* ============================================ GPIO PADREGB PAD6STRNG [18..18] ============================================ */
typedef enum { /*!< GPIO_PADREGB_PAD6STRNG */
GPIO_PADREGB_PAD6STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGB_PAD6STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGB_PAD6STRNG_Enum;
/* ============================================ GPIO PADREGB PAD6INPEN [17..17] ============================================ */
typedef enum { /*!< GPIO_PADREGB_PAD6INPEN */
GPIO_PADREGB_PAD6INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGB_PAD6INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGB_PAD6INPEN_Enum;
/* ============================================ GPIO PADREGB PAD6PULL [16..16] ============================================= */
typedef enum { /*!< GPIO_PADREGB_PAD6PULL */
GPIO_PADREGB_PAD6PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGB_PAD6PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGB_PAD6PULL_Enum;
/* ============================================ GPIO PADREGB PAD5RSEL [14..15] ============================================= */
typedef enum { /*!< GPIO_PADREGB_PAD5RSEL */
GPIO_PADREGB_PAD5RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */
GPIO_PADREGB_PAD5RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */
GPIO_PADREGB_PAD5RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */
GPIO_PADREGB_PAD5RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */
} GPIO_PADREGB_PAD5RSEL_Enum;
/* =========================================== GPIO PADREGB PAD5FNCSEL [11..13] ============================================ */
typedef enum { /*!< GPIO_PADREGB_PAD5FNCSEL */
GPIO_PADREGB_PAD5FNCSEL_M0SCL = 0, /*!< M0SCL : Configure as the IOMSTR0 I2C SCL signal */
GPIO_PADREGB_PAD5FNCSEL_M0SCK = 1, /*!< M0SCK : Configure as the IOMSTR0 SPI SCK signal */
GPIO_PADREGB_PAD5FNCSEL_UA0RTS = 2, /*!< UA0RTS : Configure as the UART0 RTS signal output */
GPIO_PADREGB_PAD5FNCSEL_GPIO5 = 3, /*!< GPIO5 : Configure as GPIO5 */
GPIO_PADREGB_PAD5FNCSEL_EXTHFA = 5, /*!< EXTHFA : Configure as the External HFA input clock */
GPIO_PADREGB_PAD5FNCSEL_CT8 = 7, /*!< CT8 : CTIMER connection 8 */
} GPIO_PADREGB_PAD5FNCSEL_Enum;
/* ============================================ GPIO PADREGB PAD5STRNG [10..10] ============================================ */
typedef enum { /*!< GPIO_PADREGB_PAD5STRNG */
GPIO_PADREGB_PAD5STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGB_PAD5STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGB_PAD5STRNG_Enum;
/* ============================================= GPIO PADREGB PAD5INPEN [9..9] ============================================= */
typedef enum { /*!< GPIO_PADREGB_PAD5INPEN */
GPIO_PADREGB_PAD5INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGB_PAD5INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGB_PAD5INPEN_Enum;
/* ============================================= GPIO PADREGB PAD5PULL [8..8] ============================================== */
typedef enum { /*!< GPIO_PADREGB_PAD5PULL */
GPIO_PADREGB_PAD5PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGB_PAD5PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGB_PAD5PULL_Enum;
/* ============================================ GPIO PADREGB PAD4FNCSEL [3..5] ============================================= */
typedef enum { /*!< GPIO_PADREGB_PAD4FNCSEL */
GPIO_PADREGB_PAD4FNCSEL_UA0CTS = 0, /*!< UA0CTS : Configure as the UART0 CTS input signal */
GPIO_PADREGB_PAD4FNCSEL_SLINT = 1, /*!< SLINT : Configure as the IOSLAVE interrupt out signal */
GPIO_PADREGB_PAD4FNCSEL_NCE4 = 2, /*!< NCE4 : IOM/SPI nCE group 4 */
GPIO_PADREGB_PAD4FNCSEL_GPIO4 = 3, /*!< GPIO4 : Configure as GPIO4 */
GPIO_PADREGB_PAD4FNCSEL_UART1RX = 5, /*!< UART1RX : Configure as the UART1 RX input */
GPIO_PADREGB_PAD4FNCSEL_CT17 = 6, /*!< CT17 : CTIMER connection 17 */
GPIO_PADREGB_PAD4FNCSEL_MSPI2 = 7, /*!< MSPI2 : MSPI data connection 2 */
} GPIO_PADREGB_PAD4FNCSEL_Enum;
/* ============================================= GPIO PADREGB PAD4STRNG [2..2] ============================================= */
typedef enum { /*!< GPIO_PADREGB_PAD4STRNG */
GPIO_PADREGB_PAD4STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGB_PAD4STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGB_PAD4STRNG_Enum;
/* ============================================= GPIO PADREGB PAD4INPEN [1..1] ============================================= */
typedef enum { /*!< GPIO_PADREGB_PAD4INPEN */
GPIO_PADREGB_PAD4INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGB_PAD4INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGB_PAD4INPEN_Enum;
/* ============================================= GPIO PADREGB PAD4PULL [0..0] ============================================== */
typedef enum { /*!< GPIO_PADREGB_PAD4PULL */
GPIO_PADREGB_PAD4PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGB_PAD4PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGB_PAD4PULL_Enum;
/* ======================================================== PADREGC ======================================================== */
/* =========================================== GPIO PADREGC PAD11FNCSEL [27..29] =========================================== */
typedef enum { /*!< GPIO_PADREGC_PAD11FNCSEL */
GPIO_PADREGC_PAD11FNCSEL_ADCSE2 = 0, /*!< ADCSE2 : Configure as the analog input for ADC single ended
input 2 */
GPIO_PADREGC_PAD11FNCSEL_NCE11 = 1, /*!< NCE11 : IOM/MSPI nCE group 11 */
GPIO_PADREGC_PAD11FNCSEL_CT31 = 2, /*!< CT31 : CTIMER connection 31 */
GPIO_PADREGC_PAD11FNCSEL_GPIO11 = 3, /*!< GPIO11 : Configure as GPIO11 */
GPIO_PADREGC_PAD11FNCSEL_SLINT = 4, /*!< SLINT : Configure as the IOSLAVE interrupt out signal */
GPIO_PADREGC_PAD11FNCSEL_UA1CTS = 5, /*!< UA1CTS : Configure as the UART1 CTS input signal */
GPIO_PADREGC_PAD11FNCSEL_UART0RX = 6, /*!< UART0RX : Configure as the UART0 RX input signal */
GPIO_PADREGC_PAD11FNCSEL_PDM_DATA = 7, /*!< PDM_DATA : Configure as the PDM Data input signal */
} GPIO_PADREGC_PAD11FNCSEL_Enum;
/* =========================================== GPIO PADREGC PAD11STRNG [26..26] ============================================ */
typedef enum { /*!< GPIO_PADREGC_PAD11STRNG */
GPIO_PADREGC_PAD11STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGC_PAD11STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGC_PAD11STRNG_Enum;
/* =========================================== GPIO PADREGC PAD11INPEN [25..25] ============================================ */
typedef enum { /*!< GPIO_PADREGC_PAD11INPEN */
GPIO_PADREGC_PAD11INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGC_PAD11INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGC_PAD11INPEN_Enum;
/* ============================================ GPIO PADREGC PAD11PULL [24..24] ============================================ */
typedef enum { /*!< GPIO_PADREGC_PAD11PULL */
GPIO_PADREGC_PAD11PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGC_PAD11PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGC_PAD11PULL_Enum;
/* =========================================== GPIO PADREGC PAD10FNCSEL [19..21] =========================================== */
typedef enum { /*!< GPIO_PADREGC_PAD10FNCSEL */
GPIO_PADREGC_PAD10FNCSEL_UART1TX = 0, /*!< UART1TX : Configure as the UART1 TX output signal */
GPIO_PADREGC_PAD10FNCSEL_M1MOSI = 1, /*!< M1MOSI : Configure as the IOMSTR1 SPI MOSI signal */
GPIO_PADREGC_PAD10FNCSEL_NCE10 = 2, /*!< NCE10 : IOM/MSPI nCE group 10 */
GPIO_PADREGC_PAD10FNCSEL_GPIO10 = 3, /*!< GPIO10 : Configure as GPIO10 */
GPIO_PADREGC_PAD10FNCSEL_PDMCLK = 4, /*!< PDMCLK : PDM serial clock out */
GPIO_PADREGC_PAD10FNCSEL_UA1RTS = 5, /*!< UA1RTS : Configure as the UART1 RTS output signal */
} GPIO_PADREGC_PAD10FNCSEL_Enum;
/* =========================================== GPIO PADREGC PAD10STRNG [18..18] ============================================ */
typedef enum { /*!< GPIO_PADREGC_PAD10STRNG */
GPIO_PADREGC_PAD10STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGC_PAD10STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGC_PAD10STRNG_Enum;
/* =========================================== GPIO PADREGC PAD10INPEN [17..17] ============================================ */
typedef enum { /*!< GPIO_PADREGC_PAD10INPEN */
GPIO_PADREGC_PAD10INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGC_PAD10INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGC_PAD10INPEN_Enum;
/* ============================================ GPIO PADREGC PAD10PULL [16..16] ============================================ */
typedef enum { /*!< GPIO_PADREGC_PAD10PULL */
GPIO_PADREGC_PAD10PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGC_PAD10PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGC_PAD10PULL_Enum;
/* ============================================ GPIO PADREGC PAD9RSEL [14..15] ============================================= */
typedef enum { /*!< GPIO_PADREGC_PAD9RSEL */
GPIO_PADREGC_PAD9RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */
GPIO_PADREGC_PAD9RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */
GPIO_PADREGC_PAD9RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */
GPIO_PADREGC_PAD9RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */
} GPIO_PADREGC_PAD9RSEL_Enum;
/* =========================================== GPIO PADREGC PAD9FNCSEL [11..13] ============================================ */
typedef enum { /*!< GPIO_PADREGC_PAD9FNCSEL */
GPIO_PADREGC_PAD9FNCSEL_M1SDAWIR3 = 0, /*!< M1SDAWIR3 : Configure as the IOMSTR1 I2C SDA or SPI WIR3 signal */
GPIO_PADREGC_PAD9FNCSEL_M1MISO = 1, /*!< M1MISO : Configure as the IOMSTR1 SPI MISO signal */
GPIO_PADREGC_PAD9FNCSEL_NCE9 = 2, /*!< NCE9 : IOM/MSPI nCE group 9 */
GPIO_PADREGC_PAD9FNCSEL_GPIO9 = 3, /*!< GPIO9 : Configure as GPIO9 */
GPIO_PADREGC_PAD9FNCSEL_SCCIO = 4, /*!< SCCIO : SCARD data I/O connection */
GPIO_PADREGC_PAD9FNCSEL_UART1RX = 6, /*!< UART1RX : Configure as UART1 RX input signal */
} GPIO_PADREGC_PAD9FNCSEL_Enum;
/* ============================================ GPIO PADREGC PAD9STRNG [10..10] ============================================ */
typedef enum { /*!< GPIO_PADREGC_PAD9STRNG */
GPIO_PADREGC_PAD9STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGC_PAD9STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGC_PAD9STRNG_Enum;
/* ============================================= GPIO PADREGC PAD9INPEN [9..9] ============================================= */
typedef enum { /*!< GPIO_PADREGC_PAD9INPEN */
GPIO_PADREGC_PAD9INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGC_PAD9INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGC_PAD9INPEN_Enum;
/* ============================================= GPIO PADREGC PAD9PULL [8..8] ============================================== */
typedef enum { /*!< GPIO_PADREGC_PAD9PULL */
GPIO_PADREGC_PAD9PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGC_PAD9PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGC_PAD9PULL_Enum;
/* ============================================= GPIO PADREGC PAD8RSEL [6..7] ============================================== */
typedef enum { /*!< GPIO_PADREGC_PAD8RSEL */
GPIO_PADREGC_PAD8RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */
GPIO_PADREGC_PAD8RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */
GPIO_PADREGC_PAD8RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */
GPIO_PADREGC_PAD8RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */
} GPIO_PADREGC_PAD8RSEL_Enum;
/* ============================================ GPIO PADREGC PAD8FNCSEL [3..5] ============================================= */
typedef enum { /*!< GPIO_PADREGC_PAD8FNCSEL */
GPIO_PADREGC_PAD8FNCSEL_M1SCL = 0, /*!< M1SCL : Configure as the IOMSTR1 I2C SCL signal */
GPIO_PADREGC_PAD8FNCSEL_M1SCK = 1, /*!< M1SCK : Configure as the IOMSTR1 SPI SCK signal */
GPIO_PADREGC_PAD8FNCSEL_NCE8 = 2, /*!< NCE8 : IOM/MSPI nCE group 8 */
GPIO_PADREGC_PAD8FNCSEL_GPIO8 = 3, /*!< GPIO8 : Configure as GPIO8 */
GPIO_PADREGC_PAD8FNCSEL_SCCLK = 4, /*!< SCCLK : SCARD serial clock output */
GPIO_PADREGC_PAD8FNCSEL_UART1TX = 6, /*!< UART1TX : Configure as the UART1 TX output signal */
} GPIO_PADREGC_PAD8FNCSEL_Enum;
/* ============================================= GPIO PADREGC PAD8STRNG [2..2] ============================================= */
typedef enum { /*!< GPIO_PADREGC_PAD8STRNG */
GPIO_PADREGC_PAD8STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGC_PAD8STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGC_PAD8STRNG_Enum;
/* ============================================= GPIO PADREGC PAD8INPEN [1..1] ============================================= */
typedef enum { /*!< GPIO_PADREGC_PAD8INPEN */
GPIO_PADREGC_PAD8INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGC_PAD8INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGC_PAD8INPEN_Enum;
/* ============================================= GPIO PADREGC PAD8PULL [0..0] ============================================== */
typedef enum { /*!< GPIO_PADREGC_PAD8PULL */
GPIO_PADREGC_PAD8PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGC_PAD8PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGC_PAD8PULL_Enum;
/* ======================================================== PADREGD ======================================================== */
/* =========================================== GPIO PADREGD PAD15FNCSEL [27..29] =========================================== */
typedef enum { /*!< GPIO_PADREGD_PAD15FNCSEL */
GPIO_PADREGD_PAD15FNCSEL_ADCD1N = 0, /*!< ADCD1N : Configure as the analog ADC differential pair 1 N input
signal */
GPIO_PADREGD_PAD15FNCSEL_NCE15 = 1, /*!< NCE15 : IOM/MSPI nCE group 15 */
GPIO_PADREGD_PAD15FNCSEL_UART1RX = 2, /*!< UART1RX : Configure as the UART1 RX signal */
GPIO_PADREGD_PAD15FNCSEL_GPIO15 = 3, /*!< GPIO15 : Configure as GPIO15 */
GPIO_PADREGD_PAD15FNCSEL_PDMDATA = 4, /*!< PDMDATA : PDM serial data input */
GPIO_PADREGD_PAD15FNCSEL_EXTXT = 5, /*!< EXTXT : Configure as the external XTAL oscillator input */
GPIO_PADREGD_PAD15FNCSEL_SWDIO = 6, /*!< SWDIO : Configure as an alternate port for the SWDIO I/O signal */
GPIO_PADREGD_PAD15FNCSEL_SWO = 7, /*!< SWO : Configure as an SWO (Serial Wire Trace output) */
} GPIO_PADREGD_PAD15FNCSEL_Enum;
/* =========================================== GPIO PADREGD PAD15STRNG [26..26] ============================================ */
typedef enum { /*!< GPIO_PADREGD_PAD15STRNG */
GPIO_PADREGD_PAD15STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGD_PAD15STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGD_PAD15STRNG_Enum;
/* =========================================== GPIO PADREGD PAD15INPEN [25..25] ============================================ */
typedef enum { /*!< GPIO_PADREGD_PAD15INPEN */
GPIO_PADREGD_PAD15INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGD_PAD15INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGD_PAD15INPEN_Enum;
/* ============================================ GPIO PADREGD PAD15PULL [24..24] ============================================ */
typedef enum { /*!< GPIO_PADREGD_PAD15PULL */
GPIO_PADREGD_PAD15PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGD_PAD15PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGD_PAD15PULL_Enum;
/* =========================================== GPIO PADREGD PAD14FNCSEL [19..21] =========================================== */
typedef enum { /*!< GPIO_PADREGD_PAD14FNCSEL */
GPIO_PADREGD_PAD14FNCSEL_ADCD1P = 0, /*!< ADCD1P : Configure as the analog ADC differential pair 1 P input
signal */
GPIO_PADREGD_PAD14FNCSEL_NCE14 = 1, /*!< NCE14 : IOM/MSPI nCE group 14 */
GPIO_PADREGD_PAD14FNCSEL_UART1TX = 2, /*!< UART1TX : Configure as the UART1 TX output signal */
GPIO_PADREGD_PAD14FNCSEL_GPIO14 = 3, /*!< GPIO14 : Configure as GPIO14 */
GPIO_PADREGD_PAD14FNCSEL_PDMCLK = 4, /*!< PDMCLK : PDM serial clock output */
GPIO_PADREGD_PAD14FNCSEL_EXTHFS = 5, /*!< EXTHFS : Configure as the External HFRC oscillator input select */
GPIO_PADREGD_PAD14FNCSEL_SWDCK = 6, /*!< SWDCK : Configure as the alternate input for the SWDCK input
signal */
GPIO_PADREGD_PAD14FNCSEL_32kHzXT = 7, /*!< 32kHzXT : Configure as the 32kHz crystal output signal */
} GPIO_PADREGD_PAD14FNCSEL_Enum;
/* =========================================== GPIO PADREGD PAD14STRNG [18..18] ============================================ */
typedef enum { /*!< GPIO_PADREGD_PAD14STRNG */
GPIO_PADREGD_PAD14STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGD_PAD14STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGD_PAD14STRNG_Enum;
/* =========================================== GPIO PADREGD PAD14INPEN [17..17] ============================================ */
typedef enum { /*!< GPIO_PADREGD_PAD14INPEN */
GPIO_PADREGD_PAD14INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGD_PAD14INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGD_PAD14INPEN_Enum;
/* ============================================ GPIO PADREGD PAD14PULL [16..16] ============================================ */
typedef enum { /*!< GPIO_PADREGD_PAD14PULL */
GPIO_PADREGD_PAD14PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGD_PAD14PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGD_PAD14PULL_Enum;
/* =========================================== GPIO PADREGD PAD13FNCSEL [11..13] =========================================== */
typedef enum { /*!< GPIO_PADREGD_PAD13FNCSEL */
GPIO_PADREGD_PAD13FNCSEL_ADCD0PSE8 = 0, /*!< ADCD0PSE8 : Configure as the ADC Differential pair 0 P, or Single
Ended input 8 analog input signal. Determination of the
D0P vs SE8 usage is done when the particular channel is
selected within the ADC module */
GPIO_PADREGD_PAD13FNCSEL_NCE13 = 1, /*!< NCE13 : IOM/MSPI nCE group 13 */
GPIO_PADREGD_PAD13FNCSEL_CT2 = 2, /*!< CT2 : CTIMER connection 2 */
GPIO_PADREGD_PAD13FNCSEL_GPIO13 = 3, /*!< GPIO13 : Configure as GPIO13 */
GPIO_PADREGD_PAD13FNCSEL_I2SBCLK = 4, /*!< I2SBCLK : I2C interface bit clock */
GPIO_PADREGD_PAD13FNCSEL_EXTHFB = 5, /*!< EXTHFB : Configure as the external HFRC oscillator input */
GPIO_PADREGD_PAD13FNCSEL_UA0RTS = 6, /*!< UA0RTS : Configure as the UART0 RTS signal output */
GPIO_PADREGD_PAD13FNCSEL_UART1RX = 7, /*!< UART1RX : Configure as the UART1 RX input signal */
} GPIO_PADREGD_PAD13FNCSEL_Enum;
/* =========================================== GPIO PADREGD PAD13STRNG [10..10] ============================================ */
typedef enum { /*!< GPIO_PADREGD_PAD13STRNG */
GPIO_PADREGD_PAD13STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGD_PAD13STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGD_PAD13STRNG_Enum;
/* ============================================ GPIO PADREGD PAD13INPEN [9..9] ============================================= */
typedef enum { /*!< GPIO_PADREGD_PAD13INPEN */
GPIO_PADREGD_PAD13INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGD_PAD13INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGD_PAD13INPEN_Enum;
/* ============================================= GPIO PADREGD PAD13PULL [8..8] ============================================= */
typedef enum { /*!< GPIO_PADREGD_PAD13PULL */
GPIO_PADREGD_PAD13PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGD_PAD13PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGD_PAD13PULL_Enum;
/* ============================================ GPIO PADREGD PAD12FNCSEL [3..5] ============================================ */
typedef enum { /*!< GPIO_PADREGD_PAD12FNCSEL */
GPIO_PADREGD_PAD12FNCSEL_ADCD0NSE9 = 0, /*!< ADCD0NSE9 : Configure as the ADC Differential pair 0 N, or Single
Ended input 9 analog input signal. Determination of the
D0N vs SE9 usage is done when the particular channel is
selected within the ADC module */
GPIO_PADREGD_PAD12FNCSEL_NCE12 = 1, /*!< NCE12 : IOM/MSPI nCE group 12 */
GPIO_PADREGD_PAD12FNCSEL_CT0 = 2, /*!< CT0 : CTIMER connection 0 */
GPIO_PADREGD_PAD12FNCSEL_GPIO12 = 3, /*!< GPIO12 : Configure as GPIO12 */
GPIO_PADREGD_PAD12FNCSEL_PDMCLK = 5, /*!< PDMCLK : PDM serial clock output */
GPIO_PADREGD_PAD12FNCSEL_UA0CTS = 6, /*!< UA0CTS : Configure as the UART0 CTS input signal */
GPIO_PADREGD_PAD12FNCSEL_UART1TX = 7, /*!< UART1TX : Configure as the UART1 TX output signal */
} GPIO_PADREGD_PAD12FNCSEL_Enum;
/* ============================================ GPIO PADREGD PAD12STRNG [2..2] ============================================= */
typedef enum { /*!< GPIO_PADREGD_PAD12STRNG */
GPIO_PADREGD_PAD12STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGD_PAD12STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGD_PAD12STRNG_Enum;
/* ============================================ GPIO PADREGD PAD12INPEN [1..1] ============================================= */
typedef enum { /*!< GPIO_PADREGD_PAD12INPEN */
GPIO_PADREGD_PAD12INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGD_PAD12INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGD_PAD12INPEN_Enum;
/* ============================================= GPIO PADREGD PAD12PULL [0..0] ============================================= */
typedef enum { /*!< GPIO_PADREGD_PAD12PULL */
GPIO_PADREGD_PAD12PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGD_PAD12PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGD_PAD12PULL_Enum;
/* ======================================================== PADREGE ======================================================== */
/* =========================================== GPIO PADREGE PAD19FNCSEL [27..29] =========================================== */
typedef enum { /*!< GPIO_PADREGE_PAD19FNCSEL */
GPIO_PADREGE_PAD19FNCSEL_CMPRF0 = 0, /*!< CMPRF0 : Configure as the analog comparator reference 0 signal */
GPIO_PADREGE_PAD19FNCSEL_NCE19 = 1, /*!< NCE19 : IOM/MSPI nCE group 19 */
GPIO_PADREGE_PAD19FNCSEL_CT6 = 2, /*!< CT6 : CTIMER conenction 6 */
GPIO_PADREGE_PAD19FNCSEL_GPIO19 = 3, /*!< GPIO19 : Configure as GPIO19 */
GPIO_PADREGE_PAD19FNCSEL_SCCLK = 4, /*!< SCCLK : SCARD serial clock */
GPIO_PADREGE_PAD19FNCSEL_ANATEST1 = 5, /*!< ANATEST1 : Configure as the ANATEST1 I/O signal */
GPIO_PADREGE_PAD19FNCSEL_UART1RX = 6, /*!< UART1RX : Configure as the UART1 RX input signal */
GPIO_PADREGE_PAD19FNCSEL_I2SBCLK = 7, /*!< I2SBCLK : Configure as the PDM I2S bit clock input signal */
} GPIO_PADREGE_PAD19FNCSEL_Enum;
/* =========================================== GPIO PADREGE PAD19STRNG [26..26] ============================================ */
typedef enum { /*!< GPIO_PADREGE_PAD19STRNG */
GPIO_PADREGE_PAD19STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGE_PAD19STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGE_PAD19STRNG_Enum;
/* =========================================== GPIO PADREGE PAD19INPEN [25..25] ============================================ */
typedef enum { /*!< GPIO_PADREGE_PAD19INPEN */
GPIO_PADREGE_PAD19INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGE_PAD19INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGE_PAD19INPEN_Enum;
/* ============================================ GPIO PADREGE PAD19PULL [24..24] ============================================ */
typedef enum { /*!< GPIO_PADREGE_PAD19PULL */
GPIO_PADREGE_PAD19PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGE_PAD19PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGE_PAD19PULL_Enum;
/* =========================================== GPIO PADREGE PAD18FNCSEL [19..21] =========================================== */
typedef enum { /*!< GPIO_PADREGE_PAD18FNCSEL */
GPIO_PADREGE_PAD18FNCSEL_CMPIN1 = 0, /*!< CMPIN1 : Configure as the analog comparator input 1 signal */
GPIO_PADREGE_PAD18FNCSEL_NCE18 = 1, /*!< NCE18 : IOM/MSPI nCE group 18 */
GPIO_PADREGE_PAD18FNCSEL_CT4 = 2, /*!< CT4 : CTIMER connection 4 */
GPIO_PADREGE_PAD18FNCSEL_GPIO18 = 3, /*!< GPIO18 : Configure as GPIO18 */
GPIO_PADREGE_PAD18FNCSEL_UA0RTS = 4, /*!< UA0RTS : Configure as UART0 RTS output signal */
GPIO_PADREGE_PAD18FNCSEL_ANATEST2 = 5, /*!< ANATEST2 : Configure as ANATEST2 I/O signal */
GPIO_PADREGE_PAD18FNCSEL_UART1TX = 6, /*!< UART1TX : Configure as UART1 TX output signal */
GPIO_PADREGE_PAD18FNCSEL_SCCIO = 7, /*!< SCCIO : SCARD data input/output connectin */
} GPIO_PADREGE_PAD18FNCSEL_Enum;
/* =========================================== GPIO PADREGE PAD18STRNG [18..18] ============================================ */
typedef enum { /*!< GPIO_PADREGE_PAD18STRNG */
GPIO_PADREGE_PAD18STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGE_PAD18STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGE_PAD18STRNG_Enum;
/* =========================================== GPIO PADREGE PAD18INPEN [17..17] ============================================ */
typedef enum { /*!< GPIO_PADREGE_PAD18INPEN */
GPIO_PADREGE_PAD18INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGE_PAD18INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGE_PAD18INPEN_Enum;
/* ============================================ GPIO PADREGE PAD18PULL [16..16] ============================================ */
typedef enum { /*!< GPIO_PADREGE_PAD18PULL */
GPIO_PADREGE_PAD18PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGE_PAD18PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGE_PAD18PULL_Enum;
/* =========================================== GPIO PADREGE PAD17FNCSEL [11..13] =========================================== */
typedef enum { /*!< GPIO_PADREGE_PAD17FNCSEL */
GPIO_PADREGE_PAD17FNCSEL_CMPRF1 = 0, /*!< CMPRF1 : Configure as the analog comparator reference signal
1 input signal */
GPIO_PADREGE_PAD17FNCSEL_NCE17 = 1, /*!< NCE17 : IOM/MSPI nCE group 17 */
GPIO_PADREGE_PAD17FNCSEL_TRIG1 = 2, /*!< TRIG1 : Configure as the ADC Trigger 1 signal */
GPIO_PADREGE_PAD17FNCSEL_GPIO17 = 3, /*!< GPIO17 : Configure as GPIO17 */
GPIO_PADREGE_PAD17FNCSEL_SCCCLK = 4, /*!< SCCCLK : SCARD serial clock output */
GPIO_PADREGE_PAD17FNCSEL_UART0RX = 6, /*!< UART0RX : Configure as UART0 RX input signal */
GPIO_PADREGE_PAD17FNCSEL_UA1CTS = 7, /*!< UA1CTS : Configure as UART1 CTS input signal */
} GPIO_PADREGE_PAD17FNCSEL_Enum;
/* =========================================== GPIO PADREGE PAD17STRNG [10..10] ============================================ */
typedef enum { /*!< GPIO_PADREGE_PAD17STRNG */
GPIO_PADREGE_PAD17STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGE_PAD17STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGE_PAD17STRNG_Enum;
/* ============================================ GPIO PADREGE PAD17INPEN [9..9] ============================================= */
typedef enum { /*!< GPIO_PADREGE_PAD17INPEN */
GPIO_PADREGE_PAD17INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGE_PAD17INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGE_PAD17INPEN_Enum;
/* ============================================= GPIO PADREGE PAD17PULL [8..8] ============================================= */
typedef enum { /*!< GPIO_PADREGE_PAD17PULL */
GPIO_PADREGE_PAD17PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGE_PAD17PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGE_PAD17PULL_Enum;
/* ============================================ GPIO PADREGE PAD16FNCSEL [3..5] ============================================ */
typedef enum { /*!< GPIO_PADREGE_PAD16FNCSEL */
GPIO_PADREGE_PAD16FNCSEL_ADCSE0 = 0, /*!< ADCSE0 : Configure as the analog ADC single ended port 0 input
signal */
GPIO_PADREGE_PAD16FNCSEL_NCE16 = 1, /*!< NCE16 : IOM/MSPI nCE group 16 */
GPIO_PADREGE_PAD16FNCSEL_TRIG0 = 2, /*!< TRIG0 : Configure as the ADC Trigger 0 signal */
GPIO_PADREGE_PAD16FNCSEL_GPIO16 = 3, /*!< GPIO16 : Configure as GPIO16 */
GPIO_PADREGE_PAD16FNCSEL_SCCRST = 4, /*!< SCCRST : SCARD reset output */
GPIO_PADREGE_PAD16FNCSEL_CMPIN0 = 5, /*!< CMPIN0 : Configure as comparator input 0 signal */
GPIO_PADREGE_PAD16FNCSEL_UART0TX = 6, /*!< UART0TX : Configure as UART0 TX output signal */
GPIO_PADREGE_PAD16FNCSEL_UA1RTS = 7, /*!< UA1RTS : Configure as UART1 RTS output signal */
} GPIO_PADREGE_PAD16FNCSEL_Enum;
/* ============================================ GPIO PADREGE PAD16STRNG [2..2] ============================================= */
typedef enum { /*!< GPIO_PADREGE_PAD16STRNG */
GPIO_PADREGE_PAD16STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGE_PAD16STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGE_PAD16STRNG_Enum;
/* ============================================ GPIO PADREGE PAD16INPEN [1..1] ============================================= */
typedef enum { /*!< GPIO_PADREGE_PAD16INPEN */
GPIO_PADREGE_PAD16INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGE_PAD16INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGE_PAD16INPEN_Enum;
/* ============================================= GPIO PADREGE PAD16PULL [0..0] ============================================= */
typedef enum { /*!< GPIO_PADREGE_PAD16PULL */
GPIO_PADREGE_PAD16PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGE_PAD16PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGE_PAD16PULL_Enum;
/* ======================================================== PADREGF ======================================================== */
/* =========================================== GPIO PADREGF PAD23FNCSEL [27..29] =========================================== */
typedef enum { /*!< GPIO_PADREGF_PAD23FNCSEL */
GPIO_PADREGF_PAD23FNCSEL_UART0RX = 0, /*!< UART0RX : Configure as the UART0 RX signal */
GPIO_PADREGF_PAD23FNCSEL_NCE23 = 1, /*!< NCE23 : IOM/MSPI nCE group 23 */
GPIO_PADREGF_PAD23FNCSEL_CT14 = 2, /*!< CT14 : CTIMER connection 14 */
GPIO_PADREGF_PAD23FNCSEL_GPIO23 = 3, /*!< GPIO23 : Configure as GPIO23 */
GPIO_PADREGF_PAD23FNCSEL_I2SWCLK = 4, /*!< I2SWCLK : I2S word clock input */
GPIO_PADREGF_PAD23FNCSEL_CMPOUT = 5, /*!< CMPOUT : Configure as voltage comparitor output */
GPIO_PADREGF_PAD23FNCSEL_MSPI3 = 6, /*!< MSPI3 : MSPI data connection 3 */
GPIO_PADREGF_PAD23FNCSEL_EXTXT = 7, /*!< EXTXT : External XTAL osacillatgor input */
} GPIO_PADREGF_PAD23FNCSEL_Enum;
/* =========================================== GPIO PADREGF PAD23STRNG [26..26] ============================================ */
typedef enum { /*!< GPIO_PADREGF_PAD23STRNG */
GPIO_PADREGF_PAD23STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGF_PAD23STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGF_PAD23STRNG_Enum;
/* =========================================== GPIO PADREGF PAD23INPEN [25..25] ============================================ */
typedef enum { /*!< GPIO_PADREGF_PAD23INPEN */
GPIO_PADREGF_PAD23INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGF_PAD23INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGF_PAD23INPEN_Enum;
/* ============================================ GPIO PADREGF PAD23PULL [24..24] ============================================ */
typedef enum { /*!< GPIO_PADREGF_PAD23PULL */
GPIO_PADREGF_PAD23PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGF_PAD23PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGF_PAD23PULL_Enum;
/* =========================================== GPIO PADREGF PAD22FNCSEL [19..21] =========================================== */
typedef enum { /*!< GPIO_PADREGF_PAD22FNCSEL */
GPIO_PADREGF_PAD22FNCSEL_UART0TX = 0, /*!< UART0TX : Configure as the UART0 TX signal */
GPIO_PADREGF_PAD22FNCSEL_NCE22 = 1, /*!< NCE22 : IOM/MSPI nCE group 22 */
GPIO_PADREGF_PAD22FNCSEL_CT12 = 2, /*!< CT12 : CTIMER connection 12 */
GPIO_PADREGF_PAD22FNCSEL_GPIO22 = 3, /*!< GPIO22 : Configure as GPIO22 */
GPIO_PADREGF_PAD22FNCSEL_PDM_CLK = 4, /*!< PDM_CLK : Configure as the PDM CLK output */
GPIO_PADREGF_PAD22FNCSEL_EXTLF = 5, /*!< EXTLF : External LFRC input */
GPIO_PADREGF_PAD22FNCSEL_MSPI0 = 6, /*!< MSPI0 : MSPI data connection 0 */
GPIO_PADREGF_PAD22FNCSEL_SWO = 7, /*!< SWO : Configure as the serial trace data output signal */
} GPIO_PADREGF_PAD22FNCSEL_Enum;
/* =========================================== GPIO PADREGF PAD22STRNG [18..18] ============================================ */
typedef enum { /*!< GPIO_PADREGF_PAD22STRNG */
GPIO_PADREGF_PAD22STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGF_PAD22STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGF_PAD22STRNG_Enum;
/* =========================================== GPIO PADREGF PAD22INPEN [17..17] ============================================ */
typedef enum { /*!< GPIO_PADREGF_PAD22INPEN */
GPIO_PADREGF_PAD22INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGF_PAD22INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGF_PAD22INPEN_Enum;
/* ============================================ GPIO PADREGF PAD22PULL [16..16] ============================================ */
typedef enum { /*!< GPIO_PADREGF_PAD22PULL */
GPIO_PADREGF_PAD22PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGF_PAD22PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGF_PAD22PULL_Enum;
/* =========================================== GPIO PADREGF PAD21FNCSEL [11..13] =========================================== */
typedef enum { /*!< GPIO_PADREGF_PAD21FNCSEL */
GPIO_PADREGF_PAD21FNCSEL_SWDIO = 0, /*!< SWDIO : Configure as the serial wire debug data signal */
GPIO_PADREGF_PAD21FNCSEL_NCE21 = 1, /*!< NCE21 : IOM/MSPI nCE group 21 */
GPIO_PADREGF_PAD21FNCSEL_GPIO21 = 3, /*!< GPIO21 : Configure as GPIO21 */
GPIO_PADREGF_PAD21FNCSEL_UART0RX = 4, /*!< UART0RX : Configure as UART0 RX input signal */
GPIO_PADREGF_PAD21FNCSEL_UART1RX = 5, /*!< UART1RX : Configure as UART1 RX input signal */
GPIO_PADREGF_PAD21FNCSEL_I2SBCLK = 6, /*!< I2SBCLK : I2S byte clock input */
GPIO_PADREGF_PAD21FNCSEL_UA1CTS = 7, /*!< UA1CTS : Configure as UART1 CTS input signal */
} GPIO_PADREGF_PAD21FNCSEL_Enum;
/* =========================================== GPIO PADREGF PAD21STRNG [10..10] ============================================ */
typedef enum { /*!< GPIO_PADREGF_PAD21STRNG */
GPIO_PADREGF_PAD21STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGF_PAD21STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGF_PAD21STRNG_Enum;
/* ============================================ GPIO PADREGF PAD21INPEN [9..9] ============================================= */
typedef enum { /*!< GPIO_PADREGF_PAD21INPEN */
GPIO_PADREGF_PAD21INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGF_PAD21INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGF_PAD21INPEN_Enum;
/* ============================================= GPIO PADREGF PAD21PULL [8..8] ============================================= */
typedef enum { /*!< GPIO_PADREGF_PAD21PULL */
GPIO_PADREGF_PAD21PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGF_PAD21PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGF_PAD21PULL_Enum;
/* ============================================ GPIO PADREGF PAD20FNCSEL [3..5] ============================================ */
typedef enum { /*!< GPIO_PADREGF_PAD20FNCSEL */
GPIO_PADREGF_PAD20FNCSEL_SWDCK = 0, /*!< SWDCK : Configure as the serial wire debug clock signal */
GPIO_PADREGF_PAD20FNCSEL_NCE20 = 1, /*!< NCE20 : IOM/MSPI nCE group 20 */
GPIO_PADREGF_PAD20FNCSEL_GPIO20 = 3, /*!< GPIO20 : Configure as GPIO20 */
GPIO_PADREGF_PAD20FNCSEL_UART0TX = 4, /*!< UART0TX : Configure as UART0 TX output signal */
GPIO_PADREGF_PAD20FNCSEL_UART1TX = 5, /*!< UART1TX : Configure as UART1 TX output signal */
GPIO_PADREGF_PAD20FNCSEL_I2SBCLK = 6, /*!< I2SBCLK : I2S byte clock input */
GPIO_PADREGF_PAD20FNCSEL_UA1RTS = 7, /*!< UA1RTS : Configure as UART1 RTS output signal */
} GPIO_PADREGF_PAD20FNCSEL_Enum;
/* ============================================ GPIO PADREGF PAD20STRNG [2..2] ============================================= */
typedef enum { /*!< GPIO_PADREGF_PAD20STRNG */
GPIO_PADREGF_PAD20STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGF_PAD20STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGF_PAD20STRNG_Enum;
/* ============================================ GPIO PADREGF PAD20INPEN [1..1] ============================================= */
typedef enum { /*!< GPIO_PADREGF_PAD20INPEN */
GPIO_PADREGF_PAD20INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGF_PAD20INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGF_PAD20INPEN_Enum;
/* ============================================= GPIO PADREGF PAD20PULL [0..0] ============================================= */
typedef enum { /*!< GPIO_PADREGF_PAD20PULL */
GPIO_PADREGF_PAD20PULL_DIS = 0, /*!< DIS : Pulldown disabled */
GPIO_PADREGF_PAD20PULL_EN = 1, /*!< EN : Pulldown enabled */
} GPIO_PADREGF_PAD20PULL_Enum;
/* ======================================================== PADREGG ======================================================== */
/* ============================================ GPIO PADREGG PAD27RSEL [30..31] ============================================ */
typedef enum { /*!< GPIO_PADREGG_PAD27RSEL */
GPIO_PADREGG_PAD27RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */
GPIO_PADREGG_PAD27RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */
GPIO_PADREGG_PAD27RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */
GPIO_PADREGG_PAD27RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */
} GPIO_PADREGG_PAD27RSEL_Enum;
/* =========================================== GPIO PADREGG PAD27FNCSEL [27..29] =========================================== */
typedef enum { /*!< GPIO_PADREGG_PAD27FNCSEL */
GPIO_PADREGG_PAD27FNCSEL_UART0RX = 0, /*!< UART0RX : Configure as UART0 RX input signal */
GPIO_PADREGG_PAD27FNCSEL_NCE27 = 1, /*!< NCE27 : IOM/MSPI nCE group 27 */
GPIO_PADREGG_PAD27FNCSEL_CT5 = 2, /*!< CT5 : CTIMER connection 5 */
GPIO_PADREGG_PAD27FNCSEL_GPIO27 = 3, /*!< GPIO27 : Configure as GPIO27 */
GPIO_PADREGG_PAD27FNCSEL_M2SCL = 4, /*!< M2SCL : Configure as I2C clock I/O signal from IOMSTR2 */
GPIO_PADREGG_PAD27FNCSEL_M2SCK = 5, /*!< M2SCK : Configure as SPI clock output signal from IOMSTR2 */
} GPIO_PADREGG_PAD27FNCSEL_Enum;
/* =========================================== GPIO PADREGG PAD27STRNG [26..26] ============================================ */
typedef enum { /*!< GPIO_PADREGG_PAD27STRNG */
GPIO_PADREGG_PAD27STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGG_PAD27STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGG_PAD27STRNG_Enum;
/* =========================================== GPIO PADREGG PAD27INPEN [25..25] ============================================ */
typedef enum { /*!< GPIO_PADREGG_PAD27INPEN */
GPIO_PADREGG_PAD27INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGG_PAD27INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGG_PAD27INPEN_Enum;
/* ============================================ GPIO PADREGG PAD27PULL [24..24] ============================================ */
typedef enum { /*!< GPIO_PADREGG_PAD27PULL */
GPIO_PADREGG_PAD27PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGG_PAD27PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGG_PAD27PULL_Enum;
/* =========================================== GPIO PADREGG PAD26FNCSEL [19..21] =========================================== */
typedef enum { /*!< GPIO_PADREGG_PAD26FNCSEL */
GPIO_PADREGG_PAD26FNCSEL_EXTHF = 0, /*!< EXTHF : Configure as the external HFRC oscillator input */
GPIO_PADREGG_PAD26FNCSEL_NCE26 = 1, /*!< NCE26 : IOM/MSPI nCE group 26 */
GPIO_PADREGG_PAD26FNCSEL_CT3 = 2, /*!< CT3 : CTIMER connection 3 */
GPIO_PADREGG_PAD26FNCSEL_GPIO26 = 3, /*!< GPIO26 : Configure as GPIO26 */
GPIO_PADREGG_PAD26FNCSEL_SCCRST = 4, /*!< SCCRST : SCARD reset output */
GPIO_PADREGG_PAD26FNCSEL_MSPI1 = 5, /*!< MSPI1 : MSPI data connection 1 */
GPIO_PADREGG_PAD26FNCSEL_UART0TX = 6, /*!< UART0TX : Configure as UART0 TX output signal */
GPIO_PADREGG_PAD26FNCSEL_UA1CTS = 7, /*!< UA1CTS : Configure as UART1 CTS input signal */
} GPIO_PADREGG_PAD26FNCSEL_Enum;
/* =========================================== GPIO PADREGG PAD26STRNG [18..18] ============================================ */
typedef enum { /*!< GPIO_PADREGG_PAD26STRNG */
GPIO_PADREGG_PAD26STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGG_PAD26STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGG_PAD26STRNG_Enum;
/* =========================================== GPIO PADREGG PAD26INPEN [17..17] ============================================ */
typedef enum { /*!< GPIO_PADREGG_PAD26INPEN */
GPIO_PADREGG_PAD26INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGG_PAD26INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGG_PAD26INPEN_Enum;
/* ============================================ GPIO PADREGG PAD26PULL [16..16] ============================================ */
typedef enum { /*!< GPIO_PADREGG_PAD26PULL */
GPIO_PADREGG_PAD26PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGG_PAD26PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGG_PAD26PULL_Enum;
/* ============================================ GPIO PADREGG PAD25RSEL [14..15] ============================================ */
typedef enum { /*!< GPIO_PADREGG_PAD25RSEL */
GPIO_PADREGG_PAD25RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */
GPIO_PADREGG_PAD25RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */
GPIO_PADREGG_PAD25RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */
GPIO_PADREGG_PAD25RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */
} GPIO_PADREGG_PAD25RSEL_Enum;
/* =========================================== GPIO PADREGG PAD25FNCSEL [11..13] =========================================== */
typedef enum { /*!< GPIO_PADREGG_PAD25FNCSEL */
GPIO_PADREGG_PAD25FNCSEL_UART1RX = 0, /*!< UART1RX : Configure as UART1 RX input signal */
GPIO_PADREGG_PAD25FNCSEL_NCE25 = 1, /*!< NCE25 : IOM/MSPI nCE group 25 */
GPIO_PADREGG_PAD25FNCSEL_CT1 = 2, /*!< CT1 : CTIMER connection 1 */
GPIO_PADREGG_PAD25FNCSEL_GPIO25 = 3, /*!< GPIO25 : Configure as GPIO25 */
GPIO_PADREGG_PAD25FNCSEL_M2SDAWIR3 = 4, /*!< M2SDAWIR3 : Configure as the IOMSTR2 I2C SDA or SPI WIR3 signal */
GPIO_PADREGG_PAD25FNCSEL_M2MISO = 5, /*!< M2MISO : Configure as the IOMSTR2 SPI MISO input signal */
} GPIO_PADREGG_PAD25FNCSEL_Enum;
/* =========================================== GPIO PADREGG PAD25STRNG [10..10] ============================================ */
typedef enum { /*!< GPIO_PADREGG_PAD25STRNG */
GPIO_PADREGG_PAD25STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGG_PAD25STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGG_PAD25STRNG_Enum;
/* ============================================ GPIO PADREGG PAD25INPEN [9..9] ============================================= */
typedef enum { /*!< GPIO_PADREGG_PAD25INPEN */
GPIO_PADREGG_PAD25INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGG_PAD25INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGG_PAD25INPEN_Enum;
/* ============================================= GPIO PADREGG PAD25PULL [8..8] ============================================= */
typedef enum { /*!< GPIO_PADREGG_PAD25PULL */
GPIO_PADREGG_PAD25PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGG_PAD25PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGG_PAD25PULL_Enum;
/* ============================================ GPIO PADREGG PAD24FNCSEL [3..5] ============================================ */
typedef enum { /*!< GPIO_PADREGG_PAD24FNCSEL */
GPIO_PADREGG_PAD24FNCSEL_UART1TX = 0, /*!< UART1TX : Configure as UART1 TX output signal */
GPIO_PADREGG_PAD24FNCSEL_NCE24 = 1, /*!< NCE24 : IOM/MSPI nCE group 24 */
GPIO_PADREGG_PAD24FNCSEL_MSPI8 = 2, /*!< MSPI8 : MSPI data connection 8 */
GPIO_PADREGG_PAD24FNCSEL_GPIO24 = 3, /*!< GPIO24 : Configure as GPIO24 */
GPIO_PADREGG_PAD24FNCSEL_UA0CTS = 4, /*!< UA0CTS : Configure as UART0 CTS input signal */
GPIO_PADREGG_PAD24FNCSEL_CT21 = 5, /*!< CT21 : CTIMER connection 21 */
GPIO_PADREGG_PAD24FNCSEL_32kHzXT = 6, /*!< 32kHzXT : Configure as the 32kHz crystal output signal */
GPIO_PADREGG_PAD24FNCSEL_SWO = 7, /*!< SWO : Configure as the serial trace data output signal */
} GPIO_PADREGG_PAD24FNCSEL_Enum;
/* ============================================ GPIO PADREGG PAD24STRNG [2..2] ============================================= */
typedef enum { /*!< GPIO_PADREGG_PAD24STRNG */
GPIO_PADREGG_PAD24STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGG_PAD24STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGG_PAD24STRNG_Enum;
/* ============================================ GPIO PADREGG PAD24INPEN [1..1] ============================================= */
typedef enum { /*!< GPIO_PADREGG_PAD24INPEN */
GPIO_PADREGG_PAD24INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGG_PAD24INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGG_PAD24INPEN_Enum;
/* ============================================= GPIO PADREGG PAD24PULL [0..0] ============================================= */
typedef enum { /*!< GPIO_PADREGG_PAD24PULL */
GPIO_PADREGG_PAD24PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGG_PAD24PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGG_PAD24PULL_Enum;
/* ======================================================== PADREGH ======================================================== */
/* =========================================== GPIO PADREGH PAD31FNCSEL [27..29] =========================================== */
typedef enum { /*!< GPIO_PADREGH_PAD31FNCSEL */
GPIO_PADREGH_PAD31FNCSEL_ADCSE3 = 0, /*!< ADCSE3 : Configure as the analog input for ADC single ended
input 3 */
GPIO_PADREGH_PAD31FNCSEL_NCE31 = 1, /*!< NCE31 : IOM/MSPI nCE group 31 */
GPIO_PADREGH_PAD31FNCSEL_CT13 = 2, /*!< CT13 : CTIMER connection 13 */
GPIO_PADREGH_PAD31FNCSEL_GPIO31 = 3, /*!< GPIO31 : Configure as GPIO31 */
GPIO_PADREGH_PAD31FNCSEL_UART0RX = 4, /*!< UART0RX : Configure as the UART0 RX input signal */
GPIO_PADREGH_PAD31FNCSEL_SCCCLK = 5, /*!< SCCCLK : SCARD serial clock output */
GPIO_PADREGH_PAD31FNCSEL_UA1RTS = 7, /*!< UA1RTS : Configure as UART1 RTS output signal */
} GPIO_PADREGH_PAD31FNCSEL_Enum;
/* =========================================== GPIO PADREGH PAD31STRNG [26..26] ============================================ */
typedef enum { /*!< GPIO_PADREGH_PAD31STRNG */
GPIO_PADREGH_PAD31STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGH_PAD31STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGH_PAD31STRNG_Enum;
/* =========================================== GPIO PADREGH PAD31INPEN [25..25] ============================================ */
typedef enum { /*!< GPIO_PADREGH_PAD31INPEN */
GPIO_PADREGH_PAD31INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGH_PAD31INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGH_PAD31INPEN_Enum;
/* ============================================ GPIO PADREGH PAD31PULL [24..24] ============================================ */
typedef enum { /*!< GPIO_PADREGH_PAD31PULL */
GPIO_PADREGH_PAD31PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGH_PAD31PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGH_PAD31PULL_Enum;
/* =========================================== GPIO PADREGH PAD30FNCSEL [19..21] =========================================== */
typedef enum { /*!< GPIO_PADREGH_PAD30FNCSEL */
GPIO_PADREGH_PAD30FNCSEL_ANATEST1 = 0, /*!< ANATEST1 : Configure as the ANATEST1 I/O signal */
GPIO_PADREGH_PAD30FNCSEL_NCE30 = 1, /*!< NCE30 : IOM/MSPI nCE group 30 */
GPIO_PADREGH_PAD30FNCSEL_CT11 = 2, /*!< CT11 : CTIMER connection 11 */
GPIO_PADREGH_PAD30FNCSEL_GPIO30 = 3, /*!< GPIO30 : Configure as GPIO30 */
GPIO_PADREGH_PAD30FNCSEL_UART0TX = 4, /*!< UART0TX : Configure as UART0 TX output signal */
GPIO_PADREGH_PAD30FNCSEL_UA1RTS = 5, /*!< UA1RTS : Configure as UART1 RTS output signal */
GPIO_PADREGH_PAD30FNCSEL_I2S_DAT = 7, /*!< I2S_DAT : Configure as the PDM I2S Data output signal */
} GPIO_PADREGH_PAD30FNCSEL_Enum;
/* =========================================== GPIO PADREGH PAD30STRNG [18..18] ============================================ */
typedef enum { /*!< GPIO_PADREGH_PAD30STRNG */
GPIO_PADREGH_PAD30STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGH_PAD30STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGH_PAD30STRNG_Enum;
/* =========================================== GPIO PADREGH PAD30INPEN [17..17] ============================================ */
typedef enum { /*!< GPIO_PADREGH_PAD30INPEN */
GPIO_PADREGH_PAD30INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGH_PAD30INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGH_PAD30INPEN_Enum;
/* ============================================ GPIO PADREGH PAD30PULL [16..16] ============================================ */
typedef enum { /*!< GPIO_PADREGH_PAD30PULL */
GPIO_PADREGH_PAD30PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGH_PAD30PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGH_PAD30PULL_Enum;
/* =========================================== GPIO PADREGH PAD29FNCSEL [11..13] =========================================== */
typedef enum { /*!< GPIO_PADREGH_PAD29FNCSEL */
GPIO_PADREGH_PAD29FNCSEL_ADCSE1 = 0, /*!< ADCSE1 : Configure as the analog input for ADC single ended
input 1 */
GPIO_PADREGH_PAD29FNCSEL_NCE29 = 1, /*!< NCE29 : IOM/MSPI nCE group 29 */
GPIO_PADREGH_PAD29FNCSEL_CT9 = 2, /*!< CT9 : CTIMER connection 9 */
GPIO_PADREGH_PAD29FNCSEL_GPIO29 = 3, /*!< GPIO29 : Configure as GPIO29 */
GPIO_PADREGH_PAD29FNCSEL_UA0CTS = 4, /*!< UA0CTS : Configure as the UART0 CTS input signal */
GPIO_PADREGH_PAD29FNCSEL_UA1CTS = 5, /*!< UA1CTS : Configure as the UART1 CTS input signal */
GPIO_PADREGH_PAD29FNCSEL_UART0RX = 6, /*!< UART0RX : Configure as the UART0 RX input signal */
GPIO_PADREGH_PAD29FNCSEL_PDM_DATA = 7, /*!< PDM_DATA : Configure as PDM DATA input */
} GPIO_PADREGH_PAD29FNCSEL_Enum;
/* =========================================== GPIO PADREGH PAD29STRNG [10..10] ============================================ */
typedef enum { /*!< GPIO_PADREGH_PAD29STRNG */
GPIO_PADREGH_PAD29STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGH_PAD29STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGH_PAD29STRNG_Enum;
/* ============================================ GPIO PADREGH PAD29INPEN [9..9] ============================================= */
typedef enum { /*!< GPIO_PADREGH_PAD29INPEN */
GPIO_PADREGH_PAD29INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGH_PAD29INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGH_PAD29INPEN_Enum;
/* ============================================= GPIO PADREGH PAD29PULL [8..8] ============================================= */
typedef enum { /*!< GPIO_PADREGH_PAD29PULL */
GPIO_PADREGH_PAD29PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGH_PAD29PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGH_PAD29PULL_Enum;
/* ============================================ GPIO PADREGH PAD28FNCSEL [3..5] ============================================ */
typedef enum { /*!< GPIO_PADREGH_PAD28FNCSEL */
GPIO_PADREGH_PAD28FNCSEL_I2S_WCLK = 0, /*!< I2S_WCLK : Configure as the PDM I2S Word Clock input */
GPIO_PADREGH_PAD28FNCSEL_NCE28 = 1, /*!< NCE28 : IOM/MSPI nCE group 28 */
GPIO_PADREGH_PAD28FNCSEL_CT7 = 2, /*!< CT7 : CTIMER connection 7 */
GPIO_PADREGH_PAD28FNCSEL_GPIO28 = 3, /*!< GPIO28 : Configure as GPIO28 */
GPIO_PADREGH_PAD28FNCSEL_M2MOSI = 5, /*!< M2MOSI : Configure as the IOMSTR2 SPI MOSI output signal */
GPIO_PADREGH_PAD28FNCSEL_UART0TX = 6, /*!< UART0TX : Configure as the UART0 TX output signal */
} GPIO_PADREGH_PAD28FNCSEL_Enum;
/* ============================================ GPIO PADREGH PAD28STRNG [2..2] ============================================= */
typedef enum { /*!< GPIO_PADREGH_PAD28STRNG */
GPIO_PADREGH_PAD28STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGH_PAD28STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGH_PAD28STRNG_Enum;
/* ============================================ GPIO PADREGH PAD28INPEN [1..1] ============================================= */
typedef enum { /*!< GPIO_PADREGH_PAD28INPEN */
GPIO_PADREGH_PAD28INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGH_PAD28INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGH_PAD28INPEN_Enum;
/* ============================================= GPIO PADREGH PAD28PULL [0..0] ============================================= */
typedef enum { /*!< GPIO_PADREGH_PAD28PULL */
GPIO_PADREGH_PAD28PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGH_PAD28PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGH_PAD28PULL_Enum;
/* ======================================================== PADREGI ======================================================== */
/* =========================================== GPIO PADREGI PAD35FNCSEL [27..29] =========================================== */
typedef enum { /*!< GPIO_PADREGI_PAD35FNCSEL */
GPIO_PADREGI_PAD35FNCSEL_ADCSE7 = 0, /*!< ADCSE7 : Configure as the analog input for ADC single ended
input 7 */
GPIO_PADREGI_PAD35FNCSEL_NCE35 = 1, /*!< NCE35 : IOM/MSPI nCE group 35 */
GPIO_PADREGI_PAD35FNCSEL_UART1TX = 2, /*!< UART1TX : Configure as the UART1 TX signal */
GPIO_PADREGI_PAD35FNCSEL_GPIO35 = 3, /*!< GPIO35 : Configure as GPIO35 */
GPIO_PADREGI_PAD35FNCSEL_I2SDAT = 4, /*!< I2SDAT : I2S serial data output */
GPIO_PADREGI_PAD35FNCSEL_CT27 = 5, /*!< CT27 : CTIMER connection 27 */
GPIO_PADREGI_PAD35FNCSEL_UA0RTS = 6, /*!< UA0RTS : Configure as the UART0 RTS output */
} GPIO_PADREGI_PAD35FNCSEL_Enum;
/* =========================================== GPIO PADREGI PAD35STRNG [26..26] ============================================ */
typedef enum { /*!< GPIO_PADREGI_PAD35STRNG */
GPIO_PADREGI_PAD35STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGI_PAD35STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGI_PAD35STRNG_Enum;
/* =========================================== GPIO PADREGI PAD35INPEN [25..25] ============================================ */
typedef enum { /*!< GPIO_PADREGI_PAD35INPEN */
GPIO_PADREGI_PAD35INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGI_PAD35INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGI_PAD35INPEN_Enum;
/* ============================================ GPIO PADREGI PAD35PULL [24..24] ============================================ */
typedef enum { /*!< GPIO_PADREGI_PAD35PULL */
GPIO_PADREGI_PAD35PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGI_PAD35PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGI_PAD35PULL_Enum;
/* =========================================== GPIO PADREGI PAD34FNCSEL [19..21] =========================================== */
typedef enum { /*!< GPIO_PADREGI_PAD34FNCSEL */
GPIO_PADREGI_PAD34FNCSEL_ADCSE6 = 0, /*!< ADCSE6 : Configure as the analog input for ADC single ended
input 6 */
GPIO_PADREGI_PAD34FNCSEL_NCE34 = 1, /*!< NCE34 : IOM/MSPI nCE group 34 */
GPIO_PADREGI_PAD34FNCSEL_UA1RTS = 2, /*!< UA1RTS : Configure as the UART1 RTS output */
GPIO_PADREGI_PAD34FNCSEL_GPIO34 = 3, /*!< GPIO34 : Configure as GPIO34 */
GPIO_PADREGI_PAD34FNCSEL_CMPRF2 = 4, /*!< CMPRF2 : Configure as the analog comparator reference 2 signal */
GPIO_PADREGI_PAD34FNCSEL_UA0RTS = 5, /*!< UA0RTS : Configure as the UART0 RTS output */
GPIO_PADREGI_PAD34FNCSEL_UART0RX = 6, /*!< UART0RX : Configure as the UART0 RX input */
GPIO_PADREGI_PAD34FNCSEL_PDMDATA = 7, /*!< PDMDATA : PDM serial data input */
} GPIO_PADREGI_PAD34FNCSEL_Enum;
/* =========================================== GPIO PADREGI PAD34STRNG [18..18] ============================================ */
typedef enum { /*!< GPIO_PADREGI_PAD34STRNG */
GPIO_PADREGI_PAD34STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGI_PAD34STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGI_PAD34STRNG_Enum;
/* =========================================== GPIO PADREGI PAD34INPEN [17..17] ============================================ */
typedef enum { /*!< GPIO_PADREGI_PAD34INPEN */
GPIO_PADREGI_PAD34INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGI_PAD34INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGI_PAD34INPEN_Enum;
/* ============================================ GPIO PADREGI PAD34PULL [16..16] ============================================ */
typedef enum { /*!< GPIO_PADREGI_PAD34PULL */
GPIO_PADREGI_PAD34PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGI_PAD34PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGI_PAD34PULL_Enum;
/* =========================================== GPIO PADREGI PAD33FNCSEL [11..13] =========================================== */
typedef enum { /*!< GPIO_PADREGI_PAD33FNCSEL */
GPIO_PADREGI_PAD33FNCSEL_ADCSE5 = 0, /*!< ADCSE5 : Configure as the analog ADC single ended port 5 input
signal */
GPIO_PADREGI_PAD33FNCSEL_NCE33 = 1, /*!< NCE33 : IOM/MSPI nCE group 33 */
GPIO_PADREGI_PAD33FNCSEL_32kHzXT = 2, /*!< 32kHzXT : Configure as the 32kHz crystal output signal */
GPIO_PADREGI_PAD33FNCSEL_GPIO33 = 3, /*!< GPIO33 : Configure as GPIO33 */
GPIO_PADREGI_PAD33FNCSEL_UA0CTS = 5, /*!< UA0CTS : Configure as the UART0 CTS input */
GPIO_PADREGI_PAD33FNCSEL_CT23 = 6, /*!< CT23 : CTIMER connection 23 */
GPIO_PADREGI_PAD33FNCSEL_SWO = 7, /*!< SWO : Configure as the serial trace data output signal */
} GPIO_PADREGI_PAD33FNCSEL_Enum;
/* =========================================== GPIO PADREGI PAD33STRNG [10..10] ============================================ */
typedef enum { /*!< GPIO_PADREGI_PAD33STRNG */
GPIO_PADREGI_PAD33STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGI_PAD33STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGI_PAD33STRNG_Enum;
/* ============================================ GPIO PADREGI PAD33INPEN [9..9] ============================================= */
typedef enum { /*!< GPIO_PADREGI_PAD33INPEN */
GPIO_PADREGI_PAD33INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGI_PAD33INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGI_PAD33INPEN_Enum;
/* ============================================= GPIO PADREGI PAD33PULL [8..8] ============================================= */
typedef enum { /*!< GPIO_PADREGI_PAD33PULL */
GPIO_PADREGI_PAD33PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGI_PAD33PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGI_PAD33PULL_Enum;
/* ============================================ GPIO PADREGI PAD32FNCSEL [3..5] ============================================ */
typedef enum { /*!< GPIO_PADREGI_PAD32FNCSEL */
GPIO_PADREGI_PAD32FNCSEL_ADCSE4 = 0, /*!< ADCSE4 : Configure as the analog input for ADC single ended
input 4 */
GPIO_PADREGI_PAD32FNCSEL_NCE32 = 1, /*!< NCE32 : IOM/MSPI nCE group 32 */
GPIO_PADREGI_PAD32FNCSEL_CT15 = 2, /*!< CT15 : CTIMER connection 15 */
GPIO_PADREGI_PAD32FNCSEL_GPIO32 = 3, /*!< GPIO32 : Configure as GPIO32 */
GPIO_PADREGI_PAD32FNCSEL_SCCIO = 4, /*!< SCCIO : SCARD serial data input/output */
GPIO_PADREGI_PAD32FNCSEL_EXTLF = 5, /*!< EXTLF : External input to the LFRC oscillator */
GPIO_PADREGI_PAD32FNCSEL_UA1CTS = 7, /*!< UA1CTS : Configure as the UART1 CTS input */
} GPIO_PADREGI_PAD32FNCSEL_Enum;
/* ============================================ GPIO PADREGI PAD32STRNG [2..2] ============================================= */
typedef enum { /*!< GPIO_PADREGI_PAD32STRNG */
GPIO_PADREGI_PAD32STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGI_PAD32STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGI_PAD32STRNG_Enum;
/* ============================================ GPIO PADREGI PAD32INPEN [1..1] ============================================= */
typedef enum { /*!< GPIO_PADREGI_PAD32INPEN */
GPIO_PADREGI_PAD32INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGI_PAD32INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGI_PAD32INPEN_Enum;
/* ============================================= GPIO PADREGI PAD32PULL [0..0] ============================================= */
typedef enum { /*!< GPIO_PADREGI_PAD32PULL */
GPIO_PADREGI_PAD32PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGI_PAD32PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGI_PAD32PULL_Enum;
/* ======================================================== PADREGJ ======================================================== */
/* ============================================ GPIO PADREGJ PAD39RSEL [30..31] ============================================ */
typedef enum { /*!< GPIO_PADREGJ_PAD39RSEL */
GPIO_PADREGJ_PAD39RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */
GPIO_PADREGJ_PAD39RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */
GPIO_PADREGJ_PAD39RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */
GPIO_PADREGJ_PAD39RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */
} GPIO_PADREGJ_PAD39RSEL_Enum;
/* =========================================== GPIO PADREGJ PAD39FNCSEL [27..29] =========================================== */
typedef enum { /*!< GPIO_PADREGJ_PAD39FNCSEL */
GPIO_PADREGJ_PAD39FNCSEL_UART0TX = 0, /*!< UART0TX : Configure as the UART0 TX output signal */
GPIO_PADREGJ_PAD39FNCSEL_UART1TX = 1, /*!< UART1TX : Configure as the UART1 TX output signal */
GPIO_PADREGJ_PAD39FNCSEL_CT25 = 2, /*!< CT25 : CTIMER connection 25 */
GPIO_PADREGJ_PAD39FNCSEL_GPIO39 = 3, /*!< GPIO39 : Configure as GPIO39 */
GPIO_PADREGJ_PAD39FNCSEL_M4SCL = 4, /*!< M4SCL : Configure as the IOMSTR4 I2C SCL signal */
GPIO_PADREGJ_PAD39FNCSEL_M4SCK = 5, /*!< M4SCK : Configure as the IOMSTR4 SPI SCK signal */
} GPIO_PADREGJ_PAD39FNCSEL_Enum;
/* =========================================== GPIO PADREGJ PAD39STRNG [26..26] ============================================ */
typedef enum { /*!< GPIO_PADREGJ_PAD39STRNG */
GPIO_PADREGJ_PAD39STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGJ_PAD39STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGJ_PAD39STRNG_Enum;
/* =========================================== GPIO PADREGJ PAD39INPEN [25..25] ============================================ */
typedef enum { /*!< GPIO_PADREGJ_PAD39INPEN */
GPIO_PADREGJ_PAD39INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGJ_PAD39INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGJ_PAD39INPEN_Enum;
/* ============================================ GPIO PADREGJ PAD39PULL [24..24] ============================================ */
typedef enum { /*!< GPIO_PADREGJ_PAD39PULL */
GPIO_PADREGJ_PAD39PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGJ_PAD39PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGJ_PAD39PULL_Enum;
/* =========================================== GPIO PADREGJ PAD38FNCSEL [19..21] =========================================== */
typedef enum { /*!< GPIO_PADREGJ_PAD38FNCSEL */
GPIO_PADREGJ_PAD38FNCSEL_TRIG3 = 0, /*!< TRIG3 : Configure as the ADC Trigger 3 signal */
GPIO_PADREGJ_PAD38FNCSEL_NCE38 = 1, /*!< NCE38 : IOM/MSPI nCE group 38 */
GPIO_PADREGJ_PAD38FNCSEL_UA0CTS = 2, /*!< UA0CTS : Configure as the UART0 CTS signal */
GPIO_PADREGJ_PAD38FNCSEL_GPIO38 = 3, /*!< GPIO38 : Configure as GPIO38 */
GPIO_PADREGJ_PAD38FNCSEL_M3MOSI = 5, /*!< M3MOSI : Configure as the IOMSTR3 SPI MOSI output signal */
GPIO_PADREGJ_PAD38FNCSEL_UART1RX = 6, /*!< UART1RX : Configure as the UART1 RX input signal */
} GPIO_PADREGJ_PAD38FNCSEL_Enum;
/* =========================================== GPIO PADREGJ PAD38STRNG [18..18] ============================================ */
typedef enum { /*!< GPIO_PADREGJ_PAD38STRNG */
GPIO_PADREGJ_PAD38STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGJ_PAD38STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGJ_PAD38STRNG_Enum;
/* =========================================== GPIO PADREGJ PAD38INPEN [17..17] ============================================ */
typedef enum { /*!< GPIO_PADREGJ_PAD38INPEN */
GPIO_PADREGJ_PAD38INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGJ_PAD38INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGJ_PAD38INPEN_Enum;
/* ============================================ GPIO PADREGJ PAD38PULL [16..16] ============================================ */
typedef enum { /*!< GPIO_PADREGJ_PAD38PULL */
GPIO_PADREGJ_PAD38PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGJ_PAD38PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGJ_PAD38PULL_Enum;
/* =========================================== GPIO PADREGJ PAD37PWRDN [15..15] ============================================ */
typedef enum { /*!< GPIO_PADREGJ_PAD37PWRDN */
GPIO_PADREGJ_PAD37PWRDN_DIS = 0, /*!< DIS : Power switch disabled */
GPIO_PADREGJ_PAD37PWRDN_EN = 1, /*!< EN : Power switch enabled (switch to GND) */
} GPIO_PADREGJ_PAD37PWRDN_Enum;
/* =========================================== GPIO PADREGJ PAD37FNCSEL [11..13] =========================================== */
typedef enum { /*!< GPIO_PADREGJ_PAD37FNCSEL */
GPIO_PADREGJ_PAD37FNCSEL_TRIG2 = 0, /*!< TRIG2 : Configure as the ADC Trigger 2 signal */
GPIO_PADREGJ_PAD37FNCSEL_NCE37 = 1, /*!< NCE37 : IOM/MSPI nCE group 37 */
GPIO_PADREGJ_PAD37FNCSEL_UA0RTS = 2, /*!< UA0RTS : Configure as the UART0 RTS output signal */
GPIO_PADREGJ_PAD37FNCSEL_GPIO37 = 3, /*!< GPIO37 : Configure as GPIO37 */
GPIO_PADREGJ_PAD37FNCSEL_SCCIO = 4, /*!< SCCIO : SCARD serial data input/output */
GPIO_PADREGJ_PAD37FNCSEL_UART1TX = 5, /*!< UART1TX : Configure as the UART1 TX output signal */
GPIO_PADREGJ_PAD37FNCSEL_PDMCLK = 6, /*!< PDMCLK : Configure as the PDM CLK output signal */
GPIO_PADREGJ_PAD37FNCSEL_CT29 = 7, /*!< CT29 : CTIMER connection 29 */
} GPIO_PADREGJ_PAD37FNCSEL_Enum;
/* =========================================== GPIO PADREGJ PAD37STRNG [10..10] ============================================ */
typedef enum { /*!< GPIO_PADREGJ_PAD37STRNG */
GPIO_PADREGJ_PAD37STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGJ_PAD37STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGJ_PAD37STRNG_Enum;
/* ============================================ GPIO PADREGJ PAD37INPEN [9..9] ============================================= */
typedef enum { /*!< GPIO_PADREGJ_PAD37INPEN */
GPIO_PADREGJ_PAD37INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGJ_PAD37INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGJ_PAD37INPEN_Enum;
/* ============================================= GPIO PADREGJ PAD37PULL [8..8] ============================================= */
typedef enum { /*!< GPIO_PADREGJ_PAD37PULL */
GPIO_PADREGJ_PAD37PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGJ_PAD37PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGJ_PAD37PULL_Enum;
/* ============================================ GPIO PADREGJ PAD36PWRUP [6..6] ============================================= */
typedef enum { /*!< GPIO_PADREGJ_PAD36PWRUP */
GPIO_PADREGJ_PAD36PWRUP_DIS = 0, /*!< DIS : Power switch disabled */
GPIO_PADREGJ_PAD36PWRUP_EN = 1, /*!< EN : Power switch enabled (switched to VDD) */
} GPIO_PADREGJ_PAD36PWRUP_Enum;
/* ============================================ GPIO PADREGJ PAD36FNCSEL [3..5] ============================================ */
typedef enum { /*!< GPIO_PADREGJ_PAD36FNCSEL */
GPIO_PADREGJ_PAD36FNCSEL_TRIG1 = 0, /*!< TRIG1 : Configure as the ADC Trigger 1 signal */
GPIO_PADREGJ_PAD36FNCSEL_NCE36 = 1, /*!< NCE36 : IOM/MSPI nCE group 36 */
GPIO_PADREGJ_PAD36FNCSEL_UART1RX = 2, /*!< UART1RX : Configure as the UART1 RX input signal */
GPIO_PADREGJ_PAD36FNCSEL_GPIO36 = 3, /*!< GPIO36 : Configure as GPIO36 */
GPIO_PADREGJ_PAD36FNCSEL_32kHzXT = 4, /*!< 32kHzXT : Configure as the 32kHz output clock from the crystal */
GPIO_PADREGJ_PAD36FNCSEL_UA1CTS = 5, /*!< UA1CTS : Configure as the UART1 CTS input signal */
GPIO_PADREGJ_PAD36FNCSEL_UA0CTS = 6, /*!< UA0CTS : Configure as the UART0 CTS input signal */
GPIO_PADREGJ_PAD36FNCSEL_PDMDATA = 7, /*!< PDMDATA : PDM serial data input */
} GPIO_PADREGJ_PAD36FNCSEL_Enum;
/* ============================================ GPIO PADREGJ PAD36STRNG [2..2] ============================================= */
typedef enum { /*!< GPIO_PADREGJ_PAD36STRNG */
GPIO_PADREGJ_PAD36STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGJ_PAD36STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGJ_PAD36STRNG_Enum;
/* ============================================ GPIO PADREGJ PAD36INPEN [1..1] ============================================= */
typedef enum { /*!< GPIO_PADREGJ_PAD36INPEN */
GPIO_PADREGJ_PAD36INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGJ_PAD36INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGJ_PAD36INPEN_Enum;
/* ============================================= GPIO PADREGJ PAD36PULL [0..0] ============================================= */
typedef enum { /*!< GPIO_PADREGJ_PAD36PULL */
GPIO_PADREGJ_PAD36PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGJ_PAD36PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGJ_PAD36PULL_Enum;
/* ======================================================== PADREGK ======================================================== */
/* ============================================ GPIO PADREGK PAD43RSEL [30..31] ============================================ */
typedef enum { /*!< GPIO_PADREGK_PAD43RSEL */
GPIO_PADREGK_PAD43RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */
GPIO_PADREGK_PAD43RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */
GPIO_PADREGK_PAD43RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */
GPIO_PADREGK_PAD43RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */
} GPIO_PADREGK_PAD43RSEL_Enum;
/* =========================================== GPIO PADREGK PAD43FNCSEL [27..29] =========================================== */
typedef enum { /*!< GPIO_PADREGK_PAD43FNCSEL */
GPIO_PADREGK_PAD43FNCSEL_UART1RX = 0, /*!< UART1RX : Configure as the UART1 RX input signal */
GPIO_PADREGK_PAD43FNCSEL_NCE43 = 1, /*!< NCE43 : IOM/MSPI nCE group 43 */
GPIO_PADREGK_PAD43FNCSEL_CT18 = 2, /*!< CT18 : CTIMER connection 18 */
GPIO_PADREGK_PAD43FNCSEL_GPIO43 = 3, /*!< GPIO43 : Configure as GPIO43 */
GPIO_PADREGK_PAD43FNCSEL_M3SDAWIR3 = 4, /*!< M3SDAWIR3 : Configure as the IOMSTR3 I2C SDA or SPI WIR3 signal */
GPIO_PADREGK_PAD43FNCSEL_M3MISO = 5, /*!< M3MISO : Configure as the IOMSTR3 SPI MISO signal */
} GPIO_PADREGK_PAD43FNCSEL_Enum;
/* =========================================== GPIO PADREGK PAD43STRNG [26..26] ============================================ */
typedef enum { /*!< GPIO_PADREGK_PAD43STRNG */
GPIO_PADREGK_PAD43STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGK_PAD43STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGK_PAD43STRNG_Enum;
/* =========================================== GPIO PADREGK PAD43INPEN [25..25] ============================================ */
typedef enum { /*!< GPIO_PADREGK_PAD43INPEN */
GPIO_PADREGK_PAD43INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGK_PAD43INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGK_PAD43INPEN_Enum;
/* ============================================ GPIO PADREGK PAD43PULL [24..24] ============================================ */
typedef enum { /*!< GPIO_PADREGK_PAD43PULL */
GPIO_PADREGK_PAD43PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGK_PAD43PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGK_PAD43PULL_Enum;
/* ============================================ GPIO PADREGK PAD42RSEL [22..23] ============================================ */
typedef enum { /*!< GPIO_PADREGK_PAD42RSEL */
GPIO_PADREGK_PAD42RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */
GPIO_PADREGK_PAD42RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */
GPIO_PADREGK_PAD42RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */
GPIO_PADREGK_PAD42RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */
} GPIO_PADREGK_PAD42RSEL_Enum;
/* =========================================== GPIO PADREGK PAD42FNCSEL [19..21] =========================================== */
typedef enum { /*!< GPIO_PADREGK_PAD42FNCSEL */
GPIO_PADREGK_PAD42FNCSEL_UART1TX = 0, /*!< UART1TX : Configure as the UART1 TX output signal */
GPIO_PADREGK_PAD42FNCSEL_NCE42 = 1, /*!< NCE42 : IOM/MSPI nCE group 42 */
GPIO_PADREGK_PAD42FNCSEL_CT16 = 2, /*!< CT16 : CTIMER connection 16 */
GPIO_PADREGK_PAD42FNCSEL_GPIO42 = 3, /*!< GPIO42 : Configure as GPIO42 */
GPIO_PADREGK_PAD42FNCSEL_M3SCL = 4, /*!< M3SCL : Configure as the IOMSTR3 I2C SCL clock I/O signal */
GPIO_PADREGK_PAD42FNCSEL_M3SCK = 5, /*!< M3SCK : Configure as the IOMSTR3 SPI SCK output */
} GPIO_PADREGK_PAD42FNCSEL_Enum;
/* =========================================== GPIO PADREGK PAD42STRNG [18..18] ============================================ */
typedef enum { /*!< GPIO_PADREGK_PAD42STRNG */
GPIO_PADREGK_PAD42STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGK_PAD42STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGK_PAD42STRNG_Enum;
/* =========================================== GPIO PADREGK PAD42INPEN [17..17] ============================================ */
typedef enum { /*!< GPIO_PADREGK_PAD42INPEN */
GPIO_PADREGK_PAD42INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGK_PAD42INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGK_PAD42INPEN_Enum;
/* ============================================ GPIO PADREGK PAD42PULL [16..16] ============================================ */
typedef enum { /*!< GPIO_PADREGK_PAD42PULL */
GPIO_PADREGK_PAD42PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGK_PAD42PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGK_PAD42PULL_Enum;
/* =========================================== GPIO PADREGK PAD41PWRDN [15..15] ============================================ */
typedef enum { /*!< GPIO_PADREGK_PAD41PWRDN */
GPIO_PADREGK_PAD41PWRDN_DIS = 0, /*!< DIS : Power switch disabled */
GPIO_PADREGK_PAD41PWRDN_EN = 1, /*!< EN : Power switch enabled (Switch pad to VSS) */
} GPIO_PADREGK_PAD41PWRDN_Enum;
/* =========================================== GPIO PADREGK PAD41FNCSEL [11..13] =========================================== */
typedef enum { /*!< GPIO_PADREGK_PAD41FNCSEL */
GPIO_PADREGK_PAD41FNCSEL_NCE41 = 0, /*!< NCE41 : IOM/MSPI nCE group 41 */
GPIO_PADREGK_PAD41FNCSEL_SWO = 2, /*!< SWO : Configure as the serial wire debug SWO signal */
GPIO_PADREGK_PAD41FNCSEL_GPIO41 = 3, /*!< GPIO41 : Configure as GPIO41 */
GPIO_PADREGK_PAD41FNCSEL_I2SWCLK = 4, /*!< I2SWCLK : I2S word clock input */
GPIO_PADREGK_PAD41FNCSEL_UA1RTS = 5, /*!< UA1RTS : Configure as the UART1 RTS output signal */
GPIO_PADREGK_PAD41FNCSEL_UART0TX = 6, /*!< UART0TX : Configure as the UART0 TX output signal */
GPIO_PADREGK_PAD41FNCSEL_UA0RTS = 7, /*!< UA0RTS : Configure as the UART0 RTS output signal */
} GPIO_PADREGK_PAD41FNCSEL_Enum;
/* =========================================== GPIO PADREGK PAD41STRNG [10..10] ============================================ */
typedef enum { /*!< GPIO_PADREGK_PAD41STRNG */
GPIO_PADREGK_PAD41STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGK_PAD41STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGK_PAD41STRNG_Enum;
/* ============================================ GPIO PADREGK PAD41INPEN [9..9] ============================================= */
typedef enum { /*!< GPIO_PADREGK_PAD41INPEN */
GPIO_PADREGK_PAD41INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGK_PAD41INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGK_PAD41INPEN_Enum;
/* ============================================= GPIO PADREGK PAD41PULL [8..8] ============================================= */
typedef enum { /*!< GPIO_PADREGK_PAD41PULL */
GPIO_PADREGK_PAD41PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGK_PAD41PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGK_PAD41PULL_Enum;
/* ============================================= GPIO PADREGK PAD40RSEL [6..7] ============================================= */
typedef enum { /*!< GPIO_PADREGK_PAD40RSEL */
GPIO_PADREGK_PAD40RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */
GPIO_PADREGK_PAD40RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */
GPIO_PADREGK_PAD40RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */
GPIO_PADREGK_PAD40RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */
} GPIO_PADREGK_PAD40RSEL_Enum;
/* ============================================ GPIO PADREGK PAD40FNCSEL [3..5] ============================================ */
typedef enum { /*!< GPIO_PADREGK_PAD40FNCSEL */
GPIO_PADREGK_PAD40FNCSEL_UART0RX = 0, /*!< UART0RX : Configure as the UART0 RX input signal */
GPIO_PADREGK_PAD40FNCSEL_UART1RX = 1, /*!< UART1RX : Configure as the UART1 RX input signal */
GPIO_PADREGK_PAD40FNCSEL_TRIG0 = 2, /*!< TRIG0 : Configure as the ADC Trigger 0 signal */
GPIO_PADREGK_PAD40FNCSEL_GPIO40 = 3, /*!< GPIO40 : Configure as GPIO40 */
GPIO_PADREGK_PAD40FNCSEL_M4SDAWIR3 = 4, /*!< M4SDAWIR3 : Configure as the IOMSTR4 I2C SDA or SPI WIR3 signal */
GPIO_PADREGK_PAD40FNCSEL_M4MISO = 5, /*!< M4MISO : Configure as the IOMSTR4 SPI MISO input signal */
} GPIO_PADREGK_PAD40FNCSEL_Enum;
/* ============================================ GPIO PADREGK PAD40STRNG [2..2] ============================================= */
typedef enum { /*!< GPIO_PADREGK_PAD40STRNG */
GPIO_PADREGK_PAD40STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGK_PAD40STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGK_PAD40STRNG_Enum;
/* ============================================ GPIO PADREGK PAD40INPEN [1..1] ============================================= */
typedef enum { /*!< GPIO_PADREGK_PAD40INPEN */
GPIO_PADREGK_PAD40INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGK_PAD40INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGK_PAD40INPEN_Enum;
/* ============================================= GPIO PADREGK PAD40PULL [0..0] ============================================= */
typedef enum { /*!< GPIO_PADREGK_PAD40PULL */
GPIO_PADREGK_PAD40PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGK_PAD40PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGK_PAD40PULL_Enum;
/* ======================================================== PADREGL ======================================================== */
/* =========================================== GPIO PADREGL PAD47FNCSEL [27..29] =========================================== */
typedef enum { /*!< GPIO_PADREGL_PAD47FNCSEL */
GPIO_PADREGL_PAD47FNCSEL_32kHzXT = 0, /*!< 32kHzXT : Configure as the 32kHz output clock from the crystal */
GPIO_PADREGL_PAD47FNCSEL_NCE47 = 1, /*!< NCE47 : IOM/MSPI nCE group 47 */
GPIO_PADREGL_PAD47FNCSEL_CT26 = 2, /*!< CT26 : CTIMER connection 26 */
GPIO_PADREGL_PAD47FNCSEL_GPIO47 = 3, /*!< GPIO47 : Configure as GPIO47 */
GPIO_PADREGL_PAD47FNCSEL_M5MOSI = 5, /*!< M5MOSI : Configure as the IOMSTR5 SPI MOSI output signal */
GPIO_PADREGL_PAD47FNCSEL_UART1RX = 6, /*!< UART1RX : Configure as the UART1 RX input signal */
} GPIO_PADREGL_PAD47FNCSEL_Enum;
/* =========================================== GPIO PADREGL PAD47STRNG [26..26] ============================================ */
typedef enum { /*!< GPIO_PADREGL_PAD47STRNG */
GPIO_PADREGL_PAD47STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGL_PAD47STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGL_PAD47STRNG_Enum;
/* =========================================== GPIO PADREGL PAD47INPEN [25..25] ============================================ */
typedef enum { /*!< GPIO_PADREGL_PAD47INPEN */
GPIO_PADREGL_PAD47INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGL_PAD47INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGL_PAD47INPEN_Enum;
/* ============================================ GPIO PADREGL PAD47PULL [24..24] ============================================ */
typedef enum { /*!< GPIO_PADREGL_PAD47PULL */
GPIO_PADREGL_PAD47PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGL_PAD47PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGL_PAD47PULL_Enum;
/* =========================================== GPIO PADREGL PAD46FNCSEL [19..21] =========================================== */
typedef enum { /*!< GPIO_PADREGL_PAD46FNCSEL */
GPIO_PADREGL_PAD46FNCSEL_32khz_XT = 0, /*!< 32khz_XT : Configure as the 32kHz output clock from the crystal */
GPIO_PADREGL_PAD46FNCSEL_NCE46 = 1, /*!< NCE46 : IOM/MSPI nCE group 46 */
GPIO_PADREGL_PAD46FNCSEL_CT24 = 2, /*!< CT24 : CTIMER connection 24 */
GPIO_PADREGL_PAD46FNCSEL_GPIO46 = 3, /*!< GPIO46 : Configure as GPIO46 */
GPIO_PADREGL_PAD46FNCSEL_SCCRST = 4, /*!< SCCRST : SCARD reset output */
GPIO_PADREGL_PAD46FNCSEL_PDMCLK = 5, /*!< PDMCLK : PDM serial clock output */
GPIO_PADREGL_PAD46FNCSEL_UART1TX = 6, /*!< UART1TX : Configure as the UART1 TX output signal */
GPIO_PADREGL_PAD46FNCSEL_SWO = 7, /*!< SWO : Configure as the serial wire debug SWO signal */
} GPIO_PADREGL_PAD46FNCSEL_Enum;
/* =========================================== GPIO PADREGL PAD46STRNG [18..18] ============================================ */
typedef enum { /*!< GPIO_PADREGL_PAD46STRNG */
GPIO_PADREGL_PAD46STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGL_PAD46STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGL_PAD46STRNG_Enum;
/* =========================================== GPIO PADREGL PAD46INPEN [17..17] ============================================ */
typedef enum { /*!< GPIO_PADREGL_PAD46INPEN */
GPIO_PADREGL_PAD46INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGL_PAD46INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGL_PAD46INPEN_Enum;
/* ============================================ GPIO PADREGL PAD46PULL [16..16] ============================================ */
typedef enum { /*!< GPIO_PADREGL_PAD46PULL */
GPIO_PADREGL_PAD46PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGL_PAD46PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGL_PAD46PULL_Enum;
/* =========================================== GPIO PADREGL PAD45FNCSEL [11..13] =========================================== */
typedef enum { /*!< GPIO_PADREGL_PAD45FNCSEL */
GPIO_PADREGL_PAD45FNCSEL_UA1CTS = 0, /*!< UA1CTS : Configure as the UART1 CTS input signal */
GPIO_PADREGL_PAD45FNCSEL_NCE45 = 1, /*!< NCE45 : IOM/MSPI nCE group 45 */
GPIO_PADREGL_PAD45FNCSEL_CT22 = 2, /*!< CT22 : CTIMER connection 22 */
GPIO_PADREGL_PAD45FNCSEL_GPIO45 = 3, /*!< GPIO45 : Configure as GPIO45 */
GPIO_PADREGL_PAD45FNCSEL_I2SDAT = 4, /*!< I2SDAT : I2S serial data output */
GPIO_PADREGL_PAD45FNCSEL_PDMDATA = 5, /*!< PDMDATA : PDM serial data input */
GPIO_PADREGL_PAD45FNCSEL_UART0RX = 6, /*!< UART0RX : Configure as the SPI channel 5 nCE signal from IOMSTR5 */
GPIO_PADREGL_PAD45FNCSEL_SWO = 7, /*!< SWO : Configure as the serial wire debug SWO signal */
} GPIO_PADREGL_PAD45FNCSEL_Enum;
/* =========================================== GPIO PADREGL PAD45STRNG [10..10] ============================================ */
typedef enum { /*!< GPIO_PADREGL_PAD45STRNG */
GPIO_PADREGL_PAD45STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGL_PAD45STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGL_PAD45STRNG_Enum;
/* ============================================ GPIO PADREGL PAD45INPEN [9..9] ============================================= */
typedef enum { /*!< GPIO_PADREGL_PAD45INPEN */
GPIO_PADREGL_PAD45INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGL_PAD45INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGL_PAD45INPEN_Enum;
/* ============================================= GPIO PADREGL PAD45PULL [8..8] ============================================= */
typedef enum { /*!< GPIO_PADREGL_PAD45PULL */
GPIO_PADREGL_PAD45PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGL_PAD45PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGL_PAD45PULL_Enum;
/* ============================================ GPIO PADREGL PAD44FNCSEL [3..5] ============================================ */
typedef enum { /*!< GPIO_PADREGL_PAD44FNCSEL */
GPIO_PADREGL_PAD44FNCSEL_UA1RTS = 0, /*!< UA1RTS : Configure as the UART1 RTS output signal */
GPIO_PADREGL_PAD44FNCSEL_NCE44 = 1, /*!< NCE44 : IOM/MSPI nCE group 44 */
GPIO_PADREGL_PAD44FNCSEL_CT20 = 2, /*!< CT20 : CTIMER connection 20 */
GPIO_PADREGL_PAD44FNCSEL_GPIO44 = 3, /*!< GPIO44 : Configure as GPIO44 */
GPIO_PADREGL_PAD44FNCSEL_M4MOSI = 5, /*!< M4MOSI : Configure as the IOMSTR4 SPI MOSI signal */
GPIO_PADREGL_PAD44FNCSEL_UART0TX = 6, /*!< UART0TX : Configure as the UART0 TX output signal */
} GPIO_PADREGL_PAD44FNCSEL_Enum;
/* ============================================ GPIO PADREGL PAD44STRNG [2..2] ============================================= */
typedef enum { /*!< GPIO_PADREGL_PAD44STRNG */
GPIO_PADREGL_PAD44STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGL_PAD44STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGL_PAD44STRNG_Enum;
/* ============================================ GPIO PADREGL PAD44INPEN [1..1] ============================================= */
typedef enum { /*!< GPIO_PADREGL_PAD44INPEN */
GPIO_PADREGL_PAD44INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGL_PAD44INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGL_PAD44INPEN_Enum;
/* ============================================= GPIO PADREGL PAD44PULL [0..0] ============================================= */
typedef enum { /*!< GPIO_PADREGL_PAD44PULL */
GPIO_PADREGL_PAD44PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGL_PAD44PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGL_PAD44PULL_Enum;
/* ======================================================== PADREGM ======================================================== */
/* ============================================ GPIO PADREGM PAD49RSEL [14..15] ============================================ */
typedef enum { /*!< GPIO_PADREGM_PAD49RSEL */
GPIO_PADREGM_PAD49RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */
GPIO_PADREGM_PAD49RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */
GPIO_PADREGM_PAD49RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */
GPIO_PADREGM_PAD49RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */
} GPIO_PADREGM_PAD49RSEL_Enum;
/* =========================================== GPIO PADREGM PAD49FNCSEL [11..13] =========================================== */
typedef enum { /*!< GPIO_PADREGM_PAD49FNCSEL */
GPIO_PADREGM_PAD49FNCSEL_UART0RX = 0, /*!< UART0RX : Configure as the UART0 RX input signal */
GPIO_PADREGM_PAD49FNCSEL_NCE49 = 1, /*!< NCE49 : IOM/MSPPI nCE group 49 */
GPIO_PADREGM_PAD49FNCSEL_CT30 = 2, /*!< CT30 : CTIMER connection 30 */
GPIO_PADREGM_PAD49FNCSEL_GPIO49 = 3, /*!< GPIO49 : Configure as GPIO49 */
GPIO_PADREGM_PAD49FNCSEL_M5SDAWIR3 = 4, /*!< M5SDAWIR3 : Configure as the IOMSTR5 I2C SDA or SPI WIR3 signal */
GPIO_PADREGM_PAD49FNCSEL_M5MISO = 5, /*!< M5MISO : Configure as the IOMSTR5 SPI MISO input signal */
} GPIO_PADREGM_PAD49FNCSEL_Enum;
/* =========================================== GPIO PADREGM PAD49STRNG [10..10] ============================================ */
typedef enum { /*!< GPIO_PADREGM_PAD49STRNG */
GPIO_PADREGM_PAD49STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGM_PAD49STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGM_PAD49STRNG_Enum;
/* ============================================ GPIO PADREGM PAD49INPEN [9..9] ============================================= */
typedef enum { /*!< GPIO_PADREGM_PAD49INPEN */
GPIO_PADREGM_PAD49INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGM_PAD49INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGM_PAD49INPEN_Enum;
/* ============================================= GPIO PADREGM PAD49PULL [8..8] ============================================= */
typedef enum { /*!< GPIO_PADREGM_PAD49PULL */
GPIO_PADREGM_PAD49PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGM_PAD49PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGM_PAD49PULL_Enum;
/* ============================================= GPIO PADREGM PAD48RSEL [6..7] ============================================= */
typedef enum { /*!< GPIO_PADREGM_PAD48RSEL */
GPIO_PADREGM_PAD48RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */
GPIO_PADREGM_PAD48RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */
GPIO_PADREGM_PAD48RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */
GPIO_PADREGM_PAD48RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */
} GPIO_PADREGM_PAD48RSEL_Enum;
/* ============================================ GPIO PADREGM PAD48FNCSEL [3..5] ============================================ */
typedef enum { /*!< GPIO_PADREGM_PAD48FNCSEL */
GPIO_PADREGM_PAD48FNCSEL_UART0TX = 0, /*!< UART0TX : Configure as the UART0 TX output signal */
GPIO_PADREGM_PAD48FNCSEL_NCE48 = 1, /*!< NCE48 : IOM/MSPI nCE group 48 */
GPIO_PADREGM_PAD48FNCSEL_CT28 = 2, /*!< CT28 : CTIMER conenction 28 */
GPIO_PADREGM_PAD48FNCSEL_GPIO48 = 3, /*!< GPIO48 : Configure as GPIO48 */
GPIO_PADREGM_PAD48FNCSEL_M5SCL = 4, /*!< M5SCL : Configure as the IOMSTR5 I2C SCL clock I/O signal */
GPIO_PADREGM_PAD48FNCSEL_M5SCK = 5, /*!< M5SCK : Configure as the IOMSTR5 SPI SCK output */
} GPIO_PADREGM_PAD48FNCSEL_Enum;
/* ============================================ GPIO PADREGM PAD48STRNG [2..2] ============================================= */
typedef enum { /*!< GPIO_PADREGM_PAD48STRNG */
GPIO_PADREGM_PAD48STRNG_LOW = 0, /*!< LOW : Low drive strength */
GPIO_PADREGM_PAD48STRNG_HIGH = 1, /*!< HIGH : High drive strength */
} GPIO_PADREGM_PAD48STRNG_Enum;
/* ============================================ GPIO PADREGM PAD48INPEN [1..1] ============================================= */
typedef enum { /*!< GPIO_PADREGM_PAD48INPEN */
GPIO_PADREGM_PAD48INPEN_DIS = 0, /*!< DIS : Pad input disabled */
GPIO_PADREGM_PAD48INPEN_EN = 1, /*!< EN : Pad input enabled */
} GPIO_PADREGM_PAD48INPEN_Enum;
/* ============================================= GPIO PADREGM PAD48PULL [0..0] ============================================= */
typedef enum { /*!< GPIO_PADREGM_PAD48PULL */
GPIO_PADREGM_PAD48PULL_DIS = 0, /*!< DIS : Pullup disabled */
GPIO_PADREGM_PAD48PULL_EN = 1, /*!< EN : Pullup enabled */
} GPIO_PADREGM_PAD48PULL_Enum;
/* ========================================================= CFGA ========================================================== */
/* ============================================= GPIO CFGA GPIO7INTD [31..31] ============================================== */
typedef enum { /*!< GPIO_CFGA_GPIO7INTD */
GPIO_CFGA_GPIO7INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x0 - nCE polarity active low */
GPIO_CFGA_GPIO7INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x0 - nCE polarity active high */
} GPIO_CFGA_GPIO7INTD_Enum;
/* ============================================ GPIO CFGA GPIO7OUTCFG [29..30] ============================================= */
typedef enum { /*!< GPIO_CFGA_GPIO7OUTCFG */
GPIO_CFGA_GPIO7OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGA_GPIO7OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGA_GPIO7OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGA_GPIO7OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGA_GPIO7OUTCFG_Enum;
/* ============================================= GPIO CFGA GPIO7INCFG [28..28] ============================================= */
typedef enum { /*!< GPIO_CFGA_GPIO7INCFG */
GPIO_CFGA_GPIO7INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGA_GPIO7INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGA_GPIO7INCFG_Enum;
/* ============================================= GPIO CFGA GPIO6INTD [27..27] ============================================== */
typedef enum { /*!< GPIO_CFGA_GPIO6INTD */
GPIO_CFGA_GPIO6INTD_INTDIS = 0, /*!< INTDIS : INCFG = 1 - No interrupt on GPIO transition */
GPIO_CFGA_GPIO6INTD_INTBOTH = 1, /*!< INTBOTH : INCFG = 1 - Interrupt on either low to high or high
to low GPIO transition */
} GPIO_CFGA_GPIO6INTD_Enum;
/* ============================================ GPIO CFGA GPIO6OUTCFG [25..26] ============================================= */
typedef enum { /*!< GPIO_CFGA_GPIO6OUTCFG */
GPIO_CFGA_GPIO6OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGA_GPIO6OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGA_GPIO6OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGA_GPIO6OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGA_GPIO6OUTCFG_Enum;
/* ============================================= GPIO CFGA GPIO6INCFG [24..24] ============================================= */
typedef enum { /*!< GPIO_CFGA_GPIO6INCFG */
GPIO_CFGA_GPIO6INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGA_GPIO6INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGA_GPIO6INCFG_Enum;
/* ============================================= GPIO CFGA GPIO5INTD [23..23] ============================================== */
typedef enum { /*!< GPIO_CFGA_GPIO5INTD */
GPIO_CFGA_GPIO5INTD_INTDIS = 0, /*!< INTDIS : INCFG = 1 - No interrupt on GPIO transition */
GPIO_CFGA_GPIO5INTD_INTBOTH = 1, /*!< INTBOTH : INCFG = 1 - Interrupt on either low to high or high
to low GPIO transition */
} GPIO_CFGA_GPIO5INTD_Enum;
/* ============================================ GPIO CFGA GPIO5OUTCFG [21..22] ============================================= */
typedef enum { /*!< GPIO_CFGA_GPIO5OUTCFG */
GPIO_CFGA_GPIO5OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGA_GPIO5OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGA_GPIO5OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGA_GPIO5OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGA_GPIO5OUTCFG_Enum;
/* ============================================= GPIO CFGA GPIO5INCFG [20..20] ============================================= */
typedef enum { /*!< GPIO_CFGA_GPIO5INCFG */
GPIO_CFGA_GPIO5INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGA_GPIO5INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGA_GPIO5INCFG_Enum;
/* ============================================= GPIO CFGA GPIO4INTD [19..19] ============================================== */
typedef enum { /*!< GPIO_CFGA_GPIO4INTD */
GPIO_CFGA_GPIO4INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x2 - nCE polarity active low */
GPIO_CFGA_GPIO4INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x2 - nCE polarity active high */
} GPIO_CFGA_GPIO4INTD_Enum;
/* ============================================ GPIO CFGA GPIO4OUTCFG [17..18] ============================================= */
typedef enum { /*!< GPIO_CFGA_GPIO4OUTCFG */
GPIO_CFGA_GPIO4OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGA_GPIO4OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGA_GPIO4OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGA_GPIO4OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGA_GPIO4OUTCFG_Enum;
/* ============================================= GPIO CFGA GPIO4INCFG [16..16] ============================================= */
typedef enum { /*!< GPIO_CFGA_GPIO4INCFG */
GPIO_CFGA_GPIO4INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGA_GPIO4INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGA_GPIO4INCFG_Enum;
/* ============================================= GPIO CFGA GPIO3INTD [15..15] ============================================== */
typedef enum { /*!< GPIO_CFGA_GPIO3INTD */
GPIO_CFGA_GPIO3INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x2 - nCE polarity active low */
GPIO_CFGA_GPIO3INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x2 - nCE polarity active high */
} GPIO_CFGA_GPIO3INTD_Enum;
/* ============================================ GPIO CFGA GPIO3OUTCFG [13..14] ============================================= */
typedef enum { /*!< GPIO_CFGA_GPIO3OUTCFG */
GPIO_CFGA_GPIO3OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGA_GPIO3OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGA_GPIO3OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGA_GPIO3OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGA_GPIO3OUTCFG_Enum;
/* ============================================= GPIO CFGA GPIO3INCFG [12..12] ============================================= */
typedef enum { /*!< GPIO_CFGA_GPIO3INCFG */
GPIO_CFGA_GPIO3INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGA_GPIO3INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGA_GPIO3INCFG_Enum;
/* ============================================= GPIO CFGA GPIO2INTD [11..11] ============================================== */
typedef enum { /*!< GPIO_CFGA_GPIO2INTD */
GPIO_CFGA_GPIO2INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x7 - nCE polarity active low */
GPIO_CFGA_GPIO2INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x7 - nCE polarity active high */
} GPIO_CFGA_GPIO2INTD_Enum;
/* ============================================= GPIO CFGA GPIO2OUTCFG [9..10] ============================================= */
typedef enum { /*!< GPIO_CFGA_GPIO2OUTCFG */
GPIO_CFGA_GPIO2OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGA_GPIO2OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGA_GPIO2OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGA_GPIO2OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGA_GPIO2OUTCFG_Enum;
/* ============================================== GPIO CFGA GPIO2INCFG [8..8] ============================================== */
typedef enum { /*!< GPIO_CFGA_GPIO2INCFG */
GPIO_CFGA_GPIO2INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGA_GPIO2INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGA_GPIO2INCFG_Enum;
/* ============================================== GPIO CFGA GPIO1INTD [7..7] =============================================== */
typedef enum { /*!< GPIO_CFGA_GPIO1INTD */
GPIO_CFGA_GPIO1INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x7 - nCE polarity active low */
GPIO_CFGA_GPIO1INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x7 - nCE polarity active high */
} GPIO_CFGA_GPIO1INTD_Enum;
/* ============================================= GPIO CFGA GPIO1OUTCFG [5..6] ============================================== */
typedef enum { /*!< GPIO_CFGA_GPIO1OUTCFG */
GPIO_CFGA_GPIO1OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGA_GPIO1OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGA_GPIO1OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGA_GPIO1OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGA_GPIO1OUTCFG_Enum;
/* ============================================== GPIO CFGA GPIO1INCFG [4..4] ============================================== */
typedef enum { /*!< GPIO_CFGA_GPIO1INCFG */
GPIO_CFGA_GPIO1INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGA_GPIO1INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGA_GPIO1INCFG_Enum;
/* ============================================== GPIO CFGA GPIO0INTD [3..3] =============================================== */
typedef enum { /*!< GPIO_CFGA_GPIO0INTD */
GPIO_CFGA_GPIO0INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x7 - nCE polarity active low */
GPIO_CFGA_GPIO0INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x7 - nCE polarity active high */
} GPIO_CFGA_GPIO0INTD_Enum;
/* ============================================= GPIO CFGA GPIO0OUTCFG [1..2] ============================================== */
typedef enum { /*!< GPIO_CFGA_GPIO0OUTCFG */
GPIO_CFGA_GPIO0OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGA_GPIO0OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGA_GPIO0OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGA_GPIO0OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGA_GPIO0OUTCFG_Enum;
/* ============================================== GPIO CFGA GPIO0INCFG [0..0] ============================================== */
typedef enum { /*!< GPIO_CFGA_GPIO0INCFG */
GPIO_CFGA_GPIO0INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGA_GPIO0INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGA_GPIO0INCFG_Enum;
/* ========================================================= CFGB ========================================================== */
/* ============================================= GPIO CFGB GPIO15INTD [31..31] ============================================= */
typedef enum { /*!< GPIO_CFGB_GPIO15INTD */
GPIO_CFGB_GPIO15INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */
GPIO_CFGB_GPIO15INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */
} GPIO_CFGB_GPIO15INTD_Enum;
/* ============================================ GPIO CFGB GPIO15OUTCFG [29..30] ============================================ */
typedef enum { /*!< GPIO_CFGB_GPIO15OUTCFG */
GPIO_CFGB_GPIO15OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGB_GPIO15OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGB_GPIO15OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGB_GPIO15OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGB_GPIO15OUTCFG_Enum;
/* ============================================ GPIO CFGB GPIO15INCFG [28..28] ============================================= */
typedef enum { /*!< GPIO_CFGB_GPIO15INCFG */
GPIO_CFGB_GPIO15INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGB_GPIO15INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGB_GPIO15INCFG_Enum;
/* ============================================= GPIO CFGB GPIO14INTD [27..27] ============================================= */
typedef enum { /*!< GPIO_CFGB_GPIO14INTD */
GPIO_CFGB_GPIO14INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */
GPIO_CFGB_GPIO14INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */
} GPIO_CFGB_GPIO14INTD_Enum;
/* ============================================ GPIO CFGB GPIO14OUTCFG [25..26] ============================================ */
typedef enum { /*!< GPIO_CFGB_GPIO14OUTCFG */
GPIO_CFGB_GPIO14OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGB_GPIO14OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGB_GPIO14OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGB_GPIO14OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGB_GPIO14OUTCFG_Enum;
/* ============================================ GPIO CFGB GPIO14INCFG [24..24] ============================================= */
typedef enum { /*!< GPIO_CFGB_GPIO14INCFG */
GPIO_CFGB_GPIO14INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGB_GPIO14INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGB_GPIO14INCFG_Enum;
/* ============================================= GPIO CFGB GPIO13INTD [23..23] ============================================= */
typedef enum { /*!< GPIO_CFGB_GPIO13INTD */
GPIO_CFGB_GPIO13INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */
GPIO_CFGB_GPIO13INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */
} GPIO_CFGB_GPIO13INTD_Enum;
/* ============================================ GPIO CFGB GPIO13OUTCFG [21..22] ============================================ */
typedef enum { /*!< GPIO_CFGB_GPIO13OUTCFG */
GPIO_CFGB_GPIO13OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGB_GPIO13OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGB_GPIO13OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGB_GPIO13OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGB_GPIO13OUTCFG_Enum;
/* ============================================ GPIO CFGB GPIO13INCFG [20..20] ============================================= */
typedef enum { /*!< GPIO_CFGB_GPIO13INCFG */
GPIO_CFGB_GPIO13INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGB_GPIO13INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGB_GPIO13INCFG_Enum;
/* ============================================= GPIO CFGB GPIO12INTD [19..19] ============================================= */
typedef enum { /*!< GPIO_CFGB_GPIO12INTD */
GPIO_CFGB_GPIO12INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */
GPIO_CFGB_GPIO12INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */
} GPIO_CFGB_GPIO12INTD_Enum;
/* ============================================ GPIO CFGB GPIO12OUTCFG [17..18] ============================================ */
typedef enum { /*!< GPIO_CFGB_GPIO12OUTCFG */
GPIO_CFGB_GPIO12OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGB_GPIO12OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGB_GPIO12OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGB_GPIO12OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGB_GPIO12OUTCFG_Enum;
/* ============================================ GPIO CFGB GPIO12INCFG [16..16] ============================================= */
typedef enum { /*!< GPIO_CFGB_GPIO12INCFG */
GPIO_CFGB_GPIO12INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGB_GPIO12INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGB_GPIO12INCFG_Enum;
/* ============================================= GPIO CFGB GPIO11INTD [15..15] ============================================= */
typedef enum { /*!< GPIO_CFGB_GPIO11INTD */
GPIO_CFGB_GPIO11INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */
GPIO_CFGB_GPIO11INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */
} GPIO_CFGB_GPIO11INTD_Enum;
/* ============================================ GPIO CFGB GPIO11OUTCFG [13..14] ============================================ */
typedef enum { /*!< GPIO_CFGB_GPIO11OUTCFG */
GPIO_CFGB_GPIO11OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGB_GPIO11OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGB_GPIO11OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGB_GPIO11OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGB_GPIO11OUTCFG_Enum;
/* ============================================ GPIO CFGB GPIO11INCFG [12..12] ============================================= */
typedef enum { /*!< GPIO_CFGB_GPIO11INCFG */
GPIO_CFGB_GPIO11INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGB_GPIO11INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGB_GPIO11INCFG_Enum;
/* ============================================= GPIO CFGB GPIO10INTD [11..11] ============================================= */
typedef enum { /*!< GPIO_CFGB_GPIO10INTD */
GPIO_CFGB_GPIO10INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x2 - nCE polarity active low */
GPIO_CFGB_GPIO10INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x2 - nCE polarity active high */
} GPIO_CFGB_GPIO10INTD_Enum;
/* ============================================ GPIO CFGB GPIO10OUTCFG [9..10] ============================================= */
typedef enum { /*!< GPIO_CFGB_GPIO10OUTCFG */
GPIO_CFGB_GPIO10OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGB_GPIO10OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGB_GPIO10OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGB_GPIO10OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGB_GPIO10OUTCFG_Enum;
/* ============================================= GPIO CFGB GPIO10INCFG [8..8] ============================================== */
typedef enum { /*!< GPIO_CFGB_GPIO10INCFG */
GPIO_CFGB_GPIO10INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGB_GPIO10INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGB_GPIO10INCFG_Enum;
/* ============================================== GPIO CFGB GPIO9INTD [7..7] =============================================== */
typedef enum { /*!< GPIO_CFGB_GPIO9INTD */
GPIO_CFGB_GPIO9INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x2 - nCE polarity active low */
GPIO_CFGB_GPIO9INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x2 - nCE polarity active high */
} GPIO_CFGB_GPIO9INTD_Enum;
/* ============================================= GPIO CFGB GPIO9OUTCFG [5..6] ============================================== */
typedef enum { /*!< GPIO_CFGB_GPIO9OUTCFG */
GPIO_CFGB_GPIO9OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGB_GPIO9OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGB_GPIO9OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGB_GPIO9OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGB_GPIO9OUTCFG_Enum;
/* ============================================== GPIO CFGB GPIO9INCFG [4..4] ============================================== */
typedef enum { /*!< GPIO_CFGB_GPIO9INCFG */
GPIO_CFGB_GPIO9INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGB_GPIO9INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGB_GPIO9INCFG_Enum;
/* ============================================== GPIO CFGB GPIO8INTD [3..3] =============================================== */
typedef enum { /*!< GPIO_CFGB_GPIO8INTD */
GPIO_CFGB_GPIO8INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x2 - nCE polarity active low */
GPIO_CFGB_GPIO8INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x2 - nCE polarity active high */
} GPIO_CFGB_GPIO8INTD_Enum;
/* ============================================= GPIO CFGB GPIO8OUTCFG [1..2] ============================================== */
typedef enum { /*!< GPIO_CFGB_GPIO8OUTCFG */
GPIO_CFGB_GPIO8OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGB_GPIO8OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGB_GPIO8OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGB_GPIO8OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGB_GPIO8OUTCFG_Enum;
/* ============================================== GPIO CFGB GPIO8INCFG [0..0] ============================================== */
typedef enum { /*!< GPIO_CFGB_GPIO8INCFG */
GPIO_CFGB_GPIO8INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGB_GPIO8INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGB_GPIO8INCFG_Enum;
/* ========================================================= CFGC ========================================================== */
/* ============================================= GPIO CFGC GPIO23INTD [31..31] ============================================= */
typedef enum { /*!< GPIO_CFGC_GPIO23INTD */
GPIO_CFGC_GPIO23INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */
GPIO_CFGC_GPIO23INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */
} GPIO_CFGC_GPIO23INTD_Enum;
/* ============================================ GPIO CFGC GPIO23OUTCFG [29..30] ============================================ */
typedef enum { /*!< GPIO_CFGC_GPIO23OUTCFG */
GPIO_CFGC_GPIO23OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGC_GPIO23OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGC_GPIO23OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGC_GPIO23OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGC_GPIO23OUTCFG_Enum;
/* ============================================ GPIO CFGC GPIO23INCFG [28..28] ============================================= */
typedef enum { /*!< GPIO_CFGC_GPIO23INCFG */
GPIO_CFGC_GPIO23INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGC_GPIO23INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGC_GPIO23INCFG_Enum;
/* ============================================= GPIO CFGC GPIO22INTD [27..27] ============================================= */
typedef enum { /*!< GPIO_CFGC_GPIO22INTD */
GPIO_CFGC_GPIO22INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */
GPIO_CFGC_GPIO22INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */
} GPIO_CFGC_GPIO22INTD_Enum;
/* ============================================ GPIO CFGC GPIO22OUTCFG [25..26] ============================================ */
typedef enum { /*!< GPIO_CFGC_GPIO22OUTCFG */
GPIO_CFGC_GPIO22OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGC_GPIO22OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGC_GPIO22OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGC_GPIO22OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGC_GPIO22OUTCFG_Enum;
/* ============================================ GPIO CFGC GPIO22INCFG [24..24] ============================================= */
typedef enum { /*!< GPIO_CFGC_GPIO22INCFG */
GPIO_CFGC_GPIO22INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGC_GPIO22INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGC_GPIO22INCFG_Enum;
/* ============================================= GPIO CFGC GPIO21INTD [23..23] ============================================= */
typedef enum { /*!< GPIO_CFGC_GPIO21INTD */
GPIO_CFGC_GPIO21INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */
GPIO_CFGC_GPIO21INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */
} GPIO_CFGC_GPIO21INTD_Enum;
/* ============================================ GPIO CFGC GPIO21OUTCFG [21..22] ============================================ */
typedef enum { /*!< GPIO_CFGC_GPIO21OUTCFG */
GPIO_CFGC_GPIO21OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGC_GPIO21OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGC_GPIO21OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGC_GPIO21OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGC_GPIO21OUTCFG_Enum;
/* ============================================ GPIO CFGC GPIO21INCFG [20..20] ============================================= */
typedef enum { /*!< GPIO_CFGC_GPIO21INCFG */
GPIO_CFGC_GPIO21INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGC_GPIO21INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGC_GPIO21INCFG_Enum;
/* ============================================= GPIO CFGC GPIO20INTD [19..19] ============================================= */
typedef enum { /*!< GPIO_CFGC_GPIO20INTD */
GPIO_CFGC_GPIO20INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */
GPIO_CFGC_GPIO20INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */
} GPIO_CFGC_GPIO20INTD_Enum;
/* ============================================ GPIO CFGC GPIO20OUTCFG [17..18] ============================================ */
typedef enum { /*!< GPIO_CFGC_GPIO20OUTCFG */
GPIO_CFGC_GPIO20OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGC_GPIO20OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGC_GPIO20OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGC_GPIO20OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGC_GPIO20OUTCFG_Enum;
/* ============================================ GPIO CFGC GPIO20INCFG [16..16] ============================================= */
typedef enum { /*!< GPIO_CFGC_GPIO20INCFG */
GPIO_CFGC_GPIO20INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGC_GPIO20INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGC_GPIO20INCFG_Enum;
/* ============================================= GPIO CFGC GPIO19INTD [15..15] ============================================= */
typedef enum { /*!< GPIO_CFGC_GPIO19INTD */
GPIO_CFGC_GPIO19INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */
GPIO_CFGC_GPIO19INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */
} GPIO_CFGC_GPIO19INTD_Enum;
/* ============================================ GPIO CFGC GPIO19OUTCFG [13..14] ============================================ */
typedef enum { /*!< GPIO_CFGC_GPIO19OUTCFG */
GPIO_CFGC_GPIO19OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGC_GPIO19OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGC_GPIO19OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGC_GPIO19OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGC_GPIO19OUTCFG_Enum;
/* ============================================ GPIO CFGC GPIO19INCFG [12..12] ============================================= */
typedef enum { /*!< GPIO_CFGC_GPIO19INCFG */
GPIO_CFGC_GPIO19INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGC_GPIO19INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGC_GPIO19INCFG_Enum;
/* ============================================= GPIO CFGC GPIO18INTD [11..11] ============================================= */
typedef enum { /*!< GPIO_CFGC_GPIO18INTD */
GPIO_CFGC_GPIO18INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */
GPIO_CFGC_GPIO18INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */
} GPIO_CFGC_GPIO18INTD_Enum;
/* ============================================ GPIO CFGC GPIO18OUTCFG [9..10] ============================================= */
typedef enum { /*!< GPIO_CFGC_GPIO18OUTCFG */
GPIO_CFGC_GPIO18OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGC_GPIO18OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGC_GPIO18OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGC_GPIO18OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGC_GPIO18OUTCFG_Enum;
/* ============================================= GPIO CFGC GPIO18INCFG [8..8] ============================================== */
typedef enum { /*!< GPIO_CFGC_GPIO18INCFG */
GPIO_CFGC_GPIO18INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGC_GPIO18INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGC_GPIO18INCFG_Enum;
/* ============================================== GPIO CFGC GPIO17INTD [7..7] ============================================== */
typedef enum { /*!< GPIO_CFGC_GPIO17INTD */
GPIO_CFGC_GPIO17INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */
GPIO_CFGC_GPIO17INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */
} GPIO_CFGC_GPIO17INTD_Enum;
/* ============================================= GPIO CFGC GPIO17OUTCFG [5..6] ============================================= */
typedef enum { /*!< GPIO_CFGC_GPIO17OUTCFG */
GPIO_CFGC_GPIO17OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGC_GPIO17OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGC_GPIO17OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGC_GPIO17OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGC_GPIO17OUTCFG_Enum;
/* ============================================= GPIO CFGC GPIO17INCFG [4..4] ============================================== */
typedef enum { /*!< GPIO_CFGC_GPIO17INCFG */
GPIO_CFGC_GPIO17INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGC_GPIO17INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGC_GPIO17INCFG_Enum;
/* ============================================== GPIO CFGC GPIO16INTD [3..3] ============================================== */
typedef enum { /*!< GPIO_CFGC_GPIO16INTD */
GPIO_CFGC_GPIO16INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */
GPIO_CFGC_GPIO16INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */
} GPIO_CFGC_GPIO16INTD_Enum;
/* ============================================= GPIO CFGC GPIO16OUTCFG [1..2] ============================================= */
typedef enum { /*!< GPIO_CFGC_GPIO16OUTCFG */
GPIO_CFGC_GPIO16OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGC_GPIO16OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGC_GPIO16OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGC_GPIO16OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGC_GPIO16OUTCFG_Enum;
/* ============================================= GPIO CFGC GPIO16INCFG [0..0] ============================================== */
typedef enum { /*!< GPIO_CFGC_GPIO16INCFG */
GPIO_CFGC_GPIO16INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGC_GPIO16INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGC_GPIO16INCFG_Enum;
/* ========================================================= CFGD ========================================================== */
/* ============================================= GPIO CFGD GPIO31INTD [31..31] ============================================= */
typedef enum { /*!< GPIO_CFGD_GPIO31INTD */
GPIO_CFGD_GPIO31INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */
GPIO_CFGD_GPIO31INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */
} GPIO_CFGD_GPIO31INTD_Enum;
/* ============================================ GPIO CFGD GPIO31OUTCFG [29..30] ============================================ */
typedef enum { /*!< GPIO_CFGD_GPIO31OUTCFG */
GPIO_CFGD_GPIO31OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGD_GPIO31OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGD_GPIO31OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGD_GPIO31OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGD_GPIO31OUTCFG_Enum;
/* ============================================ GPIO CFGD GPIO31INCFG [28..28] ============================================= */
typedef enum { /*!< GPIO_CFGD_GPIO31INCFG */
GPIO_CFGD_GPIO31INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGD_GPIO31INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGD_GPIO31INCFG_Enum;
/* ============================================= GPIO CFGD GPIO30INTD [27..27] ============================================= */
typedef enum { /*!< GPIO_CFGD_GPIO30INTD */
GPIO_CFGD_GPIO30INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */
GPIO_CFGD_GPIO30INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */
} GPIO_CFGD_GPIO30INTD_Enum;
/* ============================================ GPIO CFGD GPIO30OUTCFG [25..26] ============================================ */
typedef enum { /*!< GPIO_CFGD_GPIO30OUTCFG */
GPIO_CFGD_GPIO30OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGD_GPIO30OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGD_GPIO30OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGD_GPIO30OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGD_GPIO30OUTCFG_Enum;
/* ============================================ GPIO CFGD GPIO30INCFG [24..24] ============================================= */
typedef enum { /*!< GPIO_CFGD_GPIO30INCFG */
GPIO_CFGD_GPIO30INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGD_GPIO30INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGD_GPIO30INCFG_Enum;
/* ============================================= GPIO CFGD GPIO29INTD [23..23] ============================================= */
typedef enum { /*!< GPIO_CFGD_GPIO29INTD */
GPIO_CFGD_GPIO29INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */
GPIO_CFGD_GPIO29INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */
} GPIO_CFGD_GPIO29INTD_Enum;
/* ============================================ GPIO CFGD GPIO29OUTCFG [21..22] ============================================ */
typedef enum { /*!< GPIO_CFGD_GPIO29OUTCFG */
GPIO_CFGD_GPIO29OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGD_GPIO29OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGD_GPIO29OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGD_GPIO29OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGD_GPIO29OUTCFG_Enum;
/* ============================================ GPIO CFGD GPIO29INCFG [20..20] ============================================= */
typedef enum { /*!< GPIO_CFGD_GPIO29INCFG */
GPIO_CFGD_GPIO29INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGD_GPIO29INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGD_GPIO29INCFG_Enum;
/* ============================================= GPIO CFGD GPIO28INTD [19..19] ============================================= */
typedef enum { /*!< GPIO_CFGD_GPIO28INTD */
GPIO_CFGD_GPIO28INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */
GPIO_CFGD_GPIO28INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */
} GPIO_CFGD_GPIO28INTD_Enum;
/* ============================================ GPIO CFGD GPIO28OUTCFG [17..18] ============================================ */
typedef enum { /*!< GPIO_CFGD_GPIO28OUTCFG */
GPIO_CFGD_GPIO28OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGD_GPIO28OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGD_GPIO28OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGD_GPIO28OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGD_GPIO28OUTCFG_Enum;
/* ============================================ GPIO CFGD GPIO28INCFG [16..16] ============================================= */
typedef enum { /*!< GPIO_CFGD_GPIO28INCFG */
GPIO_CFGD_GPIO28INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGD_GPIO28INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGD_GPIO28INCFG_Enum;
/* ============================================= GPIO CFGD GPIO27INTD [15..15] ============================================= */
typedef enum { /*!< GPIO_CFGD_GPIO27INTD */
GPIO_CFGD_GPIO27INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */
GPIO_CFGD_GPIO27INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */
} GPIO_CFGD_GPIO27INTD_Enum;
/* ============================================ GPIO CFGD GPIO27OUTCFG [13..14] ============================================ */
typedef enum { /*!< GPIO_CFGD_GPIO27OUTCFG */
GPIO_CFGD_GPIO27OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGD_GPIO27OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGD_GPIO27OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGD_GPIO27OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGD_GPIO27OUTCFG_Enum;
/* ============================================ GPIO CFGD GPIO27INCFG [12..12] ============================================= */
typedef enum { /*!< GPIO_CFGD_GPIO27INCFG */
GPIO_CFGD_GPIO27INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGD_GPIO27INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGD_GPIO27INCFG_Enum;
/* ============================================= GPIO CFGD GPIO26INTD [11..11] ============================================= */
typedef enum { /*!< GPIO_CFGD_GPIO26INTD */
GPIO_CFGD_GPIO26INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */
GPIO_CFGD_GPIO26INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */
} GPIO_CFGD_GPIO26INTD_Enum;
/* ============================================ GPIO CFGD GPIO26OUTCFG [9..10] ============================================= */
typedef enum { /*!< GPIO_CFGD_GPIO26OUTCFG */
GPIO_CFGD_GPIO26OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGD_GPIO26OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGD_GPIO26OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGD_GPIO26OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGD_GPIO26OUTCFG_Enum;
/* ============================================= GPIO CFGD GPIO26INCFG [8..8] ============================================== */
typedef enum { /*!< GPIO_CFGD_GPIO26INCFG */
GPIO_CFGD_GPIO26INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGD_GPIO26INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGD_GPIO26INCFG_Enum;
/* ============================================== GPIO CFGD GPIO25INTD [7..7] ============================================== */
typedef enum { /*!< GPIO_CFGD_GPIO25INTD */
GPIO_CFGD_GPIO25INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */
GPIO_CFGD_GPIO25INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */
} GPIO_CFGD_GPIO25INTD_Enum;
/* ============================================= GPIO CFGD GPIO25OUTCFG [5..6] ============================================= */
typedef enum { /*!< GPIO_CFGD_GPIO25OUTCFG */
GPIO_CFGD_GPIO25OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGD_GPIO25OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGD_GPIO25OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGD_GPIO25OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGD_GPIO25OUTCFG_Enum;
/* ============================================= GPIO CFGD GPIO25INCFG [4..4] ============================================== */
typedef enum { /*!< GPIO_CFGD_GPIO25INCFG */
GPIO_CFGD_GPIO25INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGD_GPIO25INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGD_GPIO25INCFG_Enum;
/* ============================================== GPIO CFGD GPIO24INTD [3..3] ============================================== */
typedef enum { /*!< GPIO_CFGD_GPIO24INTD */
GPIO_CFGD_GPIO24INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */
GPIO_CFGD_GPIO24INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */
} GPIO_CFGD_GPIO24INTD_Enum;
/* ============================================= GPIO CFGD GPIO24OUTCFG [1..2] ============================================= */
typedef enum { /*!< GPIO_CFGD_GPIO24OUTCFG */
GPIO_CFGD_GPIO24OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGD_GPIO24OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGD_GPIO24OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGD_GPIO24OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGD_GPIO24OUTCFG_Enum;
/* ============================================= GPIO CFGD GPIO24INCFG [0..0] ============================================== */
typedef enum { /*!< GPIO_CFGD_GPIO24INCFG */
GPIO_CFGD_GPIO24INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGD_GPIO24INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGD_GPIO24INCFG_Enum;
/* ========================================================= CFGE ========================================================== */
/* ============================================= GPIO CFGE GPIO39INTD [31..31] ============================================= */
typedef enum { /*!< GPIO_CFGE_GPIO39INTD */
GPIO_CFGE_GPIO39INTD_INTDIS = 0, /*!< INTDIS : INCFG = 1 - No interrupt on GPIO transition */
GPIO_CFGE_GPIO39INTD_INTBOTH = 1, /*!< INTBOTH : INCFG = 1 - Interrupt on either low to high or high
to low GPIO transition */
} GPIO_CFGE_GPIO39INTD_Enum;
/* ============================================ GPIO CFGE GPIO39OUTCFG [29..30] ============================================ */
typedef enum { /*!< GPIO_CFGE_GPIO39OUTCFG */
GPIO_CFGE_GPIO39OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGE_GPIO39OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGE_GPIO39OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGE_GPIO39OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGE_GPIO39OUTCFG_Enum;
/* ============================================ GPIO CFGE GPIO39INCFG [28..28] ============================================= */
typedef enum { /*!< GPIO_CFGE_GPIO39INCFG */
GPIO_CFGE_GPIO39INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGE_GPIO39INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGE_GPIO39INCFG_Enum;
/* ============================================= GPIO CFGE GPIO38INTD [27..27] ============================================= */
typedef enum { /*!< GPIO_CFGE_GPIO38INTD */
GPIO_CFGE_GPIO38INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */
GPIO_CFGE_GPIO38INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */
} GPIO_CFGE_GPIO38INTD_Enum;
/* ============================================ GPIO CFGE GPIO38OUTCFG [25..26] ============================================ */
typedef enum { /*!< GPIO_CFGE_GPIO38OUTCFG */
GPIO_CFGE_GPIO38OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGE_GPIO38OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGE_GPIO38OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGE_GPIO38OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGE_GPIO38OUTCFG_Enum;
/* ============================================ GPIO CFGE GPIO38INCFG [24..24] ============================================= */
typedef enum { /*!< GPIO_CFGE_GPIO38INCFG */
GPIO_CFGE_GPIO38INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGE_GPIO38INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGE_GPIO38INCFG_Enum;
/* ============================================= GPIO CFGE GPIO37INTD [23..23] ============================================= */
typedef enum { /*!< GPIO_CFGE_GPIO37INTD */
GPIO_CFGE_GPIO37INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */
GPIO_CFGE_GPIO37INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */
} GPIO_CFGE_GPIO37INTD_Enum;
/* ============================================ GPIO CFGE GPIO37OUTCFG [21..22] ============================================ */
typedef enum { /*!< GPIO_CFGE_GPIO37OUTCFG */
GPIO_CFGE_GPIO37OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGE_GPIO37OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGE_GPIO37OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGE_GPIO37OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGE_GPIO37OUTCFG_Enum;
/* ============================================ GPIO CFGE GPIO37INCFG [20..20] ============================================= */
typedef enum { /*!< GPIO_CFGE_GPIO37INCFG */
GPIO_CFGE_GPIO37INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGE_GPIO37INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGE_GPIO37INCFG_Enum;
/* ============================================= GPIO CFGE GPIO36INTD [19..19] ============================================= */
typedef enum { /*!< GPIO_CFGE_GPIO36INTD */
GPIO_CFGE_GPIO36INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */
GPIO_CFGE_GPIO36INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */
} GPIO_CFGE_GPIO36INTD_Enum;
/* ============================================ GPIO CFGE GPIO36OUTCFG [17..18] ============================================ */
typedef enum { /*!< GPIO_CFGE_GPIO36OUTCFG */
GPIO_CFGE_GPIO36OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGE_GPIO36OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGE_GPIO36OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGE_GPIO36OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGE_GPIO36OUTCFG_Enum;
/* ============================================ GPIO CFGE GPIO36INCFG [16..16] ============================================= */
typedef enum { /*!< GPIO_CFGE_GPIO36INCFG */
GPIO_CFGE_GPIO36INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGE_GPIO36INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGE_GPIO36INCFG_Enum;
/* ============================================= GPIO CFGE GPIO35INTD [15..15] ============================================= */
typedef enum { /*!< GPIO_CFGE_GPIO35INTD */
GPIO_CFGE_GPIO35INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */
GPIO_CFGE_GPIO35INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */
} GPIO_CFGE_GPIO35INTD_Enum;
/* ============================================ GPIO CFGE GPIO35OUTCFG [13..14] ============================================ */
typedef enum { /*!< GPIO_CFGE_GPIO35OUTCFG */
GPIO_CFGE_GPIO35OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGE_GPIO35OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGE_GPIO35OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGE_GPIO35OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGE_GPIO35OUTCFG_Enum;
/* ============================================ GPIO CFGE GPIO35INCFG [12..12] ============================================= */
typedef enum { /*!< GPIO_CFGE_GPIO35INCFG */
GPIO_CFGE_GPIO35INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGE_GPIO35INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGE_GPIO35INCFG_Enum;
/* ============================================= GPIO CFGE GPIO34INTD [11..11] ============================================= */
typedef enum { /*!< GPIO_CFGE_GPIO34INTD */
GPIO_CFGE_GPIO34INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */
GPIO_CFGE_GPIO34INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */
} GPIO_CFGE_GPIO34INTD_Enum;
/* ============================================ GPIO CFGE GPIO34OUTCFG [9..10] ============================================= */
typedef enum { /*!< GPIO_CFGE_GPIO34OUTCFG */
GPIO_CFGE_GPIO34OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGE_GPIO34OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGE_GPIO34OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGE_GPIO34OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGE_GPIO34OUTCFG_Enum;
/* ============================================= GPIO CFGE GPIO34INCFG [8..8] ============================================== */
typedef enum { /*!< GPIO_CFGE_GPIO34INCFG */
GPIO_CFGE_GPIO34INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGE_GPIO34INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGE_GPIO34INCFG_Enum;
/* ============================================== GPIO CFGE GPIO33INTD [7..7] ============================================== */
typedef enum { /*!< GPIO_CFGE_GPIO33INTD */
GPIO_CFGE_GPIO33INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */
GPIO_CFGE_GPIO33INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */
} GPIO_CFGE_GPIO33INTD_Enum;
/* ============================================= GPIO CFGE GPIO33OUTCFG [5..6] ============================================= */
typedef enum { /*!< GPIO_CFGE_GPIO33OUTCFG */
GPIO_CFGE_GPIO33OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGE_GPIO33OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGE_GPIO33OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGE_GPIO33OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGE_GPIO33OUTCFG_Enum;
/* ============================================= GPIO CFGE GPIO33INCFG [4..4] ============================================== */
typedef enum { /*!< GPIO_CFGE_GPIO33INCFG */
GPIO_CFGE_GPIO33INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGE_GPIO33INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGE_GPIO33INCFG_Enum;
/* ============================================== GPIO CFGE GPIO32INTD [3..3] ============================================== */
typedef enum { /*!< GPIO_CFGE_GPIO32INTD */
GPIO_CFGE_GPIO32INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */
GPIO_CFGE_GPIO32INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */
} GPIO_CFGE_GPIO32INTD_Enum;
/* ============================================= GPIO CFGE GPIO32OUTCFG [1..2] ============================================= */
typedef enum { /*!< GPIO_CFGE_GPIO32OUTCFG */
GPIO_CFGE_GPIO32OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGE_GPIO32OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGE_GPIO32OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGE_GPIO32OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGE_GPIO32OUTCFG_Enum;
/* ============================================= GPIO CFGE GPIO32INCFG [0..0] ============================================== */
typedef enum { /*!< GPIO_CFGE_GPIO32INCFG */
GPIO_CFGE_GPIO32INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGE_GPIO32INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGE_GPIO32INCFG_Enum;
/* ========================================================= CFGF ========================================================== */
/* ============================================= GPIO CFGF GPIO47INTD [31..31] ============================================= */
typedef enum { /*!< GPIO_CFGF_GPIO47INTD */
GPIO_CFGF_GPIO47INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */
GPIO_CFGF_GPIO47INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */
} GPIO_CFGF_GPIO47INTD_Enum;
/* ============================================ GPIO CFGF GPIO47OUTCFG [29..30] ============================================ */
typedef enum { /*!< GPIO_CFGF_GPIO47OUTCFG */
GPIO_CFGF_GPIO47OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGF_GPIO47OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGF_GPIO47OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGF_GPIO47OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGF_GPIO47OUTCFG_Enum;
/* ============================================ GPIO CFGF GPIO47INCFG [28..28] ============================================= */
typedef enum { /*!< GPIO_CFGF_GPIO47INCFG */
GPIO_CFGF_GPIO47INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGF_GPIO47INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGF_GPIO47INCFG_Enum;
/* ============================================= GPIO CFGF GPIO46INTD [27..27] ============================================= */
typedef enum { /*!< GPIO_CFGF_GPIO46INTD */
GPIO_CFGF_GPIO46INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */
GPIO_CFGF_GPIO46INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */
} GPIO_CFGF_GPIO46INTD_Enum;
/* ============================================ GPIO CFGF GPIO46OUTCFG [25..26] ============================================ */
typedef enum { /*!< GPIO_CFGF_GPIO46OUTCFG */
GPIO_CFGF_GPIO46OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGF_GPIO46OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGF_GPIO46OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGF_GPIO46OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGF_GPIO46OUTCFG_Enum;
/* ============================================ GPIO CFGF GPIO46INCFG [24..24] ============================================= */
typedef enum { /*!< GPIO_CFGF_GPIO46INCFG */
GPIO_CFGF_GPIO46INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGF_GPIO46INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGF_GPIO46INCFG_Enum;
/* ============================================= GPIO CFGF GPIO45INTD [23..23] ============================================= */
typedef enum { /*!< GPIO_CFGF_GPIO45INTD */
GPIO_CFGF_GPIO45INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */
GPIO_CFGF_GPIO45INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */
} GPIO_CFGF_GPIO45INTD_Enum;
/* ============================================ GPIO CFGF GPIO45OUTCFG [21..22] ============================================ */
typedef enum { /*!< GPIO_CFGF_GPIO45OUTCFG */
GPIO_CFGF_GPIO45OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGF_GPIO45OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGF_GPIO45OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGF_GPIO45OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGF_GPIO45OUTCFG_Enum;
/* ============================================ GPIO CFGF GPIO45INCFG [20..20] ============================================= */
typedef enum { /*!< GPIO_CFGF_GPIO45INCFG */
GPIO_CFGF_GPIO45INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGF_GPIO45INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGF_GPIO45INCFG_Enum;
/* ============================================= GPIO CFGF GPIO44INTD [19..19] ============================================= */
typedef enum { /*!< GPIO_CFGF_GPIO44INTD */
GPIO_CFGF_GPIO44INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */
GPIO_CFGF_GPIO44INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */
} GPIO_CFGF_GPIO44INTD_Enum;
/* ============================================ GPIO CFGF GPIO44OUTCFG [17..18] ============================================ */
typedef enum { /*!< GPIO_CFGF_GPIO44OUTCFG */
GPIO_CFGF_GPIO44OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGF_GPIO44OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGF_GPIO44OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGF_GPIO44OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGF_GPIO44OUTCFG_Enum;
/* ============================================ GPIO CFGF GPIO44INCFG [16..16] ============================================= */
typedef enum { /*!< GPIO_CFGF_GPIO44INCFG */
GPIO_CFGF_GPIO44INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGF_GPIO44INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGF_GPIO44INCFG_Enum;
/* ============================================= GPIO CFGF GPIO43INTD [15..15] ============================================= */
typedef enum { /*!< GPIO_CFGF_GPIO43INTD */
GPIO_CFGF_GPIO43INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */
GPIO_CFGF_GPIO43INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */
} GPIO_CFGF_GPIO43INTD_Enum;
/* ============================================ GPIO CFGF GPIO43OUTCFG [13..14] ============================================ */
typedef enum { /*!< GPIO_CFGF_GPIO43OUTCFG */
GPIO_CFGF_GPIO43OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGF_GPIO43OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGF_GPIO43OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGF_GPIO43OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGF_GPIO43OUTCFG_Enum;
/* ============================================ GPIO CFGF GPIO43INCFG [12..12] ============================================= */
typedef enum { /*!< GPIO_CFGF_GPIO43INCFG */
GPIO_CFGF_GPIO43INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGF_GPIO43INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGF_GPIO43INCFG_Enum;
/* ============================================= GPIO CFGF GPIO42INTD [11..11] ============================================= */
typedef enum { /*!< GPIO_CFGF_GPIO42INTD */
GPIO_CFGF_GPIO42INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */
GPIO_CFGF_GPIO42INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */
} GPIO_CFGF_GPIO42INTD_Enum;
/* ============================================ GPIO CFGF GPIO42OUTCFG [9..10] ============================================= */
typedef enum { /*!< GPIO_CFGF_GPIO42OUTCFG */
GPIO_CFGF_GPIO42OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGF_GPIO42OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGF_GPIO42OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGF_GPIO42OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGF_GPIO42OUTCFG_Enum;
/* ============================================= GPIO CFGF GPIO42INCFG [8..8] ============================================== */
typedef enum { /*!< GPIO_CFGF_GPIO42INCFG */
GPIO_CFGF_GPIO42INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGF_GPIO42INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGF_GPIO42INCFG_Enum;
/* ============================================== GPIO CFGF GPIO41INTD [7..7] ============================================== */
typedef enum { /*!< GPIO_CFGF_GPIO41INTD */
GPIO_CFGF_GPIO41INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x0 - nCE polarity active low */
GPIO_CFGF_GPIO41INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x0 - nCE polarity active high */
} GPIO_CFGF_GPIO41INTD_Enum;
/* ============================================= GPIO CFGF GPIO41OUTCFG [5..6] ============================================= */
typedef enum { /*!< GPIO_CFGF_GPIO41OUTCFG */
GPIO_CFGF_GPIO41OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGF_GPIO41OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGF_GPIO41OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGF_GPIO41OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGF_GPIO41OUTCFG_Enum;
/* ============================================= GPIO CFGF GPIO41INCFG [4..4] ============================================== */
typedef enum { /*!< GPIO_CFGF_GPIO41INCFG */
GPIO_CFGF_GPIO41INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGF_GPIO41INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGF_GPIO41INCFG_Enum;
/* ============================================== GPIO CFGF GPIO40INTD [3..3] ============================================== */
typedef enum { /*!< GPIO_CFGF_GPIO40INTD */
GPIO_CFGF_GPIO40INTD_INTDIS = 0, /*!< INTDIS : INCFG = 1 - No interrupt on GPIO transition */
GPIO_CFGF_GPIO40INTD_INTBOTH = 1, /*!< INTBOTH : INCFG = 1 - Interrupt on either low to high or high
to low GPIO transition */
} GPIO_CFGF_GPIO40INTD_Enum;
/* ============================================= GPIO CFGF GPIO40OUTCFG [1..2] ============================================= */
typedef enum { /*!< GPIO_CFGF_GPIO40OUTCFG */
GPIO_CFGF_GPIO40OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGF_GPIO40OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGF_GPIO40OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGF_GPIO40OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGF_GPIO40OUTCFG_Enum;
/* ============================================= GPIO CFGF GPIO40INCFG [0..0] ============================================== */
typedef enum { /*!< GPIO_CFGF_GPIO40INCFG */
GPIO_CFGF_GPIO40INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGF_GPIO40INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGF_GPIO40INCFG_Enum;
/* ========================================================= CFGG ========================================================== */
/* ============================================== GPIO CFGG GPIO49INTD [7..7] ============================================== */
typedef enum { /*!< GPIO_CFGG_GPIO49INTD */
GPIO_CFGG_GPIO49INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */
GPIO_CFGG_GPIO49INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */
} GPIO_CFGG_GPIO49INTD_Enum;
/* ============================================= GPIO CFGG GPIO49OUTCFG [5..6] ============================================= */
typedef enum { /*!< GPIO_CFGG_GPIO49OUTCFG */
GPIO_CFGG_GPIO49OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGG_GPIO49OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGG_GPIO49OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGG_GPIO49OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGG_GPIO49OUTCFG_Enum;
/* ============================================= GPIO CFGG GPIO49INCFG [4..4] ============================================== */
typedef enum { /*!< GPIO_CFGG_GPIO49INCFG */
GPIO_CFGG_GPIO49INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGG_GPIO49INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGG_GPIO49INCFG_Enum;
/* ============================================== GPIO CFGG GPIO48INTD [3..3] ============================================== */
typedef enum { /*!< GPIO_CFGG_GPIO48INTD */
GPIO_CFGG_GPIO48INTD_nCELOW = 0, /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low */
GPIO_CFGG_GPIO48INTD_nCEHIGH = 1, /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high */
} GPIO_CFGG_GPIO48INTD_Enum;
/* ============================================= GPIO CFGG GPIO48OUTCFG [1..2] ============================================= */
typedef enum { /*!< GPIO_CFGG_GPIO48OUTCFG */
GPIO_CFGG_GPIO48OUTCFG_DIS = 0, /*!< DIS : FNCSEL = 0x3 - Output disabled */
GPIO_CFGG_GPIO48OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull */
GPIO_CFGG_GPIO48OUTCFG_OD = 2, /*!< OD : FNCSEL = 0x3 - Output is open drain */
GPIO_CFGG_GPIO48OUTCFG_TS = 3, /*!< TS : FNCSEL = 0x3 - Output is tri-state */
} GPIO_CFGG_GPIO48OUTCFG_Enum;
/* ============================================= GPIO CFGG GPIO48INCFG [0..0] ============================================== */
typedef enum { /*!< GPIO_CFGG_GPIO48INCFG */
GPIO_CFGG_GPIO48INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
GPIO_CFGG_GPIO48INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */
} GPIO_CFGG_GPIO48INCFG_Enum;
/* ======================================================== PADKEY ========================================================= */
/* ============================================== GPIO PADKEY PADKEY [0..31] =============================================== */
typedef enum { /*!< GPIO_PADKEY_PADKEY */
GPIO_PADKEY_PADKEY_Key = 115, /*!< Key : Key value to unlock the register. */
} GPIO_PADKEY_PADKEY_Enum;
/* ========================================================== RDA ========================================================== */
/* ========================================================== RDB ========================================================== */
/* ========================================================== WTA ========================================================== */
/* ========================================================== WTB ========================================================== */
/* ========================================================= WTSA ========================================================== */
/* ========================================================= WTSB ========================================================== */
/* ========================================================= WTCA ========================================================== */
/* ========================================================= WTCB ========================================================== */
/* ========================================================== ENA ========================================================== */
/* ========================================================== ENB ========================================================== */
/* ========================================================= ENSA ========================================================== */
/* ========================================================= ENSB ========================================================== */
/* ========================================================= ENCA ========================================================== */
/* ========================================================= ENCB ========================================================== */
/* ======================================================== STMRCAP ======================================================== */
/* ============================================= GPIO STMRCAP STPOL3 [30..30] ============================================== */
typedef enum { /*!< GPIO_STMRCAP_STPOL3 */
GPIO_STMRCAP_STPOL3_CAPLH = 0, /*!< CAPLH : Capture on low to high GPIO transition */
GPIO_STMRCAP_STPOL3_CAPHL = 1, /*!< CAPHL : Capture on high to low GPIO transition */
} GPIO_STMRCAP_STPOL3_Enum;
/* ============================================= GPIO STMRCAP STPOL2 [22..22] ============================================== */
typedef enum { /*!< GPIO_STMRCAP_STPOL2 */
GPIO_STMRCAP_STPOL2_CAPLH = 0, /*!< CAPLH : Capture on low to high GPIO transition */
GPIO_STMRCAP_STPOL2_CAPHL = 1, /*!< CAPHL : Capture on high to low GPIO transition */
} GPIO_STMRCAP_STPOL2_Enum;
/* ============================================= GPIO STMRCAP STPOL1 [14..14] ============================================== */
typedef enum { /*!< GPIO_STMRCAP_STPOL1 */
GPIO_STMRCAP_STPOL1_CAPLH = 0, /*!< CAPLH : Capture on low to high GPIO transition */
GPIO_STMRCAP_STPOL1_CAPHL = 1, /*!< CAPHL : Capture on high to low GPIO transition */
} GPIO_STMRCAP_STPOL1_Enum;
/* ============================================== GPIO STMRCAP STPOL0 [6..6] =============================================== */
typedef enum { /*!< GPIO_STMRCAP_STPOL0 */
GPIO_STMRCAP_STPOL0_CAPLH = 0, /*!< CAPLH : Capture on low to high GPIO transition */
GPIO_STMRCAP_STPOL0_CAPHL = 1, /*!< CAPHL : Capture on high to low GPIO transition */
} GPIO_STMRCAP_STPOL0_Enum;
/* ======================================================== IOM0IRQ ======================================================== */
/* ======================================================== IOM1IRQ ======================================================== */
/* ======================================================== IOM2IRQ ======================================================== */
/* ======================================================== IOM3IRQ ======================================================== */
/* ======================================================== IOM4IRQ ======================================================== */
/* ======================================================== IOM5IRQ ======================================================== */
/* ======================================================= BLEIFIRQ ======================================================== */
/* ======================================================== GPIOOBS ======================================================== */
/* ====================================================== ALTPADCFGA ======================================================= */
/* =========================================== GPIO ALTPADCFGA PAD3_SR [28..28] ============================================ */
typedef enum { /*!< GPIO_ALTPADCFGA_PAD3_SR */
GPIO_ALTPADCFGA_PAD3_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGA_PAD3_SR_Enum;
/* =========================================== GPIO ALTPADCFGA PAD2_SR [20..20] ============================================ */
typedef enum { /*!< GPIO_ALTPADCFGA_PAD2_SR */
GPIO_ALTPADCFGA_PAD2_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGA_PAD2_SR_Enum;
/* =========================================== GPIO ALTPADCFGA PAD1_SR [12..12] ============================================ */
typedef enum { /*!< GPIO_ALTPADCFGA_PAD1_SR */
GPIO_ALTPADCFGA_PAD1_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGA_PAD1_SR_Enum;
/* ============================================ GPIO ALTPADCFGA PAD0_SR [4..4] ============================================= */
typedef enum { /*!< GPIO_ALTPADCFGA_PAD0_SR */
GPIO_ALTPADCFGA_PAD0_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGA_PAD0_SR_Enum;
/* ====================================================== ALTPADCFGB ======================================================= */
/* =========================================== GPIO ALTPADCFGB PAD7_SR [28..28] ============================================ */
typedef enum { /*!< GPIO_ALTPADCFGB_PAD7_SR */
GPIO_ALTPADCFGB_PAD7_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGB_PAD7_SR_Enum;
/* =========================================== GPIO ALTPADCFGB PAD6_SR [20..20] ============================================ */
typedef enum { /*!< GPIO_ALTPADCFGB_PAD6_SR */
GPIO_ALTPADCFGB_PAD6_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGB_PAD6_SR_Enum;
/* =========================================== GPIO ALTPADCFGB PAD5_SR [12..12] ============================================ */
typedef enum { /*!< GPIO_ALTPADCFGB_PAD5_SR */
GPIO_ALTPADCFGB_PAD5_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGB_PAD5_SR_Enum;
/* ============================================ GPIO ALTPADCFGB PAD4_SR [4..4] ============================================= */
typedef enum { /*!< GPIO_ALTPADCFGB_PAD4_SR */
GPIO_ALTPADCFGB_PAD4_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGB_PAD4_SR_Enum;
/* ====================================================== ALTPADCFGC ======================================================= */
/* =========================================== GPIO ALTPADCFGC PAD11_SR [28..28] =========================================== */
typedef enum { /*!< GPIO_ALTPADCFGC_PAD11_SR */
GPIO_ALTPADCFGC_PAD11_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGC_PAD11_SR_Enum;
/* =========================================== GPIO ALTPADCFGC PAD10_SR [20..20] =========================================== */
typedef enum { /*!< GPIO_ALTPADCFGC_PAD10_SR */
GPIO_ALTPADCFGC_PAD10_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGC_PAD10_SR_Enum;
/* =========================================== GPIO ALTPADCFGC PAD9_SR [12..12] ============================================ */
typedef enum { /*!< GPIO_ALTPADCFGC_PAD9_SR */
GPIO_ALTPADCFGC_PAD9_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGC_PAD9_SR_Enum;
/* ============================================ GPIO ALTPADCFGC PAD8_SR [4..4] ============================================= */
typedef enum { /*!< GPIO_ALTPADCFGC_PAD8_SR */
GPIO_ALTPADCFGC_PAD8_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGC_PAD8_SR_Enum;
/* ====================================================== ALTPADCFGD ======================================================= */
/* =========================================== GPIO ALTPADCFGD PAD15_SR [28..28] =========================================== */
typedef enum { /*!< GPIO_ALTPADCFGD_PAD15_SR */
GPIO_ALTPADCFGD_PAD15_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGD_PAD15_SR_Enum;
/* =========================================== GPIO ALTPADCFGD PAD14_SR [20..20] =========================================== */
typedef enum { /*!< GPIO_ALTPADCFGD_PAD14_SR */
GPIO_ALTPADCFGD_PAD14_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGD_PAD14_SR_Enum;
/* =========================================== GPIO ALTPADCFGD PAD13_SR [12..12] =========================================== */
typedef enum { /*!< GPIO_ALTPADCFGD_PAD13_SR */
GPIO_ALTPADCFGD_PAD13_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGD_PAD13_SR_Enum;
/* ============================================ GPIO ALTPADCFGD PAD12_SR [4..4] ============================================ */
typedef enum { /*!< GPIO_ALTPADCFGD_PAD12_SR */
GPIO_ALTPADCFGD_PAD12_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGD_PAD12_SR_Enum;
/* ====================================================== ALTPADCFGE ======================================================= */
/* =========================================== GPIO ALTPADCFGE PAD19_SR [28..28] =========================================== */
typedef enum { /*!< GPIO_ALTPADCFGE_PAD19_SR */
GPIO_ALTPADCFGE_PAD19_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGE_PAD19_SR_Enum;
/* =========================================== GPIO ALTPADCFGE PAD18_SR [20..20] =========================================== */
typedef enum { /*!< GPIO_ALTPADCFGE_PAD18_SR */
GPIO_ALTPADCFGE_PAD18_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGE_PAD18_SR_Enum;
/* =========================================== GPIO ALTPADCFGE PAD17_SR [12..12] =========================================== */
typedef enum { /*!< GPIO_ALTPADCFGE_PAD17_SR */
GPIO_ALTPADCFGE_PAD17_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGE_PAD17_SR_Enum;
/* ============================================ GPIO ALTPADCFGE PAD16_SR [4..4] ============================================ */
typedef enum { /*!< GPIO_ALTPADCFGE_PAD16_SR */
GPIO_ALTPADCFGE_PAD16_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGE_PAD16_SR_Enum;
/* ====================================================== ALTPADCFGF ======================================================= */
/* =========================================== GPIO ALTPADCFGF PAD23_SR [28..28] =========================================== */
typedef enum { /*!< GPIO_ALTPADCFGF_PAD23_SR */
GPIO_ALTPADCFGF_PAD23_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGF_PAD23_SR_Enum;
/* =========================================== GPIO ALTPADCFGF PAD22_SR [20..20] =========================================== */
typedef enum { /*!< GPIO_ALTPADCFGF_PAD22_SR */
GPIO_ALTPADCFGF_PAD22_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGF_PAD22_SR_Enum;
/* =========================================== GPIO ALTPADCFGF PAD21_SR [12..12] =========================================== */
typedef enum { /*!< GPIO_ALTPADCFGF_PAD21_SR */
GPIO_ALTPADCFGF_PAD21_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGF_PAD21_SR_Enum;
/* ============================================ GPIO ALTPADCFGF PAD20_SR [4..4] ============================================ */
typedef enum { /*!< GPIO_ALTPADCFGF_PAD20_SR */
GPIO_ALTPADCFGF_PAD20_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGF_PAD20_SR_Enum;
/* ====================================================== ALTPADCFGG ======================================================= */
/* =========================================== GPIO ALTPADCFGG PAD27_SR [28..28] =========================================== */
typedef enum { /*!< GPIO_ALTPADCFGG_PAD27_SR */
GPIO_ALTPADCFGG_PAD27_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGG_PAD27_SR_Enum;
/* =========================================== GPIO ALTPADCFGG PAD26_SR [20..20] =========================================== */
typedef enum { /*!< GPIO_ALTPADCFGG_PAD26_SR */
GPIO_ALTPADCFGG_PAD26_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGG_PAD26_SR_Enum;
/* =========================================== GPIO ALTPADCFGG PAD25_SR [12..12] =========================================== */
typedef enum { /*!< GPIO_ALTPADCFGG_PAD25_SR */
GPIO_ALTPADCFGG_PAD25_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGG_PAD25_SR_Enum;
/* ============================================ GPIO ALTPADCFGG PAD24_SR [4..4] ============================================ */
typedef enum { /*!< GPIO_ALTPADCFGG_PAD24_SR */
GPIO_ALTPADCFGG_PAD24_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGG_PAD24_SR_Enum;
/* ====================================================== ALTPADCFGH ======================================================= */
/* =========================================== GPIO ALTPADCFGH PAD31_SR [28..28] =========================================== */
typedef enum { /*!< GPIO_ALTPADCFGH_PAD31_SR */
GPIO_ALTPADCFGH_PAD31_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGH_PAD31_SR_Enum;
/* =========================================== GPIO ALTPADCFGH PAD30_SR [20..20] =========================================== */
typedef enum { /*!< GPIO_ALTPADCFGH_PAD30_SR */
GPIO_ALTPADCFGH_PAD30_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGH_PAD30_SR_Enum;
/* =========================================== GPIO ALTPADCFGH PAD29_SR [12..12] =========================================== */
typedef enum { /*!< GPIO_ALTPADCFGH_PAD29_SR */
GPIO_ALTPADCFGH_PAD29_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGH_PAD29_SR_Enum;
/* ============================================ GPIO ALTPADCFGH PAD28_SR [4..4] ============================================ */
typedef enum { /*!< GPIO_ALTPADCFGH_PAD28_SR */
GPIO_ALTPADCFGH_PAD28_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGH_PAD28_SR_Enum;
/* ====================================================== ALTPADCFGI ======================================================= */
/* =========================================== GPIO ALTPADCFGI PAD35_SR [28..28] =========================================== */
typedef enum { /*!< GPIO_ALTPADCFGI_PAD35_SR */
GPIO_ALTPADCFGI_PAD35_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGI_PAD35_SR_Enum;
/* =========================================== GPIO ALTPADCFGI PAD34_SR [20..20] =========================================== */
typedef enum { /*!< GPIO_ALTPADCFGI_PAD34_SR */
GPIO_ALTPADCFGI_PAD34_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGI_PAD34_SR_Enum;
/* =========================================== GPIO ALTPADCFGI PAD33_SR [12..12] =========================================== */
typedef enum { /*!< GPIO_ALTPADCFGI_PAD33_SR */
GPIO_ALTPADCFGI_PAD33_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGI_PAD33_SR_Enum;
/* ============================================ GPIO ALTPADCFGI PAD32_SR [4..4] ============================================ */
typedef enum { /*!< GPIO_ALTPADCFGI_PAD32_SR */
GPIO_ALTPADCFGI_PAD32_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGI_PAD32_SR_Enum;
/* ====================================================== ALTPADCFGJ ======================================================= */
/* =========================================== GPIO ALTPADCFGJ PAD39_SR [28..28] =========================================== */
typedef enum { /*!< GPIO_ALTPADCFGJ_PAD39_SR */
GPIO_ALTPADCFGJ_PAD39_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGJ_PAD39_SR_Enum;
/* =========================================== GPIO ALTPADCFGJ PAD38_SR [20..20] =========================================== */
typedef enum { /*!< GPIO_ALTPADCFGJ_PAD38_SR */
GPIO_ALTPADCFGJ_PAD38_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGJ_PAD38_SR_Enum;
/* =========================================== GPIO ALTPADCFGJ PAD37_SR [12..12] =========================================== */
typedef enum { /*!< GPIO_ALTPADCFGJ_PAD37_SR */
GPIO_ALTPADCFGJ_PAD37_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGJ_PAD37_SR_Enum;
/* ============================================ GPIO ALTPADCFGJ PAD36_SR [4..4] ============================================ */
typedef enum { /*!< GPIO_ALTPADCFGJ_PAD36_SR */
GPIO_ALTPADCFGJ_PAD36_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGJ_PAD36_SR_Enum;
/* ====================================================== ALTPADCFGK ======================================================= */
/* =========================================== GPIO ALTPADCFGK PAD43_SR [28..28] =========================================== */
typedef enum { /*!< GPIO_ALTPADCFGK_PAD43_SR */
GPIO_ALTPADCFGK_PAD43_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGK_PAD43_SR_Enum;
/* =========================================== GPIO ALTPADCFGK PAD42_SR [20..20] =========================================== */
typedef enum { /*!< GPIO_ALTPADCFGK_PAD42_SR */
GPIO_ALTPADCFGK_PAD42_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGK_PAD42_SR_Enum;
/* =========================================== GPIO ALTPADCFGK PAD41_SR [12..12] =========================================== */
typedef enum { /*!< GPIO_ALTPADCFGK_PAD41_SR */
GPIO_ALTPADCFGK_PAD41_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGK_PAD41_SR_Enum;
/* ============================================ GPIO ALTPADCFGK PAD40_SR [4..4] ============================================ */
typedef enum { /*!< GPIO_ALTPADCFGK_PAD40_SR */
GPIO_ALTPADCFGK_PAD40_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGK_PAD40_SR_Enum;
/* ====================================================== ALTPADCFGL ======================================================= */
/* =========================================== GPIO ALTPADCFGL PAD47_SR [28..28] =========================================== */
typedef enum { /*!< GPIO_ALTPADCFGL_PAD47_SR */
GPIO_ALTPADCFGL_PAD47_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGL_PAD47_SR_Enum;
/* =========================================== GPIO ALTPADCFGL PAD46_SR [20..20] =========================================== */
typedef enum { /*!< GPIO_ALTPADCFGL_PAD46_SR */
GPIO_ALTPADCFGL_PAD46_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGL_PAD46_SR_Enum;
/* =========================================== GPIO ALTPADCFGL PAD45_SR [12..12] =========================================== */
typedef enum { /*!< GPIO_ALTPADCFGL_PAD45_SR */
GPIO_ALTPADCFGL_PAD45_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGL_PAD45_SR_Enum;
/* ============================================ GPIO ALTPADCFGL PAD44_SR [4..4] ============================================ */
typedef enum { /*!< GPIO_ALTPADCFGL_PAD44_SR */
GPIO_ALTPADCFGL_PAD44_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGL_PAD44_SR_Enum;
/* ====================================================== ALTPADCFGM ======================================================= */
/* =========================================== GPIO ALTPADCFGM PAD49_SR [12..12] =========================================== */
typedef enum { /*!< GPIO_ALTPADCFGM_PAD49_SR */
GPIO_ALTPADCFGM_PAD49_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGM_PAD49_SR_Enum;
/* ============================================ GPIO ALTPADCFGM PAD48_SR [4..4] ============================================ */
typedef enum { /*!< GPIO_ALTPADCFGM_PAD48_SR */
GPIO_ALTPADCFGM_PAD48_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */
} GPIO_ALTPADCFGM_PAD48_SR_Enum;
/* ========================================================= SCDET ========================================================= */
/* ======================================================== CTENCFG ======================================================== */
/* ============================================== GPIO CTENCFG EN31 [31..31] =============================================== */
typedef enum { /*!< GPIO_CTENCFG_EN31 */
GPIO_CTENCFG_EN31_DIS = 1, /*!< DIS : Disable CT31 for output */
GPIO_CTENCFG_EN31_EN = 0, /*!< EN : Enable CT31 for output */
} GPIO_CTENCFG_EN31_Enum;
/* ============================================== GPIO CTENCFG EN30 [30..30] =============================================== */
typedef enum { /*!< GPIO_CTENCFG_EN30 */
GPIO_CTENCFG_EN30_DIS = 1, /*!< DIS : Disable CT30 for output */
GPIO_CTENCFG_EN30_EN = 0, /*!< EN : Enable CT30 for output */
} GPIO_CTENCFG_EN30_Enum;
/* ============================================== GPIO CTENCFG EN29 [29..29] =============================================== */
typedef enum { /*!< GPIO_CTENCFG_EN29 */
GPIO_CTENCFG_EN29_DIS = 1, /*!< DIS : Disable CT29 for output */
GPIO_CTENCFG_EN29_EN = 0, /*!< EN : Enable CT29 for output */
} GPIO_CTENCFG_EN29_Enum;
/* ============================================== GPIO CTENCFG EN28 [28..28] =============================================== */
typedef enum { /*!< GPIO_CTENCFG_EN28 */
GPIO_CTENCFG_EN28_DIS = 1, /*!< DIS : Disable CT28 for output */
GPIO_CTENCFG_EN28_EN = 0, /*!< EN : Enable CT28 for output */
} GPIO_CTENCFG_EN28_Enum;
/* ============================================== GPIO CTENCFG EN27 [27..27] =============================================== */
typedef enum { /*!< GPIO_CTENCFG_EN27 */
GPIO_CTENCFG_EN27_DIS = 1, /*!< DIS : Disable CT27 for output */
GPIO_CTENCFG_EN27_EN = 0, /*!< EN : Enable CT27 for output */
} GPIO_CTENCFG_EN27_Enum;
/* ============================================== GPIO CTENCFG EN26 [26..26] =============================================== */
typedef enum { /*!< GPIO_CTENCFG_EN26 */
GPIO_CTENCFG_EN26_DIS = 1, /*!< DIS : Disable CT26 for output */
GPIO_CTENCFG_EN26_EN = 0, /*!< EN : Enable CT26 for output */
} GPIO_CTENCFG_EN26_Enum;
/* ============================================== GPIO CTENCFG EN25 [25..25] =============================================== */
typedef enum { /*!< GPIO_CTENCFG_EN25 */
GPIO_CTENCFG_EN25_DIS = 1, /*!< DIS : Disable CT25 for output */
GPIO_CTENCFG_EN25_EN = 0, /*!< EN : Enable CT25 for output */
} GPIO_CTENCFG_EN25_Enum;
/* ============================================== GPIO CTENCFG EN24 [24..24] =============================================== */
typedef enum { /*!< GPIO_CTENCFG_EN24 */
GPIO_CTENCFG_EN24_DIS = 1, /*!< DIS : Disable CT24 for output */
GPIO_CTENCFG_EN24_EN = 0, /*!< EN : Enable CT24 for output */
} GPIO_CTENCFG_EN24_Enum;
/* ============================================== GPIO CTENCFG EN23 [23..23] =============================================== */
typedef enum { /*!< GPIO_CTENCFG_EN23 */
GPIO_CTENCFG_EN23_DIS = 1, /*!< DIS : Disable CT23 for output */
GPIO_CTENCFG_EN23_EN = 0, /*!< EN : Enable CT23 for output */
} GPIO_CTENCFG_EN23_Enum;
/* ============================================== GPIO CTENCFG EN22 [22..22] =============================================== */
typedef enum { /*!< GPIO_CTENCFG_EN22 */
GPIO_CTENCFG_EN22_DIS = 1, /*!< DIS : Disable CT22 for output */
GPIO_CTENCFG_EN22_EN = 0, /*!< EN : Enable CT22 for output */
} GPIO_CTENCFG_EN22_Enum;
/* ============================================== GPIO CTENCFG EN21 [21..21] =============================================== */
typedef enum { /*!< GPIO_CTENCFG_EN21 */
GPIO_CTENCFG_EN21_DIS = 1, /*!< DIS : Disable CT21 for output */
GPIO_CTENCFG_EN21_EN = 0, /*!< EN : Enable CT21 for output */
} GPIO_CTENCFG_EN21_Enum;
/* ============================================== GPIO CTENCFG EN20 [20..20] =============================================== */
typedef enum { /*!< GPIO_CTENCFG_EN20 */
GPIO_CTENCFG_EN20_DIS = 1, /*!< DIS : Disable CT20 for output */
GPIO_CTENCFG_EN20_EN = 0, /*!< EN : Enable CT20 for output */
} GPIO_CTENCFG_EN20_Enum;
/* ============================================== GPIO CTENCFG EN19 [19..19] =============================================== */
typedef enum { /*!< GPIO_CTENCFG_EN19 */
GPIO_CTENCFG_EN19_DIS = 1, /*!< DIS : Disable CT19 for output */
GPIO_CTENCFG_EN19_EN = 0, /*!< EN : Enable CT19 for output */
} GPIO_CTENCFG_EN19_Enum;
/* ============================================== GPIO CTENCFG EN18 [18..18] =============================================== */
typedef enum { /*!< GPIO_CTENCFG_EN18 */
GPIO_CTENCFG_EN18_DIS = 1, /*!< DIS : Disable CT18 for output */
GPIO_CTENCFG_EN18_EN = 0, /*!< EN : Enable CT18 for output */
} GPIO_CTENCFG_EN18_Enum;
/* ============================================== GPIO CTENCFG EN17 [17..17] =============================================== */
typedef enum { /*!< GPIO_CTENCFG_EN17 */
GPIO_CTENCFG_EN17_DIS = 1, /*!< DIS : Disable CT17 for output */
GPIO_CTENCFG_EN17_EN = 0, /*!< EN : Enable CT17 for output */
} GPIO_CTENCFG_EN17_Enum;
/* ============================================== GPIO CTENCFG EN16 [16..16] =============================================== */
typedef enum { /*!< GPIO_CTENCFG_EN16 */
GPIO_CTENCFG_EN16_DIS = 1, /*!< DIS : Disable CT16 for output */
GPIO_CTENCFG_EN16_EN = 0, /*!< EN : Enable CT16 for output */
} GPIO_CTENCFG_EN16_Enum;
/* ============================================== GPIO CTENCFG EN15 [15..15] =============================================== */
typedef enum { /*!< GPIO_CTENCFG_EN15 */
GPIO_CTENCFG_EN15_DIS = 1, /*!< DIS : Disable CT15 for output */
GPIO_CTENCFG_EN15_EN = 0, /*!< EN : Enable CT15 for output */
} GPIO_CTENCFG_EN15_Enum;
/* ============================================== GPIO CTENCFG EN14 [14..14] =============================================== */
typedef enum { /*!< GPIO_CTENCFG_EN14 */
GPIO_CTENCFG_EN14_DIS = 1, /*!< DIS : Disable CT14 for output */
GPIO_CTENCFG_EN14_EN = 0, /*!< EN : Enable CT14 for output */
} GPIO_CTENCFG_EN14_Enum;
/* ============================================== GPIO CTENCFG EN13 [13..13] =============================================== */
typedef enum { /*!< GPIO_CTENCFG_EN13 */
GPIO_CTENCFG_EN13_DIS = 1, /*!< DIS : Disable CT13 for output */
GPIO_CTENCFG_EN13_EN = 0, /*!< EN : Enable CT13 for output */
} GPIO_CTENCFG_EN13_Enum;
/* ============================================== GPIO CTENCFG EN12 [12..12] =============================================== */
typedef enum { /*!< GPIO_CTENCFG_EN12 */
GPIO_CTENCFG_EN12_DIS = 1, /*!< DIS : Disable CT12 for output */
GPIO_CTENCFG_EN12_EN = 0, /*!< EN : Enable CT12 for output */
} GPIO_CTENCFG_EN12_Enum;
/* ============================================== GPIO CTENCFG EN11 [11..11] =============================================== */
typedef enum { /*!< GPIO_CTENCFG_EN11 */
GPIO_CTENCFG_EN11_DIS = 1, /*!< DIS : Disable CT11 for output */
GPIO_CTENCFG_EN11_EN = 0, /*!< EN : Enable CT11 for output */
} GPIO_CTENCFG_EN11_Enum;
/* ============================================== GPIO CTENCFG EN10 [10..10] =============================================== */
typedef enum { /*!< GPIO_CTENCFG_EN10 */
GPIO_CTENCFG_EN10_DIS = 1, /*!< DIS : Disable CT10 for output */
GPIO_CTENCFG_EN10_EN = 0, /*!< EN : Enable CT10 for output */
} GPIO_CTENCFG_EN10_Enum;
/* ================================================ GPIO CTENCFG EN9 [9..9] ================================================ */
typedef enum { /*!< GPIO_CTENCFG_EN9 */
GPIO_CTENCFG_EN9_DIS = 0, /*!< DIS : Disable CT9 for output */
} GPIO_CTENCFG_EN9_Enum;
/* ================================================ GPIO CTENCFG EN8 [8..8] ================================================ */
typedef enum { /*!< GPIO_CTENCFG_EN8 */
GPIO_CTENCFG_EN8_DIS = 1, /*!< DIS : Disable CT8 for output */
GPIO_CTENCFG_EN8_EN = 0, /*!< EN : Enable CT8 for output */
} GPIO_CTENCFG_EN8_Enum;
/* ================================================ GPIO CTENCFG EN7 [7..7] ================================================ */
typedef enum { /*!< GPIO_CTENCFG_EN7 */
GPIO_CTENCFG_EN7_DIS = 1, /*!< DIS : Disable CT7 for output */
GPIO_CTENCFG_EN7_EN = 0, /*!< EN : Enable CT7 for output */
} GPIO_CTENCFG_EN7_Enum;
/* ================================================ GPIO CTENCFG EN6 [6..6] ================================================ */
typedef enum { /*!< GPIO_CTENCFG_EN6 */
GPIO_CTENCFG_EN6_DIS = 1, /*!< DIS : Disable CT6 for output */
GPIO_CTENCFG_EN6_EN = 0, /*!< EN : Enable CT6 for output */
} GPIO_CTENCFG_EN6_Enum;
/* ================================================ GPIO CTENCFG EN5 [5..5] ================================================ */
typedef enum { /*!< GPIO_CTENCFG_EN5 */
GPIO_CTENCFG_EN5_DIS = 1, /*!< DIS : Disable CT5 for output */
GPIO_CTENCFG_EN5_EN = 0, /*!< EN : Enable CT5 for output */
} GPIO_CTENCFG_EN5_Enum;
/* ================================================ GPIO CTENCFG EN4 [4..4] ================================================ */
typedef enum { /*!< GPIO_CTENCFG_EN4 */
GPIO_CTENCFG_EN4_DIS = 1, /*!< DIS : Disable CT4 for output */
GPIO_CTENCFG_EN4_EN = 0, /*!< EN : Enable CT4 for output */
} GPIO_CTENCFG_EN4_Enum;
/* ================================================ GPIO CTENCFG EN3 [3..3] ================================================ */
typedef enum { /*!< GPIO_CTENCFG_EN3 */
GPIO_CTENCFG_EN3_DIS = 1, /*!< DIS : Disable CT3 for output */
GPIO_CTENCFG_EN3_EN = 0, /*!< EN : Enable CT3 for output */
} GPIO_CTENCFG_EN3_Enum;
/* ================================================ GPIO CTENCFG EN2 [2..2] ================================================ */
typedef enum { /*!< GPIO_CTENCFG_EN2 */
GPIO_CTENCFG_EN2_DIS = 1, /*!< DIS : Disable CT2 for output */
GPIO_CTENCFG_EN2_EN = 0, /*!< EN : Enable CT2 for output */
} GPIO_CTENCFG_EN2_Enum;
/* ================================================ GPIO CTENCFG EN1 [1..1] ================================================ */
typedef enum { /*!< GPIO_CTENCFG_EN1 */
GPIO_CTENCFG_EN1_DIS = 1, /*!< DIS : Disable CT1 for output */
GPIO_CTENCFG_EN1_EN = 0, /*!< EN : Enable CT1 for output */
} GPIO_CTENCFG_EN1_Enum;
/* ================================================ GPIO CTENCFG EN0 [0..0] ================================================ */
typedef enum { /*!< GPIO_CTENCFG_EN0 */
GPIO_CTENCFG_EN0_DIS = 1, /*!< DIS : Disable CT0 for output */
GPIO_CTENCFG_EN0_EN = 0, /*!< EN : Enable CT0 for output */
} GPIO_CTENCFG_EN0_Enum;
/* ======================================================== INT0EN ========================================================= */
/* ======================================================= INT0STAT ======================================================== */
/* ======================================================== INT0CLR ======================================================== */
/* ======================================================== INT0SET ======================================================== */
/* ======================================================== INT1EN ========================================================= */
/* ======================================================= INT1STAT ======================================================== */
/* ======================================================== INT1CLR ======================================================== */
/* ======================================================== INT1SET ======================================================== */
/* =========================================================================================================================== */
/* ================ IOM0 ================ */
/* =========================================================================================================================== */
/* ========================================================= FIFO ========================================================== */
/* ======================================================== FIFOPTR ======================================================== */
/* ======================================================== FIFOTHR ======================================================== */
/* ======================================================== FIFOPOP ======================================================== */
/* ======================================================= FIFOPUSH ======================================================== */
/* ======================================================= FIFOCTRL ======================================================== */
/* ======================================================== FIFOLOC ======================================================== */
/* ========================================================= INTEN ========================================================= */
/* ======================================================== INTSTAT ======================================================== */
/* ======================================================== INTCLR ========================================================= */
/* ======================================================== INTSET ========================================================= */
/* ======================================================== CLKCFG ========================================================= */
/* ============================================== IOM0 CLKCFG DIVEN [12..12] =============================================== */
typedef enum { /*!< IOM0_CLKCFG_DIVEN */
IOM0_CLKCFG_DIVEN_DIS = 0, /*!< DIS : Disable TOTPER division. */
IOM0_CLKCFG_DIVEN_EN = 1, /*!< EN : Enable TOTPER division. */
} IOM0_CLKCFG_DIVEN_Enum;
/* =============================================== IOM0 CLKCFG DIV3 [11..11] =============================================== */
typedef enum { /*!< IOM0_CLKCFG_DIV3 */
IOM0_CLKCFG_DIV3_DIS = 0, /*!< DIS : Select divide by 1. */
IOM0_CLKCFG_DIV3_EN = 1, /*!< EN : Select divide by 3. */
} IOM0_CLKCFG_DIV3_Enum;
/* =============================================== IOM0 CLKCFG FSEL [8..10] ================================================ */
typedef enum { /*!< IOM0_CLKCFG_FSEL */
IOM0_CLKCFG_FSEL_MIN_PWR = 0, /*!< MIN_PWR : Selects the minimum power clock. This setting should
be used whenever the IOM is not active. */
IOM0_CLKCFG_FSEL_HFRC = 1, /*!< HFRC : Selects the HFRC as the input clock. */
IOM0_CLKCFG_FSEL_HFRC_DIV2 = 2, /*!< HFRC_DIV2 : Selects the HFRC / 2 as the input clock. */
IOM0_CLKCFG_FSEL_HFRC_DIV4 = 3, /*!< HFRC_DIV4 : Selects the HFRC / 4 as the input clock. */
IOM0_CLKCFG_FSEL_HFRC_DIV8 = 4, /*!< HFRC_DIV8 : Selects the HFRC / 8 as the input clock. */
IOM0_CLKCFG_FSEL_HFRC_DIV16 = 5, /*!< HFRC_DIV16 : Selects the HFRC / 16 as the input clock. */
IOM0_CLKCFG_FSEL_HFRC_DIV32 = 6, /*!< HFRC_DIV32 : Selects the HFRC / 32 as the input clock. */
IOM0_CLKCFG_FSEL_HFRC_DIV64 = 7, /*!< HFRC_DIV64 : Selects the HFRC / 64 as the input clock. */
} IOM0_CLKCFG_FSEL_Enum;
/* ====================================================== SUBMODCTRL ======================================================= */
/* =========================================== IOM0 SUBMODCTRL SMOD1TYPE [5..7] ============================================ */
typedef enum { /*!< IOM0_SUBMODCTRL_SMOD1TYPE */
IOM0_SUBMODCTRL_SMOD1TYPE_MSPI = 0, /*!< MSPI : SPI Master submodule */
IOM0_SUBMODCTRL_SMOD1TYPE_I2C_MASTER = 1, /*!< I2C_MASTER : MI2C submodule */
IOM0_SUBMODCTRL_SMOD1TYPE_SSPI = 2, /*!< SSPI : SPI Slave submodule */
IOM0_SUBMODCTRL_SMOD1TYPE_SI2C = 3, /*!< SI2C : I2C Slave submodule */
IOM0_SUBMODCTRL_SMOD1TYPE_NA = 7, /*!< NA : NOT INSTALLED */
} IOM0_SUBMODCTRL_SMOD1TYPE_Enum;
/* =========================================== IOM0 SUBMODCTRL SMOD0TYPE [1..3] ============================================ */
typedef enum { /*!< IOM0_SUBMODCTRL_SMOD0TYPE */
IOM0_SUBMODCTRL_SMOD0TYPE_SPI_MASTER = 0, /*!< SPI_MASTER : MSPI submodule */
IOM0_SUBMODCTRL_SMOD0TYPE_I2C_MASTER = 1, /*!< I2C_MASTER : I2C Master submodule */
IOM0_SUBMODCTRL_SMOD0TYPE_SSPI = 2, /*!< SSPI : SPI Slave submodule */
IOM0_SUBMODCTRL_SMOD0TYPE_SI2C = 3, /*!< SI2C : I2C Slave submodule */
IOM0_SUBMODCTRL_SMOD0TYPE_NA = 7, /*!< NA : NOT INSTALLED */
} IOM0_SUBMODCTRL_SMOD0TYPE_Enum;
/* ========================================================== CMD ========================================================== */
/* ================================================== IOM0 CMD CMD [0..4] ================================================== */
typedef enum { /*!< IOM0_CMD_CMD */
IOM0_CMD_CMD_WRITE = 1, /*!< WRITE : Write command using count of offset bytes specified
in the OFFSETCNT field */
IOM0_CMD_CMD_READ = 2, /*!< READ : Read command using count of offset bytes specified in
the OFFSETCNT field */
IOM0_CMD_CMD_TMW = 3, /*!< TMW : SPI only. Test mode to do constant write operations. Useful
for debug and power measurements. Will continually send
data in OFFSET field */
IOM0_CMD_CMD_TMR = 4, /*!< TMR : SPI Only. Test mode to do constant read operations. Useful
for debug and power measurements. Will continually read
data from external input */
} IOM0_CMD_CMD_Enum;
/* ========================================================== DCX ========================================================== */
/* ================================================= IOM0 DCX DCXEN [4..4] ================================================= */
typedef enum { /*!< IOM0_DCX_DCXEN */
IOM0_DCX_DCXEN_EN = 1, /*!< EN : Enable DCX. */
IOM0_DCX_DCXEN_DIS = 0, /*!< DIS : Disable DCX. */
} IOM0_DCX_DCXEN_Enum;
/* ======================================================= OFFSETHI ======================================================== */
/* ======================================================== CMDSTAT ======================================================== */
/* ============================================== IOM0 CMDSTAT CMDSTAT [5..7] ============================================== */
typedef enum { /*!< IOM0_CMDSTAT_CMDSTAT */
IOM0_CMDSTAT_CMDSTAT_ERR = 1, /*!< ERR : Error encountered with command */
IOM0_CMDSTAT_CMDSTAT_ACTIVE = 2, /*!< ACTIVE : Actively processing command */
IOM0_CMDSTAT_CMDSTAT_IDLE = 4, /*!< IDLE : Idle state, no active command, no error */
IOM0_CMDSTAT_CMDSTAT_WAIT = 6, /*!< WAIT : Command in progress, but waiting on data from host */
} IOM0_CMDSTAT_CMDSTAT_Enum;
/* ======================================================= DMATRIGEN ======================================================= */
/* ====================================================== DMATRIGSTAT ====================================================== */
/* ======================================================== DMACFG ========================================================= */
/* ============================================== IOM0 DMACFG DPWROFF [9..9] =============================================== */
typedef enum { /*!< IOM0_DMACFG_DPWROFF */
IOM0_DMACFG_DPWROFF_DIS = 0, /*!< DIS : Power off disabled */
IOM0_DMACFG_DPWROFF_EN = 1, /*!< EN : Power off enabled */
} IOM0_DMACFG_DPWROFF_Enum;
/* =============================================== IOM0 DMACFG DMAPRI [8..8] =============================================== */
typedef enum { /*!< IOM0_DMACFG_DMAPRI */
IOM0_DMACFG_DMAPRI_LOW = 0, /*!< LOW : Low Priority (service as best effort) */
IOM0_DMACFG_DMAPRI_HIGH = 1, /*!< HIGH : High Priority (service immediately) */
} IOM0_DMACFG_DMAPRI_Enum;
/* =============================================== IOM0 DMACFG DMADIR [1..1] =============================================== */
typedef enum { /*!< IOM0_DMACFG_DMADIR */
IOM0_DMACFG_DMADIR_P2M = 0, /*!< P2M : Peripheral to Memory (SRAM) transaction. To be set when
doing IOM read operations, ie reading data from external
devices. */
IOM0_DMACFG_DMADIR_M2P = 1, /*!< M2P : Memory to Peripheral transaction. To be set when doing
IOM write operations, ie writing data to external devices. */
} IOM0_DMACFG_DMADIR_Enum;
/* =============================================== IOM0 DMACFG DMAEN [0..0] ================================================ */
typedef enum { /*!< IOM0_DMACFG_DMAEN */
IOM0_DMACFG_DMAEN_DIS = 0, /*!< DIS : Disable DMA Function */
IOM0_DMACFG_DMAEN_EN = 1, /*!< EN : Enable DMA Function */
} IOM0_DMACFG_DMAEN_Enum;
/* ====================================================== DMATOTCOUNT ====================================================== */
/* ====================================================== DMATARGADDR ====================================================== */
/* ======================================================== DMASTAT ======================================================== */
/* ========================================================= CQCFG ========================================================= */
/* ================================================ IOM0 CQCFG CQPRI [1..1] ================================================ */
typedef enum { /*!< IOM0_CQCFG_CQPRI */
IOM0_CQCFG_CQPRI_LOW = 0, /*!< LOW : Low Priority (service as best effort) */
IOM0_CQCFG_CQPRI_HIGH = 1, /*!< HIGH : High Priority (service immediately) */
} IOM0_CQCFG_CQPRI_Enum;
/* ================================================ IOM0 CQCFG CQEN [0..0] ================================================= */
typedef enum { /*!< IOM0_CQCFG_CQEN */
IOM0_CQCFG_CQEN_DIS = 0, /*!< DIS : Disable CQ Function */
IOM0_CQCFG_CQEN_EN = 1, /*!< EN : Enable CQ Function */
} IOM0_CQCFG_CQEN_Enum;
/* ======================================================== CQADDR ========================================================= */
/* ======================================================== CQSTAT ========================================================= */
/* ======================================================== CQFLAGS ======================================================== */
/* ====================================================== CQSETCLEAR ======================================================= */
/* ======================================================= CQPAUSEEN ======================================================= */
/* ============================================= IOM0 CQPAUSEEN CQPEN [0..15] ============================================== */
typedef enum { /*!< IOM0_CQPAUSEEN_CQPEN */
IOM0_CQPAUSEEN_CQPEN_IDXEQ = 32768, /*!< IDXEQ : Pauses the command queue when the current index matches
the last index */
IOM0_CQPAUSEEN_CQPEN_BLEXOREN = 16384, /*!< BLEXOREN : Pause command queue when input BLE bit XORed with
SWFLAG4 is '1' */
IOM0_CQPAUSEEN_CQPEN_IOMXOREN = 8192, /*!< IOMXOREN : Pause command queue when input IOM bit XORed with
SWFLAG3 is '1' */
IOM0_CQPAUSEEN_CQPEN_GPIOXOREN = 4096, /*!< GPIOXOREN : Pause command queue when input GPIO irq_bit XORed
with SWFLAG2 is '1' */
IOM0_CQPAUSEEN_CQPEN_MSPI1XNOREN = 2048, /*!< MSPI1XNOREN : Pause command queue when input MSPI1 bit XNORed
with SWFLAG1 is '1' */
IOM0_CQPAUSEEN_CQPEN_MSPI0XNOREN = 1024, /*!< MSPI0XNOREN : Pause command queue when input MSPI0 bit XNORed
with SWFLAG0 is '1' */
IOM0_CQPAUSEEN_CQPEN_MSPI1XOREN = 512, /*!< MSPI1XOREN : Pause command queue when input MSPI1 bit XORed
with SWFLAG1 is '1' */
IOM0_CQPAUSEEN_CQPEN_MSPI0XOREN = 256, /*!< MSPI0XOREN : Pause command queue when input MSPI0 bit XORed
with SWFLAG0 is '1' */
IOM0_CQPAUSEEN_CQPEN_SWFLAGEN7 = 128, /*!< SWFLAGEN7 : Pause the command queue when software flag bit 7
is '1'. */
IOM0_CQPAUSEEN_CQPEN_SWFLAGEN6 = 64, /*!< SWFLAGEN6 : Pause the command queue when software flag bit 6
is '1' */
IOM0_CQPAUSEEN_CQPEN_SWFLAGEN5 = 32, /*!< SWFLAGEN5 : Pause the command queue when software flag bit 5
is '1' */
IOM0_CQPAUSEEN_CQPEN_SWFLAGEN4 = 16, /*!< SWFLAGEN4 : Pause the command queue when software flag bit 4
is '1' */
IOM0_CQPAUSEEN_CQPEN_SWFLAGEN3 = 8, /*!< SWFLAGEN3 : Pause the command queue when software flag bit 3
is '1' */
IOM0_CQPAUSEEN_CQPEN_SWFLAGEN2 = 4, /*!< SWFLAGEN2 : Pause the command queue when software flag bit 2
is '1' */
IOM0_CQPAUSEEN_CQPEN_SWFLAGEN1 = 2, /*!< SWFLAGEN1 : Pause the command queue when software flag bit 1
is '1' */
IOM0_CQPAUSEEN_CQPEN_SWFLAGEN0 = 1, /*!< SWFLAGEN0 : Pause the command queue when software flag bit 0
is '1' */
} IOM0_CQPAUSEEN_CQPEN_Enum;
/* ======================================================= CQCURIDX ======================================================== */
/* ======================================================= CQENDIDX ======================================================== */
/* ======================================================== STATUS ========================================================= */
/* =============================================== IOM0 STATUS IDLEST [2..2] =============================================== */
typedef enum { /*!< IOM0_STATUS_IDLEST */
IOM0_STATUS_IDLEST_IDLE = 1, /*!< IDLE : The I/O state machine is in the idle state. */
} IOM0_STATUS_IDLEST_Enum;
/* =============================================== IOM0 STATUS CMDACT [1..1] =============================================== */
typedef enum { /*!< IOM0_STATUS_CMDACT */
IOM0_STATUS_CMDACT_ACTIVE = 1, /*!< ACTIVE : An I/O command is active. Indicates the active module
has an active command and is processing this. De-asserted
when the command is completed. */
} IOM0_STATUS_CMDACT_Enum;
/* ================================================ IOM0 STATUS ERR [0..0] ================================================= */
typedef enum { /*!< IOM0_STATUS_ERR */
IOM0_STATUS_ERR_ERROR = 1, /*!< ERROR : Bit has been deprecated and will always return 0. */
} IOM0_STATUS_ERR_Enum;
/* ======================================================== MSPICFG ======================================================== */
/* ============================================= IOM0 MSPICFG SPILSB [23..23] ============================================== */
typedef enum { /*!< IOM0_MSPICFG_SPILSB */
IOM0_MSPICFG_SPILSB_MSB = 0, /*!< MSB : Send and receive MSB bit first */
IOM0_MSPICFG_SPILSB_LSB = 1, /*!< LSB : Send and receive LSB bit first */
} IOM0_MSPICFG_SPILSB_Enum;
/* ============================================= IOM0 MSPICFG RDFCPOL [22..22] ============================================= */
typedef enum { /*!< IOM0_MSPICFG_RDFCPOL */
IOM0_MSPICFG_RDFCPOL_HIGH = 0, /*!< HIGH : Flow control signal high creates flow control. */
IOM0_MSPICFG_RDFCPOL_LOW = 1, /*!< LOW : Flow control signal low creates flow control. */
} IOM0_MSPICFG_RDFCPOL_Enum;
/* ============================================= IOM0 MSPICFG WTFCPOL [21..21] ============================================= */
typedef enum { /*!< IOM0_MSPICFG_WTFCPOL */
IOM0_MSPICFG_WTFCPOL_HIGH = 0, /*!< HIGH : Flow control signal high(1) creates flow control and
byte transfers will stop until the flow control signal
goes low. */
IOM0_MSPICFG_WTFCPOL_LOW = 1, /*!< LOW : Flow control signal low(0) creates flow control and byte
transfers will stop until the flow control signal goes
high(1). */
} IOM0_MSPICFG_WTFCPOL_Enum;
/* ============================================= IOM0 MSPICFG WTFCIRQ [20..20] ============================================= */
typedef enum { /*!< IOM0_MSPICFG_WTFCIRQ */
IOM0_MSPICFG_WTFCIRQ_MISO = 0, /*!< MISO : MISO is used as the write mode flow control signal. */
IOM0_MSPICFG_WTFCIRQ_IRQ = 1, /*!< IRQ : IRQ is used as the write mode flow control signal. */
} IOM0_MSPICFG_WTFCIRQ_Enum;
/* ============================================= IOM0 MSPICFG MOSIINV [18..18] ============================================= */
typedef enum { /*!< IOM0_MSPICFG_MOSIINV */
IOM0_MSPICFG_MOSIINV_NORMAL = 0, /*!< NORMAL : MOSI is set to 0 in read mode and 1 in write mode. */
IOM0_MSPICFG_MOSIINV_INVERT = 1, /*!< INVERT : MOSI is set to 1 in read mode and 0 in write mode. */
} IOM0_MSPICFG_MOSIINV_Enum;
/* ============================================== IOM0 MSPICFG RDFC [17..17] =============================================== */
typedef enum { /*!< IOM0_MSPICFG_RDFC */
IOM0_MSPICFG_RDFC_DIS = 0, /*!< DIS : Read mode flow control disabled. */
IOM0_MSPICFG_RDFC_EN = 1, /*!< EN : Read mode flow control enabled. */
} IOM0_MSPICFG_RDFC_Enum;
/* ============================================== IOM0 MSPICFG WTFC [16..16] =============================================== */
typedef enum { /*!< IOM0_MSPICFG_WTFC */
IOM0_MSPICFG_WTFC_DIS = 0, /*!< DIS : Write mode flow control disabled. */
IOM0_MSPICFG_WTFC_EN = 1, /*!< EN : Write mode flow control enabled. */
} IOM0_MSPICFG_WTFC_Enum;
/* =============================================== IOM0 MSPICFG SPHA [1..1] ================================================ */
typedef enum { /*!< IOM0_MSPICFG_SPHA */
IOM0_MSPICFG_SPHA_SAMPLE_LEADING_EDGE = 0, /*!< SAMPLE_LEADING_EDGE : Sample on the leading (first) clock edge. */
IOM0_MSPICFG_SPHA_SAMPLE_TRAILING_EDGE = 1, /*!< SAMPLE_TRAILING_EDGE : Sample on the trailing (second) clock
edge. */
} IOM0_MSPICFG_SPHA_Enum;
/* =============================================== IOM0 MSPICFG SPOL [0..0] ================================================ */
typedef enum { /*!< IOM0_MSPICFG_SPOL */
IOM0_MSPICFG_SPOL_CLK_BASE_0 = 0, /*!< CLK_BASE_0 : The base value of the clock is 0. */
IOM0_MSPICFG_SPOL_CLK_BASE_1 = 1, /*!< CLK_BASE_1 : The base value of the clock is 1. */
} IOM0_MSPICFG_SPOL_Enum;
/* ======================================================== MI2CCFG ======================================================== */
/* =============================================== IOM0 MI2CCFG ARBEN [2..2] =============================================== */
typedef enum { /*!< IOM0_MI2CCFG_ARBEN */
IOM0_MI2CCFG_ARBEN_ARBEN = 1, /*!< ARBEN : Enable multi-master bus arbitration support for this
i2c master */
IOM0_MI2CCFG_ARBEN_ARBDIS = 0, /*!< ARBDIS : Disable multi-master bus arbitration support for this
i2c master */
} IOM0_MI2CCFG_ARBEN_Enum;
/* ============================================== IOM0 MI2CCFG I2CLSB [1..1] =============================================== */
typedef enum { /*!< IOM0_MI2CCFG_I2CLSB */
IOM0_MI2CCFG_I2CLSB_MSBFIRST = 0, /*!< MSBFIRST : Byte data is transmitted MSB first onto the bus/read
from the bus */
IOM0_MI2CCFG_I2CLSB_LSBFIRST = 1, /*!< LSBFIRST : Byte data is transmitted LSB first onto the bus/read
from the bus */
} IOM0_MI2CCFG_I2CLSB_Enum;
/* ============================================== IOM0 MI2CCFG ADDRSZ [0..0] =============================================== */
typedef enum { /*!< IOM0_MI2CCFG_ADDRSZ */
IOM0_MI2CCFG_ADDRSZ_ADDRSZ7 = 0, /*!< ADDRSZ7 : Use 7b addressing for I2C master transactions */
IOM0_MI2CCFG_ADDRSZ_ADDRSZ10 = 1, /*!< ADDRSZ10 : Use 10b addressing for I2C master transactions */
} IOM0_MI2CCFG_ADDRSZ_Enum;
/* ======================================================== DEVCFG ========================================================= */
/* ======================================================== IOMDBG ========================================================= */
/* =========================================================================================================================== */
/* ================ IOSLAVE ================ */
/* =========================================================================================================================== */
/* ======================================================== FIFOPTR ======================================================== */
/* ======================================================== FIFOCFG ======================================================== */
/* ======================================================== FIFOTHR ======================================================== */
/* ========================================================= FUPD ========================================================== */
/* ======================================================== FIFOCTR ======================================================== */
/* ======================================================== FIFOINC ======================================================== */
/* ========================================================== CFG ========================================================== */
/* ============================================== IOSLAVE CFG IFCEN [31..31] =============================================== */
typedef enum { /*!< IOSLAVE_CFG_IFCEN */
IOSLAVE_CFG_IFCEN_DIS = 0, /*!< DIS : Disable the IOSLAVE */
IOSLAVE_CFG_IFCEN_EN = 1, /*!< EN : Enable the IOSLAVE */
} IOSLAVE_CFG_IFCEN_Enum;
/* ============================================== IOSLAVE CFG STARTRD [4..4] =============================================== */
typedef enum { /*!< IOSLAVE_CFG_STARTRD */
IOSLAVE_CFG_STARTRD_LATE = 0, /*!< LATE : Initiate I/O RAM read late in each transferred byte. */
IOSLAVE_CFG_STARTRD_EARLY = 1, /*!< EARLY : Initiate I/O RAM read early in each transferred byte. */
} IOSLAVE_CFG_STARTRD_Enum;
/* ================================================ IOSLAVE CFG LSB [2..2] ================================================= */
typedef enum { /*!< IOSLAVE_CFG_LSB */
IOSLAVE_CFG_LSB_MSB_FIRST = 0, /*!< MSB_FIRST : Data is assumed to be sent and received with MSB
first. */
IOSLAVE_CFG_LSB_LSB_FIRST = 1, /*!< LSB_FIRST : Data is assumed to be sent and received with LSB
first. */
} IOSLAVE_CFG_LSB_Enum;
/* ================================================ IOSLAVE CFG SPOL [1..1] ================================================ */
typedef enum { /*!< IOSLAVE_CFG_SPOL */
IOSLAVE_CFG_SPOL_SPI_MODES_0_3 = 0, /*!< SPI_MODES_0_3 : Polarity 0, handles SPI modes 0 and 3. */
IOSLAVE_CFG_SPOL_SPI_MODES_1_2 = 1, /*!< SPI_MODES_1_2 : Polarity 1, handles SPI modes 1 and 2. */
} IOSLAVE_CFG_SPOL_Enum;
/* =============================================== IOSLAVE CFG IFCSEL [0..0] =============================================== */
typedef enum { /*!< IOSLAVE_CFG_IFCSEL */
IOSLAVE_CFG_IFCSEL_I2C = 0, /*!< I2C : Selects I2C interface for the IO Slave. */
IOSLAVE_CFG_IFCSEL_SPI = 1, /*!< SPI : Selects SPI interface for the IO Slave. */
} IOSLAVE_CFG_IFCSEL_Enum;
/* ========================================================= PRENC ========================================================= */
/* ======================================================= IOINTCTL ======================================================== */
/* ======================================================== GENADD ========================================================= */
/* ========================================================= INTEN ========================================================= */
/* ======================================================== INTSTAT ======================================================== */
/* ======================================================== INTCLR ========================================================= */
/* ======================================================== INTSET ========================================================= */
/* ====================================================== REGACCINTEN ====================================================== */
/* ===================================================== REGACCINTSTAT ===================================================== */
/* ===================================================== REGACCINTCLR ====================================================== */
/* ===================================================== REGACCINTSET ====================================================== */
/* =========================================================================================================================== */
/* ================ MCUCTRL ================ */
/* =========================================================================================================================== */
/* ======================================================== CHIPPN ========================================================= */
/* ============================================ MCUCTRL CHIPPN PARTNUM [0..31] ============================================= */
typedef enum { /*!< MCUCTRL_CHIPPN_PARTNUM */
MCUCTRL_CHIPPN_PARTNUM_APOLLO3 = 100663296,/*!< APOLLO3 : Apollo3 Blue part number is 0x06xxxxxx. */
MCUCTRL_CHIPPN_PARTNUM_APOLLO2 = 50331648,/*!< APOLLO2 : Apollo2 part number is 0x03xxxxxx. */
MCUCTRL_CHIPPN_PARTNUM_APOLLO = 16777216,/*!< APOLLO : Apollo part number is 0x01xxxxxx. */
MCUCTRL_CHIPPN_PARTNUM_PN_M = -16777216,/*!< PN_M : Mask for the part number field. */
MCUCTRL_CHIPPN_PARTNUM_PN_S = 24, /*!< PN_S : Bit position for the part number field. */
MCUCTRL_CHIPPN_PARTNUM_FLASHSIZE_M = 15728640,/*!< FLASHSIZE_M : Mask for the FLASH_SIZE field.Values:0: 16KB1:
32KB2: 64KB3: 128KB4: 256KB5: 512KB6: 1MB7: 2MB */
MCUCTRL_CHIPPN_PARTNUM_FLASHSIZE_S = 20, /*!< FLASHSIZE_S : Bit position for the FLASH_SIZE field. */
MCUCTRL_CHIPPN_PARTNUM_SRAMSIZE_M = 983040,/*!< SRAMSIZE_M : Mask for the SRAM_SIZE field.Values:0: 16KB1: 32KB2:
64KB3: 128KB4: 256KB5: 512KB6: 1MB7: 384KB8: 768KB */
MCUCTRL_CHIPPN_PARTNUM_SRAMSIZE_S = 16, /*!< SRAMSIZE_S : Bit position for the SRAM_SIZE field. */
MCUCTRL_CHIPPN_PARTNUM_REV_M = 65280, /*!< REV_M : Mask for the revision field. Bits [15:12] are major
rev, [11:8] are minor rev.Values:0: Major Rev A, Minor
Rev 01: Major Rev B, Minor Rev 1 */
MCUCTRL_CHIPPN_PARTNUM_REV_S = 8, /*!< REV_S : Bit position for the revision field. */
MCUCTRL_CHIPPN_PARTNUM_PKG_M = 192, /*!< PKG_M : Mask for the package field.Values:0: SIP1: QFN2: BGA3:
CSP */
MCUCTRL_CHIPPN_PARTNUM_PKG_S = 6, /*!< PKG_S : Bit position for the package field. */
MCUCTRL_CHIPPN_PARTNUM_PINS_M = 56, /*!< PINS_M : Mask for the pins field.Values:0: 25 pins1: 49 pins2:
64 pins3: 81 pins4: 104 pins */
MCUCTRL_CHIPPN_PARTNUM_PINS_S = 3, /*!< PINS_S : Bit position for the pins field. */
MCUCTRL_CHIPPN_PARTNUM_TEMP_S = 1, /*!< TEMP_S : Bit position for the temperature field. */
MCUCTRL_CHIPPN_PARTNUM_QUAL_S = 0, /*!< QUAL_S : Bit position for the qualified field. */
} MCUCTRL_CHIPPN_PARTNUM_Enum;
/* ======================================================== CHIPID0 ======================================================== */
/* ============================================ MCUCTRL CHIPID0 CHIPID0 [0..31] ============================================ */
typedef enum { /*!< MCUCTRL_CHIPID0_CHIPID0 */
MCUCTRL_CHIPID0_CHIPID0_APOLLO3 = 0, /*!< APOLLO3 : Apollo3 Blue CHIPID0. */
} MCUCTRL_CHIPID0_CHIPID0_Enum;
/* ======================================================== CHIPID1 ======================================================== */
/* ============================================ MCUCTRL CHIPID1 CHIPID1 [0..31] ============================================ */
typedef enum { /*!< MCUCTRL_CHIPID1_CHIPID1 */
MCUCTRL_CHIPID1_CHIPID1_APOLLO3 = 0, /*!< APOLLO3 : Apollo3 Blue CHIPID1. */
} MCUCTRL_CHIPID1_CHIPID1_Enum;
/* ======================================================== CHIPREV ======================================================== */
/* ============================================= MCUCTRL CHIPREV REVMAJ [4..7] ============================================= */
typedef enum { /*!< MCUCTRL_CHIPREV_REVMAJ */
MCUCTRL_CHIPREV_REVMAJ_B = 2, /*!< B : Apollo3 Blue revision B */
MCUCTRL_CHIPREV_REVMAJ_A = 1, /*!< A : Apollo3 Blue revision A */
} MCUCTRL_CHIPREV_REVMAJ_Enum;
/* ============================================= MCUCTRL CHIPREV REVMIN [0..3] ============================================= */
typedef enum { /*!< MCUCTRL_CHIPREV_REVMIN */
MCUCTRL_CHIPREV_REVMIN_REV1 = 2, /*!< REV1 : Apollo3 Blue minor rev 1. */
MCUCTRL_CHIPREV_REVMIN_REV0 = 1, /*!< REV0 : Apollo3 Blue minor rev 0. Minor revision value, succeeding
minor revisions will increment from this value. */
} MCUCTRL_CHIPREV_REVMIN_Enum;
/* ======================================================= VENDORID ======================================================== */
/* =========================================== MCUCTRL VENDORID VENDORID [0..31] =========================================== */
typedef enum { /*!< MCUCTRL_VENDORID_VENDORID */
MCUCTRL_VENDORID_VENDORID_AMBIQ = 1095582289,/*!< AMBIQ : Ambiq Vendor ID 'AMBQ' */
} MCUCTRL_VENDORID_VENDORID_Enum;
/* ========================================================== SKU ========================================================== */
/* ===================================================== FEATUREENABLE ===================================================== */
/* ======================================== MCUCTRL FEATUREENABLE BURSTAVAIL [6..6] ======================================== */
typedef enum { /*!< MCUCTRL_FEATUREENABLE_BURSTAVAIL */
MCUCTRL_FEATUREENABLE_BURSTAVAIL_AVAIL = 1, /*!< AVAIL : Burst functionality available */
MCUCTRL_FEATUREENABLE_BURSTAVAIL_NOTAVAIL = 0,/*!< NOTAVAIL : Burst functionality not available */
} MCUCTRL_FEATUREENABLE_BURSTAVAIL_Enum;
/* ========================================= MCUCTRL FEATUREENABLE BURSTREQ [4..4] ========================================= */
typedef enum { /*!< MCUCTRL_FEATUREENABLE_BURSTREQ */
MCUCTRL_FEATUREENABLE_BURSTREQ_EN = 1, /*!< EN : Enable the Burst functionality */
MCUCTRL_FEATUREENABLE_BURSTREQ_DIS = 0, /*!< DIS : Disable the Burst functionality */
} MCUCTRL_FEATUREENABLE_BURSTREQ_Enum;
/* ========================================= MCUCTRL FEATUREENABLE BLEAVAIL [2..2] ========================================= */
typedef enum { /*!< MCUCTRL_FEATUREENABLE_BLEAVAIL */
MCUCTRL_FEATUREENABLE_BLEAVAIL_AVAIL = 1, /*!< AVAIL : BLE functionality available */
MCUCTRL_FEATUREENABLE_BLEAVAIL_NOTAVAIL = 0, /*!< NOTAVAIL : BLE functionality not available */
} MCUCTRL_FEATUREENABLE_BLEAVAIL_Enum;
/* ========================================== MCUCTRL FEATUREENABLE BLEREQ [0..0] ========================================== */
typedef enum { /*!< MCUCTRL_FEATUREENABLE_BLEREQ */
MCUCTRL_FEATUREENABLE_BLEREQ_EN = 1, /*!< EN : Enable the BLE functionality */
MCUCTRL_FEATUREENABLE_BLEREQ_DIS = 0, /*!< DIS : Disable the BLE functionality */
} MCUCTRL_FEATUREENABLE_BLEREQ_Enum;
/* ======================================================= DEBUGGER ======================================================== */
/* ======================================================== BODCTRL ======================================================== */
/* ======================================================= ADCPWRDLY ======================================================= */
/* ======================================================== ADCCAL ========================================================= */
/* ========================================== MCUCTRL ADCCAL ADCCALIBRATED [1..1] ========================================== */
typedef enum { /*!< MCUCTRL_ADCCAL_ADCCALIBRATED */
MCUCTRL_ADCCAL_ADCCALIBRATED_FALSE = 0, /*!< FALSE : ADC is not calibrated */
MCUCTRL_ADCCAL_ADCCALIBRATED_TRUE = 1, /*!< TRUE : ADC is calibrated */
} MCUCTRL_ADCCAL_ADCCALIBRATED_Enum;
/* =========================================== MCUCTRL ADCCAL CALONPWRUP [0..0] ============================================ */
typedef enum { /*!< MCUCTRL_ADCCAL_CALONPWRUP */
MCUCTRL_ADCCAL_CALONPWRUP_DIS = 0, /*!< DIS : Disable automatic calibration on initial power up */
MCUCTRL_ADCCAL_CALONPWRUP_EN = 1, /*!< EN : Enable automatic calibration on initial power up */
} MCUCTRL_ADCCAL_CALONPWRUP_Enum;
/* ====================================================== ADCBATTLOAD ====================================================== */
/* ========================================== MCUCTRL ADCBATTLOAD BATTLOAD [0..0] ========================================== */
typedef enum { /*!< MCUCTRL_ADCBATTLOAD_BATTLOAD */
MCUCTRL_ADCBATTLOAD_BATTLOAD_DIS = 0, /*!< DIS : Battery load is disconnected */
MCUCTRL_ADCBATTLOAD_BATTLOAD_EN = 1, /*!< EN : Battery load is enabled */
} MCUCTRL_ADCBATTLOAD_BATTLOAD_Enum;
/* ======================================================== ADCTRIM ======================================================== */
/* ====================================================== ADCREFCOMP ======================================================= */
/* ======================================================= XTALCTRL ======================================================== */
/* ========================================== MCUCTRL XTALCTRL PWDBODXTAL [5..5] =========================================== */
typedef enum { /*!< MCUCTRL_XTALCTRL_PWDBODXTAL */
MCUCTRL_XTALCTRL_PWDBODXTAL_PWRUPBOD = 0, /*!< PWRUPBOD : Power up XTAL on BOD. */
MCUCTRL_XTALCTRL_PWDBODXTAL_PWRDNBOD = 1, /*!< PWRDNBOD : Power down XTAL on BOD. */
} MCUCTRL_XTALCTRL_PWDBODXTAL_Enum;
/* ========================================= MCUCTRL XTALCTRL PDNBCMPRXTAL [4..4] ========================================== */
typedef enum { /*!< MCUCTRL_XTALCTRL_PDNBCMPRXTAL */
MCUCTRL_XTALCTRL_PDNBCMPRXTAL_PWRUPCOMP = 1, /*!< PWRUPCOMP : Power up XTAL oscillator comparator. */
MCUCTRL_XTALCTRL_PDNBCMPRXTAL_PWRDNCOMP = 0, /*!< PWRDNCOMP : Power down XTAL oscillator comparator. */
} MCUCTRL_XTALCTRL_PDNBCMPRXTAL_Enum;
/* ========================================= MCUCTRL XTALCTRL PDNBCOREXTAL [3..3] ========================================== */
typedef enum { /*!< MCUCTRL_XTALCTRL_PDNBCOREXTAL */
MCUCTRL_XTALCTRL_PDNBCOREXTAL_PWRUPCORE = 1, /*!< PWRUPCORE : Power up XTAL oscillator core. */
MCUCTRL_XTALCTRL_PDNBCOREXTAL_PWRDNCORE = 0, /*!< PWRDNCORE : Power down XTAL oscillator core. */
} MCUCTRL_XTALCTRL_PDNBCOREXTAL_Enum;
/* ========================================== MCUCTRL XTALCTRL BYPCMPRXTAL [2..2] ========================================== */
typedef enum { /*!< MCUCTRL_XTALCTRL_BYPCMPRXTAL */
MCUCTRL_XTALCTRL_BYPCMPRXTAL_USECOMP = 0, /*!< USECOMP : Use the XTAL oscillator comparator. */
MCUCTRL_XTALCTRL_BYPCMPRXTAL_BYPCOMP = 1, /*!< BYPCOMP : Bypass the XTAL oscillator comparator. */
} MCUCTRL_XTALCTRL_BYPCMPRXTAL_Enum;
/* ========================================= MCUCTRL XTALCTRL FDBKDSBLXTAL [1..1] ========================================== */
typedef enum { /*!< MCUCTRL_XTALCTRL_FDBKDSBLXTAL */
MCUCTRL_XTALCTRL_FDBKDSBLXTAL_EN = 0, /*!< EN : Enable XTAL oscillator comparator. */
MCUCTRL_XTALCTRL_FDBKDSBLXTAL_DIS = 1, /*!< DIS : Disable XTAL oscillator comparator. */
} MCUCTRL_XTALCTRL_FDBKDSBLXTAL_Enum;
/* ============================================ MCUCTRL XTALCTRL XTALSWE [0..0] ============================================ */
typedef enum { /*!< MCUCTRL_XTALCTRL_XTALSWE */
MCUCTRL_XTALCTRL_XTALSWE_OVERRIDE_DIS = 0, /*!< OVERRIDE_DIS : XTAL Software Override Disable. */
MCUCTRL_XTALCTRL_XTALSWE_OVERRIDE_EN = 1, /*!< OVERRIDE_EN : XTAL Software Override Enable. */
} MCUCTRL_XTALCTRL_XTALSWE_Enum;
/* ====================================================== XTALGENCTRL ====================================================== */
/* ========================================== MCUCTRL XTALGENCTRL ACWARMUP [0..1] ========================================== */
typedef enum { /*!< MCUCTRL_XTALGENCTRL_ACWARMUP */
MCUCTRL_XTALGENCTRL_ACWARMUP_SEC1 = 0, /*!< SEC1 : Warm-up period of 1-2 seconds */
MCUCTRL_XTALGENCTRL_ACWARMUP_SEC2 = 1, /*!< SEC2 : Warm-up period of 2-4 seconds */
MCUCTRL_XTALGENCTRL_ACWARMUP_SEC4 = 2, /*!< SEC4 : Warm-up period of 4-8 seconds */
MCUCTRL_XTALGENCTRL_ACWARMUP_SEC8 = 3, /*!< SEC8 : Warm-up period of 8-16 seconds */
} MCUCTRL_XTALGENCTRL_ACWARMUP_Enum;
/* ======================================================= MISCCTRL ======================================================== */
/* ====================================================== BOOTLOADER ======================================================= */
/* ======================================= MCUCTRL BOOTLOADER SECBOOTONRST [30..31] ======================================== */
typedef enum { /*!< MCUCTRL_BOOTLOADER_SECBOOTONRST */
MCUCTRL_BOOTLOADER_SECBOOTONRST_DISABLED = 0, /*!< DISABLED : Secure boot disabled */
MCUCTRL_BOOTLOADER_SECBOOTONRST_ENABLED = 1, /*!< ENABLED : Secure boot enabled */
MCUCTRL_BOOTLOADER_SECBOOTONRST_ERROR = 2, /*!< ERROR : Error in secure boot configuration */
} MCUCTRL_BOOTLOADER_SECBOOTONRST_Enum;
/* ========================================== MCUCTRL BOOTLOADER SECBOOT [28..29] ========================================== */
typedef enum { /*!< MCUCTRL_BOOTLOADER_SECBOOT */
MCUCTRL_BOOTLOADER_SECBOOT_DISABLED = 0, /*!< DISABLED : Secure boot disabled */
MCUCTRL_BOOTLOADER_SECBOOT_ENABLED = 1, /*!< ENABLED : Secure boot enabled */
MCUCTRL_BOOTLOADER_SECBOOT_ERROR = 2, /*!< ERROR : Error in secure boot configuration */
} MCUCTRL_BOOTLOADER_SECBOOT_Enum;
/* ====================================== MCUCTRL BOOTLOADER SECBOOTFEATURE [26..27] ======================================= */
typedef enum { /*!< MCUCTRL_BOOTLOADER_SECBOOTFEATURE */
MCUCTRL_BOOTLOADER_SECBOOTFEATURE_DISABLED = 0,/*!< DISABLED : Secure boot disabled */
MCUCTRL_BOOTLOADER_SECBOOTFEATURE_ENABLED = 1,/*!< ENABLED : Secure boot enabled */
MCUCTRL_BOOTLOADER_SECBOOTFEATURE_ERROR = 2, /*!< ERROR : Error in secure boot configuration */
} MCUCTRL_BOOTLOADER_SECBOOTFEATURE_Enum;
/* ========================================== MCUCTRL BOOTLOADER PROTLOCK [2..2] =========================================== */
typedef enum { /*!< MCUCTRL_BOOTLOADER_PROTLOCK */
MCUCTRL_BOOTLOADER_PROTLOCK_LOCK = 1, /*!< LOCK : Enable the secure boot lock */
} MCUCTRL_BOOTLOADER_PROTLOCK_Enum;
/* =========================================== MCUCTRL BOOTLOADER SBLOCK [1..1] ============================================ */
typedef enum { /*!< MCUCTRL_BOOTLOADER_SBLOCK */
MCUCTRL_BOOTLOADER_SBLOCK_LOCK = 1, /*!< LOCK : Enable the secure boot lock */
} MCUCTRL_BOOTLOADER_SBLOCK_Enum;
/* ======================================== MCUCTRL BOOTLOADER BOOTLOADERLOW [0..0] ======================================== */
typedef enum { /*!< MCUCTRL_BOOTLOADER_BOOTLOADERLOW */
MCUCTRL_BOOTLOADER_BOOTLOADERLOW_ADDR0 = 1, /*!< ADDR0 : Bootloader code at 0x00000000. */
} MCUCTRL_BOOTLOADER_BOOTLOADERLOW_Enum;
/* ====================================================== SHADOWVALID ====================================================== */
/* ======================================== MCUCTRL SHADOWVALID INFO0_VALID [2..2] ========================================= */
typedef enum { /*!< MCUCTRL_SHADOWVALID_INFO0_VALID */
MCUCTRL_SHADOWVALID_INFO0_VALID_VALID = 1, /*!< VALID : Flash INFO0 (customer) space contains valid data. */
} MCUCTRL_SHADOWVALID_INFO0_VALID_Enum;
/* ========================================== MCUCTRL SHADOWVALID BLDSLEEP [1..1] ========================================== */
typedef enum { /*!< MCUCTRL_SHADOWVALID_BLDSLEEP */
MCUCTRL_SHADOWVALID_BLDSLEEP_DEEPSLEEP = 1, /*!< DEEPSLEEP : Bootloader will go to deep sleep if no flash image
loaded */
} MCUCTRL_SHADOWVALID_BLDSLEEP_Enum;
/* =========================================== MCUCTRL SHADOWVALID VALID [0..0] ============================================ */
typedef enum { /*!< MCUCTRL_SHADOWVALID_VALID */
MCUCTRL_SHADOWVALID_VALID_VALID = 1, /*!< VALID : Flash information space contains valid data. */
} MCUCTRL_SHADOWVALID_VALID_Enum;
/* ======================================================= SCRATCH0 ======================================================== */
/* ======================================================= SCRATCH1 ======================================================== */
/* ==================================================== ICODEFAULTADDR ===================================================== */
/* ==================================================== DCODEFAULTADDR ===================================================== */
/* ===================================================== SYSFAULTADDR ====================================================== */
/* ====================================================== FAULTSTATUS ====================================================== */
/* ========================================== MCUCTRL FAULTSTATUS SYSFAULT [2..2] ========================================== */
typedef enum { /*!< MCUCTRL_FAULTSTATUS_SYSFAULT */
MCUCTRL_FAULTSTATUS_SYSFAULT_NOFAULT = 0, /*!< NOFAULT : No bus fault has been detected. */
MCUCTRL_FAULTSTATUS_SYSFAULT_FAULT = 1, /*!< FAULT : Bus fault detected. */
} MCUCTRL_FAULTSTATUS_SYSFAULT_Enum;
/* ========================================= MCUCTRL FAULTSTATUS DCODEFAULT [1..1] ========================================= */
typedef enum { /*!< MCUCTRL_FAULTSTATUS_DCODEFAULT */
MCUCTRL_FAULTSTATUS_DCODEFAULT_NOFAULT = 0, /*!< NOFAULT : No DCODE fault has been detected. */
MCUCTRL_FAULTSTATUS_DCODEFAULT_FAULT = 1, /*!< FAULT : DCODE fault detected. */
} MCUCTRL_FAULTSTATUS_DCODEFAULT_Enum;
/* ========================================= MCUCTRL FAULTSTATUS ICODEFAULT [0..0] ========================================= */
typedef enum { /*!< MCUCTRL_FAULTSTATUS_ICODEFAULT */
MCUCTRL_FAULTSTATUS_ICODEFAULT_NOFAULT = 0, /*!< NOFAULT : No ICODE fault has been detected. */
MCUCTRL_FAULTSTATUS_ICODEFAULT_FAULT = 1, /*!< FAULT : ICODE fault detected. */
} MCUCTRL_FAULTSTATUS_ICODEFAULT_Enum;
/* ==================================================== FAULTCAPTUREEN ===================================================== */
/* ===================================== MCUCTRL FAULTCAPTUREEN FAULTCAPTUREEN [0..0] ====================================== */
typedef enum { /*!< MCUCTRL_FAULTCAPTUREEN_FAULTCAPTUREEN */
MCUCTRL_FAULTCAPTUREEN_FAULTCAPTUREEN_DIS = 0,/*!< DIS : Disable fault capture. */
MCUCTRL_FAULTCAPTUREEN_FAULTCAPTUREEN_EN = 1, /*!< EN : Enable fault capture. */
} MCUCTRL_FAULTCAPTUREEN_FAULTCAPTUREEN_Enum;
/* ========================================================= DBGR1 ========================================================= */
/* ========================================================= DBGR2 ========================================================= */
/* ======================================================= PMUENABLE ======================================================= */
/* ============================================ MCUCTRL PMUENABLE ENABLE [0..0] ============================================ */
typedef enum { /*!< MCUCTRL_PMUENABLE_ENABLE */
MCUCTRL_PMUENABLE_ENABLE_DIS = 0, /*!< DIS : Disable MCU power management. */
MCUCTRL_PMUENABLE_ENABLE_EN = 1, /*!< EN : Enable MCU power management. */
} MCUCTRL_PMUENABLE_ENABLE_Enum;
/* ======================================================= TPIUCTRL ======================================================== */
/* ============================================ MCUCTRL TPIUCTRL CLKSEL [8..10] ============================================ */
typedef enum { /*!< MCUCTRL_TPIUCTRL_CLKSEL */
MCUCTRL_TPIUCTRL_CLKSEL_LOWPWR = 0, /*!< LOWPWR : Low power state. */
MCUCTRL_TPIUCTRL_CLKSEL_HFRCDIV2 = 1, /*!< HFRCDIV2 : Selects HFRC divided by 2 as the source TPIU clock */
MCUCTRL_TPIUCTRL_CLKSEL_HFRCDIV8 = 2, /*!< HFRCDIV8 : Selects HFRC divided by 8 as the source TPIU clock */
MCUCTRL_TPIUCTRL_CLKSEL_HFRCDIV16 = 3, /*!< HFRCDIV16 : Selects HFRC divided by 16 as the source TPIU clock */
MCUCTRL_TPIUCTRL_CLKSEL_HFRCDIV32 = 4, /*!< HFRCDIV32 : Selects HFRC divided by 32 as the source TPIU clock */
} MCUCTRL_TPIUCTRL_CLKSEL_Enum;
/* ============================================ MCUCTRL TPIUCTRL ENABLE [0..0] ============================================= */
typedef enum { /*!< MCUCTRL_TPIUCTRL_ENABLE */
MCUCTRL_TPIUCTRL_ENABLE_DIS = 0, /*!< DIS : Disable the TPIU. */
MCUCTRL_TPIUCTRL_ENABLE_EN = 1, /*!< EN : Enable the TPIU. */
} MCUCTRL_TPIUCTRL_ENABLE_Enum;
/* ====================================================== OTAPOINTER ======================================================= */
/* ====================================================== APBDMACTRL ======================================================= */
/* ========================================= MCUCTRL APBDMACTRL DECODEABORT [1..1] ========================================= */
typedef enum { /*!< MCUCTRL_APBDMACTRL_DECODEABORT */
MCUCTRL_APBDMACTRL_DECODEABORT_DISABLE = 0, /*!< DISABLE : Bus operations to powered down peripherals are quietly
discarded */
MCUCTRL_APBDMACTRL_DECODEABORT_ENABLE = 1, /*!< ENABLE : Bus operations to powered down peripherals result in
a bus fault. */
} MCUCTRL_APBDMACTRL_DECODEABORT_Enum;
/* ========================================= MCUCTRL APBDMACTRL DMA_ENABLE [0..0] ========================================== */
typedef enum { /*!< MCUCTRL_APBDMACTRL_DMA_ENABLE */
MCUCTRL_APBDMACTRL_DMA_ENABLE_DISABLE = 0, /*!< DISABLE : DMA operations disabled */
MCUCTRL_APBDMACTRL_DMA_ENABLE_ENABLE = 1, /*!< ENABLE : DMA operations enabled */
} MCUCTRL_APBDMACTRL_DMA_ENABLE_Enum;
/* ======================================================= SRAMMODE ======================================================== */
/* ====================================================== KEXTCLKSEL ======================================================= */
/* ========================================= MCUCTRL KEXTCLKSEL KEXTCLKSEL [0..31] ========================================= */
typedef enum { /*!< MCUCTRL_KEXTCLKSEL_KEXTCLKSEL */
MCUCTRL_KEXTCLKSEL_KEXTCLKSEL_Key = 83, /*!< Key : Key value to unlock the register. */
} MCUCTRL_KEXTCLKSEL_KEXTCLKSEL_Enum;
/* ======================================================= SIMOBUCK1 ======================================================= */
/* ======================================================= SIMOBUCK2 ======================================================= */
/* ======================================================= SIMOBUCK3 ======================================================= */
/* ======================================================= SIMOBUCK4 ======================================================= */
/* ======================================================= BLEBUCK2 ======================================================== */
/* ====================================================== FLASHWPROT0 ====================================================== */
/* ====================================================== FLASHWPROT1 ====================================================== */
/* ====================================================== FLASHRPROT0 ====================================================== */
/* ====================================================== FLASHRPROT1 ====================================================== */
/* ================================================= DMASRAMWRITEPROTECT0 ================================================== */
/* ================================================= DMASRAMWRITEPROTECT1 ================================================== */
/* ================================================== DMASRAMREADPROTECT0 ================================================== */
/* ================================================== DMASRAMREADPROTECT1 ================================================== */
/* =========================================================================================================================== */
/* ================ MSPI ================ */
/* =========================================================================================================================== */
/* ========================================================= CTRL ========================================================== */
/* ========================================================== CFG ========================================================== */
/* ================================================ MSPI CFG CPOL [17..17] ================================================= */
typedef enum { /*!< MSPI_CFG_CPOL */
MSPI_CFG_CPOL_LOW = 0, /*!< LOW : Clock inactive state is low. */
MSPI_CFG_CPOL_HIGH = 1, /*!< HIGH : Clock inactive state is high. */
} MSPI_CFG_CPOL_Enum;
/* ================================================ MSPI CFG CPHA [16..16] ================================================= */
typedef enum { /*!< MSPI_CFG_CPHA */
MSPI_CFG_CPHA_MIDDLE = 0, /*!< MIDDLE : Clock toggles in middle of data bit. */
MSPI_CFG_CPHA_START = 1, /*!< START : Clock toggles at start of data bit. */
} MSPI_CFG_CPHA_Enum;
/* ================================================= MSPI CFG ASIZE [4..5] ================================================= */
typedef enum { /*!< MSPI_CFG_ASIZE */
MSPI_CFG_ASIZE_A1 = 0, /*!< A1 : Send one address byte */
MSPI_CFG_ASIZE_A2 = 1, /*!< A2 : Send two address bytes */
MSPI_CFG_ASIZE_A3 = 2, /*!< A3 : Send three address bytes */
MSPI_CFG_ASIZE_A4 = 3, /*!< A4 : Send four address bytes */
} MSPI_CFG_ASIZE_Enum;
/* ================================================ MSPI CFG DEVCFG [0..3] ================================================= */
typedef enum { /*!< MSPI_CFG_DEVCFG */
MSPI_CFG_DEVCFG_SERIAL0 = 1, /*!< SERIAL0 : Single bit SPI flash on chip select 0 */
MSPI_CFG_DEVCFG_SERIAL1 = 2, /*!< SERIAL1 : Single bit SPI flash on chip select 1 */
MSPI_CFG_DEVCFG_DUAL0 = 5, /*!< DUAL0 : Dual SPI flash on chip select 0 */
MSPI_CFG_DEVCFG_DUAL1 = 6, /*!< DUAL1 : Dual bit SPI flash on chip select 1 */
MSPI_CFG_DEVCFG_QUAD0 = 9, /*!< QUAD0 : Quad SPI flash on chip select 0 */
MSPI_CFG_DEVCFG_QUAD1 = 10, /*!< QUAD1 : Quad SPI flash on chip select 1 */
MSPI_CFG_DEVCFG_OCTAL0 = 13, /*!< OCTAL0 : Octal SPI flash on chip select 0 */
MSPI_CFG_DEVCFG_OCTAL1 = 14, /*!< OCTAL1 : Octal SPI flash on chip select 1 */
MSPI_CFG_DEVCFG_QUADPAIRED = 15, /*!< QUADPAIRED : Dual Quad SPI flash on chip selects 0/1. */
MSPI_CFG_DEVCFG_QUADPAIRED_SERIAL = 3, /*!< QUADPAIRED_SERIAL : Dual Quad SPI flash on chip selects 0/1,
but transmit in serial mode for initialization operations */
} MSPI_CFG_DEVCFG_Enum;
/* ========================================================= ADDR ========================================================== */
/* ========================================================= INSTR ========================================================= */
/* ======================================================== TXFIFO ========================================================= */
/* ======================================================== RXFIFO ========================================================= */
/* ======================================================= TXENTRIES ======================================================= */
/* ======================================================= RXENTRIES ======================================================= */
/* ======================================================= THRESHOLD ======================================================= */
/* ======================================================== MSPICFG ======================================================== */
/* ============================================== MSPI MSPICFG CLKDIV [8..13] ============================================== */
typedef enum { /*!< MSPI_MSPICFG_CLKDIV */
MSPI_MSPICFG_CLKDIV_CLK48 = 1, /*!< CLK48 : 48 MHz MSPI clock */
MSPI_MSPICFG_CLKDIV_CLK24 = 2, /*!< CLK24 : 24 MHz MSPI clock */
MSPI_MSPICFG_CLKDIV_CLK12 = 4, /*!< CLK12 : 12 MHz MSPI clock */
MSPI_MSPICFG_CLKDIV_CLK6 = 8, /*!< CLK6 : 6 MHz MSPI clock */
MSPI_MSPICFG_CLKDIV_CLK3 = 16, /*!< CLK3 : 3 MHz MSPI clock */
MSPI_MSPICFG_CLKDIV_CLK1_5 = 32, /*!< CLK1_5 : 1.5 MHz MSPI clock */
} MSPI_MSPICFG_CLKDIV_Enum;
/* ============================================== MSPI MSPICFG IOMSEL [4..6] =============================================== */
typedef enum { /*!< MSPI_MSPICFG_IOMSEL */
MSPI_MSPICFG_IOMSEL_IOM0 = 0, /*!< IOM0 : Select IOM0 */
MSPI_MSPICFG_IOMSEL_IOM1 = 1, /*!< IOM1 : Select IOM1 */
MSPI_MSPICFG_IOMSEL_IOM2 = 2, /*!< IOM2 : Select IOM2 */
MSPI_MSPICFG_IOMSEL_IOM3 = 3, /*!< IOM3 : Select IOM3 */
MSPI_MSPICFG_IOMSEL_IOM4 = 4, /*!< IOM4 : Select IOM4 */
MSPI_MSPICFG_IOMSEL_IOM5 = 5, /*!< IOM5 : Select IOM5 */
MSPI_MSPICFG_IOMSEL_DISABLED = 7, /*!< DISABLED : No IOM selected. Signals always zero. */
} MSPI_MSPICFG_IOMSEL_Enum;
/* =============================================== MSPI MSPICFG TXNEG [3..3] =============================================== */
typedef enum { /*!< MSPI_MSPICFG_TXNEG */
MSPI_MSPICFG_TXNEG_NORMAL = 0, /*!< NORMAL : TX launched from posedge internal clock */
MSPI_MSPICFG_TXNEG_NEGEDGE = 1, /*!< NEGEDGE : TX data launched from negedge of internal clock */
} MSPI_MSPICFG_TXNEG_Enum;
/* =============================================== MSPI MSPICFG RXNEG [2..2] =============================================== */
typedef enum { /*!< MSPI_MSPICFG_RXNEG */
MSPI_MSPICFG_RXNEG_NORMAL = 0, /*!< NORMAL : RX data sampled on posedge of internal clock */
MSPI_MSPICFG_RXNEG_NEGEDGE = 1, /*!< NEGEDGE : RX data sampled on negedge of internal clock */
} MSPI_MSPICFG_RXNEG_Enum;
/* =============================================== MSPI MSPICFG RXCAP [1..1] =============================================== */
typedef enum { /*!< MSPI_MSPICFG_RXCAP */
MSPI_MSPICFG_RXCAP_NORMAL = 0, /*!< NORMAL : RX Capture phase aligns with CPHA setting */
MSPI_MSPICFG_RXCAP_DELAY = 1, /*!< DELAY : RX Capture phase is delayed from CPHA setting by one
clock edge */
} MSPI_MSPICFG_RXCAP_Enum;
/* ============================================== MSPI MSPICFG APBCLK [0..0] =============================================== */
typedef enum { /*!< MSPI_MSPICFG_APBCLK */
MSPI_MSPICFG_APBCLK_DIS = 0, /*!< DIS : Disable continuous clock. */
MSPI_MSPICFG_APBCLK_EN = 1, /*!< EN : Enable continuous clock. */
} MSPI_MSPICFG_APBCLK_Enum;
/* ======================================================== PADCFG ========================================================= */
/* ======================================================= PADOUTEN ======================================================== */
/* ============================================== MSPI PADOUTEN OUTEN [0..8] =============================================== */
typedef enum { /*!< MSPI_PADOUTEN_OUTEN */
MSPI_PADOUTEN_OUTEN_QUAD0 = 271, /*!< QUAD0 : Quad0 (4 data + 1 clock) */
MSPI_PADOUTEN_OUTEN_QUAD1 = 496, /*!< QUAD1 : Quad1 (4 data + 1 clock) */
MSPI_PADOUTEN_OUTEN_OCTAL = 511, /*!< OCTAL : Octal (8 data + 1 clock) */
MSPI_PADOUTEN_OUTEN_SERIAL0 = 259, /*!< SERIAL0 : Serial (2 data + 1 clock) */
MSPI_PADOUTEN_OUTEN_SERIAL1 = 304, /*!< SERIAL1 : Serial (2 data + 1 clock) */
} MSPI_PADOUTEN_OUTEN_Enum;
/* ========================================================= FLASH ========================================================= */
/* ============================================== MSPI FLASH XIPMIXED [8..10] ============================================== */
typedef enum { /*!< MSPI_FLASH_XIPMIXED */
MSPI_FLASH_XIPMIXED_NORMAL = 0, /*!< NORMAL : Transfers all proceed using the settings in DEVCFG
register (everything in the same data rate) */
MSPI_FLASH_XIPMIXED_D2 = 1, /*!< D2 : Data operations proceed in dual data rate */
MSPI_FLASH_XIPMIXED_AD2 = 3, /*!< AD2 : Address and Data operations proceed in dual data rate */
MSPI_FLASH_XIPMIXED_D4 = 5, /*!< D4 : Data operations proceed in quad data rate */
MSPI_FLASH_XIPMIXED_AD4 = 7, /*!< AD4 : Address and Data operations proceed in quad data rate */
} MSPI_FLASH_XIPMIXED_Enum;
/* =============================================== MSPI FLASH XIPACK [2..3] ================================================ */
typedef enum { /*!< MSPI_FLASH_XIPACK */
MSPI_FLASH_XIPACK_NOACK = 0, /*!< NOACK : No acknowledgment sent. Data IOs are tri-stated the
first turnaround cycle */
MSPI_FLASH_XIPACK_ACK = 2, /*!< ACK : Positive acknowledgment sent. Data IOs are driven to 0
the first turnaround cycle to acknowledge XIP mode */
MSPI_FLASH_XIPACK_TERMINATE = 3, /*!< TERMINATE : Negative acknowledgment sent. Data IOs are driven
to 1 the first turnaround cycle to terminate XIP mode.
XIPSENDI should be re-enabled for the next transfer */
} MSPI_FLASH_XIPACK_Enum;
/* ====================================================== SCRAMBLING ======================================================= */
/* ========================================================= INTEN ========================================================= */
/* ======================================================== INTSTAT ======================================================== */
/* ======================================================== INTCLR ========================================================= */
/* ======================================================== INTSET ========================================================= */
/* ======================================================== DMACFG ========================================================= */
/* =============================================== MSPI DMACFG DMAPRI [3..4] =============================================== */
typedef enum { /*!< MSPI_DMACFG_DMAPRI */
MSPI_DMACFG_DMAPRI_LOW = 0, /*!< LOW : Low Priority (service as best effort) */
MSPI_DMACFG_DMAPRI_HIGH = 1, /*!< HIGH : High Priority (service immediately) */
MSPI_DMACFG_DMAPRI_AUTO = 2, /*!< AUTO : Auto Priority (priority raised once TX FIFO empties or
RX FIFO fills) */
} MSPI_DMACFG_DMAPRI_Enum;
/* =============================================== MSPI DMACFG DMADIR [2..2] =============================================== */
typedef enum { /*!< MSPI_DMACFG_DMADIR */
MSPI_DMACFG_DMADIR_P2M = 0, /*!< P2M : Peripheral to Memory (SRAM) transaction */
MSPI_DMACFG_DMADIR_M2P = 1, /*!< M2P : Memory to Peripheral transaction */
} MSPI_DMACFG_DMADIR_Enum;
/* =============================================== MSPI DMACFG DMAEN [0..1] ================================================ */
typedef enum { /*!< MSPI_DMACFG_DMAEN */
MSPI_DMACFG_DMAEN_DIS = 0, /*!< DIS : Disable DMA Function */
MSPI_DMACFG_DMAEN_EN = 3, /*!< EN : Enable HW controlled DMA Function to manage DMA to flash
devices. HW will automatically handle issuance of instruction/address
bytes based on settings in the FLASH register. */
} MSPI_DMACFG_DMAEN_Enum;
/* ======================================================== DMASTAT ======================================================== */
/* ====================================================== DMATARGADDR ====================================================== */
/* ====================================================== DMADEVADDR ======================================================= */
/* ====================================================== DMATOTCOUNT ====================================================== */
/* ======================================================= DMABCOUNT ======================================================= */
/* ======================================================= DMATHRESH ======================================================= */
/* ========================================================= CQCFG ========================================================= */
/* ================================================ MSPI CQCFG CQPRI [1..1] ================================================ */
typedef enum { /*!< MSPI_CQCFG_CQPRI */
MSPI_CQCFG_CQPRI_LOW = 0, /*!< LOW : Low Priority (service as best effort) */
MSPI_CQCFG_CQPRI_HIGH = 1, /*!< HIGH : High Priority (service immediately) */
} MSPI_CQCFG_CQPRI_Enum;
/* ================================================ MSPI CQCFG CQEN [0..0] ================================================= */
typedef enum { /*!< MSPI_CQCFG_CQEN */
MSPI_CQCFG_CQEN_DIS = 0, /*!< DIS : Disable CQ Function */
MSPI_CQCFG_CQEN_EN = 1, /*!< EN : Enable CQ Function */
} MSPI_CQCFG_CQEN_Enum;
/* ======================================================== CQADDR ========================================================= */
/* ======================================================== CQSTAT ========================================================= */
/* ======================================================== CQFLAGS ======================================================== */
/* ============================================= MSPI CQFLAGS CQFLAGS [0..15] ============================================== */
typedef enum { /*!< MSPI_CQFLAGS_CQFLAGS */
MSPI_CQFLAGS_CQFLAGS_STOP = 32768, /*!< STOP : CQ Stop Flag. When set, CQ processing will complete. */
MSPI_CQFLAGS_CQFLAGS_CQIDX = 16384, /*!< CQIDX : CQ Index Pointers (CURIDX/ENDIDX) match. */
MSPI_CQFLAGS_CQFLAGS_DMACPL = 2048, /*!< DMACPL : DMA Complete Status (hardwired DMACPL bit in DMASTAT) */
MSPI_CQFLAGS_CQFLAGS_CMDCPL = 1024, /*!< CMDCPL : PIO Operation completed (STATUS bit in CTRL register) */
MSPI_CQFLAGS_CQFLAGS_IOM1READY = 512, /*!< IOM1READY : IOM Buffer 1 Ready Status (from selected IOM). This
status is the result of XNOR'ing the IOM0START with the
incoming status from the IOM. When high, MSPI can send
to the buffer. */
MSPI_CQFLAGS_CQFLAGS_IOM0READY = 256, /*!< IOM0READY : IOM Buffer 0 Ready Status (from selected IOM). This
status is the result of XNOR'ing the IOM0START with the
incoming status from the IOM. When high, MSPI can send
to the buffer. */
MSPI_CQFLAGS_CQFLAGS_SWFLAG7 = 128, /*!< SWFLAG7 : Software flag 7. Can be used by software to start/pause
operations. */
MSPI_CQFLAGS_CQFLAGS_SWFLAG6 = 64, /*!< SWFLAG6 : Software flag 6. Can be used by software to start/pause
operations. */
MSPI_CQFLAGS_CQFLAGS_SWFLAG5 = 32, /*!< SWFLAG5 : Software flag 5. Can be used by software to start/pause
operations. */
MSPI_CQFLAGS_CQFLAGS_SWFLAG4 = 16, /*!< SWFLAG4 : Software flag 4. Can be used by software to start/pause
operations. */
MSPI_CQFLAGS_CQFLAGS_SWFLAG3 = 8, /*!< SWFLAG3 : Software flag 3. Can be used by software to start/pause
operations. */
MSPI_CQFLAGS_CQFLAGS_SWFLAG2 = 4, /*!< SWFLAG2 : Software flag 2. Can be used by software to start/pause
operations. */
MSPI_CQFLAGS_CQFLAGS_SWFLAG1 = 2, /*!< SWFLAG1 : Software flag 1. Can be used by software to start/pause
operations. */
MSPI_CQFLAGS_CQFLAGS_SWFLAG0 = 1, /*!< SWFLAG0 : Software flag 0. Can be used by software to start/pause
operations. */
} MSPI_CQFLAGS_CQFLAGS_Enum;
/* ====================================================== CQSETCLEAR ======================================================= */
/* ======================================================== CQPAUSE ======================================================== */
/* ============================================== MSPI CQPAUSE CQMASK [0..15] ============================================== */
typedef enum { /*!< MSPI_CQPAUSE_CQMASK */
MSPI_CQPAUSE_CQMASK_STOP = 32768, /*!< STOP : CQ Stop Flag. When set, CQ processing will complete. */
MSPI_CQPAUSE_CQMASK_CQIDX = 16384, /*!< CQIDX : CQ Index Pointers (CURIDX/ENDIDX) match. */
MSPI_CQPAUSE_CQMASK_DMACPL = 2048, /*!< DMACPL : DMA Complete Status (hardwired DMACPL bit in DMASTAT) */
MSPI_CQPAUSE_CQMASK_CMDCPL = 1024, /*!< CMDCPL : PIO Operation completed (STATUS bit in CTRL register) */
MSPI_CQPAUSE_CQMASK_IOM1READY = 512, /*!< IOM1READY : IOM Buffer 1 Ready Status (from selected IOM). This
status is the result of XNOR'ing the IOM0START with the
incoming status from the IOM. When high, MSPI can send
to the buffer. */
MSPI_CQPAUSE_CQMASK_IOM0READY = 256, /*!< IOM0READY : IOM Buffer 0 Ready Status (from selected IOM). This
status is the result of XNOR'ing the IOM0START with the
incoming status from the IOM. When high, MSPI can send
to the buffer. */
MSPI_CQPAUSE_CQMASK_SWFLAG7 = 128, /*!< SWFLAG7 : Software flag 7. Can be used by software to start/pause
operations. */
MSPI_CQPAUSE_CQMASK_SWFLAG6 = 64, /*!< SWFLAG6 : Software flag 6. Can be used by software to start/pause
operations. */
MSPI_CQPAUSE_CQMASK_SWFLAG5 = 32, /*!< SWFLAG5 : Software flag 5. Can be used by software to start/pause
operations. */
MSPI_CQPAUSE_CQMASK_SWFLAG4 = 16, /*!< SWFLAG4 : Software flag 4. Can be used by software to start/pause
operations. */
MSPI_CQPAUSE_CQMASK_SWFLAG3 = 8, /*!< SWFLAG3 : Software flag 3. Can be used by software to start/pause
operations. */
MSPI_CQPAUSE_CQMASK_SWFLAG2 = 4, /*!< SWFLAG2 : Software flag 2. Can be used by software to start/pause
operations. */
MSPI_CQPAUSE_CQMASK_SWFLAG1 = 2, /*!< SWFLAG1 : Software flag 1. Can be used by software to start/pause
operations. */
MSPI_CQPAUSE_CQMASK_SWFLAG0 = 1, /*!< SWFLAG0 : Software flag 0. Can be used by software to start/pause
operations. */
} MSPI_CQPAUSE_CQMASK_Enum;
/* ======================================================= CQCURIDX ======================================================== */
/* ======================================================= CQENDIDX ======================================================== */
/* =========================================================================================================================== */
/* ================ PDM ================ */
/* =========================================================================================================================== */
/* ========================================================= PCFG ========================================================== */
/* =============================================== PDM PCFG LRSWAP [31..31] ================================================ */
typedef enum { /*!< PDM_PCFG_LRSWAP */
PDM_PCFG_LRSWAP_EN = 1, /*!< EN : Swap left and right channels (FIFO Read RIGHT_LEFT). */
PDM_PCFG_LRSWAP_NOSWAP = 0, /*!< NOSWAP : No channel swapping (IFO Read LEFT_RIGHT). */
} PDM_PCFG_LRSWAP_Enum;
/* ============================================== PDM PCFG PGARIGHT [26..30] =============================================== */
typedef enum { /*!< PDM_PCFG_PGARIGHT */
PDM_PCFG_PGARIGHT_P405DB = 31, /*!< P405DB : 40.5 db gain. */
PDM_PCFG_PGARIGHT_P390DB = 30, /*!< P390DB : 39.0 db gain. */
PDM_PCFG_PGARIGHT_P375DB = 29, /*!< P375DB : 37.5 db gain. */
PDM_PCFG_PGARIGHT_P360DB = 28, /*!< P360DB : 36.0 db gain. */
PDM_PCFG_PGARIGHT_P345DB = 27, /*!< P345DB : 34.5 db gain. */
PDM_PCFG_PGARIGHT_P330DB = 26, /*!< P330DB : 33.0 db gain. */
PDM_PCFG_PGARIGHT_P315DB = 25, /*!< P315DB : 31.5 db gain. */
PDM_PCFG_PGARIGHT_P300DB = 24, /*!< P300DB : 30.0 db gain. */
PDM_PCFG_PGARIGHT_P285DB = 23, /*!< P285DB : 28.5 db gain. */
PDM_PCFG_PGARIGHT_P270DB = 22, /*!< P270DB : 27.0 db gain. */
PDM_PCFG_PGARIGHT_P255DB = 21, /*!< P255DB : 25.5 db gain. */
PDM_PCFG_PGARIGHT_P240DB = 20, /*!< P240DB : 24.0 db gain. */
PDM_PCFG_PGARIGHT_P225DB = 19, /*!< P225DB : 22.5 db gain. */
PDM_PCFG_PGARIGHT_P210DB = 18, /*!< P210DB : 21.0 db gain. */
PDM_PCFG_PGARIGHT_P195DB = 17, /*!< P195DB : 19.5 db gain. */
PDM_PCFG_PGARIGHT_P180DB = 16, /*!< P180DB : 18.0 db gain. */
PDM_PCFG_PGARIGHT_P165DB = 15, /*!< P165DB : 16.5 db gain. */
PDM_PCFG_PGARIGHT_P150DB = 14, /*!< P150DB : 15.0 db gain. */
PDM_PCFG_PGARIGHT_P135DB = 13, /*!< P135DB : 13.5 db gain. */
PDM_PCFG_PGARIGHT_P120DB = 12, /*!< P120DB : 12.0 db gain. */
PDM_PCFG_PGARIGHT_P105DB = 11, /*!< P105DB : 10.5 db gain. */
PDM_PCFG_PGARIGHT_P90DB = 10, /*!< P90DB : 9.0 db gain. */
PDM_PCFG_PGARIGHT_P75DB = 9, /*!< P75DB : 7.5 db gain. */
PDM_PCFG_PGARIGHT_P60DB = 8, /*!< P60DB : 6.0 db gain. */
PDM_PCFG_PGARIGHT_P45DB = 7, /*!< P45DB : 4.5 db gain. */
PDM_PCFG_PGARIGHT_P30DB = 6, /*!< P30DB : 3.0 db gain. */
PDM_PCFG_PGARIGHT_P15DB = 5, /*!< P15DB : 1.5 db gain. */
PDM_PCFG_PGARIGHT_0DB = 4, /*!< 0DB : 0.0 db gain. */
PDM_PCFG_PGARIGHT_M15DB = 3, /*!< M15DB : -1.5 db gain. */
PDM_PCFG_PGARIGHT_M300DB = 2, /*!< M300DB : -3.0 db gain. */
PDM_PCFG_PGARIGHT_M45DB = 1, /*!< M45DB : -4.5 db gain. */
PDM_PCFG_PGARIGHT_M60DB = 0, /*!< M60DB : -6.0 db gain. */
} PDM_PCFG_PGARIGHT_Enum;
/* =============================================== PDM PCFG PGALEFT [21..25] =============================================== */
typedef enum { /*!< PDM_PCFG_PGALEFT */
PDM_PCFG_PGALEFT_P405DB = 31, /*!< P405DB : 40.5 db gain. */
PDM_PCFG_PGALEFT_P390DB = 30, /*!< P390DB : 39.0 db gain. */
PDM_PCFG_PGALEFT_P375DB = 29, /*!< P375DB : 37.5 db gain. */
PDM_PCFG_PGALEFT_P360DB = 28, /*!< P360DB : 36.0 db gain. */
PDM_PCFG_PGALEFT_P345DB = 27, /*!< P345DB : 34.5 db gain. */
PDM_PCFG_PGALEFT_P330DB = 26, /*!< P330DB : 33.0 db gain. */
PDM_PCFG_PGALEFT_P315DB = 25, /*!< P315DB : 31.5 db gain. */
PDM_PCFG_PGALEFT_P300DB = 24, /*!< P300DB : 30.0 db gain. */
PDM_PCFG_PGALEFT_P285DB = 23, /*!< P285DB : 28.5 db gain. */
PDM_PCFG_PGALEFT_P270DB = 22, /*!< P270DB : 27.0 db gain. */
PDM_PCFG_PGALEFT_P255DB = 21, /*!< P255DB : 25.5 db gain. */
PDM_PCFG_PGALEFT_P240DB = 20, /*!< P240DB : 24.0 db gain. */
PDM_PCFG_PGALEFT_P225DB = 19, /*!< P225DB : 22.5 db gain. */
PDM_PCFG_PGALEFT_P210DB = 18, /*!< P210DB : 21.0 db gain. */
PDM_PCFG_PGALEFT_P195DB = 17, /*!< P195DB : 19.5 db gain. */
PDM_PCFG_PGALEFT_P180DB = 16, /*!< P180DB : 18.0 db gain. */
PDM_PCFG_PGALEFT_P165DB = 15, /*!< P165DB : 16.5 db gain. */
PDM_PCFG_PGALEFT_P150DB = 14, /*!< P150DB : 15.0 db gain. */
PDM_PCFG_PGALEFT_P135DB = 13, /*!< P135DB : 13.5 db gain. */
PDM_PCFG_PGALEFT_P120DB = 12, /*!< P120DB : 12.0 db gain. */
PDM_PCFG_PGALEFT_P105DB = 11, /*!< P105DB : 10.5 db gain. */
PDM_PCFG_PGALEFT_P90DB = 10, /*!< P90DB : 9.0 db gain. */
PDM_PCFG_PGALEFT_P75DB = 9, /*!< P75DB : 7.5 db gain. */
PDM_PCFG_PGALEFT_P60DB = 8, /*!< P60DB : 6.0 db gain. */
PDM_PCFG_PGALEFT_P45DB = 7, /*!< P45DB : 4.5 db gain. */
PDM_PCFG_PGALEFT_P30DB = 6, /*!< P30DB : 3.0 db gain. */
PDM_PCFG_PGALEFT_P15DB = 5, /*!< P15DB : 1.5 db gain. */
PDM_PCFG_PGALEFT_0DB = 4, /*!< 0DB : 0.0 db gain. */
PDM_PCFG_PGALEFT_M15DB = 3, /*!< M15DB : -1.5 db gain. */
PDM_PCFG_PGALEFT_M300DB = 2, /*!< M300DB : -3.0 db gain. */
PDM_PCFG_PGALEFT_M45DB = 1, /*!< M45DB : -4.5 db gain. */
PDM_PCFG_PGALEFT_M60DB = 0, /*!< M60DB : -6.0 db gain. */
} PDM_PCFG_PGALEFT_Enum;
/* =============================================== PDM PCFG MCLKDIV [17..18] =============================================== */
typedef enum { /*!< PDM_PCFG_MCLKDIV */
PDM_PCFG_MCLKDIV_MCKDIV4 = 3, /*!< MCKDIV4 : Divide input clock by 4 */
PDM_PCFG_MCLKDIV_MCKDIV3 = 2, /*!< MCKDIV3 : Divide input clock by 3 */
PDM_PCFG_MCLKDIV_MCKDIV2 = 1, /*!< MCKDIV2 : Divide input clock by 2 */
PDM_PCFG_MCLKDIV_MCKDIV1 = 0, /*!< MCKDIV1 : Divide input clock by 1 */
} PDM_PCFG_MCLKDIV_Enum;
/* ================================================ PDM PCFG ADCHPD [9..9] ================================================= */
typedef enum { /*!< PDM_PCFG_ADCHPD */
PDM_PCFG_ADCHPD_EN = 0, /*!< EN : Enable high pass filter. */
PDM_PCFG_ADCHPD_DIS = 1, /*!< DIS : Disable high pass filter. */
} PDM_PCFG_ADCHPD_Enum;
/* =============================================== PDM PCFG SOFTMUTE [1..1] ================================================ */
typedef enum { /*!< PDM_PCFG_SOFTMUTE */
PDM_PCFG_SOFTMUTE_EN = 1, /*!< EN : Enable Soft Mute. */
PDM_PCFG_SOFTMUTE_DIS = 0, /*!< DIS : Disable Soft Mute. */
} PDM_PCFG_SOFTMUTE_Enum;
/* =============================================== PDM PCFG PDMCOREEN [0..0] =============================================== */
typedef enum { /*!< PDM_PCFG_PDMCOREEN */
PDM_PCFG_PDMCOREEN_EN = 1, /*!< EN : Enable Data Streaming. */
PDM_PCFG_PDMCOREEN_DIS = 0, /*!< DIS : Disable Data Streaming. */
} PDM_PCFG_PDMCOREEN_Enum;
/* ========================================================= VCFG ========================================================== */
/* =============================================== PDM VCFG IOCLKEN [31..31] =============================================== */
typedef enum { /*!< PDM_VCFG_IOCLKEN */
PDM_VCFG_IOCLKEN_DIS = 0, /*!< DIS : Disable FIFO read. */
PDM_VCFG_IOCLKEN_EN = 1, /*!< EN : Enable FIFO read. */
} PDM_VCFG_IOCLKEN_Enum;
/* ================================================ PDM VCFG RSTB [30..30] ================================================= */
typedef enum { /*!< PDM_VCFG_RSTB */
PDM_VCFG_RSTB_RESET = 0, /*!< RESET : Reset the core. */
PDM_VCFG_RSTB_NORM = 1, /*!< NORM : Enable the core. */
} PDM_VCFG_RSTB_Enum;
/* ============================================== PDM VCFG PDMCLKSEL [27..29] ============================================== */
typedef enum { /*!< PDM_VCFG_PDMCLKSEL */
PDM_VCFG_PDMCLKSEL_DISABLE = 0, /*!< DISABLE : Static value. */
PDM_VCFG_PDMCLKSEL_12MHz = 1, /*!< 12MHz : PDM clock is 12 MHz. */
PDM_VCFG_PDMCLKSEL_6MHz = 2, /*!< 6MHz : PDM clock is 6 MHz. */
PDM_VCFG_PDMCLKSEL_3MHz = 3, /*!< 3MHz : PDM clock is 3 MHz. */
PDM_VCFG_PDMCLKSEL_1_5MHz = 4, /*!< 1_5MHz : PDM clock is 1.5 MHz. */
PDM_VCFG_PDMCLKSEL_750KHz = 5, /*!< 750KHz : PDM clock is 750 KHz. */
PDM_VCFG_PDMCLKSEL_375KHz = 6, /*!< 375KHz : PDM clock is 375 KHz. */
PDM_VCFG_PDMCLKSEL_187KHz = 7, /*!< 187KHz : PDM clock is 187.5 KHz. */
} PDM_VCFG_PDMCLKSEL_Enum;
/* ============================================== PDM VCFG PDMCLKEN [26..26] =============================================== */
typedef enum { /*!< PDM_VCFG_PDMCLKEN */
PDM_VCFG_PDMCLKEN_DIS = 0, /*!< DIS : Disable serial clock. */
PDM_VCFG_PDMCLKEN_EN = 1, /*!< EN : Enable serial clock. */
} PDM_VCFG_PDMCLKEN_Enum;
/* ================================================ PDM VCFG I2SEN [20..20] ================================================ */
typedef enum { /*!< PDM_VCFG_I2SEN */
PDM_VCFG_I2SEN_DIS = 0, /*!< DIS : Disable I2S interface. */
PDM_VCFG_I2SEN_EN = 1, /*!< EN : Enable I2S interface. */
} PDM_VCFG_I2SEN_Enum;
/* =============================================== PDM VCFG BCLKINV [19..19] =============================================== */
typedef enum { /*!< PDM_VCFG_BCLKINV */
PDM_VCFG_BCLKINV_INV = 0, /*!< INV : BCLK inverted. */
PDM_VCFG_BCLKINV_NORM = 1, /*!< NORM : BCLK not inverted. */
} PDM_VCFG_BCLKINV_Enum;
/* ============================================== PDM VCFG DMICKDEL [17..17] =============================================== */
typedef enum { /*!< PDM_VCFG_DMICKDEL */
PDM_VCFG_DMICKDEL_0CYC = 0, /*!< 0CYC : No delay. */
PDM_VCFG_DMICKDEL_1CYC = 1, /*!< 1CYC : 1 cycle delay. */
} PDM_VCFG_DMICKDEL_Enum;
/* ================================================ PDM VCFG SELAP [16..16] ================================================ */
typedef enum { /*!< PDM_VCFG_SELAP */
PDM_VCFG_SELAP_I2S = 1, /*!< I2S : Clock source from I2S BCLK. */
PDM_VCFG_SELAP_INTERNAL = 0, /*!< INTERNAL : Clock source from internal clock generator. */
} PDM_VCFG_SELAP_Enum;
/* ================================================ PDM VCFG PCMPACK [8..8] ================================================ */
typedef enum { /*!< PDM_VCFG_PCMPACK */
PDM_VCFG_PCMPACK_DIS = 0, /*!< DIS : Disable PCM packing. */
PDM_VCFG_PCMPACK_EN = 1, /*!< EN : Enable PCM packing. */
} PDM_VCFG_PCMPACK_Enum;
/* ================================================= PDM VCFG CHSET [3..4] ================================================= */
typedef enum { /*!< PDM_VCFG_CHSET */
PDM_VCFG_CHSET_DIS = 0, /*!< DIS : Channel disabled. */
PDM_VCFG_CHSET_LEFT = 1, /*!< LEFT : Mono left channel. */
PDM_VCFG_CHSET_RIGHT = 2, /*!< RIGHT : Mono right channel. */
PDM_VCFG_CHSET_STEREO = 3, /*!< STEREO : Stereo channels. */
} PDM_VCFG_CHSET_Enum;
/* ======================================================= VOICESTAT ======================================================= */
/* ======================================================= FIFOREAD ======================================================== */
/* ======================================================= FIFOFLUSH ======================================================= */
/* ======================================================== FIFOTHR ======================================================== */
/* ========================================================= INTEN ========================================================= */
/* ======================================================== INTSTAT ======================================================== */
/* ======================================================== INTCLR ========================================================= */
/* ======================================================== INTSET ========================================================= */
/* ======================================================= DMATRIGEN ======================================================= */
/* ====================================================== DMATRIGSTAT ====================================================== */
/* ======================================================== DMACFG ========================================================= */
/* =============================================== PDM DMACFG DMAPRI [8..8] ================================================ */
typedef enum { /*!< PDM_DMACFG_DMAPRI */
PDM_DMACFG_DMAPRI_LOW = 0, /*!< LOW : Low Priority (service as best effort) */
PDM_DMACFG_DMAPRI_HIGH = 1, /*!< HIGH : High Priority (service immediately) */
} PDM_DMACFG_DMAPRI_Enum;
/* =============================================== PDM DMACFG DMADIR [2..2] ================================================ */
typedef enum { /*!< PDM_DMACFG_DMADIR */
PDM_DMACFG_DMADIR_P2M = 0, /*!< P2M : Peripheral to Memory (SRAM) transaction. THe PDM module
will only DMA to memory. */
PDM_DMACFG_DMADIR_M2P = 1, /*!< M2P : Memory to Peripheral transaction. Not available for PDM
module */
} PDM_DMACFG_DMADIR_Enum;
/* ================================================ PDM DMACFG DMAEN [0..0] ================================================ */
typedef enum { /*!< PDM_DMACFG_DMAEN */
PDM_DMACFG_DMAEN_DIS = 0, /*!< DIS : Disable DMA Function */
PDM_DMACFG_DMAEN_EN = 1, /*!< EN : Enable DMA Function */
} PDM_DMACFG_DMAEN_Enum;
/* ====================================================== DMATOTCOUNT ====================================================== */
/* ====================================================== DMATARGADDR ====================================================== */
/* ======================================================== DMASTAT ======================================================== */
/* =========================================================================================================================== */
/* ================ PWRCTRL ================ */
/* =========================================================================================================================== */
/* ======================================================= SUPPLYSRC ======================================================= */
/* ========================================== PWRCTRL SUPPLYSRC BLEBUCKEN [0..0] =========================================== */
typedef enum { /*!< PWRCTRL_SUPPLYSRC_BLEBUCKEN */
PWRCTRL_SUPPLYSRC_BLEBUCKEN_EN = 1, /*!< EN : Enable the BLE Buck. */
PWRCTRL_SUPPLYSRC_BLEBUCKEN_DIS = 0, /*!< DIS : Disable the BLE Buck. */
} PWRCTRL_SUPPLYSRC_BLEBUCKEN_Enum;
/* ===================================================== SUPPLYSTATUS ====================================================== */
/* ========================================= PWRCTRL SUPPLYSTATUS BLEBUCKON [1..1] ========================================= */
typedef enum { /*!< PWRCTRL_SUPPLYSTATUS_BLEBUCKON */
PWRCTRL_SUPPLYSTATUS_BLEBUCKON_LDO = 0, /*!< LDO : Indicates the the LDO is supplying the BLE/Burst power
domain */
PWRCTRL_SUPPLYSTATUS_BLEBUCKON_BUCK = 1, /*!< BUCK : Indicates the the Buck is supplying the BLE/Burst power
domain */
} PWRCTRL_SUPPLYSTATUS_BLEBUCKON_Enum;
/* ======================================== PWRCTRL SUPPLYSTATUS SIMOBUCKON [0..0] ========================================= */
typedef enum { /*!< PWRCTRL_SUPPLYSTATUS_SIMOBUCKON */
PWRCTRL_SUPPLYSTATUS_SIMOBUCKON_OFF = 0, /*!< OFF : Indicates the the SIMO Buck is OFF. */
PWRCTRL_SUPPLYSTATUS_SIMOBUCKON_ON = 1, /*!< ON : Indicates the the SIMO Buck is ON. */
} PWRCTRL_SUPPLYSTATUS_SIMOBUCKON_Enum;
/* ======================================================= DEVPWREN ======================================================== */
/* =========================================== PWRCTRL DEVPWREN PWRBLEL [13..13] =========================================== */
typedef enum { /*!< PWRCTRL_DEVPWREN_PWRBLEL */
PWRCTRL_DEVPWREN_PWRBLEL_EN = 1, /*!< EN : Power up BLE controller */
PWRCTRL_DEVPWREN_PWRBLEL_DIS = 0, /*!< DIS : Power down BLE controller */
} PWRCTRL_DEVPWREN_PWRBLEL_Enum;
/* =========================================== PWRCTRL DEVPWREN PWRPDM [12..12] ============================================ */
typedef enum { /*!< PWRCTRL_DEVPWREN_PWRPDM */
PWRCTRL_DEVPWREN_PWRPDM_EN = 1, /*!< EN : Power up PDM */
PWRCTRL_DEVPWREN_PWRPDM_DIS = 0, /*!< DIS : Power down PDM */
} PWRCTRL_DEVPWREN_PWRPDM_Enum;
/* =========================================== PWRCTRL DEVPWREN PWRMSPI [11..11] =========================================== */
typedef enum { /*!< PWRCTRL_DEVPWREN_PWRMSPI */
PWRCTRL_DEVPWREN_PWRMSPI_EN = 1, /*!< EN : Power up MSPI */
PWRCTRL_DEVPWREN_PWRMSPI_DIS = 0, /*!< DIS : Power down MSPI */
} PWRCTRL_DEVPWREN_PWRMSPI_Enum;
/* ========================================== PWRCTRL DEVPWREN PWRSCARD [10..10] =========================================== */
typedef enum { /*!< PWRCTRL_DEVPWREN_PWRSCARD */
PWRCTRL_DEVPWREN_PWRSCARD_EN = 1, /*!< EN : Power up SCARD */
PWRCTRL_DEVPWREN_PWRSCARD_DIS = 0, /*!< DIS : Power down SCARD */
} PWRCTRL_DEVPWREN_PWRSCARD_Enum;
/* ============================================ PWRCTRL DEVPWREN PWRADC [9..9] ============================================= */
typedef enum { /*!< PWRCTRL_DEVPWREN_PWRADC */
PWRCTRL_DEVPWREN_PWRADC_EN = 1, /*!< EN : Power up ADC */
PWRCTRL_DEVPWREN_PWRADC_DIS = 0, /*!< DIS : Power Down ADC */
} PWRCTRL_DEVPWREN_PWRADC_Enum;
/* =========================================== PWRCTRL DEVPWREN PWRUART1 [8..8] ============================================ */
typedef enum { /*!< PWRCTRL_DEVPWREN_PWRUART1 */
PWRCTRL_DEVPWREN_PWRUART1_EN = 1, /*!< EN : Power up UART 1 */
PWRCTRL_DEVPWREN_PWRUART1_DIS = 0, /*!< DIS : Power down UART 1 */
} PWRCTRL_DEVPWREN_PWRUART1_Enum;
/* =========================================== PWRCTRL DEVPWREN PWRUART0 [7..7] ============================================ */
typedef enum { /*!< PWRCTRL_DEVPWREN_PWRUART0 */
PWRCTRL_DEVPWREN_PWRUART0_EN = 1, /*!< EN : Power up UART 0 */
PWRCTRL_DEVPWREN_PWRUART0_DIS = 0, /*!< DIS : Power down UART 0 */
} PWRCTRL_DEVPWREN_PWRUART0_Enum;
/* ============================================ PWRCTRL DEVPWREN PWRIOM5 [6..6] ============================================ */
typedef enum { /*!< PWRCTRL_DEVPWREN_PWRIOM5 */
PWRCTRL_DEVPWREN_PWRIOM5_EN = 1, /*!< EN : Power up IO Master 5 */
PWRCTRL_DEVPWREN_PWRIOM5_DIS = 0, /*!< DIS : Power down IO Master 5 */
} PWRCTRL_DEVPWREN_PWRIOM5_Enum;
/* ============================================ PWRCTRL DEVPWREN PWRIOM4 [5..5] ============================================ */
typedef enum { /*!< PWRCTRL_DEVPWREN_PWRIOM4 */
PWRCTRL_DEVPWREN_PWRIOM4_EN = 1, /*!< EN : Power up IO Master 4 */
PWRCTRL_DEVPWREN_PWRIOM4_DIS = 0, /*!< DIS : Power down IO Master 4 */
} PWRCTRL_DEVPWREN_PWRIOM4_Enum;
/* ============================================ PWRCTRL DEVPWREN PWRIOM3 [4..4] ============================================ */
typedef enum { /*!< PWRCTRL_DEVPWREN_PWRIOM3 */
PWRCTRL_DEVPWREN_PWRIOM3_EN = 1, /*!< EN : Power up IO Master 3 */
PWRCTRL_DEVPWREN_PWRIOM3_DIS = 0, /*!< DIS : Power down IO Master 3 */
} PWRCTRL_DEVPWREN_PWRIOM3_Enum;
/* ============================================ PWRCTRL DEVPWREN PWRIOM2 [3..3] ============================================ */
typedef enum { /*!< PWRCTRL_DEVPWREN_PWRIOM2 */
PWRCTRL_DEVPWREN_PWRIOM2_EN = 1, /*!< EN : Power up IO Master 2 */
PWRCTRL_DEVPWREN_PWRIOM2_DIS = 0, /*!< DIS : Power down IO Master 2 */
} PWRCTRL_DEVPWREN_PWRIOM2_Enum;
/* ============================================ PWRCTRL DEVPWREN PWRIOM1 [2..2] ============================================ */
typedef enum { /*!< PWRCTRL_DEVPWREN_PWRIOM1 */
PWRCTRL_DEVPWREN_PWRIOM1_EN = 1, /*!< EN : Power up IO Master 1 */
PWRCTRL_DEVPWREN_PWRIOM1_DIS = 0, /*!< DIS : Power down IO Master 1 */
} PWRCTRL_DEVPWREN_PWRIOM1_Enum;
/* ============================================ PWRCTRL DEVPWREN PWRIOM0 [1..1] ============================================ */
typedef enum { /*!< PWRCTRL_DEVPWREN_PWRIOM0 */
PWRCTRL_DEVPWREN_PWRIOM0_EN = 1, /*!< EN : Power up IO Master 0 */
PWRCTRL_DEVPWREN_PWRIOM0_DIS = 0, /*!< DIS : Power down IO Master 0 */
} PWRCTRL_DEVPWREN_PWRIOM0_Enum;
/* ============================================ PWRCTRL DEVPWREN PWRIOS [0..0] ============================================= */
typedef enum { /*!< PWRCTRL_DEVPWREN_PWRIOS */
PWRCTRL_DEVPWREN_PWRIOS_EN = 1, /*!< EN : Power up IO slave */
PWRCTRL_DEVPWREN_PWRIOS_DIS = 0, /*!< DIS : Power down IO slave */
} PWRCTRL_DEVPWREN_PWRIOS_Enum;
/* ===================================================== MEMPWDINSLEEP ===================================================== */
/* ====================================== PWRCTRL MEMPWDINSLEEP CACHEPWDSLP [31..31] ======================================= */
typedef enum { /*!< PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP */
PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_EN = 1, /*!< EN : Power down cache in deep sleep */
PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_DIS = 0, /*!< DIS : Retain cache in deep sleep */
} PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_Enum;
/* ====================================== PWRCTRL MEMPWDINSLEEP FLASH1PWDSLP [14..14] ====================================== */
typedef enum { /*!< PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP */
PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP_EN = 1, /*!< EN : FLASH1 is powered down during deep sleep */
PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP_DIS = 0, /*!< DIS : FLASH1 is kept powered on during deep sleep */
} PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP_Enum;
/* ====================================== PWRCTRL MEMPWDINSLEEP FLASH0PWDSLP [13..13] ====================================== */
typedef enum { /*!< PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP */
PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_EN = 1, /*!< EN : FLASH0 is powered down during deep sleep */
PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_DIS = 0, /*!< DIS : FLASH0 is kept powered on during deep sleep */
} PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_Enum;
/* ======================================= PWRCTRL MEMPWDINSLEEP SRAMPWDSLP [3..12] ======================================== */
typedef enum { /*!< PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP */
PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_NONE = 0, /*!< NONE : All banks retained */
PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP0 = 1, /*!< GROUP0 : SRAM GROUP0 powered down (64KB-96KB) */
PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP1 = 2, /*!< GROUP1 : SRAM GROUP1 powered down (96KB-128KB) */
PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP2 = 4, /*!< GROUP2 : SRAM GROUP2 powered down (128KB-160KB) */
PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP3 = 8, /*!< GROUP3 : SRAM GROUP3 powered down (160KB-192KB) */
PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP4 = 16, /*!< GROUP4 : SRAM GROUP4 powered down (192KB-224KB) */
PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP5 = 32, /*!< GROUP5 : SRAM GROUP5 powered down (224KB-256KB) */
PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP6 = 64, /*!< GROUP6 : SRAM GROUP6 powered down (256KB-288KB) */
PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP7 = 128,/*!< GROUP7 : SRAM GROUP7 powered down (288KB-320KB) */
PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP8 = 256,/*!< GROUP8 : SRAM GROUP8 powered down (320KB-352KB) */
PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP9 = 512,/*!< GROUP9 : SRAM GROUP9 powered down (352KB-384KB) */
PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_SRAM64K = 3, /*!< SRAM64K : Power-down lower 64k SRAM (64KB-128KB) */
PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_SRAM128K = 15,/*!< SRAM128K : Power-down lower 128k SRAM (64KB-192KB) */
PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_ALLBUTLOWER32K = 1022,/*!< ALLBUTLOWER32K : All SRAM banks but lower 32k powered down (96KB-384KB). */
PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_ALLBUTLOWER64K = 1020,/*!< ALLBUTLOWER64K : All banks but lower 64k powered down. */
PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_ALLBUTLOWER128K = 1008,/*!< ALLBUTLOWER128K : All banks but lower 128k powered down. */
PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_ALL = 1023, /*!< ALL : All banks powered down. */
} PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_Enum;
/* ======================================== PWRCTRL MEMPWDINSLEEP DTCMPWDSLP [0..2] ======================================== */
typedef enum { /*!< PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP */
PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_NONE = 0, /*!< NONE : All DTCM retained */
PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_GROUP0DTCM0 = 1,/*!< GROUP0DTCM0 : Group0_DTCM0 powered down in deep sleep (0KB-8KB) */
PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_GROUP0DTCM1 = 2,/*!< GROUP0DTCM1 : Group0_DTCM1 powered down in deep sleep (8KB-32KB) */
PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_GROUP0 = 3, /*!< GROUP0 : Both DTCMs in group0 are powered down in deep sleep
(0KB-32KB) */
PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_ALLBUTGROUP0DTCM0 = 6,/*!< ALLBUTGROUP0DTCM0 : Group1 and Group0_DTCM1 are powered down
in deep sleep (8KB-64KB) */
PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_GROUP1 = 4, /*!< GROUP1 : Group1 DTCM powered down in deep sleep (32KB-64KB) */
PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_ALL = 7, /*!< ALL : All DTCMs powered down in deep sleep (0KB-64KB) */
} PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_Enum;
/* ======================================================= MEMPWREN ======================================================== */
/* =========================================== PWRCTRL MEMPWREN CACHEB2 [31..31] =========================================== */
typedef enum { /*!< PWRCTRL_MEMPWREN_CACHEB2 */
PWRCTRL_MEMPWREN_CACHEB2_EN = 1, /*!< EN : Power up Cache Bank 2 */
PWRCTRL_MEMPWREN_CACHEB2_DIS = 0, /*!< DIS : Power down Cache Bank 2 */
} PWRCTRL_MEMPWREN_CACHEB2_Enum;
/* =========================================== PWRCTRL MEMPWREN CACHEB0 [30..30] =========================================== */
typedef enum { /*!< PWRCTRL_MEMPWREN_CACHEB0 */
PWRCTRL_MEMPWREN_CACHEB0_EN = 1, /*!< EN : Power up Cache Bank 0 */
PWRCTRL_MEMPWREN_CACHEB0_DIS = 0, /*!< DIS : Power down Cache Bank 0 */
} PWRCTRL_MEMPWREN_CACHEB0_Enum;
/* =========================================== PWRCTRL MEMPWREN FLASH1 [14..14] ============================================ */
typedef enum { /*!< PWRCTRL_MEMPWREN_FLASH1 */
PWRCTRL_MEMPWREN_FLASH1_EN = 1, /*!< EN : Power up FLASH1 */
PWRCTRL_MEMPWREN_FLASH1_DIS = 0, /*!< DIS : Power down FLASH1 */
} PWRCTRL_MEMPWREN_FLASH1_Enum;
/* =========================================== PWRCTRL MEMPWREN FLASH0 [13..13] ============================================ */
typedef enum { /*!< PWRCTRL_MEMPWREN_FLASH0 */
PWRCTRL_MEMPWREN_FLASH0_EN = 1, /*!< EN : Power up FLASH0 */
PWRCTRL_MEMPWREN_FLASH0_DIS = 0, /*!< DIS : Power down FLASH0 */
} PWRCTRL_MEMPWREN_FLASH0_Enum;
/* ============================================= PWRCTRL MEMPWREN SRAM [3..12] ============================================= */
typedef enum { /*!< PWRCTRL_MEMPWREN_SRAM */
PWRCTRL_MEMPWREN_SRAM_NONE = 0, /*!< NONE : Do not power ON any of the SRAM banks */
PWRCTRL_MEMPWREN_SRAM_GROUP0 = 1, /*!< GROUP0 : Power ON only SRAM group0 (0KB-32KB) */
PWRCTRL_MEMPWREN_SRAM_GROUP1 = 2, /*!< GROUP1 : Power ON only SRAM group1 (32KB-64KB) */
PWRCTRL_MEMPWREN_SRAM_GROUP2 = 4, /*!< GROUP2 : Power ON only SRAM group2 (64KB-96KB) */
PWRCTRL_MEMPWREN_SRAM_GROUP3 = 8, /*!< GROUP3 : Power ON only SRAM group3 (96KB-128KB) */
PWRCTRL_MEMPWREN_SRAM_GROUP4 = 16, /*!< GROUP4 : Power ON only SRAM group4 (128KB-160KB) */
PWRCTRL_MEMPWREN_SRAM_GROUP5 = 32, /*!< GROUP5 : Power ON only SRAM group5 (160KB-192KB) */
PWRCTRL_MEMPWREN_SRAM_GROUP6 = 64, /*!< GROUP6 : Power ON only SRAM group6 (192KB-224KB) */
PWRCTRL_MEMPWREN_SRAM_GROUP7 = 128, /*!< GROUP7 : Power ON only SRAM group7 (224KB-256KB) */
PWRCTRL_MEMPWREN_SRAM_GROUP8 = 256, /*!< GROUP8 : Power ON only SRAM group8 (256KB-288KB) */
PWRCTRL_MEMPWREN_SRAM_GROUP9 = 512, /*!< GROUP9 : Power ON only SRAM group9 (288KB-320KB) */
PWRCTRL_MEMPWREN_SRAM_SRAM64K = 3, /*!< SRAM64K : Power ON only lower 64k */
PWRCTRL_MEMPWREN_SRAM_SRAM128K = 15, /*!< SRAM128K : Power ON only lower 128k */
PWRCTRL_MEMPWREN_SRAM_SRAM256K = 255, /*!< SRAM256K : Power ON only lower 256k */
PWRCTRL_MEMPWREN_SRAM_ALL = 1023, /*!< ALL : All SRAM banks (320K) powered ON */
} PWRCTRL_MEMPWREN_SRAM_Enum;
/* ============================================= PWRCTRL MEMPWREN DTCM [0..2] ============================================== */
typedef enum { /*!< PWRCTRL_MEMPWREN_DTCM */
PWRCTRL_MEMPWREN_DTCM_NONE = 0, /*!< NONE : Do not enable power to any DTCMs */
PWRCTRL_MEMPWREN_DTCM_GROUP0DTCM0 = 1, /*!< GROUP0DTCM0 : Power ON only GROUP0_DTCM0 */
PWRCTRL_MEMPWREN_DTCM_GROUP0DTCM1 = 2, /*!< GROUP0DTCM1 : Power ON only GROUP0_DTCM1 */
PWRCTRL_MEMPWREN_DTCM_GROUP0 = 3, /*!< GROUP0 : Power ON only DTCMs in group0 */
PWRCTRL_MEMPWREN_DTCM_GROUP1 = 4, /*!< GROUP1 : Power ON only DTCMs in group1 */
PWRCTRL_MEMPWREN_DTCM_ALL = 7, /*!< ALL : Power ON all DTCMs */
} PWRCTRL_MEMPWREN_DTCM_Enum;
/* ===================================================== MEMPWRSTATUS ====================================================== */
/* ===================================================== DEVPWRSTATUS ====================================================== */
/* ======================================================= SRAMCTRL ======================================================== */
/* ======================================== PWRCTRL SRAMCTRL SRAMLIGHTSLEEP [8..19] ======================================== */
typedef enum { /*!< PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP */
PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_ALL = 255, /*!< ALL : Enable LIGHT SLEEP for ALL SRAMs */
PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_DIS = 0, /*!< DIS : Disables LIGHT SLEEP for ALL SRAMs */
} PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_Enum;
/* ======================================= PWRCTRL SRAMCTRL SRAMMASTERCLKGATE [2..2] ======================================= */
typedef enum { /*!< PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE */
PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_EN = 1, /*!< EN : Enable Master SRAM Clock Gate */
PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_DIS = 0, /*!< DIS : Disables Master SRAM Clock Gating */
} PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_Enum;
/* ========================================== PWRCTRL SRAMCTRL SRAMCLKGATE [1..1] ========================================== */
typedef enum { /*!< PWRCTRL_SRAMCTRL_SRAMCLKGATE */
PWRCTRL_SRAMCTRL_SRAMCLKGATE_EN = 1, /*!< EN : Enable Individual SRAM Clock Gating */
PWRCTRL_SRAMCTRL_SRAMCLKGATE_DIS = 0, /*!< DIS : Disables Individual SRAM Clock Gating */
} PWRCTRL_SRAMCTRL_SRAMCLKGATE_Enum;
/* ======================================================= ADCSTATUS ======================================================= */
/* ========================================================= MISC ========================================================== */
/* ============================================ PWRCTRL MISC MEMVRLPBLE [6..6] ============================================= */
typedef enum { /*!< PWRCTRL_MISC_MEMVRLPBLE */
PWRCTRL_MISC_MEMVRLPBLE_EN = 1, /*!< EN : Mem VR can go to lp mode even when BLE is powered on. */
PWRCTRL_MISC_MEMVRLPBLE_DIS = 0, /*!< DIS : Mem VR will stay in active mode when BLE is powered on. */
} PWRCTRL_MISC_MEMVRLPBLE_Enum;
/* ===================================================== DEVPWREVENTEN ===================================================== */
/* ======================================= PWRCTRL DEVPWREVENTEN BURSTEVEN [31..31] ======================================== */
typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_BURSTEVEN */
PWRCTRL_DEVPWREVENTEN_BURSTEVEN_EN = 1, /*!< EN : Enable BURST status event */
PWRCTRL_DEVPWREVENTEN_BURSTEVEN_DIS = 0, /*!< DIS : Disable BURST status event */
} PWRCTRL_DEVPWREVENTEN_BURSTEVEN_Enum;
/* ==================================== PWRCTRL DEVPWREVENTEN BURSTFEATUREEVEN [30..30] ==================================== */
typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_BURSTFEATUREEVEN */
PWRCTRL_DEVPWREVENTEN_BURSTFEATUREEVEN_EN = 1,/*!< EN : Enable BURSTFEATURE status event */
PWRCTRL_DEVPWREVENTEN_BURSTFEATUREEVEN_DIS = 0,/*!< DIS : Disable BURSTFEATURE status event */
} PWRCTRL_DEVPWREVENTEN_BURSTFEATUREEVEN_Enum;
/* ===================================== PWRCTRL DEVPWREVENTEN BLEFEATUREEVEN [29..29] ===================================== */
typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_BLEFEATUREEVEN */
PWRCTRL_DEVPWREVENTEN_BLEFEATUREEVEN_EN = 1, /*!< EN : Enable BLEFEATURE status event */
PWRCTRL_DEVPWREVENTEN_BLEFEATUREEVEN_DIS = 0, /*!< DIS : Disable BLEFEATURE status event */
} PWRCTRL_DEVPWREVENTEN_BLEFEATUREEVEN_Enum;
/* ========================================= PWRCTRL DEVPWREVENTEN BLELEVEN [8..8] ========================================= */
typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_BLELEVEN */
PWRCTRL_DEVPWREVENTEN_BLELEVEN_EN = 1, /*!< EN : Enable BLE power-on status event */
PWRCTRL_DEVPWREVENTEN_BLELEVEN_DIS = 0, /*!< DIS : Disable BLE power-on status event */
} PWRCTRL_DEVPWREVENTEN_BLELEVEN_Enum;
/* ========================================= PWRCTRL DEVPWREVENTEN PDMEVEN [7..7] ========================================== */
typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_PDMEVEN */
PWRCTRL_DEVPWREVENTEN_PDMEVEN_EN = 1, /*!< EN : Enable PDM power-on status event */
PWRCTRL_DEVPWREVENTEN_PDMEVEN_DIS = 0, /*!< DIS : Disable PDM power-on status event */
} PWRCTRL_DEVPWREVENTEN_PDMEVEN_Enum;
/* ========================================= PWRCTRL DEVPWREVENTEN MSPIEVEN [6..6] ========================================= */
typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_MSPIEVEN */
PWRCTRL_DEVPWREVENTEN_MSPIEVEN_EN = 1, /*!< EN : Enable MSPI power-on status event */
PWRCTRL_DEVPWREVENTEN_MSPIEVEN_DIS = 0, /*!< DIS : Disable MSPI power-on status event */
} PWRCTRL_DEVPWREVENTEN_MSPIEVEN_Enum;
/* ========================================= PWRCTRL DEVPWREVENTEN ADCEVEN [5..5] ========================================== */
typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_ADCEVEN */
PWRCTRL_DEVPWREVENTEN_ADCEVEN_EN = 1, /*!< EN : Enable ADC power-on status event */
PWRCTRL_DEVPWREVENTEN_ADCEVEN_DIS = 0, /*!< DIS : Disable ADC power-on status event */
} PWRCTRL_DEVPWREVENTEN_ADCEVEN_Enum;
/* ========================================= PWRCTRL DEVPWREVENTEN HCPCEVEN [4..4] ========================================= */
typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_HCPCEVEN */
PWRCTRL_DEVPWREVENTEN_HCPCEVEN_EN = 1, /*!< EN : Enable HCPC power-on status event */
PWRCTRL_DEVPWREVENTEN_HCPCEVEN_DIS = 0, /*!< DIS : Disable HCPC power-on status event */
} PWRCTRL_DEVPWREVENTEN_HCPCEVEN_Enum;
/* ========================================= PWRCTRL DEVPWREVENTEN HCPBEVEN [3..3] ========================================= */
typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_HCPBEVEN */
PWRCTRL_DEVPWREVENTEN_HCPBEVEN_EN = 1, /*!< EN : Enable HCPB power-on status event */
PWRCTRL_DEVPWREVENTEN_HCPBEVEN_DIS = 0, /*!< DIS : Disable HCPB power-on status event */
} PWRCTRL_DEVPWREVENTEN_HCPBEVEN_Enum;
/* ========================================= PWRCTRL DEVPWREVENTEN HCPAEVEN [2..2] ========================================= */
typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_HCPAEVEN */
PWRCTRL_DEVPWREVENTEN_HCPAEVEN_EN = 1, /*!< EN : Enable HCPA power-on status event */
PWRCTRL_DEVPWREVENTEN_HCPAEVEN_DIS = 0, /*!< DIS : Disable HCPA power-on status event */
} PWRCTRL_DEVPWREVENTEN_HCPAEVEN_Enum;
/* ========================================= PWRCTRL DEVPWREVENTEN MCUHEVEN [1..1] ========================================= */
typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_MCUHEVEN */
PWRCTRL_DEVPWREVENTEN_MCUHEVEN_EN = 1, /*!< EN : Enable MCHU power-on status event */
PWRCTRL_DEVPWREVENTEN_MCUHEVEN_DIS = 0, /*!< DIS : Disable MCUH power-on status event */
} PWRCTRL_DEVPWREVENTEN_MCUHEVEN_Enum;
/* ========================================= PWRCTRL DEVPWREVENTEN MCULEVEN [0..0] ========================================= */
typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_MCULEVEN */
PWRCTRL_DEVPWREVENTEN_MCULEVEN_EN = 1, /*!< EN : Enable MCUL power-on status event */
PWRCTRL_DEVPWREVENTEN_MCULEVEN_DIS = 0, /*!< DIS : Disable MCUL power-on status event */
} PWRCTRL_DEVPWREVENTEN_MCULEVEN_Enum;
/* ===================================================== MEMPWREVENTEN ===================================================== */
/* ======================================= PWRCTRL MEMPWREVENTEN CACHEB2EN [31..31] ======================================== */
typedef enum { /*!< PWRCTRL_MEMPWREVENTEN_CACHEB2EN */
PWRCTRL_MEMPWREVENTEN_CACHEB2EN_EN = 1, /*!< EN : Enable CACHE BANK 2 status event */
PWRCTRL_MEMPWREVENTEN_CACHEB2EN_DIS = 0, /*!< DIS : Disable CACHE BANK 2 status event */
} PWRCTRL_MEMPWREVENTEN_CACHEB2EN_Enum;
/* ======================================= PWRCTRL MEMPWREVENTEN CACHEB0EN [30..30] ======================================== */
typedef enum { /*!< PWRCTRL_MEMPWREVENTEN_CACHEB0EN */
PWRCTRL_MEMPWREVENTEN_CACHEB0EN_EN = 1, /*!< EN : Enable CACHE BANK 0 status event */
PWRCTRL_MEMPWREVENTEN_CACHEB0EN_DIS = 0, /*!< DIS : Disable CACHE BANK 0 status event */
} PWRCTRL_MEMPWREVENTEN_CACHEB0EN_Enum;
/* ======================================== PWRCTRL MEMPWREVENTEN FLASH1EN [14..14] ======================================== */
typedef enum { /*!< PWRCTRL_MEMPWREVENTEN_FLASH1EN */
PWRCTRL_MEMPWREVENTEN_FLASH1EN_EN = 1, /*!< EN : Enable FLASH status event */
PWRCTRL_MEMPWREVENTEN_FLASH1EN_DIS = 0, /*!< DIS : Disables FLASH status event */
} PWRCTRL_MEMPWREVENTEN_FLASH1EN_Enum;
/* ======================================== PWRCTRL MEMPWREVENTEN FLASH0EN [13..13] ======================================== */
typedef enum { /*!< PWRCTRL_MEMPWREVENTEN_FLASH0EN */
PWRCTRL_MEMPWREVENTEN_FLASH0EN_EN = 1, /*!< EN : Enable FLASH status event */
PWRCTRL_MEMPWREVENTEN_FLASH0EN_DIS = 0, /*!< DIS : Disables FLASH status event */
} PWRCTRL_MEMPWREVENTEN_FLASH0EN_Enum;
/* ========================================= PWRCTRL MEMPWREVENTEN SRAMEN [3..12] ========================================== */
typedef enum { /*!< PWRCTRL_MEMPWREVENTEN_SRAMEN */
PWRCTRL_MEMPWREVENTEN_SRAMEN_NONE = 0, /*!< NONE : Disable SRAM power-on status event */
PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP0EN = 1, /*!< GROUP0EN : Enable SRAM group0 (0KB-32KB) power on status event */
PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP1EN = 2, /*!< GROUP1EN : Enable SRAM group1 (32KB-64KB) power on status event */
PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP2EN = 4, /*!< GROUP2EN : Enable SRAM group2 (64KB-96KB) power on status event */
PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP3EN = 8, /*!< GROUP3EN : Enable SRAM group3 (96KB-128KB) power on status event */
PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP4EN = 16, /*!< GROUP4EN : Enable SRAM group4 (128KB-160KB) power on status
event */
PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP5EN = 32, /*!< GROUP5EN : Enable SRAM group5 (160KB-192KB) power on status
event */
PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP6EN = 64, /*!< GROUP6EN : Enable SRAM group6 (192KB-224KB) power on status
event */
PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP7EN = 128, /*!< GROUP7EN : Enable SRAM group7 (224KB-256KB) power on status
event */
PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP8EN = 256, /*!< GROUP8EN : Enable SRAM group8 (256KB-288KB) power on status
event */
PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP9EN = 512, /*!< GROUP9EN : Enable SRAM group9 (288KB-320KB) power on status
event */
} PWRCTRL_MEMPWREVENTEN_SRAMEN_Enum;
/* ========================================== PWRCTRL MEMPWREVENTEN DTCMEN [0..2] ========================================== */
typedef enum { /*!< PWRCTRL_MEMPWREVENTEN_DTCMEN */
PWRCTRL_MEMPWREVENTEN_DTCMEN_NONE = 0, /*!< NONE : Do not enable DTCM power-on status event */
PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP0DTCM0EN = 1,/*!< GROUP0DTCM0EN : Enable GROUP0_DTCM0 power on status event */
PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP0DTCM1EN = 2,/*!< GROUP0DTCM1EN : Enable GROUP0_DTCM1 power on status event */
PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP0EN = 3, /*!< GROUP0EN : Enable DTCMs in group0 power on status event */
PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP1EN = 4, /*!< GROUP1EN : Enable DTCMs in group1 power on status event */
PWRCTRL_MEMPWREVENTEN_DTCMEN_ALL = 7, /*!< ALL : Enable all DTCM power on status event */
} PWRCTRL_MEMPWREVENTEN_DTCMEN_Enum;
/* =========================================================================================================================== */
/* ================ RSTGEN ================ */
/* =========================================================================================================================== */
/* ========================================================== CFG ========================================================== */
/* ========================================================= SWPOI ========================================================= */
/* ============================================= RSTGEN SWPOI SWPOIKEY [0..7] ============================================== */
typedef enum { /*!< RSTGEN_SWPOI_SWPOIKEY */
RSTGEN_SWPOI_SWPOIKEY_KEYVALUE = 27, /*!< KEYVALUE : Writing 0x1B key value generates a software POI reset. */
} RSTGEN_SWPOI_SWPOIKEY_Enum;
/* ========================================================= SWPOR ========================================================= */
/* ============================================= RSTGEN SWPOR SWPORKEY [0..7] ============================================== */
typedef enum { /*!< RSTGEN_SWPOR_SWPORKEY */
RSTGEN_SWPOR_SWPORKEY_KEYVALUE = 212, /*!< KEYVALUE : Writing 0xD4 key value generates a software POR reset. */
} RSTGEN_SWPOR_SWPORKEY_Enum;
/* ======================================================== TPIURST ======================================================== */
/* ========================================================= INTEN ========================================================= */
/* ======================================================== INTSTAT ======================================================== */
/* ======================================================== INTCLR ========================================================= */
/* ======================================================== INTSET ========================================================= */
/* ========================================================= STAT ========================================================== */
/* =========================================================================================================================== */
/* ================ RTC ================ */
/* =========================================================================================================================== */
/* ======================================================== CTRLOW ========================================================= */
/* ========================================================= CTRUP ========================================================= */
/* =============================================== RTC CTRUP CTERR [31..31] ================================================ */
typedef enum { /*!< RTC_CTRUP_CTERR */
RTC_CTRUP_CTERR_NOERR = 0, /*!< NOERR : No read error occurred */
RTC_CTRUP_CTERR_RDERR = 1, /*!< RDERR : Read error occurred */
} RTC_CTRUP_CTERR_Enum;
/* ================================================ RTC CTRUP CEB [28..28] ================================================= */
typedef enum { /*!< RTC_CTRUP_CEB */
RTC_CTRUP_CEB_DIS = 0, /*!< DIS : Disable the Century bit from changing */
RTC_CTRUP_CEB_EN = 1, /*!< EN : Enable the Century bit to change */
} RTC_CTRUP_CEB_Enum;
/* ================================================= RTC CTRUP CB [27..27] ================================================= */
typedef enum { /*!< RTC_CTRUP_CB */
RTC_CTRUP_CB_2000 = 0, /*!< 2000 : Century is 2000s */
RTC_CTRUP_CB_1900_2100 = 1, /*!< 1900_2100 : Century is 1900s/2100s */
} RTC_CTRUP_CB_Enum;
/* ======================================================== ALMLOW ========================================================= */
/* ========================================================= ALMUP ========================================================= */
/* ======================================================== RTCCTL ========================================================= */
/* =============================================== RTC RTCCTL HR1224 [5..5] ================================================ */
typedef enum { /*!< RTC_RTCCTL_HR1224 */
RTC_RTCCTL_HR1224_24HR = 0, /*!< 24HR : Hours in 24 hour mode */
RTC_RTCCTL_HR1224_12HR = 1, /*!< 12HR : Hours in 12 hour mode */
} RTC_RTCCTL_HR1224_Enum;
/* ================================================ RTC RTCCTL RSTOP [4..4] ================================================ */
typedef enum { /*!< RTC_RTCCTL_RSTOP */
RTC_RTCCTL_RSTOP_RUN = 0, /*!< RUN : Allow the RTC input clock to run */
RTC_RTCCTL_RSTOP_STOP = 1, /*!< STOP : Stop the RTC input clock */
} RTC_RTCCTL_RSTOP_Enum;
/* ================================================= RTC RTCCTL RPT [1..3] ================================================= */
typedef enum { /*!< RTC_RTCCTL_RPT */
RTC_RTCCTL_RPT_DIS = 0, /*!< DIS : Alarm interrupt disabled */
RTC_RTCCTL_RPT_YEAR = 1, /*!< YEAR : Interrupt every year */
RTC_RTCCTL_RPT_MONTH = 2, /*!< MONTH : Interrupt every month */
RTC_RTCCTL_RPT_WEEK = 3, /*!< WEEK : Interrupt every week */
RTC_RTCCTL_RPT_DAY = 4, /*!< DAY : Interrupt every day */
RTC_RTCCTL_RPT_HR = 5, /*!< HR : Interrupt every hour */
RTC_RTCCTL_RPT_MIN = 6, /*!< MIN : Interrupt every minute */
RTC_RTCCTL_RPT_SEC = 7, /*!< SEC : Interrupt every second/10th/100th */
} RTC_RTCCTL_RPT_Enum;
/* ================================================ RTC RTCCTL WRTC [0..0] ================================================= */
typedef enum { /*!< RTC_RTCCTL_WRTC */
RTC_RTCCTL_WRTC_DIS = 0, /*!< DIS : Counter writes are disabled */
RTC_RTCCTL_WRTC_EN = 1, /*!< EN : Counter writes are enabled */
} RTC_RTCCTL_WRTC_Enum;
/* ========================================================= INTEN ========================================================= */
/* ======================================================== INTSTAT ======================================================== */
/* ======================================================== INTCLR ========================================================= */
/* ======================================================== INTSET ========================================================= */
/* =========================================================================================================================== */
/* ================ SCARD ================ */
/* =========================================================================================================================== */
/* ========================================================== SR =========================================================== */
/* ================================================== SCARD SR FHF [6..6] ================================================== */
typedef enum { /*!< SCARD_SR_FHF */
SCARD_SR_FHF_HALFFULL = 1, /*!< HALFFULL : FIFO is half full. */
} SCARD_SR_FHF_Enum;
/* ================================================ SCARD SR FT2REND [5..5] ================================================ */
typedef enum { /*!< SCARD_SR_FT2REND */
SCARD_SR_FT2REND_CMPL = 1, /*!< CMPL : TX to RX completed. */
SCARD_SR_FT2REND_NOTCMPL = 0, /*!< NOTCMPL : TX to RX not completed. */
} SCARD_SR_FT2REND_Enum;
/* ================================================== SCARD SR PE [4..4] =================================================== */
typedef enum { /*!< SCARD_SR_PE */
SCARD_SR_PE_PEERR = 1, /*!< PEERR : Parity error. */
SCARD_SR_PE_PENONE = 0, /*!< PENONE : No parity error. */
} SCARD_SR_PE_Enum;
/* ================================================== SCARD SR OVR [3..3] ================================================== */
typedef enum { /*!< SCARD_SR_OVR */
SCARD_SR_OVR_RXOVR = 1, /*!< RXOVR : RX FIFO overflow. */
SCARD_SR_OVR_RXOVRNONE = 0, /*!< RXOVRNONE : RX FIFO no overflow. */
} SCARD_SR_OVR_Enum;
/* ================================================== SCARD SR FER [2..2] ================================================== */
typedef enum { /*!< SCARD_SR_FER */
SCARD_SR_FER_FRAMINGERR = 1, /*!< FRAMINGERR : Framing error. */
SCARD_SR_FER_NOFRAMINGERR = 0, /*!< NOFRAMINGERR : No framing error detected. */
} SCARD_SR_FER_Enum;
/* ================================================ SCARD SR TBERBF [1..1] ================================================= */
typedef enum { /*!< SCARD_SR_TBERBF */
SCARD_SR_TBERBF_TXFIFOEMPTY = 1, /*!< TXFIFOEMPTY : Transmit: FIFO empty. */
SCARD_SR_TBERBF_TXFIFONOTEMPTY = 0, /*!< TXFIFONOTEMPTY : Transmit: FIFO not empty. */
} SCARD_SR_TBERBF_Enum;
/* ================================================== SCARD SR FNE [0..0] ================================================== */
typedef enum { /*!< SCARD_SR_FNE */
SCARD_SR_FNE_NOTEMPTY = 1, /*!< NOTEMPTY : RX FIFO not empty. */
SCARD_SR_FNE_EMPTY = 0, /*!< EMPTY : RX FIFO empty. */
} SCARD_SR_FNE_Enum;
/* ========================================================== IER ========================================================== */
/* ========================================================== TCR ========================================================== */
/* ========================================================== UCR ========================================================== */
/* ========================================================== DR =========================================================== */
/* ========================================================= BPRL ========================================================== */
/* ========================================================= BPRH ========================================================== */
/* ========================================================= UCR1 ========================================================== */
/* ========================================================== SR1 ========================================================== */
/* ================================================= SCARD SR1 IDLE [3..3] ================================================= */
typedef enum { /*!< SCARD_SR1_IDLE */
SCARD_SR1_IDLE_IDLE = 1, /*!< IDLE : ISO7816 idle. */
SCARD_SR1_IDLE_ACTIVE = 0, /*!< ACTIVE : ISO7816 active. */
} SCARD_SR1_IDLE_Enum;
/* =============================================== SCARD SR1 SYNCEND [2..2] ================================================ */
typedef enum { /*!< SCARD_SR1_SYNCEND */
SCARD_SR1_SYNCEND_CMPL = 1, /*!< CMPL : Synchronization complete. */
SCARD_SR1_SYNCEND_INCMPL = 0, /*!< INCMPL : Incomplete. */
} SCARD_SR1_SYNCEND_Enum;
/* ================================================= SCARD SR1 PRL [1..1] ================================================== */
typedef enum { /*!< SCARD_SR1_PRL */
SCARD_SR1_PRL_INSREM = 1, /*!< INSREM : Card inserted/removed. */
} SCARD_SR1_PRL_Enum;
/* =============================================== SCARD SR1 ECNTOVER [0..0] =============================================== */
typedef enum { /*!< SCARD_SR1_ECNTOVER */
SCARD_SR1_ECNTOVER_OVR = 1, /*!< OVR : ETU overflow. */
} SCARD_SR1_ECNTOVER_Enum;
/* ========================================================= IER1 ========================================================== */
/* ========================================================= ECNTL ========================================================= */
/* ========================================================= ECNTH ========================================================= */
/* ========================================================== GTR ========================================================== */
/* ======================================================== RETXCNT ======================================================== */
/* ====================================================== RETXCNTRMI ======================================================= */
/* ======================================================== CLKCTRL ======================================================== */
/* =========================================================================================================================== */
/* ================ SECURITY ================ */
/* =========================================================================================================================== */
/* ========================================================= CTRL ========================================================== */
/* ============================================= SECURITY CTRL FUNCTION [4..7] ============================================= */
typedef enum { /*!< SECURITY_CTRL_FUNCTION */
SECURITY_CTRL_FUNCTION_CRC32 = 0, /*!< CRC32 : Perform CRC32 operation */
} SECURITY_CTRL_FUNCTION_Enum;
/* ======================================================== SRCADDR ======================================================== */
/* ========================================================== LEN ========================================================== */
/* ======================================================== RESULT ========================================================= */
/* ======================================================= LOCKCTRL ======================================================== */
/* ============================================ SECURITY LOCKCTRL SELECT [0..7] ============================================ */
typedef enum { /*!< SECURITY_LOCKCTRL_SELECT */
SECURITY_LOCKCTRL_SELECT_CUSTOMER_KEY = 1, /*!< CUSTOMER_KEY : Unlock Customer Key (access to top half of info0) */
SECURITY_LOCKCTRL_SELECT_NONE = 0, /*!< NONE : Lock Control should be set to NONE when not in use. */
} SECURITY_LOCKCTRL_SELECT_Enum;
/* ======================================================= LOCKSTAT ======================================================== */
/* =========================================== SECURITY LOCKSTAT STATUS [0..31] ============================================ */
typedef enum { /*!< SECURITY_LOCKSTAT_STATUS */
SECURITY_LOCKSTAT_STATUS_CUSTOMER_KEY = 1, /*!< CUSTOMER_KEY : Customer Key is unlocked (access is granted to
top half of info0) */
SECURITY_LOCKSTAT_STATUS_NONE = 0, /*!< NONE : No resources are unlocked */
} SECURITY_LOCKSTAT_STATUS_Enum;
/* ========================================================= KEY0 ========================================================== */
/* ========================================================= KEY1 ========================================================== */
/* ========================================================= KEY2 ========================================================== */
/* ========================================================= KEY3 ========================================================== */
/* =========================================================================================================================== */
/* ================ UART0 ================ */
/* =========================================================================================================================== */
/* ========================================================== DR =========================================================== */
/* =============================================== UART0 DR OEDATA [11..11] ================================================ */
typedef enum { /*!< UART0_DR_OEDATA */
UART0_DR_OEDATA_NOERR = 0, /*!< NOERR : No error on UART OEDATA, overrun error indicator. */
UART0_DR_OEDATA_ERR = 1, /*!< ERR : Error on UART OEDATA, overrun error indicator. */
} UART0_DR_OEDATA_Enum;
/* =============================================== UART0 DR BEDATA [10..10] ================================================ */
typedef enum { /*!< UART0_DR_BEDATA */
UART0_DR_BEDATA_NOERR = 0, /*!< NOERR : No error on UART BEDATA, break error indicator. */
UART0_DR_BEDATA_ERR = 1, /*!< ERR : Error on UART BEDATA, break error indicator. */
} UART0_DR_BEDATA_Enum;
/* ================================================ UART0 DR PEDATA [9..9] ================================================= */
typedef enum { /*!< UART0_DR_PEDATA */
UART0_DR_PEDATA_NOERR = 0, /*!< NOERR : No error on UART PEDATA, parity error indicator. */
UART0_DR_PEDATA_ERR = 1, /*!< ERR : Error on UART PEDATA, parity error indicator. */
} UART0_DR_PEDATA_Enum;
/* ================================================ UART0 DR FEDATA [8..8] ================================================= */
typedef enum { /*!< UART0_DR_FEDATA */
UART0_DR_FEDATA_NOERR = 0, /*!< NOERR : No error on UART FEDATA, framing error indicator. */
UART0_DR_FEDATA_ERR = 1, /*!< ERR : Error on UART FEDATA, framing error indicator. */
} UART0_DR_FEDATA_Enum;
/* ========================================================== RSR ========================================================== */
/* ================================================ UART0 RSR OESTAT [3..3] ================================================ */
typedef enum { /*!< UART0_RSR_OESTAT */
UART0_RSR_OESTAT_NOERR = 0, /*!< NOERR : No error on UART OESTAT, overrun error indicator. */
UART0_RSR_OESTAT_ERR = 1, /*!< ERR : Error on UART OESTAT, overrun error indicator. */
} UART0_RSR_OESTAT_Enum;
/* ================================================ UART0 RSR BESTAT [2..2] ================================================ */
typedef enum { /*!< UART0_RSR_BESTAT */
UART0_RSR_BESTAT_NOERR = 0, /*!< NOERR : No error on UART BESTAT, break error indicator. */
UART0_RSR_BESTAT_ERR = 1, /*!< ERR : Error on UART BESTAT, break error indicator. */
} UART0_RSR_BESTAT_Enum;
/* ================================================ UART0 RSR PESTAT [1..1] ================================================ */
typedef enum { /*!< UART0_RSR_PESTAT */
UART0_RSR_PESTAT_NOERR = 0, /*!< NOERR : No error on UART PESTAT, parity error indicator. */
UART0_RSR_PESTAT_ERR = 1, /*!< ERR : Error on UART PESTAT, parity error indicator. */
} UART0_RSR_PESTAT_Enum;
/* ================================================ UART0 RSR FESTAT [0..0] ================================================ */
typedef enum { /*!< UART0_RSR_FESTAT */
UART0_RSR_FESTAT_NOERR = 0, /*!< NOERR : No error on UART FESTAT, framing error indicator. */
UART0_RSR_FESTAT_ERR = 1, /*!< ERR : Error on UART FESTAT, framing error indicator. */
} UART0_RSR_FESTAT_Enum;
/* ========================================================== FR =========================================================== */
/* ================================================= UART0 FR TXFE [7..7] ================================================== */
typedef enum { /*!< UART0_FR_TXFE */
UART0_FR_TXFE_XMTFIFO_EMPTY = 1, /*!< XMTFIFO_EMPTY : Transmit fifo is empty. */
} UART0_FR_TXFE_Enum;
/* ================================================= UART0 FR RXFF [6..6] ================================================== */
typedef enum { /*!< UART0_FR_RXFF */
UART0_FR_RXFF_RCVFIFO_FULL = 1, /*!< RCVFIFO_FULL : Receive fifo is full. */
} UART0_FR_RXFF_Enum;
/* ================================================= UART0 FR TXFF [5..5] ================================================== */
typedef enum { /*!< UART0_FR_TXFF */
UART0_FR_TXFF_XMTFIFO_FULL = 1, /*!< XMTFIFO_FULL : Transmit fifo is full. */
} UART0_FR_TXFF_Enum;
/* ================================================= UART0 FR RXFE [4..4] ================================================== */
typedef enum { /*!< UART0_FR_RXFE */
UART0_FR_RXFE_RCVFIFO_EMPTY = 1, /*!< RCVFIFO_EMPTY : Receive fifo is empty. */
} UART0_FR_RXFE_Enum;
/* ================================================= UART0 FR BUSY [3..3] ================================================== */
typedef enum { /*!< UART0_FR_BUSY */
UART0_FR_BUSY_BUSY = 1, /*!< BUSY : UART busy indicator. */
} UART0_FR_BUSY_Enum;
/* ================================================== UART0 FR DCD [2..2] ================================================== */
typedef enum { /*!< UART0_FR_DCD */
UART0_FR_DCD_DETECTED = 1, /*!< DETECTED : Data carrier detect detected. */
} UART0_FR_DCD_Enum;
/* ================================================== UART0 FR DSR [1..1] ================================================== */
typedef enum { /*!< UART0_FR_DSR */
UART0_FR_DSR_READY = 1, /*!< READY : Data set ready. */
} UART0_FR_DSR_Enum;
/* ================================================== UART0 FR CTS [0..0] ================================================== */
typedef enum { /*!< UART0_FR_CTS */
UART0_FR_CTS_CLEARTOSEND = 1, /*!< CLEARTOSEND : Clear to send is indicated. */
} UART0_FR_CTS_Enum;
/* ========================================================= ILPR ========================================================== */
/* ========================================================= IBRD ========================================================== */
/* ========================================================= FBRD ========================================================== */
/* ========================================================= LCRH ========================================================== */
/* ========================================================== CR =========================================================== */
/* ================================================ UART0 CR CLKSEL [4..6] ================================================= */
typedef enum { /*!< UART0_CR_CLKSEL */
UART0_CR_CLKSEL_NOCLK = 0, /*!< NOCLK : No UART clock. This is the low power default. */
UART0_CR_CLKSEL_24MHZ = 1, /*!< 24MHZ : 24 MHz clock. */
UART0_CR_CLKSEL_12MHZ = 2, /*!< 12MHZ : 12 MHz clock. */
UART0_CR_CLKSEL_6MHZ = 3, /*!< 6MHZ : 6 MHz clock. */
UART0_CR_CLKSEL_3MHZ = 4, /*!< 3MHZ : 3 MHz clock. */
} UART0_CR_CLKSEL_Enum;
/* ========================================================= IFLS ========================================================== */
/* ========================================================== IER ========================================================== */
/* ========================================================== IES ========================================================== */
/* ========================================================== MIS ========================================================== */
/* ========================================================== IEC ========================================================== */
/* =========================================================================================================================== */
/* ================ VCOMP ================ */
/* =========================================================================================================================== */
/* ========================================================== CFG ========================================================== */
/* =============================================== VCOMP CFG LVLSEL [16..19] =============================================== */
typedef enum { /*!< VCOMP_CFG_LVLSEL */
VCOMP_CFG_LVLSEL_0P58V = 0, /*!< 0P58V : Set Reference input to 0.58 Volts. */
VCOMP_CFG_LVLSEL_0P77V = 1, /*!< 0P77V : Set Reference input to 0.77 Volts. */
VCOMP_CFG_LVLSEL_0P97V = 2, /*!< 0P97V : Set Reference input to 0.97 Volts. */
VCOMP_CFG_LVLSEL_1P16V = 3, /*!< 1P16V : Set Reference input to 1.16 Volts. */
VCOMP_CFG_LVLSEL_1P35V = 4, /*!< 1P35V : Set Reference input to 1.35 Volts. */
VCOMP_CFG_LVLSEL_1P55V = 5, /*!< 1P55V : Set Reference input to 1.55 Volts. */
VCOMP_CFG_LVLSEL_1P74V = 6, /*!< 1P74V : Set Reference input to 1.74 Volts. */
VCOMP_CFG_LVLSEL_1P93V = 7, /*!< 1P93V : Set Reference input to 1.93 Volts. */
VCOMP_CFG_LVLSEL_2P13V = 8, /*!< 2P13V : Set Reference input to 2.13 Volts. */
VCOMP_CFG_LVLSEL_2P32V = 9, /*!< 2P32V : Set Reference input to 2.32 Volts. */
VCOMP_CFG_LVLSEL_2P51V = 10, /*!< 2P51V : Set Reference input to 2.51 Volts. */
VCOMP_CFG_LVLSEL_2P71V = 11, /*!< 2P71V : Set Reference input to 2.71 Volts. */
VCOMP_CFG_LVLSEL_2P90V = 12, /*!< 2P90V : Set Reference input to 2.90 Volts. */
VCOMP_CFG_LVLSEL_3P09V = 13, /*!< 3P09V : Set Reference input to 3.09 Volts. */
VCOMP_CFG_LVLSEL_3P29V = 14, /*!< 3P29V : Set Reference input to 3.29 Volts. */
VCOMP_CFG_LVLSEL_3P48V = 15, /*!< 3P48V : Set Reference input to 3.48 Volts. */
} VCOMP_CFG_LVLSEL_Enum;
/* ================================================= VCOMP CFG NSEL [8..9] ================================================= */
typedef enum { /*!< VCOMP_CFG_NSEL */
VCOMP_CFG_NSEL_VREFEXT1 = 0, /*!< VREFEXT1 : Use external reference 1 for reference input. */
VCOMP_CFG_NSEL_VREFEXT2 = 1, /*!< VREFEXT2 : Use external reference 2 for reference input. */
VCOMP_CFG_NSEL_VREFEXT3 = 2, /*!< VREFEXT3 : Use external reference 3 for reference input. */
VCOMP_CFG_NSEL_DAC = 3, /*!< DAC : Use DAC output selected by LVLSEL for reference input. */
} VCOMP_CFG_NSEL_Enum;
/* ================================================= VCOMP CFG PSEL [0..1] ================================================= */
typedef enum { /*!< VCOMP_CFG_PSEL */
VCOMP_CFG_PSEL_VDDADJ = 0, /*!< VDDADJ : Use VDDADJ for the positive input. */
VCOMP_CFG_PSEL_VTEMP = 1, /*!< VTEMP : Use the temperature sensor output for the positive input.
Note: If this channel is selected for PSEL, the bandap
circuit required for temperature comparisons will automatically
turn on. The bandgap circuit requires 11us to stabalize. */
VCOMP_CFG_PSEL_VEXT1 = 2, /*!< VEXT1 : Use external voltage 0 for positive input. */
VCOMP_CFG_PSEL_VEXT2 = 3, /*!< VEXT2 : Use external voltage 1 for positive input. */
} VCOMP_CFG_PSEL_Enum;
/* ========================================================= STAT ========================================================== */
/* =============================================== VCOMP STAT PWDSTAT [1..1] =============================================== */
typedef enum { /*!< VCOMP_STAT_PWDSTAT */
VCOMP_STAT_PWDSTAT_POWERED_DOWN = 1, /*!< POWERED_DOWN : The voltage comparator is powered down. */
} VCOMP_STAT_PWDSTAT_Enum;
/* =============================================== VCOMP STAT CMPOUT [0..0] ================================================ */
typedef enum { /*!< VCOMP_STAT_CMPOUT */
VCOMP_STAT_CMPOUT_VOUT_LOW = 0, /*!< VOUT_LOW : The negative input of the comparator is greater than
the positive input. */
VCOMP_STAT_CMPOUT_VOUT_HIGH = 1, /*!< VOUT_HIGH : The positive input of the comparator is greater
than the negative input. */
} VCOMP_STAT_CMPOUT_Enum;
/* ======================================================== PWDKEY ========================================================= */
/* ============================================== VCOMP PWDKEY PWDKEY [0..31] ============================================== */
typedef enum { /*!< VCOMP_PWDKEY_PWDKEY */
VCOMP_PWDKEY_PWDKEY_Key = 55, /*!< Key : Key value to unlock the register. */
} VCOMP_PWDKEY_PWDKEY_Enum;
/* ========================================================= INTEN ========================================================= */
/* ======================================================== INTSTAT ======================================================== */
/* ======================================================== INTCLR ========================================================= */
/* ======================================================== INTSET ========================================================= */
/* =========================================================================================================================== */
/* ================ WDT ================ */
/* =========================================================================================================================== */
/* ========================================================== CFG ========================================================== */
/* ================================================ WDT CFG CLKSEL [24..26] ================================================ */
typedef enum { /*!< WDT_CFG_CLKSEL */
WDT_CFG_CLKSEL_OFF = 0, /*!< OFF : Low Power Mode. This setting disables the watch dog timer. */
WDT_CFG_CLKSEL_128HZ = 1, /*!< 128HZ : 128 Hz LFRC clock. */
WDT_CFG_CLKSEL_16HZ = 2, /*!< 16HZ : 16 Hz LFRC clock. */
WDT_CFG_CLKSEL_1HZ = 3, /*!< 1HZ : 1 Hz LFRC clock. */
WDT_CFG_CLKSEL_1_16HZ = 4, /*!< 1_16HZ : 1/16th Hz LFRC clock. */
} WDT_CFG_CLKSEL_Enum;
/* ========================================================= RSTRT ========================================================= */
/* ================================================ WDT RSTRT RSTRT [0..7] ================================================= */
typedef enum { /*!< WDT_RSTRT_RSTRT */
WDT_RSTRT_RSTRT_KEYVALUE = 178, /*!< KEYVALUE : This is the key value to write to WDTRSTRT to restart
the WDT. This is a write only register. */
} WDT_RSTRT_RSTRT_Enum;
/* ========================================================= LOCK ========================================================== */
/* ================================================= WDT LOCK LOCK [0..7] ================================================== */
typedef enum { /*!< WDT_LOCK_LOCK */
WDT_LOCK_LOCK_KEYVALUE = 58, /*!< KEYVALUE : This is the key value to write to WDTLOCK to lock
the WDT. */
} WDT_LOCK_LOCK_Enum;
/* ========================================================= COUNT ========================================================= */
/* ========================================================= INTEN ========================================================= */
/* ======================================================== INTSTAT ======================================================== */
/* ======================================================== INTCLR ========================================================= */
/* ======================================================== INTSET ========================================================= */
/** @} */ /* End of group EnumValue_peripherals */
#ifdef __cplusplus
}
#endif
#endif /* APOLLO3_H */
/** @} */ /* End of group apollo3 */
/** @} */ /* End of group Ambiq Micro */