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139 lines
2.9 KiB
139 lines
2.9 KiB
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2016-09-07 Urey the first version
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*/
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#include <rtthread.h>
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#include "mips.h"
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extern void cache_init(rt_ubase_t cache_size, rt_ubase_t cache_line_size);
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void r4k_cache_init(void)
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{
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// cache_init(dcache_size, cpu_dcache_line_size);
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}
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void r4k_cache_flush_all(void)
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{
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blast_dcache16();
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blast_icache16();
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}
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void r4k_icache_flush_all(void)
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{
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blast_icache16();
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}
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void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size)
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{
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rt_ubase_t end, a;
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if (size > g_mips_core.icache_size)
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{
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blast_icache16();
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}
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else
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{
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rt_ubase_t ic_lsize = g_mips_core.icache_line_size;
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a = addr & ~(ic_lsize - 1);
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end = ((addr + size) - 1) & ~(ic_lsize - 1);
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while (1)
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{
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flush_icache_line(a);
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if (a == end)
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break;
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a += ic_lsize;
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}
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}
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}
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void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size)
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{
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rt_ubase_t end, a;
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rt_ubase_t ic_lsize = g_mips_core.icache_line_size;
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a = addr & ~(ic_lsize - 1);
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end = ((addr + size) - 1) & ~(ic_lsize - 1);
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while (1)
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{
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lock_icache_line(a);
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if (a == end)
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break;
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a += ic_lsize;
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}
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}
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void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size)
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{
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rt_ubase_t end, a;
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rt_ubase_t dc_lsize = g_mips_core.dcache_line_size;
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a = addr & ~(dc_lsize - 1);
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end = ((addr + size) - 1) & ~(dc_lsize - 1);
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while (1)
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{
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invalidate_dcache_line(a);
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if (a == end)
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break;
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a += dc_lsize;
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}
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}
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void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size)
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{
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rt_ubase_t end, a;
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if (size >= g_mips_core.dcache_size)
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{
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blast_dcache16();
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}
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else
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{
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rt_ubase_t dc_lsize = g_mips_core.dcache_line_size;
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a = addr & ~(dc_lsize - 1);
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end = ((addr + size) - 1) & ~(dc_lsize - 1);
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while (1)
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{
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flush_dcache_line(a);
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if (a == end)
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break;
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a += dc_lsize;
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}
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}
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}
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#define dma_cache_wback_inv(start,size) \
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do { (void) (start); (void) (size); } while (0)
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#define dma_cache_wback(start,size) \
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do { (void) (start); (void) (size); } while (0)
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#define dma_cache_inv(start,size) \
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do { (void) (start); (void) (size); } while (0)
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void r4k_dma_cache_sync(rt_ubase_t addr, rt_size_t size, enum dma_data_direction direction)
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{
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switch (direction)
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{
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case DMA_TO_DEVICE:
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r4k_dcache_wback_inv(addr, size);
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break;
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case DMA_FROM_DEVICE:
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r4k_dcache_wback_inv(addr, size);
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break;
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case DMA_BIDIRECTIONAL:
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dma_cache_wback_inv(addr, size);
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break;
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default:
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RT_ASSERT(0) ;
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}
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}
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