You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
134 lines
4.5 KiB
134 lines
4.5 KiB
/*
|
|
* Copyright (c) 2006-2023, RT-Thread Development Team
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*
|
|
* Change Logs:
|
|
* Date Author Notes
|
|
* 2023-03-24 spaceman the first version
|
|
*/
|
|
|
|
#include <rtthread.h>
|
|
#include "board.h"
|
|
#include <drv_common.h>
|
|
|
|
#define AXI_SRAM_ADDR (0X24000000)
|
|
#define AXI_SRAM_SIZE (512*1024)
|
|
#define SRAM1_ADDR (0X30000000)
|
|
#define SRAM1_SIZE (128*1024)
|
|
#define SRAM2_ADDR (0X30020000)
|
|
#define SRAM2_SIZE (128*1024)
|
|
#define SRAM3_ADDR (0X30040000)
|
|
#define SRAM3_SIZE (32*1024)
|
|
#define SRAM4_ADDR (0X38000000)
|
|
#define SRAM4_SIZE (64*1024)
|
|
#define BACKUP_ADDR (0X38800000)
|
|
#define BACKUP_SIZE (4*1024)
|
|
|
|
static struct rt_memheap _heap_axi_sram;
|
|
static struct rt_memheap _heap_sram1;
|
|
static struct rt_memheap _heap_sram2;
|
|
static struct rt_memheap _heap_sram3;
|
|
static struct rt_memheap _heap_sram4;
|
|
static struct rt_memheap _heap_backup_sram;
|
|
|
|
/**
|
|
* @brief System Clock Configuration
|
|
* @retval None
|
|
*/
|
|
void SystemClock_Config(void)
|
|
{
|
|
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
|
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
|
|
|
/** Supply configuration update enable
|
|
*/
|
|
HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
|
|
/** Configure the main internal regulator output voltage
|
|
*/
|
|
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
|
|
|
|
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
|
|
/** Configure LSE Drive Capability
|
|
*/
|
|
HAL_PWR_EnableBkUpAccess();
|
|
__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
|
|
/** Initializes the RCC Oscillators according to the specified parameters
|
|
* in the RCC_OscInitTypeDef structure.
|
|
*/
|
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_LSE;
|
|
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
|
|
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
|
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
|
|
RCC_OscInitStruct.PLL.PLLM = 5;
|
|
RCC_OscInitStruct.PLL.PLLN = 192;
|
|
RCC_OscInitStruct.PLL.PLLP = 2;
|
|
RCC_OscInitStruct.PLL.PLLQ = 2;
|
|
RCC_OscInitStruct.PLL.PLLR = 2;
|
|
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
|
|
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
|
|
RCC_OscInitStruct.PLL.PLLFRACN = 0;
|
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
|
{
|
|
Error_Handler();
|
|
}
|
|
/** Initializes the CPU, AHB and APB buses clocks
|
|
*/
|
|
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|
|
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
|
|
|RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
|
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
|
RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
|
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
|
|
RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
|
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
|
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
|
|
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
|
|
|
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
|
|
{
|
|
Error_Handler();
|
|
}
|
|
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_UART4
|
|
|RCC_PERIPHCLK_USART1;
|
|
PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1;
|
|
PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2;
|
|
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
|
|
{
|
|
Error_Handler();
|
|
}
|
|
}
|
|
|
|
static int init_sram(void)
|
|
{
|
|
__HAL_RCC_D2SRAM1_CLK_ENABLE();
|
|
__HAL_RCC_D2SRAM2_CLK_ENABLE();
|
|
__HAL_RCC_D2SRAM3_CLK_ENABLE();
|
|
rt_memheap_init(&_heap_axi_sram, "axi_sram", (void *)AXI_SRAM_ADDR, AXI_SRAM_SIZE);
|
|
rt_memheap_init(&_heap_sram1, "sram1", (void *)SRAM1_ADDR, SRAM1_SIZE);
|
|
rt_memheap_init(&_heap_sram2, "sram2", (void *)SRAM2_ADDR, SRAM2_SIZE);
|
|
rt_memheap_init(&_heap_sram3, "sram3", (void *)SRAM3_ADDR, SRAM3_SIZE);
|
|
rt_memheap_init(&_heap_sram4, "sram4", (void *)SRAM4_ADDR, SRAM4_SIZE);
|
|
rt_memheap_init(&_heap_backup_sram, "bak_sram", (void *)BACKUP_ADDR, BACKUP_SIZE);
|
|
|
|
return 0;
|
|
}
|
|
INIT_BOARD_EXPORT(init_sram);
|
|
|
|
/**
|
|
* Function ota_app_vtor_reconfig
|
|
* Description Set Vector Table base location to the start addr of app(RT_APP_PART_ADDR).
|
|
*/
|
|
static int ota_app_vtor_reconfig(void)
|
|
{
|
|
#define RT_APP_PART_ADDR 0x08020000
|
|
#define NVIC_VTOR_MASK 0x3FFFFF80
|
|
/* Set the Vector Table base location by user application firmware definition */
|
|
SCB->VTOR = RT_APP_PART_ADDR & NVIC_VTOR_MASK;
|
|
|
|
return 0;
|
|
}
|
|
// INIT_BOARD_EXPORT(ota_app_vtor_reconfig);
|
|
|