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62 lines
2.0 KiB
62 lines
2.0 KiB
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-04-14 whj4674672 first version
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*/
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#include <rtthread.h>
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#include "stm32h7xx.h"
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int mpu_init(void)
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{
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MPU_Region_InitTypeDef MPU_InitStruct;
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/* Disable the MPU */
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HAL_MPU_Disable();
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/* Configure the MPU attributes as WT for AXI SRAM */
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MPU_InitStruct.Enable = MPU_REGION_ENABLE;
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MPU_InitStruct.BaseAddress = 0x24000000;
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MPU_InitStruct.Size = MPU_REGION_SIZE_512KB;
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MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
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MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
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MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
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MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
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MPU_InitStruct.Number = MPU_REGION_NUMBER0;
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MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
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MPU_InitStruct.SubRegionDisable = 0X00;
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MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
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HAL_MPU_ConfigRegion(&MPU_InitStruct);
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#ifdef BSP_USING_SDRAM
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/* Configure the MPU attributes as WT for SDRAM */
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MPU_InitStruct.Enable = MPU_REGION_ENABLE;
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MPU_InitStruct.BaseAddress = 0xC0000000;
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MPU_InitStruct.Size = MPU_REGION_SIZE_32MB;
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MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
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MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
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MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
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MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
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MPU_InitStruct.Number = MPU_REGION_NUMBER1;
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MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
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MPU_InitStruct.SubRegionDisable = 0x00;
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MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
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HAL_MPU_ConfigRegion(&MPU_InitStruct);
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#endif
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/* Enable the MPU */
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HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
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/* Enable CACHE */
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SCB_EnableICache();
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SCB_EnableDCache();
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return 0;
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}
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INIT_BOARD_EXPORT(mpu_init);
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