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261 lines
6.5 KiB
261 lines
6.5 KiB
/** @file dma.h
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* @brief DMA Driver Definition File
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* @date 29.May.2013
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* @version 03.05.02
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*
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*/
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/* (c) Texas Instruments 2009-2013, All rights reserved. */
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#ifndef __DMA_H__
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#define __DMA_H__
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#include "reg_dma.h"
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/* dma configuration definitions */
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#define BLOCK_TRANSFER 1U
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#define FRAME_TRANSFER 0U
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#define AUTOINIT_ON 1U
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#define AUTOINIT_OFF 0U
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#define ADDR_FIXED 0U
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#define ADDR_INC1 1U
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#define ADDR_RESERVED 2U
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#define ADDR_OFFSET 3U
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#define INTERRUPT_ENABLE 1U
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#define INTERRUPT_DISABLE 0U
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/*Bit Masks*/
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#define DMA_GCTRL_BUSBUSY (1U << 14U)
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/** @enum dmaREQTYPE
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* @brief DMA TRANSFER Type definitions
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*
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* Used to define DMA transfer type
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*/
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enum dmaREQTYPE
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{
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DMA_HW = 0x0U, /**< Hardware trigger */
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DMA_SW = 0x1U /**< Software trigger */
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};
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/** @enum dmaCHANNEL
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* @brief DMA CHANNEL definitions
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*
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* Used to define DMA Channel Number
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*/
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enum dmaCHANNEL
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{
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DMA_CH0 = 0x00U,
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DMA_CH1 = 0x01U,
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DMA_CH2 = 0x02U,
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DMA_CH3 = 0x03U,
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DMA_CH4 = 0x04U,
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DMA_CH5 = 0x05U,
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DMA_CH6 = 0x06U,
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DMA_CH7 = 0x07U,
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DMA_CH8 = 0x08U,
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DMA_CH9 = 0x09U,
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DMA_CH10 = 0x0AU,
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DMA_CH11 = 0x0BU,
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DMA_CH12 = 0x0CU,
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DMA_CH13 = 0x0DU,
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DMA_CH14 = 0x0EU,
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DMA_CH15 = 0x0FU,
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DMA_CH16 = 0x10U,
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DMA_CH17 = 0x11U,
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DMA_CH18 = 0x12U,
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DMA_CH19 = 0x13U,
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DMA_CH20 = 0x14U,
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DMA_CH21 = 0x15U,
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DMA_CH22 = 0x16U,
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DMA_CH23 = 0x17U,
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DMA_CH24 = 0x18U,
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DMA_CH25 = 0x19U,
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DMA_CH26 = 0x1AU,
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DMA_CH27 = 0x1BU,
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DMA_CH28 = 0x1CU,
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DMA_CH29 = 0x1DU,
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DMA_CH30 = 0x1EU,
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DMA_CH31 = 0x1FU,
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DMA_CH32 = 0x20U
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};
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/** @enum dmaACCESS
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* @brief DMA ACESS WIDTH definitions
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*
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* Used to define DMA access width
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*/
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typedef enum dmaACCESS
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{
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ACCESS_8_BIT = 0U,
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ACCESS_16_BIT = 1U,
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ACCESS_32_BIT = 2U,
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ACCESS_64_BIT = 3U
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}dmaACCESS_t;
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/** @enum dmaPRIORITY
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* @brief DMA Channel Priority
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*
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* Used to define to which priority queue a DMA channel is assigned to
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*/
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typedef enum dmaPRIORITY
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{
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LOWPRIORITY = 0U,
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HIGHPRIORITY = 1U
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}dmaPRIORITY_t;
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/** @enum dmaREGION
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* @brief DMA Memory Protection Region
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*
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* Used to define DMA Memory Protection Region
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*/
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typedef enum dmaREGION
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{
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DMA_REGION0 = 0U,
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DMA_REGION1 = 1U,
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DMA_REGION2 = 2U,
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DMA_REGION3 = 3U
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}dmaREGION_t;
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/** @enum dmaRegionAccess
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* @brief DMA Memory Protection Region Access
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*
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* Used to define access permission of DMA memory protection regions
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*/
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typedef enum dmaRegionAccess
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{
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FULLACCESS = 0U,
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READONLY = 1U,
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WRITEONLY = 2U,
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NOACCESS = 3U
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}dmaRegionAccess_t;
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/** @enum dmaInterrupt
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* @brief DMA Interrupt
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*
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* Used to define DMA interrupts
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*/
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typedef enum dmaInterrupt
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{
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FTC = 1U, /**< Frame transfer complete Interrupt */
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LFS = 2U, /**< Last frame transfer started Interrupt */
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HBC = 3U, /**< First half of block complete Interrupt */
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BTC = 4U /**< Block transfer complete Interrupt */
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}dmaInterrupt_t;
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/** @struct g_dmaCTRL
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* @brief Interrupt mode globals
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*
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*/
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typedef struct dmaCTRLPKT
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{
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uint32 SADD; /* initial source address */
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uint32 DADD; /* initial destination address */
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uint32 CHCTRL; /* channel count */
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uint32 FRCNT; /* frame count */
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uint32 ELCNT; /* element count */
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uint32 ELDOFFSET; /* element destination offset */
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uint32 ELSOFFSET; /* element source offset */
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uint32 FRDOFFSET; /* frame detination offset */
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uint32 FRSOFFSET; /* frame source offset */
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uint32 PORTASGN; /* dma port */
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uint32 RDSIZE; /* read element size */
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uint32 WRSIZE; /* write element size */
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uint32 TTYPE; /* trigger type - frame/block */
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uint32 ADDMODERD; /* addresssing mode for source */
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uint32 ADDMODEWR; /* addresssing mode for destination */
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uint32 AUTOINIT; /* auto-init mode */
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uint32 COMBO; /* next ctrl packet trigger */
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} g_dmaCTRL;
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typedef volatile struct
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{
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struct /* 0x000-0x400 */
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{
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uint32 ISADDR;
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uint32 IDADDR;
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uint32 ITCOUNT;
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uint32 rsvd1;
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uint32 CHCTRL;
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uint32 EIOFF;
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uint32 FIOFF;
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uint32 rsvd2;
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}PCP[32U];
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struct /* 0x400-0x800 */
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{
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uint32 res[256U];
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} RESERVED;
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struct /* 0x800-0xA00 */
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{
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uint32 CSADDR;
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uint32 CDADDR;
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uint32 CTCOUNT;
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uint32 rsvd3;
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}WCP[32U];
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} dmaRAMBASE_t;
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#define dmaRAMREG ((dmaRAMBASE_t *)0xFFF80000U)
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/**
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* @defgroup DMA DMA
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* @brief Direct Memory Access Controller
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*
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* The DMA controller is used to transfer data between two locations in the memory map in the background
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* of CPU operations. Typically, the DMA is used to:
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* - Transfer blocks of data between external and internal data memories
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* - Restructure portions of internal data memory
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* - Continually service a peripheral
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* - Page program sections to internal program memory
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*
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* Related files:
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* - reg_dma.h
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* - sys_dma.h
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* - sys_dma.c
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*
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* @addtogroup DMA
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* @{
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*/
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/* DMA Interface Functions */
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void dmaEnable(void);
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void dmaDisable(void);
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void dmaSetCtrlPacket(uint32 channel, g_dmaCTRL g_dmaCTRLPKT);
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void dmaSetChEnable(uint32 channel,uint32 type);
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void dmaReqAssign(uint32 channel,uint32 reqline);
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uint32 dmaGetReq(uint32 channel);
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void dmaSetPriority(uint32 channel, dmaPRIORITY_t priority);
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void dmaEnableInterrupt(uint32 channel, dmaInterrupt_t inttype);
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void dmaDisableInterrupt(uint32 channel, dmaInterrupt_t inttype);
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void dmaDefineRegion(dmaREGION_t region, uint32 start_add, uint32 end_add);
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void dmaEnableRegion(dmaREGION_t region, dmaRegionAccess_t access, boolean intenable);
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void dmaDisableRegion(dmaREGION_t region);
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void dmaEnableParityCheck(void);
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void dmaDisableParityCheck(void);
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/** @fn void dmaGroupANotification(dmaInterrupt_t inttype, sint32 channel)
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* @brief Interrupt callback
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* @param[in] inttype Interrupt type
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* - FTC
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* - LFS
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* - HBC
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* - BTC
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* @param[in] channel channel number 0..15
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* This is a callback that is provided by the application and is called apon
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* an interrupt. The parameter passed to the callback is a copy of the
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* interrupt flag register.
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*/
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void dmaGroupANotification(dmaInterrupt_t inttype, sint32 channel);
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/**@}*/
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#endif
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