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60 lines
1.9 KiB
60 lines
1.9 KiB
/** @file reg_emif.h
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* @brief EMIF Register Layer Header File
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* @date 29.May.2013
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* @version 03.05.02
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*
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* This file contains:
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* - Definitions
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* - Types
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* - Interface Prototypes
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* .
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* which are relevant for the EMIF driver.
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*/
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/* (c) Texas Instruments 2009-2013, All rights reserved. */
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#ifndef __REG_EMIF_H__
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#define __REG_EMIF_H__
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#include "sys_common.h"
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/* USER CODE BEGIN (0) */
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/* USER CODE END */
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/* Emif Register Frame Definition */
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/** @struct emifBASE_t
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* @brief emifBASE Register Definition
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*
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* This structure is used to access the EMIF module registers.
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*/
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typedef volatile struct emifBase
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{
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uint32 MIDR; /**< 0x0000 Module ID Register */
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uint32 AWCC; /**< 0x0004 Asynchronous wait cycle register*/
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uint32 SDCR; /**< 0x0008 SDRAM configuration register */
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uint32 SDRCR ; /**< 0x000C Set Interrupt Enable Register */
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uint32 CE2CFG; /**< 0x0010 Asynchronous 1 Configuration Register */
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uint32 CE3CFG; /**< 0x0014 Asynchronous 2 Configuration Register */
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uint32 CE4CFG; /**< 0x0018 Asynchronous 3 Configuration Register */
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uint32 CE5CFG; /**< 0x001C Asynchronous 4 Configuration Register */
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uint32 SDTIMR; /**< 0x0020 SDRAM Timing Register */
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uint32 dummy1[6]; /** reserved **/
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uint32 SDSRETR; /**< 0x003c SDRAM Self Refresh Exit Timing Register */
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uint32 INTRAW; /**< 0x0040 0x0020 Interrupt Vector Offset*/
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uint32 INTMSK; /**< 0x0044 EMIF Interrupt Mask Register */
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uint32 INTMSKSET; /**< 48 EMIF Interrupt Mask Set Register */
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uint32 INTMSKCLR; /**< 0x004c EMIF Interrupt Mask Register */
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uint32 dummy2[6]; /** reserved **/
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uint32 PMCR; /**< 0x0068 Page Mode Control Register*/
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} emifBASE_t;
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#define emifREG ((emifBASE_t *)0xFCFFE800U)
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/* USER CODE BEGIN (1) */
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/* USER CODE END */
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#endif
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