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150 lines
4.3 KiB
150 lines
4.3 KiB
#include "rtconfig.h"
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#if defined(TARGET_ARMV8_AARCH64)
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#include <rthw.h>
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#include <rtthread.h>
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#include "interrupt.h"
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#include "gic.h"
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#include "gicv3.h"
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#include "ioremap.h"
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#include "phytium_cpu.h"
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#include "ftypes.h"
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#include "fparameters.h"
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struct arm_gic *phytium_gic_table;
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extern struct rt_irq_desc isr_table[MAX_HANDLERS];
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int arm_gic_redist_address_set(rt_uint64_t index, rt_uint64_t redist_addr, int cpu_id)
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{
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RT_ASSERT(index < ARM_GIC_MAX_NR);
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if (cpu_id == 0)
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{
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rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, &cpu_id, sizeof(cpu_id));
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}
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phytium_gic_table[index].redist_hw_base[cpu_id] = redist_addr;
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return 0;
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}
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static int arm_gicv3_wait_rwp(rt_uint64_t index, rt_uint64_t irq)
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{
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rt_uint64_t rwp_bit;
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rt_uint64_t base;
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RT_ASSERT(index < ARM_GIC_MAX_NR);
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if (irq < 32)
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{
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rt_int32_t cpu_id = rt_hw_cpu_id();
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base = phytium_gic_table[index].redist_hw_base[cpu_id];
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rwp_bit = GICR_CTLR_RWP;
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}
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else
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{
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base = phytium_gic_table[index].dist_hw_base;
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rwp_bit = GICD_CTLR_RWP;
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}
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while (HWREG32(base) & rwp_bit)
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{
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}
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return 0;
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}
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int phytium_aarch64_arm_gic_redist_init()
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{
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rt_uint64_t cpu_id = rt_hw_cpu_id();
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rt_uint64_t redist_base = phytium_gic_table[0].redist_hw_base[cpu_id];
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/* redistributor enable */
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GIC_RDIST_WAKER(redist_base) &= ~(1 << 1);
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while (GIC_RDIST_WAKER(redist_base) & (1 << 2))
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{
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}
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/* Disable all sgi and ppi interrupt */
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GIC_RDISTSGI_ICENABLER0(redist_base) = 0xffffffff;
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arm_gicv3_wait_rwp(0, 0);
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/* Clear all inetrrupt pending */
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GIC_RDISTSGI_ICPENDR0(redist_base) = 0xffffffff;
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/* the corresponding interrupt is Group 1 or Non-secure Group 1. */
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GIC_RDISTSGI_IGROUPR0(redist_base, 0) = 0xffffffff;
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GIC_RDISTSGI_IGRPMODR0(redist_base, 0) = 0xffffffff;
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/* Configure default priorities for SGI 0:15 and PPI 16:31. */
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for (int i = 0; i < 32; i += 4)
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{
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GIC_RDISTSGI_IPRIORITYR(redist_base, i) = 0xa0a0a0a0U;
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}
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/* Trigger level for PPI interrupts*/
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GIC_RDISTSGI_ICFGR1(redist_base) = 0;
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return 0;
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}
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void phytium_interrupt_init(void)
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{
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rt_uint64_t gic_cpu_base;
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rt_uint64_t gic_dist_base;
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rt_uint64_t gic_irq_start;
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rt_uint64_t redist_addr;
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phytium_gic_table = (struct arm_gic *)arm_gic_get_gic_table_addr();
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/* initialize vector table */
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rt_hw_vector_init();
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/* initialize exceptions table */
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rt_memset(isr_table, 0x00, sizeof(isr_table));
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#if defined(RT_USING_SMART)
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gic_dist_base = (rt_uint64_t)rt_ioremap((void *)platform_get_gic_dist_base(), 0x40000);
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gic_cpu_base = (rt_uint64_t)rt_ioremap((void*)platform_get_gic_cpu_base(), 0x1000);
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redist_addr = (rt_uint64_t)rt_ioremap(GICV3_RD_BASE_ADDR, 4 * GICV3_RD_OFFSET);
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#else
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gic_dist_base = platform_get_gic_dist_base();
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gic_cpu_base = platform_get_gic_cpu_base();
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redist_addr = GICV3_RD_BASE_ADDR;
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#endif
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gic_irq_start = 0;
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arm_gic_dist_init(0, gic_dist_base, gic_irq_start);
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arm_gic_cpu_init(0, gic_cpu_base);
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arm_gic_redist_address_set(0, redist_addr + 2 * GICV3_RD_OFFSET, 0);
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#if defined(TARGET_E2000Q) || defined(TARGET_PHYTIUMPI)
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#if RT_CPUS_NR == 2
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arm_gic_redist_address_set(0, redist_addr + 3 * GICV3_RD_OFFSET, 1);
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#elif RT_CPUS_NR == 3
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arm_gic_redist_address_set(0, redist_addr + 3 * GICV3_RD_OFFSET, 1);
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arm_gic_redist_address_set(0, redist_addr, 2);
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#elif RT_CPUS_NR == 4
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arm_gic_redist_address_set(0, redist_addr + 3 * GICV3_RD_OFFSET, 1);
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arm_gic_redist_address_set(0, redist_addr, 2);
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arm_gic_redist_address_set(0, redist_addr + GICV3_RD_OFFSET, 3);
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#endif
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#else
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#if defined(TARGET_E2000D)
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rt_uint32_t cpu_offset = 2;
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#endif
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#if RT_CPUS_NR == 2
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arm_gic_redist_address_set(0, redist_addr + (1 + cpu_offset) * GICV3_RD_OFFSET, 1);
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#elif RT_CPUS_NR == 3
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arm_gic_redist_address_set(0, redist_addr + (1 + cpu_offset) * GICV3_RD_OFFSET, 1);
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arm_gic_redist_address_set(0, redist_addr + (2 + cpu_offset) * GICV3_RD_OFFSET, 2);
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#elif RT_CPUS_NR == 4
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arm_gic_redist_address_set(0, redist_addr + (1 + cpu_offset) * GICV3_RD_OFFSET, 1);
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arm_gic_redist_address_set(0, redist_addr + (2 + cpu_offset) * GICV3_RD_OFFSET, 2);
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arm_gic_redist_address_set(0, redist_addr + (3 + cpu_offset) * GICV3_RD_OFFSET, 3);
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#endif
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#endif
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phytium_aarch64_arm_gic_redist_init();
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}
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#endif
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