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121 lines
4.8 KiB
121 lines
4.8 KiB
# SAMD51J19A Adafruit Metro M4 BSP Introduction
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[中文](README_zh.md)
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- MCU: ATSAMD51J19A @120MHz, 512KB FLASH, 192KB RAM
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- D51: Cortex-M4F + Adavanced Feature Set
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- Pin: G=48 pins, J=64 pins, N=100 pins, P=128 pins
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- Flash: 18=256KB, 19=512KB, 20=1024KB (size=2^n)
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- SRAM : 128KB(Flash 256KB), 192KB(Flash 512KB), 256KB(Flash 1MB)
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- Datasheet: <https://www.microchip.com/en-us/product/ATSAMD51J19>
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#### KEY FEATURES
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#### Core
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- 32-bit Arm® Cortex®-M4 core with single-precision FPU and 4 KB combined instruction cache and data cache; frequency up to 120 MHz, MPU, 403 CoreMark® at 120 MHz, and DSP instructions
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#### Memories
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- 1 MB/512 KB/256 KB in-system self-programmable Flash with:
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- Error Correction Code (ECC)
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- Dual bank with Read-While-Write (RWW) support
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- EEPROM hardware emulation
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- 128 KB, 192 KB, 256 KB SRAM main memory
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- 64 KB, 96 KB, 128 KB of Error Correction Code (ECC) RAM option
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- Up to 4 KB of Tightly Coupled Memory (TCM)
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- Up to 8 KB additional SRAM
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- Can be retained in backup mode
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- Eight 32-bit backup registers
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#### System
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- Power-on Reset (POR) and Brown-out detection (BOD)
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- Internal and external clock options
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- External Interrupt Controller (EIC)
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- 16 external interrupts
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- One non-maskable interrupt
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- Two-pin Serial Wire Debug (SWD) programming, test, and debugging interface
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#### High-Performance Peripherals
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- 32-channel Direct Memory Access Controller (DMAC)
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- Up to two SD/MMC Host Controller (SDHC)
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- Up to 50 MHz operation
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- 4-bit or 1-bit interface
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- Compatibility with SD and SDHC memory card specification version 3.01
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- Compatibility with SDIO specification version 3.0
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- Compliant with JDEC specification, MMC memory cards V4.51
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- One Quad I/O Serial Peripheral Interface (QSPI)
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- Dedicated AHB memory zone
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- One Ethernet MAC (SAM E53 and SAM E54)– 10/100 Mbps in MII and RMII with dedicated DMA
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- IEEE® 1588 Precision Time Protocol (PTP) support
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- IEEE 1588 Time Stamping Unit (TSU) support
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- IEEE802.3AZ energy efficiency support
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- Support for 802.1AS and 1588 precision clock synchronization protocol
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- Wake on LAN support
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- Up to two Controller Area Network (CAN) (that is., SAM E51 and SAM E54)
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- Support for CAN 2.0A/CAN 2.0B and CAN-FD (ISO 11898-1:2016)
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- One Full-Speed (12 Mbps) Universal Serial Bus (USB) 2.0 interface
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- Embedded host and device function
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- Eight endpoints
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- On-chip transceiver with integrated serial resistor
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#### System Peripherals
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- Up to 114 I/O lines with external interrupt capability (edge- or level-sensitivity), debouncing, glitch filtering and On-die Series Resistor Termination
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- Five Parallel Input/Output Controllers (PIO)
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- 32-channel Event System
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- Up to eight Serial Communication Interfaces (SERCOM), can be configured as USART/I2C/SPI
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- Up to eight 16-bit Timers/Counters (TC), can be configured as 8/16/32bit TC.
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- Two 24-bit Timer/Counters for Control (TCC), with extended functions
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- Up to Three 16-bit Timer/Counters for Control (TCC) with extended functions.
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- 32-bit Real Time Counter (RTC) with clock/calendar function
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- Up to 4 wake-up pins with tamper detection and debouncing filter
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- Watchdog Timer (WDT) with Window mode
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- CRC-32 generator
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- One two-channel Inter-IC Sound Interface (I2S)
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- Position Decoder (PDEC)
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- Frequency meter (FREQM)
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- Four Configurable Custom Logic (CCL)
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- Dual 12-bit, 1 MSPS Analog-to-Digital Converter (ADC) with up to 16 channels each:
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- Dual 12-bit, 1 MSPS output Digital-to-Analog Converter (DAC)
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- Two Analog Comparators (AC) with Window Compare function
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- One temperature sensor
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- Parallel Capture Controller (PCC)
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- Peripheral Touch Controller (PTC) - Capacitive Touch buttons, sliders, and wheels
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#### Cryptography
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- One Advanced Encryption System (AES) with 256-bit key length and up to 2 MB/s data rate
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- Five confidential modes of operation (ECB, CBC, CFB, OFB, CTR)
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- Supports counter with CBC-MAC mode
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- Galois Counter Mode (GCM) - True Random Number Generator (TRNG)
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- Public Key Cryptography Controller (PUKCC) and associated Classical Public Key Cryptography Library (PUKCL)
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- RSA, DSA : Elliptic Curves Cryptography (ECC) ECC GF(2n), ECC GF(p)
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- Integrity Check Module (ICM) based on Secure Hash Algorithm (SHA1, SHA224, SHA256), DMA assisted
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#### I/O
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- Up to 99 programmable I/O pins
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#### Qualification
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- AEC-Q100 Grade 1 (-40°C to 125°C)
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#### Package Type
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- VQFN48, 48-lead VQFN, 7x7 mm, pitch 0.5 mm, I/O Pins up to 37
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- VQFN64, 64-lead VQFN, 9x9 mm, pitch 0.5 mm, I/O Pins up to 51
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- TQFP64, 64-lead TQFP, 10x10 mm, pitch 0.5 mm, I/O Pins up to 51
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- TQFP100, 100-lead TQFP, 14x14 mm, pitch 0.5 mm, I/O Pins up to 81
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- TQFP128, 128-lead TQFP, 14x14 mm, pitch 0.4 mm, I/O Pins up to 99
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- TFBGA120, 120-ball TFBGA, 8x8 mm, pitch 0.5 mm, I/O Pins up to 90
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#### Board info
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- [Adafruit Metro M4 feat. Microchip ATSAMD51](https://www.adafruit.com/product/3382)
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#### Contact Info
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- [luhuadong](https://github.com/luhuadong), <luhuadong@163.com>
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