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155 lines
3.6 KiB
155 lines
3.6 KiB
/*
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* Copyright (c) 2006-2024, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2024-03-28 qiujingbao first version
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*/
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#ifndef __DRV_SPI_H__
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#define __DRV_SPI_H__
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#include "rtdevice.h"
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#include <rthw.h>
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#include <rtthread.h>
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#include "mmio.h"
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#include "pinctrl.h"
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#define SPI0 0x0
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#define SPI1 0x1
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#define SPI2 0x2
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#define SPI3 0x3
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#define SPI0_BASE 0x04180000
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#define SPI1_BASE 0x04190000
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#define SPI2_BASE 0x041A0000
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#define SPI3_BASE 0x041B0000
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#define SPI_IRQ_MSAK 0x3e
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#define SPI_FREQUENCY 187500000
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/* Transmit FiFO Threshold Level */
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#define SPI_TXFTLR 0xf
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#define SPI_CTRL0_DATA_FREAM_SHIFT 0
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#define SPI_CTRL0_FREAM_FORMAT_SHIFT 4
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#define SPI_CTRL0_CPHA_SHIFT 6
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#define SPI_CTRL0_CPOL_SHIFT 7
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#define SPI_CTRL0_TRANS_MODE 8
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#define SPI_CTRL0_LOOP_SHIFT 11
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#define SPI_CTRL0_CTRL_FREAM_SHIFT 12
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struct cv1800_spi {
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uint8_t spi_id;
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char *device_name;
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uint8_t fifo_len;
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uint8_t data_width;
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const void *send_buf;
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void *recv_buf;
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const void *send_end;
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void *recv_end;
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struct rt_spi_bus spi_bus;
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struct spi_regs *reg;
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};
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struct spi_regs {
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uint32_t spi_ctrl0; // 0x00
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uint32_t spi_ctrl1; // 0x04
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uint32_t spi_ssienr; // 0x08
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uint32_t spi_mwcr; // 0x0c
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uint32_t spi_ser; // 0x10
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uint32_t spi_baudr; // 0x14
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uint32_t spi_txftlr; // 0x18
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uint32_t spi_rxftlr; // 0x1c
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uint32_t spi_txflr; // 0x20
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uint32_t spi_rxflr; // 0x24
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uint32_t spi_sr; // 0x28
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uint32_t spi_imr; // 0x2c
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uint32_t spi_isr; // 0x30
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uint32_t spi_risr; // 0x34
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uint32_t spi_txoicr; // 0x38
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uint32_t spi_rxoicr; // 0x3c
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uint32_t spi_rxuicr; // 0x40
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uint32_t spi_msticr; // 0x44
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uint32_t spi_icr; // 0x48
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uint32_t spi_dmacr; // 0x4c
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uint32_t spi_dmatdlr; // 0x50
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uint32_t spi_dmardlr; // 0x54
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uint32_t spi_idr; // 0x58
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uint32_t spi_version; // 0x5c
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uint32_t spi_dr; // 0x60
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uint32_t spi_rx_sample_dly; // 0xf0
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uint32_t spi_cs_override; // 0xf4
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};
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uint32_t gen_spi_mode(struct rt_spi_configuration *cfg, uint32_t *mode)
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{
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uint32_t value = 0;
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if (cfg->data_width != 8 && cfg->data_width != 16)
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return -1;
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value |= (cfg->data_width - 1) >> SPI_CTRL0_DATA_FREAM_SHIFT;
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value |= cfg->mode >> SPI_CTRL0_CPHA_SHIFT;
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*mode = value;
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return 0;
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}
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/* set spi mode */
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static inline void spi_set_mode(struct spi_regs *reg, uint32_t mode)
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{
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mmio_write_32((uintptr_t)®->spi_ctrl0, mode);
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}
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/* clear irq */
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static inline void spi_clear_irq(struct spi_regs *reg, uint32_t mode)
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{
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mmio_write_32((uintptr_t)®->spi_imr, mode);
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}
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static inline void spi_enable_cs(struct spi_regs *reg, uint32_t enable)
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{
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if (enable)
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enable = 0x1;
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else
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enable = 0x0;
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mmio_write_32((uintptr_t)®->spi_ser, enable);
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}
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/* set spi frequency*/
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static inline rt_err_t spi_set_frequency(struct spi_regs *reg, uint32_t speed)
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{
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uint16_t value;
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/* The value of the BAUDR register must be an even number between 2-65534 */
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value = SPI_FREQUENCY / speed;
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if (value % 2 != 0)
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value++;
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if (value < 4 || value > 65534)
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value = 4;
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mmio_write_32((uintptr_t)®->spi_baudr, value);
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return RT_EOK;
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}
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static inline void spi_enable(struct spi_regs *reg, uint32_t enable)
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{
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if (enable)
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enable = 0x1;
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else
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enable = 0x0;
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mmio_write_32((uintptr_t)®->spi_ssienr, enable);
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}
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#endif /* __DRV_SPI_H__ */
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