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113 lines
1.6 KiB
113 lines
1.6 KiB
#include <stdint.h>
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#include "arm.h"
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__asm uint32_t arm_read_p15_c1(void)
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{
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MRC p15, 0, R0, c1, c0, 0
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BX LR
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}
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__asm void arm_write_p15_c1(uint32_t value)
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{
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MCR p15, 0, R0, c1, c0, 0
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BX LR
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}
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__asm void arm_set_ttb(uint32_t base)
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{
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MCR p15, 0, R0, c2, c0, 0
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BX LR
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}
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__asm uint32_t arm_get_ttb(void)
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{
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MRC p15, 0, R0, c2, c0, 0
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BX LR
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}
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__asm void arm_set_domain(uint32_t domain)
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{
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MCR p15, 0, R0, c3, c0, 0
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BX LR
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}
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__asm uint32_t arm_get_domain(void)
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{
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MCR p15, 0, R0, c3, c0, 0
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BX LR
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}
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__asm void arm_invalidate_tlb(void)
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{
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PUSH {R0}
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MOV R0, #0
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MCR p15, 0, R0, c7, c10, 4
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MCR p15, 0, R0, c8, c6, 0
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MCR p15, 0, R0, c8, c5, 0
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POP {R0}
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BX LR
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}
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void arm_enable_dcache(void)
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{
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uint32_t value = arm_read_p15_c1();
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arm_write_p15_c1(value | (1 << 2));
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}
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void arm_disable_dcache(void)
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{
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uint32_t value = arm_read_p15_c1();
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arm_write_p15_c1(value & ~(1 << 2));
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}
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void arm_enable_icache(void)
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{
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uint32_t value = arm_read_p15_c1();
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arm_write_p15_c1(value | (1 << 12));
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}
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void arm_disable_icache(void)
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{
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uint32_t value = arm_read_p15_c1();
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arm_write_p15_c1(value & ~(1 << 12));
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}
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void arm_enable_mmu(void)
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{
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uint32_t value = arm_read_p15_c1();
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arm_write_p15_c1(value | (1 << 0));
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}
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void arm_disable_mmu(void)
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{
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uint32_t value = arm_read_p15_c1();
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arm_write_p15_c1(value & ~(1 << 0));
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}
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__asm uint32_t arm_read_cpsr_c(void)
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{
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MRS R0, CPSR
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BX LR
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}
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__asm void arm_write_cpsr_c(uint32_t value)
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{
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MSR CPSR_c, R0
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BX LR
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}
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__asm void arm_enable_irq(void)
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{
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MRS R0, CPSR
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AND R0, R0, #0x7F
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MSR CPSR_c, R0
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BX LR
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}
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__asm void arm_disable_irq(void)
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{
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MRS R0, CPSR
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ORR R0, R0, #0x80
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MSR CPSR_c, R0
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BX LR
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}
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