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10309 lines
981 KiB
10309 lines
981 KiB
/*
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* Copyright (c) 2020, Ambiq Micro, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* Third party software included in this distribution is subject to the
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* additional license terms as defined in the /docs/licenses directory.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* @file apollo1.h
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* @brief CMSIS HeaderFile
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* @version 1.0
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* @date 05. March 2020
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* @note Generated by SVDConv V3.3.27 on Thursday, 05.03.2020 15:23:36
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* from File './apollo1.svd',
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* last modified on Thursday, 05.03.2020 21:23:35
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*/
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/** @addtogroup Ambiq Micro
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* @{
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*/
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/** @addtogroup apollo1
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* @{
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*/
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#ifndef APOLLO1_H
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#define APOLLO1_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @addtogroup Configuration_of_CMSIS
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* @{
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*/
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/* =========================================================================================================================== */
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/* ================ Interrupt Number Definition ================ */
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/* =========================================================================================================================== */
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typedef enum {
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/* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */
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Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
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NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
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HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
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MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation
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and No Match */
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BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
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related Fault */
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UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
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SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
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DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
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PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
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SysTick_IRQn = -1, /*!< -1 System Tick Timer */
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/* ========================================== apollo1 Specific Interrupt Numbers =========================================== */
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BROWNOUT_IRQn = 0, /*!< 0 BROWNOUT */
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WDT_IRQn = 1, /*!< 1 WDT */
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CLKGEN_RTC_IRQn = 2, /*!< 2 CLKGEN_RTC */
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VCOMP_IRQn = 3, /*!< 3 VCOMP */
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IOSLAVE_IRQn = 4, /*!< 4 IOSLAVE */
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IOSLAVEACC_IRQn = 5, /*!< 5 IOSLAVEACC */
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IOMSTR0_IRQn = 6, /*!< 6 IOMSTR0 */
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IOMSTR1_IRQn = 7, /*!< 7 IOMSTR1 */
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ADC_IRQn = 8, /*!< 8 ADC */
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GPIO_IRQn = 9, /*!< 9 GPIO */
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CTIMER_IRQn = 10, /*!< 10 CTIMER */
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UART_IRQn = 11 /*!< 11 UART */
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} IRQn_Type;
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/* =========================================================================================================================== */
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/* ================ Processor and Core Peripheral Section ================ */
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/* =========================================================================================================================== */
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/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */
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#define __CM4_REV 0x0100U /*!< CM4 Core Revision */
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#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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#define __MPU_PRESENT 1 /*!< MPU present */
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#define __FPU_PRESENT 1 /*!< FPU present */
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/** @} */ /* End of group Configuration_of_CMSIS */
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#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */
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#include "system_apollo1.h" /*!< apollo1 System */
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#ifndef __IM /*!< Fallback for older CMSIS versions */
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#define __IM __I
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#endif
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#ifndef __OM /*!< Fallback for older CMSIS versions */
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#define __OM __O
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#endif
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#ifndef __IOM /*!< Fallback for older CMSIS versions */
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#define __IOM __IO
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#endif
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/* ======================================== Start of section using anonymous unions ======================================== */
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#if defined (__CC_ARM)
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#pragma push
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#pragma anon_unions
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#elif defined (__ICCARM__)
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#pragma language=extended
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#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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#pragma clang diagnostic push
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#pragma clang diagnostic ignored "-Wc11-extensions"
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#pragma clang diagnostic ignored "-Wreserved-id-macro"
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#pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
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#pragma clang diagnostic ignored "-Wnested-anon-types"
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#elif defined (__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined (__TMS470__)
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/* anonymous unions are enabled by default */
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#elif defined (__TASKING__)
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#pragma warning 586
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#elif defined (__CSMC__)
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/* anonymous unions are enabled by default */
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#else
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#warning Not supported compiler type
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#endif
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/* =========================================================================================================================== */
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/* ================ Device Specific Peripheral Section ================ */
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/* =========================================================================================================================== */
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/** @addtogroup Device_Peripheral_peripherals
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* @{
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*/
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/* =========================================================================================================================== */
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/* ================ ADC ================ */
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/* =========================================================================================================================== */
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/**
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* @brief Analog Digital Converter Control (ADC)
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*/
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typedef struct { /*!< (@ 0x50008000) ADC Structure */
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union {
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__IOM uint32_t CFG; /*!< (@ 0x00000000) Configuration Register */
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struct {
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__IOM uint32_t ADCEN : 1; /*!< [0..0] This bit enables the ADC module. While the ADC is enabled,
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the ADCCFG and SLOT Configuration regsiter settings must
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remain stable and unchanged. */
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__IOM uint32_t TMPSPWR : 1; /*!< [1..1] This enables power to the temperature sensor module.
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After setting this bit, the temperature sensor will remain
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powered down while the ADC is power is disconnected (i.e,
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when the ADC PWDSTAT is 2'b10). */
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__IOM uint32_t RPTEN : 1; /*!< [2..2] This bit enables Repeating Scan Mode. */
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__IOM uint32_t LPMODE : 2; /*!< [4..3] Select power mode to enter between active scans. */
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__IOM uint32_t OPMODE : 2; /*!< [6..5] Select the sample rate mode. It adjusts the current in
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the ADC for higher sample rates. A 12MHz ADC clock can
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result in a sample rate up to 1Msps depending on the trigger
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or repeating mode rate. A 1.5MHz ADC clock can result in
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a sample rate up 125K sps. NOTE: All other values not specified
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below are undefined. */
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__IOM uint32_t BATTLOAD : 1; /*!< [7..7] Control 500 Ohm battery load resistor. */
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__IOM uint32_t REFSEL : 2; /*!< [9..8] Select the ADC reference voltage. */
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__IM uint32_t : 6;
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__IOM uint32_t TRIGSEL : 4; /*!< [19..16] Select the ADC trigger source. */
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__IOM uint32_t TRIGPOL : 1; /*!< [20..20] This bit selects the ADC trigger polarity for external
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off chip triggers. */
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__IM uint32_t : 3;
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__IOM uint32_t CLKSEL : 3; /*!< [26..24] Select the source and frequency for the ADC clock.
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All values not enumerated below are undefined. */
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} CFG_b;
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} ;
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union {
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__IOM uint32_t STAT; /*!< (@ 0x00000004) ADC Power Status */
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struct {
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__IOM uint32_t PWDSTAT : 2; /*!< [1..0] Indicates the power-status of the ADC. */
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} STAT_b;
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} ;
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union {
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__IOM uint32_t SWT; /*!< (@ 0x00000008) Software trigger */
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struct {
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__IOM uint32_t SWT : 8; /*!< [7..0] Writing 0x37 to this register generates a software trigger. */
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} SWT_b;
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} ;
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union {
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__IOM uint32_t SL0CFG; /*!< (@ 0x0000000C) Slot 0 Configuration Register */
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struct {
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__IOM uint32_t SLEN0 : 1; /*!< [0..0] This bit enables slot 0 for ADC conversions. */
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__IOM uint32_t WCEN0 : 1; /*!< [1..1] This bit enables the window compare function for slot
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0. */
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__IM uint32_t : 6;
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__IOM uint32_t CHSEL0 : 4; /*!< [11..8] Select one of the 13 channel inputs for this slot. */
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__IM uint32_t : 4;
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__IOM uint32_t THSEL0 : 3; /*!< [18..16] Select the track and hold delay for this slot. NOTE:
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The track and hold delay must be less than 50us for correct
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operation. When the ADC is configured to use the 1.5Mhz
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clock, the track and hold delay cannot exceed 64 clocks. */
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__IM uint32_t : 5;
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__IOM uint32_t ADSEL0 : 3; /*!< [26..24] Select the number of measurements to average in the
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accumulate divide module for this slot. */
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} SL0CFG_b;
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} ;
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union {
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__IOM uint32_t SL1CFG; /*!< (@ 0x00000010) Slot 1 Configuration Register */
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struct {
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__IOM uint32_t SLEN1 : 1; /*!< [0..0] This bit enables slot 1 for ADC conversions. */
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__IOM uint32_t WCEN1 : 1; /*!< [1..1] This bit enables the window compare function for slot
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1. */
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__IM uint32_t : 6;
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__IOM uint32_t CHSEL1 : 4; /*!< [11..8] Select one of the 13 channel inputs for this slot. */
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__IM uint32_t : 4;
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__IOM uint32_t THSEL1 : 3; /*!< [18..16] Select the track and hold delay for this slot. NOTE:
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The track and hold delay must be less than 50us for correct
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operation. When the ADC is configured to use the 1.5 Mhz
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clock, the track and hold delay cannot exceed 64 clocks. */
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__IM uint32_t : 5;
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__IOM uint32_t ADSEL1 : 3; /*!< [26..24] Select the number of measurements to average in the
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accumulate divide module for this slot. */
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} SL1CFG_b;
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} ;
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union {
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__IOM uint32_t SL2CFG; /*!< (@ 0x00000014) Slot 2 Configuration Register */
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struct {
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__IOM uint32_t SLEN2 : 1; /*!< [0..0] This bit enables slot 2 for ADC conversions. */
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__IOM uint32_t WCEN2 : 1; /*!< [1..1] This bit enables the window compare function for slot
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2. */
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__IM uint32_t : 6;
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__IOM uint32_t CHSEL2 : 4; /*!< [11..8] Select one of the 13 channel inputs for this slot. */
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__IM uint32_t : 4;
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__IOM uint32_t THSEL2 : 3; /*!< [18..16] Select the track and hold delay for this slot. NOTE:
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The track and hold delay must be less than 50us for correct
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operation. When the ADC is configured to use the 1.5Mhz
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clock, the track and hold delay cannot exceed 64 clocks. */
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__IM uint32_t : 5;
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__IOM uint32_t ADSEL2 : 3; /*!< [26..24] Select the number of measurements to average in the
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accumulate divide module for this slot. */
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} SL2CFG_b;
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} ;
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union {
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__IOM uint32_t SL3CFG; /*!< (@ 0x00000018) Slot 3 Configuration Register */
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struct {
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__IOM uint32_t SLEN3 : 1; /*!< [0..0] This bit enables slot 3 for ADC conversions. */
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__IOM uint32_t WCEN3 : 1; /*!< [1..1] This bit enables the window compare function for slot
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3. */
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__IM uint32_t : 6;
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__IOM uint32_t CHSEL3 : 4; /*!< [11..8] Select one of the 13 channel inputs for this slot. */
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__IM uint32_t : 4;
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__IOM uint32_t THSEL3 : 3; /*!< [18..16] Select the track and hold delay for this slot. NOTE:
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The track and hold delay must be less than 50us for correct
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operation. When the ADC is configured to use the 1.5Mhz
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clock, the track and hold delay cannot exceed 64 clocks. */
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__IM uint32_t : 5;
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__IOM uint32_t ADSEL3 : 3; /*!< [26..24] Select the number of measurements to average in the
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accumulate divide module for this slot. */
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} SL3CFG_b;
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} ;
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union {
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__IOM uint32_t SL4CFG; /*!< (@ 0x0000001C) Slot 4 Configuration Register */
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struct {
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__IOM uint32_t SLEN4 : 1; /*!< [0..0] This bit enables slot 4 for ADC conversions. */
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__IOM uint32_t WCEN4 : 1; /*!< [1..1] This bit enables the window compare function for slot
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4. */
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__IM uint32_t : 6;
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__IOM uint32_t CHSEL4 : 4; /*!< [11..8] Select one of the 13 channel inputs for this slot. */
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__IM uint32_t : 4;
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__IOM uint32_t THSEL4 : 3; /*!< [18..16] Select the track and hold delay for this slot. NOTE:
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The track and hold delay must be less than 50us for correct
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operation. When the ADC is configured to use the 1.5Mhz
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clock, the track and hold delay cannot exceed 64 clocks. */
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__IM uint32_t : 5;
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__IOM uint32_t ADSEL4 : 3; /*!< [26..24] Select the number of measurements to average in the
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accumulate divide module for this slot. */
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} SL4CFG_b;
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} ;
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union {
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__IOM uint32_t SL5CFG; /*!< (@ 0x00000020) Slot 5 Configuration Register */
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struct {
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__IOM uint32_t SLEN5 : 1; /*!< [0..0] This bit enables slot 5 for ADC conversions. */
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__IOM uint32_t WCEN5 : 1; /*!< [1..1] This bit enables the window compare function for slot
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5. */
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__IM uint32_t : 6;
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__IOM uint32_t CHSEL5 : 4; /*!< [11..8] Select one of the 13 channel inputs for this slot. */
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__IM uint32_t : 4;
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__IOM uint32_t THSEL5 : 3; /*!< [18..16] Select track and hold delay for this slot. NOTE: The
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track and hold delay must be less than 50us for correct
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operation. When the ADC is configured to use the 1.5Mhz
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clock, the track and hold delay cannot exceed 64 clocks. */
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__IM uint32_t : 5;
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__IOM uint32_t ADSEL5 : 3; /*!< [26..24] Select number of measurements to average in the accumulate
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divide module for this slot. */
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} SL5CFG_b;
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} ;
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union {
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__IOM uint32_t SL6CFG; /*!< (@ 0x00000024) Slot 6 Configuration Register */
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struct {
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__IOM uint32_t SLEN6 : 1; /*!< [0..0] This bit enables slot 6 for ADC conversions. */
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__IOM uint32_t WCEN6 : 1; /*!< [1..1] This bit enables the window compare function for slot
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6. */
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__IM uint32_t : 6;
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__IOM uint32_t CHSEL6 : 4; /*!< [11..8] Select one of the 13 channel inputs for this slot. */
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__IM uint32_t : 4;
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__IOM uint32_t THSEL6 : 3; /*!< [18..16] Select track and hold delay for this slot. NOTE: The
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track and hold delay must be less than 50us for correct
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operation. When the ADC is configured to use the 1.5Mhz
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clock, the track and hold delay cannot exceed 64 clocks. */
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__IM uint32_t : 5;
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__IOM uint32_t ADSEL6 : 3; /*!< [26..24] Select the number of measurements to average in the
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accumulate divide module for this slot. */
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} SL6CFG_b;
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} ;
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union {
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__IOM uint32_t SL7CFG; /*!< (@ 0x00000028) Slot 7 Configuration Register */
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struct {
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__IOM uint32_t SLEN7 : 1; /*!< [0..0] This bit enables slot 7 for ADC conversions. */
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__IOM uint32_t WCEN7 : 1; /*!< [1..1] This bit enables the window compare function for slot
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7. */
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__IM uint32_t : 6;
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__IOM uint32_t CHSEL7 : 4; /*!< [11..8] Select one of the 13 channel inputs for this slot. */
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__IM uint32_t : 4;
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__IOM uint32_t THSEL7 : 3; /*!< [18..16] Select track and hold delay for this slot. NOTE: The
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track and hold delay must be less than 50us for correct
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operation. When the ADC is configured to use the 1.5Mhz
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clock, the track and hold delay cannot exceed 64 clocks. */
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__IM uint32_t : 5;
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__IOM uint32_t ADSEL7 : 3; /*!< [26..24] Select the number of measurements to average in the
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accumulate divide module for this slot. */
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} SL7CFG_b;
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} ;
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union {
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__IOM uint32_t WLIM; /*!< (@ 0x0000002C) Window Comparator Limits Register */
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struct {
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__IOM uint32_t LLIM : 16; /*!< [15..0] Sets the lower limit for the wondow comparator. */
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__IOM uint32_t ULIM : 16; /*!< [31..16] Sets the upper limit for the wondow comparator. */
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} WLIM_b;
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} ;
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union {
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__IOM uint32_t FIFO; /*!< (@ 0x00000030) FIFO Data and Valid Count Register */
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struct {
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__IOM uint32_t DATA : 16; /*!< [15..0] Oldest data in the FIFO. */
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__IOM uint32_t COUNT : 4; /*!< [19..16] Number of valid entries in the ADC FIFO. */
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__IOM uint32_t RSVD_20 : 4; /*!< [23..20] RESERVED. */
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__IOM uint32_t SLOTNUM : 3; /*!< [26..24] Slot number associated with this FIFO data. */
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__IOM uint32_t RSVD_27 : 5; /*!< [31..27] RESERVED. */
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} FIFO_b;
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} ;
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__IM uint32_t RESERVED[115];
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union {
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__IOM uint32_t INTEN; /*!< (@ 0x00000200) ADC Interrupt registers: Enable */
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struct {
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__IOM uint32_t CNVCMP : 1; /*!< [0..0] ADC conversion complete interrupt. */
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__IOM uint32_t SCNCMP : 1; /*!< [1..1] ADC scan complete interrupt. */
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__IOM uint32_t FIFOOVR1 : 1; /*!< [2..2] FIFO 75 percent full interrupt. */
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__IOM uint32_t FIFOOVR2 : 1; /*!< [3..3] FIFO 100 percent full interrupt. */
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__IOM uint32_t WCEXC : 1; /*!< [4..4] Window comparator voltage excursion interrupt. */
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__IOM uint32_t WCINC : 1; /*!< [5..5] Window comparator voltage incursion interrupt. */
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} INTEN_b;
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} ;
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union {
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__IOM uint32_t INTSTAT; /*!< (@ 0x00000204) ADC Interrupt registers: Status */
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struct {
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__IOM uint32_t CNVCMP : 1; /*!< [0..0] ADC conversion complete interrupt. */
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__IOM uint32_t SCNCMP : 1; /*!< [1..1] ADC scan complete interrupt. */
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__IOM uint32_t FIFOOVR1 : 1; /*!< [2..2] FIFO 75 percent full interrupt. */
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__IOM uint32_t FIFOOVR2 : 1; /*!< [3..3] FIFO 100 percent full interrupt. */
|
|
__IOM uint32_t WCEXC : 1; /*!< [4..4] Window comparator voltage excursion interrupt. */
|
|
__IOM uint32_t WCINC : 1; /*!< [5..5] Window comparator voltage incursion interrupt. */
|
|
} INTSTAT_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t INTCLR; /*!< (@ 0x00000208) ADC Interrupt registers: Clear */
|
|
|
|
struct {
|
|
__IOM uint32_t CNVCMP : 1; /*!< [0..0] ADC conversion complete interrupt. */
|
|
__IOM uint32_t SCNCMP : 1; /*!< [1..1] ADC scan complete interrupt. */
|
|
__IOM uint32_t FIFOOVR1 : 1; /*!< [2..2] FIFO 75 percent full interrupt. */
|
|
__IOM uint32_t FIFOOVR2 : 1; /*!< [3..3] FIFO 100 percent full interrupt. */
|
|
__IOM uint32_t WCEXC : 1; /*!< [4..4] Window comparator voltage excursion interrupt. */
|
|
__IOM uint32_t WCINC : 1; /*!< [5..5] Window comparator voltage incursion interrupt. */
|
|
} INTCLR_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t INTSET; /*!< (@ 0x0000020C) ADC Interrupt registers: Set */
|
|
|
|
struct {
|
|
__IOM uint32_t CNVCMP : 1; /*!< [0..0] ADC conversion complete interrupt. */
|
|
__IOM uint32_t SCNCMP : 1; /*!< [1..1] ADC scan complete interrupt. */
|
|
__IOM uint32_t FIFOOVR1 : 1; /*!< [2..2] FIFO 75 percent full interrupt. */
|
|
__IOM uint32_t FIFOOVR2 : 1; /*!< [3..3] FIFO 100 percent full interrupt. */
|
|
__IOM uint32_t WCEXC : 1; /*!< [4..4] Window comparator voltage excursion interrupt. */
|
|
__IOM uint32_t WCINC : 1; /*!< [5..5] Window comparator voltage incursion interrupt. */
|
|
} INTSET_b;
|
|
} ;
|
|
} ADC_Type; /*!< Size = 528 (0x210) */
|
|
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ CLKGEN ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/**
|
|
* @brief Clock Generator (CLKGEN)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x40004000) CLKGEN Structure */
|
|
|
|
union {
|
|
__IOM uint32_t CALXT; /*!< (@ 0x00000000) XT Oscillator Control */
|
|
|
|
struct {
|
|
__IOM uint32_t CALXT : 11; /*!< [10..0] XT Oscillator calibration value */
|
|
} CALXT_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t CALRC; /*!< (@ 0x00000004) RC Oscillator Control */
|
|
|
|
struct {
|
|
__IOM uint32_t CALRC : 18; /*!< [17..0] LFRC Oscillator calibration value */
|
|
} CALRC_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t ACALCTR; /*!< (@ 0x00000008) Autocalibration Counter */
|
|
|
|
struct {
|
|
__IOM uint32_t ACALCTR : 24; /*!< [23..0] Autocalibration Counter result. */
|
|
} ACALCTR_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t OCTRL; /*!< (@ 0x0000000C) Oscillator Control */
|
|
|
|
struct {
|
|
__IOM uint32_t STOPXT : 1; /*!< [0..0] Stop the XT Oscillator to the RTC */
|
|
__IOM uint32_t STOPRC : 1; /*!< [1..1] Stop the LFRC Oscillator to the RTC */
|
|
__IM uint32_t : 4;
|
|
__IOM uint32_t FOS : 1; /*!< [6..6] Oscillator switch on failure function */
|
|
__IOM uint32_t OSEL : 1; /*!< [7..7] Selects the RTC oscillator (1 => LFRC, 0 => XT) */
|
|
__IOM uint32_t ACAL : 3; /*!< [10..8] Autocalibration control */
|
|
} OCTRL_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t CLKOUT; /*!< (@ 0x00000010) CLKOUT Frequency Select */
|
|
|
|
struct {
|
|
__IOM uint32_t CKSEL : 6; /*!< [5..0] CLKOUT signal select */
|
|
__IM uint32_t : 1;
|
|
__IOM uint32_t CKEN : 1; /*!< [7..7] Enable the CLKOUT signal */
|
|
} CLKOUT_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t CLKKEY; /*!< (@ 0x00000014) Key Register for Clock Control Register */
|
|
|
|
struct {
|
|
__IOM uint32_t CLKKEY : 32; /*!< [31..0] Key register value. */
|
|
} CLKKEY_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t CCTRL; /*!< (@ 0x00000018) HFRC Clock Control */
|
|
|
|
struct {
|
|
__IOM uint32_t CORESEL : 3; /*!< [2..0] Core Clock divisor */
|
|
__IOM uint32_t MEMSEL : 1; /*!< [3..3] Flash Clock divisor */
|
|
} CCTRL_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t STATUS; /*!< (@ 0x0000001C) Clock Generator Status */
|
|
|
|
struct {
|
|
__IOM uint32_t OMODE : 1; /*!< [0..0] Current RTC oscillator (1 => LFRC, 0 => XT) */
|
|
__IOM uint32_t OSCF : 1; /*!< [1..1] XT Oscillator is enabled but not oscillating */
|
|
} STATUS_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t HFADJ; /*!< (@ 0x00000020) HFRC Adjustment */
|
|
|
|
struct {
|
|
__IOM uint32_t HFADJEN : 1; /*!< [0..0] HFRC adjustment control */
|
|
__IOM uint32_t HFADJCK : 3; /*!< [3..1] Repeat period for HFRC adjustment */
|
|
__IM uint32_t : 4;
|
|
__IOM uint32_t HFXTADJ : 11; /*!< [18..8] Target HFRC adjustment value. */
|
|
__IOM uint32_t HFWARMUP : 1; /*!< [19..19] XT warmup period for HFRC adjustment */
|
|
} HFADJ_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t HFVAL; /*!< (@ 0x00000024) HFADJ readback */
|
|
|
|
struct {
|
|
__IOM uint32_t HFTUNERB : 11; /*!< [10..0] Current HFTUNE value */
|
|
} HFVAL_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t CLOCKEN; /*!< (@ 0x00000028) Clock Enable Status */
|
|
|
|
struct {
|
|
__IOM uint32_t CLOCKEN : 32; /*!< [31..0] Clock enable status */
|
|
} CLOCKEN_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t UARTEN; /*!< (@ 0x0000002C) UART Enable */
|
|
|
|
struct {
|
|
__IOM uint32_t UARTEN : 1; /*!< [0..0] UART system clock control */
|
|
} UARTEN_b;
|
|
} ;
|
|
__IM uint32_t RESERVED[52];
|
|
|
|
union {
|
|
__IOM uint32_t INTEN; /*!< (@ 0x00000100) CLKGEN Interrupt Register: Enable */
|
|
|
|
struct {
|
|
__IOM uint32_t ACF : 1; /*!< [0..0] Autocalibration Fail interrupt */
|
|
__IOM uint32_t ACC : 1; /*!< [1..1] Autocalibration Complete interrupt */
|
|
__IOM uint32_t OF : 1; /*!< [2..2] XT Oscillator Fail interrupt */
|
|
__IOM uint32_t ALM : 1; /*!< [3..3] RTC Alarm interrupt */
|
|
} INTEN_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t INTSTAT; /*!< (@ 0x00000104) CLKGEN Interrupt Register: Status */
|
|
|
|
struct {
|
|
__IOM uint32_t ACF : 1; /*!< [0..0] Autocalibration Fail interrupt */
|
|
__IOM uint32_t ACC : 1; /*!< [1..1] Autocalibration Complete interrupt */
|
|
__IOM uint32_t OF : 1; /*!< [2..2] XT Oscillator Fail interrupt */
|
|
__IOM uint32_t ALM : 1; /*!< [3..3] RTC Alarm interrupt */
|
|
} INTSTAT_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t INTCLR; /*!< (@ 0x00000108) CLKGEN Interrupt Register: Clear */
|
|
|
|
struct {
|
|
__IOM uint32_t ACF : 1; /*!< [0..0] Autocalibration Fail interrupt */
|
|
__IOM uint32_t ACC : 1; /*!< [1..1] Autocalibration Complete interrupt */
|
|
__IOM uint32_t OF : 1; /*!< [2..2] XT Oscillator Fail interrupt */
|
|
__IOM uint32_t ALM : 1; /*!< [3..3] RTC Alarm interrupt */
|
|
} INTCLR_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t INTSET; /*!< (@ 0x0000010C) CLKGEN Interrupt Register: Set */
|
|
|
|
struct {
|
|
__IOM uint32_t ACF : 1; /*!< [0..0] Autocalibration Fail interrupt */
|
|
__IOM uint32_t ACC : 1; /*!< [1..1] Autocalibration Complete interrupt */
|
|
__IOM uint32_t OF : 1; /*!< [2..2] XT Oscillator Fail interrupt */
|
|
__IOM uint32_t ALM : 1; /*!< [3..3] RTC Alarm interrupt */
|
|
} INTSET_b;
|
|
} ;
|
|
} CLKGEN_Type; /*!< Size = 272 (0x110) */
|
|
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ CTIMER ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/**
|
|
* @brief Counter/Timer (CTIMER)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x40008000) CTIMER Structure */
|
|
|
|
union {
|
|
__IOM uint32_t TMR0; /*!< (@ 0x00000000) Counter/Timer Register */
|
|
|
|
struct {
|
|
__IOM uint32_t CTTMRA0 : 16; /*!< [15..0] Counter/Timer A0. */
|
|
__IOM uint32_t CTTMRB0 : 16; /*!< [31..16] Counter/Timer B0. */
|
|
} TMR0_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t CMPRA0; /*!< (@ 0x00000004) Counter/Timer A0 Compare Registers */
|
|
|
|
struct {
|
|
__IOM uint32_t CMPR0A0 : 16; /*!< [15..0] Counter/Timer A0 Compare Register 0. Holds the lower
|
|
limit for timer half A. */
|
|
__IOM uint32_t CMPR1A0 : 16; /*!< [31..16] Counter/Timer A0 Compare Register 1. Holds the upper
|
|
limit for timer half A. */
|
|
} CMPRA0_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t CMPRB0; /*!< (@ 0x00000008) Counter/Timer B0 Compare Registers */
|
|
|
|
struct {
|
|
__IOM uint32_t CMPR0B0 : 16; /*!< [15..0] Counter/Timer B0 Compare Register 0. Holds the lower
|
|
limit for timer half B. */
|
|
__IOM uint32_t CMPR1B0 : 16; /*!< [31..16] Counter/Timer B0 Compare Register 1. Holds the upper
|
|
limit for timer half B. */
|
|
} CMPRB0_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t CTRL0; /*!< (@ 0x0000000C) Counter/Timer Control */
|
|
|
|
struct {
|
|
__IOM uint32_t TMRA0EN : 1; /*!< [0..0] Counter/Timer A0 Enable bit. */
|
|
__IOM uint32_t TMRA0CLK : 5; /*!< [5..1] Counter/Timer A0 Clock Select. */
|
|
__IOM uint32_t TMRA0FN : 3; /*!< [8..6] Counter/Timer A0 Function Select. */
|
|
__IOM uint32_t TMRA0IE : 1; /*!< [9..9] Counter/Timer A0 Interrupt Enable bit. */
|
|
__IOM uint32_t TMRA0PE : 1; /*!< [10..10] Counter/Timer A0 Output Enable bit. */
|
|
__IOM uint32_t TMRA0CLR : 1; /*!< [11..11] Counter/Timer A0 Clear bit. */
|
|
__IOM uint32_t TMRA0POL : 1; /*!< [12..12] Counter/Timer A0 output polarity. */
|
|
__IM uint32_t : 3;
|
|
__IOM uint32_t TMRB0EN : 1; /*!< [16..16] Counter/Timer B0 Enable bit. */
|
|
__IOM uint32_t TMRB0CLK : 5; /*!< [21..17] Counter/Timer B0 Clock Select. */
|
|
__IOM uint32_t TMRB0FN : 3; /*!< [24..22] Counter/Timer B0 Function Select. */
|
|
__IOM uint32_t TMRB0IE : 1; /*!< [25..25] Counter/Timer B0 Interrupt Enable bit. */
|
|
__IOM uint32_t TMRB0PE : 1; /*!< [26..26] Counter/Timer B0 Output Enable bit. */
|
|
__IOM uint32_t TMRB0CLR : 1; /*!< [27..27] Counter/Timer B0 Clear bit. */
|
|
__IOM uint32_t TMRB0POL : 1; /*!< [28..28] Counter/Timer B0 output polarity. */
|
|
__IM uint32_t : 2;
|
|
__IOM uint32_t CTLINK0 : 1; /*!< [31..31] Counter/Timer A0/B0 Link bit. */
|
|
} CTRL0_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t TMR1; /*!< (@ 0x00000010) Counter/Timer Register */
|
|
|
|
struct {
|
|
__IOM uint32_t CTTMRA1 : 16; /*!< [15..0] Counter/Timer A1. */
|
|
__IOM uint32_t CTTMRB1 : 16; /*!< [31..16] Counter/Timer B1. */
|
|
} TMR1_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t CMPRA1; /*!< (@ 0x00000014) Counter/Timer A1 Compare Registers */
|
|
|
|
struct {
|
|
__IOM uint32_t CMPR0A1 : 16; /*!< [15..0] Counter/Timer A1 Compare Register 0. */
|
|
__IOM uint32_t CMPR1A1 : 16; /*!< [31..16] Counter/Timer A1 Compare Register 1. */
|
|
} CMPRA1_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t CMPRB1; /*!< (@ 0x00000018) Counter/Timer B1 Compare Registers */
|
|
|
|
struct {
|
|
__IOM uint32_t CMPR0B1 : 16; /*!< [15..0] Counter/Timer B1 Compare Register 0. */
|
|
__IOM uint32_t CMPR1B1 : 16; /*!< [31..16] Counter/Timer B1 Compare Register 1. */
|
|
} CMPRB1_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t CTRL1; /*!< (@ 0x0000001C) Counter/Timer Control */
|
|
|
|
struct {
|
|
__IOM uint32_t TMRA1EN : 1; /*!< [0..0] Counter/Timer A1 Enable bit. */
|
|
__IOM uint32_t TMRA1CLK : 5; /*!< [5..1] Counter/Timer A1 Clock Select. */
|
|
__IOM uint32_t TMRA1FN : 3; /*!< [8..6] Counter/Timer A1 Function Select. */
|
|
__IOM uint32_t TMRA1IE : 1; /*!< [9..9] Counter/Timer A1 Interrupt Enable bit. */
|
|
__IOM uint32_t TMRA1PE : 1; /*!< [10..10] Counter/Timer A1 Output Enable bit. */
|
|
__IOM uint32_t TMRA1CLR : 1; /*!< [11..11] Counter/Timer A1 Clear bit. */
|
|
__IOM uint32_t TMRA1POL : 1; /*!< [12..12] Counter/Timer A1 output polarity. */
|
|
__IM uint32_t : 3;
|
|
__IOM uint32_t TMRB1EN : 1; /*!< [16..16] Counter/Timer B1 Enable bit. */
|
|
__IOM uint32_t TMRB1CLK : 5; /*!< [21..17] Counter/Timer B1 Clock Select. */
|
|
__IOM uint32_t TMRB1FN : 3; /*!< [24..22] Counter/Timer B1 Function Select. */
|
|
__IOM uint32_t TMRB1IE : 1; /*!< [25..25] Counter/Timer B1 Interrupt Enable bit. */
|
|
__IOM uint32_t TMRB1PE : 1; /*!< [26..26] Counter/Timer B1 Output Enable bit. */
|
|
__IOM uint32_t TMRB1CLR : 1; /*!< [27..27] Counter/Timer B1 Clear bit. */
|
|
__IOM uint32_t TMRB1POL : 1; /*!< [28..28] Counter/Timer B1 output polarity. */
|
|
__IM uint32_t : 2;
|
|
__IOM uint32_t CTLINK1 : 1; /*!< [31..31] Counter/Timer A1/B1 Link bit. */
|
|
} CTRL1_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t TMR2; /*!< (@ 0x00000020) Counter/Timer Register */
|
|
|
|
struct {
|
|
__IOM uint32_t CTTMRA2 : 16; /*!< [15..0] Counter/Timer A2. */
|
|
__IOM uint32_t CTTMRB2 : 16; /*!< [31..16] Counter/Timer B2. */
|
|
} TMR2_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t CMPRA2; /*!< (@ 0x00000024) Counter/Timer A2 Compare Registers */
|
|
|
|
struct {
|
|
__IOM uint32_t CMPR0A2 : 16; /*!< [15..0] Counter/Timer A2 Compare Register 0. */
|
|
__IOM uint32_t CMPR1A2 : 16; /*!< [31..16] Counter/Timer A2 Compare Register 1. */
|
|
} CMPRA2_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t CMPRB2; /*!< (@ 0x00000028) Counter/Timer B2 Compare Registers */
|
|
|
|
struct {
|
|
__IOM uint32_t CMPR0B2 : 16; /*!< [15..0] Counter/Timer B2 Compare Register 0. */
|
|
__IOM uint32_t CMPR1B2 : 16; /*!< [31..16] Counter/Timer B2 Compare Register 1. */
|
|
} CMPRB2_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t CTRL2; /*!< (@ 0x0000002C) Counter/Timer Control */
|
|
|
|
struct {
|
|
__IOM uint32_t TMRA2EN : 1; /*!< [0..0] Counter/Timer A2 Enable bit. */
|
|
__IOM uint32_t TMRA2CLK : 5; /*!< [5..1] Counter/Timer A2 Clock Select. */
|
|
__IOM uint32_t TMRA2FN : 3; /*!< [8..6] Counter/Timer A2 Function Select. */
|
|
__IOM uint32_t TMRA2IE : 1; /*!< [9..9] Counter/Timer A2 Interrupt Enable bit. */
|
|
__IOM uint32_t TMRA2PE : 1; /*!< [10..10] Counter/Timer A2 Output Enable bit. */
|
|
__IOM uint32_t TMRA2CLR : 1; /*!< [11..11] Counter/Timer A2 Clear bit. */
|
|
__IOM uint32_t TMRA2POL : 1; /*!< [12..12] Counter/Timer A2 output polarity. */
|
|
__IM uint32_t : 3;
|
|
__IOM uint32_t TMRB2EN : 1; /*!< [16..16] Counter/Timer B2 Enable bit. */
|
|
__IOM uint32_t TMRB2CLK : 5; /*!< [21..17] Counter/Timer B2 Clock Select. */
|
|
__IOM uint32_t TMRB2FN : 3; /*!< [24..22] Counter/Timer B2 Function Select. */
|
|
__IOM uint32_t TMRB2IE : 1; /*!< [25..25] Counter/Timer B2 Interrupt Enable bit. */
|
|
__IOM uint32_t TMRB2PE : 1; /*!< [26..26] Counter/Timer B2 Output Enable bit. */
|
|
__IOM uint32_t TMRB2CLR : 1; /*!< [27..27] Counter/Timer B2 Clear bit. */
|
|
__IOM uint32_t TMRB2POL : 1; /*!< [28..28] Counter/Timer B2 output polarity. */
|
|
__IM uint32_t : 2;
|
|
__IOM uint32_t CTLINK2 : 1; /*!< [31..31] Counter/Timer A2/B2 Link bit. */
|
|
} CTRL2_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t TMR3; /*!< (@ 0x00000030) Counter/Timer Register */
|
|
|
|
struct {
|
|
__IOM uint32_t CTTMRA3 : 16; /*!< [15..0] Counter/Timer A3. */
|
|
__IOM uint32_t CTTMRB3 : 16; /*!< [31..16] Counter/Timer B3. */
|
|
} TMR3_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t CMPRA3; /*!< (@ 0x00000034) Counter/Timer A3 Compare Registers */
|
|
|
|
struct {
|
|
__IOM uint32_t CMPR0A3 : 16; /*!< [15..0] Counter/Timer A3 Compare Register 0. */
|
|
__IOM uint32_t CMPR1A3 : 16; /*!< [31..16] Counter/Timer A3 Compare Register 1. */
|
|
} CMPRA3_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t CMPRB3; /*!< (@ 0x00000038) Counter/Timer B3 Compare Registers */
|
|
|
|
struct {
|
|
__IOM uint32_t CMPR0B3 : 16; /*!< [15..0] Counter/Timer B3 Compare Register 0. */
|
|
__IOM uint32_t CMPR1B3 : 16; /*!< [31..16] Counter/Timer B3 Compare Register 1. */
|
|
} CMPRB3_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t CTRL3; /*!< (@ 0x0000003C) Counter/Timer Control */
|
|
|
|
struct {
|
|
__IOM uint32_t TMRA3EN : 1; /*!< [0..0] Counter/Timer A3 Enable bit. */
|
|
__IOM uint32_t TMRA3CLK : 5; /*!< [5..1] Counter/Timer A3 Clock Select. */
|
|
__IOM uint32_t TMRA3FN : 3; /*!< [8..6] Counter/Timer A3 Function Select. */
|
|
__IOM uint32_t TMRA3IE : 1; /*!< [9..9] Counter/Timer A3 Interrupt Enable bit. */
|
|
__IOM uint32_t TMRA3PE : 1; /*!< [10..10] Counter/Timer A3 Output Enable bit. */
|
|
__IOM uint32_t TMRA3CLR : 1; /*!< [11..11] Counter/Timer A3 Clear bit. */
|
|
__IOM uint32_t TMRA3POL : 1; /*!< [12..12] Counter/Timer A3 output polarity. */
|
|
__IM uint32_t : 2;
|
|
__IOM uint32_t ADCEN : 1; /*!< [15..15] Special Timer A3 enable for ADC function. */
|
|
__IOM uint32_t TMRB3EN : 1; /*!< [16..16] Counter/Timer B3 Enable bit. */
|
|
__IOM uint32_t TMRB3CLK : 5; /*!< [21..17] Counter/Timer B3 Clock Select. */
|
|
__IOM uint32_t TMRB3FN : 3; /*!< [24..22] Counter/Timer B3 Function Select. */
|
|
__IOM uint32_t TMRB3IE : 1; /*!< [25..25] Counter/Timer B3 Interrupt Enable bit. */
|
|
__IOM uint32_t TMRB3PE : 1; /*!< [26..26] Counter/Timer B3 Output Enable bit. */
|
|
__IOM uint32_t TMRB3CLR : 1; /*!< [27..27] Counter/Timer B3 Clear bit. */
|
|
__IOM uint32_t TMRB3POL : 1; /*!< [28..28] Counter/Timer B3 output polarity. */
|
|
__IM uint32_t : 2;
|
|
__IOM uint32_t CTLINK3 : 1; /*!< [31..31] Counter/Timer A/B Link bit. */
|
|
} CTRL3_b;
|
|
} ;
|
|
__IM uint32_t RESERVED[112];
|
|
|
|
union {
|
|
__IOM uint32_t INTEN; /*!< (@ 0x00000200) Counter/Timer Interrupts: Enable */
|
|
|
|
struct {
|
|
__IOM uint32_t CTMRA0INT : 1; /*!< [0..0] Counter/Timer A0 interrupt. */
|
|
__IOM uint32_t CTMRB0INT : 1; /*!< [1..1] Counter/Timer B0 interrupt. */
|
|
__IOM uint32_t CTMRA1INT : 1; /*!< [2..2] Counter/Timer A1 interrupt. */
|
|
__IOM uint32_t CTMRB1INT : 1; /*!< [3..3] Counter/Timer B1 interrupt. */
|
|
__IOM uint32_t CTMRA2INT : 1; /*!< [4..4] Counter/Timer A2 interrupt. */
|
|
__IOM uint32_t CTMRB2INT : 1; /*!< [5..5] Counter/Timer B2 interrupt. */
|
|
__IOM uint32_t CTMRA3INT : 1; /*!< [6..6] Counter/Timer A3 interrupt. */
|
|
__IOM uint32_t CTMRB3INT : 1; /*!< [7..7] Counter/Timer B3 interrupt. */
|
|
} INTEN_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t INTSTAT; /*!< (@ 0x00000204) Counter/Timer Interrupts: Status */
|
|
|
|
struct {
|
|
__IOM uint32_t CTMRA0INT : 1; /*!< [0..0] Counter/Timer A0 interrupt. */
|
|
__IOM uint32_t CTMRB0INT : 1; /*!< [1..1] Counter/Timer B0 interrupt. */
|
|
__IOM uint32_t CTMRA1INT : 1; /*!< [2..2] Counter/Timer A1 interrupt. */
|
|
__IOM uint32_t CTMRB1INT : 1; /*!< [3..3] Counter/Timer B1 interrupt. */
|
|
__IOM uint32_t CTMRA2INT : 1; /*!< [4..4] Counter/Timer A2 interrupt. */
|
|
__IOM uint32_t CTMRB2INT : 1; /*!< [5..5] Counter/Timer B2 interrupt. */
|
|
__IOM uint32_t CTMRA3INT : 1; /*!< [6..6] Counter/Timer A3 interrupt. */
|
|
__IOM uint32_t CTMRB3INT : 1; /*!< [7..7] Counter/Timer B3 interrupt. */
|
|
} INTSTAT_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t INTCLR; /*!< (@ 0x00000208) Counter/Timer Interrupts: Clear */
|
|
|
|
struct {
|
|
__IOM uint32_t CTMRA0INT : 1; /*!< [0..0] Counter/Timer A0 interrupt. */
|
|
__IOM uint32_t CTMRB0INT : 1; /*!< [1..1] Counter/Timer B0 interrupt. */
|
|
__IOM uint32_t CTMRA1INT : 1; /*!< [2..2] Counter/Timer A1 interrupt. */
|
|
__IOM uint32_t CTMRB1INT : 1; /*!< [3..3] Counter/Timer B1 interrupt. */
|
|
__IOM uint32_t CTMRA2INT : 1; /*!< [4..4] Counter/Timer A2 interrupt. */
|
|
__IOM uint32_t CTMRB2INT : 1; /*!< [5..5] Counter/Timer B2 interrupt. */
|
|
__IOM uint32_t CTMRA3INT : 1; /*!< [6..6] Counter/Timer A3 interrupt. */
|
|
__IOM uint32_t CTMRB3INT : 1; /*!< [7..7] Counter/Timer B3 interrupt. */
|
|
} INTCLR_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t INTSET; /*!< (@ 0x0000020C) Counter/Timer Interrupts: Set */
|
|
|
|
struct {
|
|
__IOM uint32_t CTMRA0INT : 1; /*!< [0..0] Counter/Timer A0 interrupt. */
|
|
__IOM uint32_t CTMRB0INT : 1; /*!< [1..1] Counter/Timer B0 interrupt. */
|
|
__IOM uint32_t CTMRA1INT : 1; /*!< [2..2] Counter/Timer A1 interrupt. */
|
|
__IOM uint32_t CTMRB1INT : 1; /*!< [3..3] Counter/Timer B1 interrupt. */
|
|
__IOM uint32_t CTMRA2INT : 1; /*!< [4..4] Counter/Timer A2 interrupt. */
|
|
__IOM uint32_t CTMRB2INT : 1; /*!< [5..5] Counter/Timer B2 interrupt. */
|
|
__IOM uint32_t CTMRA3INT : 1; /*!< [6..6] Counter/Timer A3 interrupt. */
|
|
__IOM uint32_t CTMRB3INT : 1; /*!< [7..7] Counter/Timer B3 interrupt. */
|
|
} INTSET_b;
|
|
} ;
|
|
} CTIMER_Type; /*!< Size = 528 (0x210) */
|
|
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ GPIO ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/**
|
|
* @brief General Purpose IO (GPIO)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x40010000) GPIO Structure */
|
|
|
|
union {
|
|
__IOM uint32_t PADREGA; /*!< (@ 0x00000000) Pad Configuration Register A */
|
|
|
|
struct {
|
|
__IOM uint32_t PAD0PULL : 1; /*!< [0..0] Pad 0 pullup enable */
|
|
__IOM uint32_t PAD0INPEN : 1; /*!< [1..1] Pad 0 input enable */
|
|
__IOM uint32_t PAD0STRNG : 1; /*!< [2..2] Pad 0 drive strength */
|
|
__IOM uint32_t PAD0FNCSEL : 3; /*!< [5..3] Pad 0 function select */
|
|
__IM uint32_t : 2;
|
|
__IOM uint32_t PAD1PULL : 1; /*!< [8..8] Pad 1 pullup enable */
|
|
__IOM uint32_t PAD1INPEN : 1; /*!< [9..9] Pad 1 input enable */
|
|
__IOM uint32_t PAD1STRNG : 1; /*!< [10..10] Pad 1 drive strength */
|
|
__IOM uint32_t PAD1FNCSEL : 3; /*!< [13..11] Pad 1 function select */
|
|
__IM uint32_t : 2;
|
|
__IOM uint32_t PAD2PULL : 1; /*!< [16..16] Pad 2 pullup enable */
|
|
__IOM uint32_t PAD2INPEN : 1; /*!< [17..17] Pad 2 input enable */
|
|
__IOM uint32_t PAD2STRNG : 1; /*!< [18..18] Pad 2 drive strength */
|
|
__IOM uint32_t PAD2FNCSEL : 3; /*!< [21..19] Pad 2 function select */
|
|
__IM uint32_t : 2;
|
|
__IOM uint32_t PAD3PULL : 1; /*!< [24..24] Pad 3 pullup enable */
|
|
__IOM uint32_t PAD3INPEN : 1; /*!< [25..25] Pad 3 input enable. */
|
|
__IOM uint32_t PAD3STRNG : 1; /*!< [26..26] Pad 3 drive strength. */
|
|
__IOM uint32_t PAD3FNCSEL : 3; /*!< [29..27] Pad 3 function select */
|
|
__IM uint32_t : 1;
|
|
__IOM uint32_t PAD3PWRUP : 1; /*!< [31..31] Pad 3 upper power switch enable */
|
|
} PADREGA_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t PADREGB; /*!< (@ 0x00000004) Pad Configuration Register B */
|
|
|
|
struct {
|
|
__IOM uint32_t PAD4PULL : 1; /*!< [0..0] Pad 4 pullup enable */
|
|
__IOM uint32_t PAD4INPEN : 1; /*!< [1..1] Pad 4 input enable */
|
|
__IOM uint32_t PAD4STRNG : 1; /*!< [2..2] Pad 4 drive strength */
|
|
__IOM uint32_t PAD4FNCSEL : 3; /*!< [5..3] Pad 4 function select */
|
|
__IM uint32_t : 1;
|
|
__IOM uint32_t PAD4PWRUP : 1; /*!< [7..7] Pad 4 upper power switch enable */
|
|
__IOM uint32_t PAD5PULL : 1; /*!< [8..8] Pad 5 pullup enable */
|
|
__IOM uint32_t PAD5INPEN : 1; /*!< [9..9] Pad 5 input enable */
|
|
__IOM uint32_t PAD5STRNG : 1; /*!< [10..10] Pad 5 drive strength */
|
|
__IOM uint32_t PAD5FNCSEL : 3; /*!< [13..11] Pad 5 function select */
|
|
__IOM uint32_t PAD5RSEL : 2; /*!< [15..14] Pad 5 pullup resistor selection. */
|
|
__IOM uint32_t PAD6PULL : 1; /*!< [16..16] Pad 6 pullup enable */
|
|
__IOM uint32_t PAD6INPEN : 1; /*!< [17..17] Pad 6 input enable */
|
|
__IOM uint32_t PAD6STRNG : 1; /*!< [18..18] Pad 6 drive strength */
|
|
__IOM uint32_t PAD6FNCSEL : 3; /*!< [21..19] Pad 6 function select */
|
|
__IOM uint32_t PAD6RSEL : 2; /*!< [23..22] Pad 6 pullup resistor selection. */
|
|
__IOM uint32_t PAD7PULL : 1; /*!< [24..24] Pad 7 pullup enable */
|
|
__IOM uint32_t PAD7INPEN : 1; /*!< [25..25] Pad 7 input enable */
|
|
__IOM uint32_t PAD7STRNG : 1; /*!< [26..26] Pad 7 drive strentgh */
|
|
__IOM uint32_t PAD7FNCSEL : 3; /*!< [29..27] Pad 7 function select */
|
|
} PADREGB_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t PADREGC; /*!< (@ 0x00000008) Pad Configuration Register C */
|
|
|
|
struct {
|
|
__IOM uint32_t PAD8PULL : 1; /*!< [0..0] Pad 8 pullup enable */
|
|
__IOM uint32_t PAD8INPEN : 1; /*!< [1..1] Pad 8 input enable */
|
|
__IOM uint32_t PAD8STRNG : 1; /*!< [2..2] Pad 8 drive strength */
|
|
__IOM uint32_t PAD8FNCSEL : 3; /*!< [5..3] Pad 8 function select */
|
|
__IOM uint32_t PAD8RSEL : 2; /*!< [7..6] Pad 8 pullup resistor selection. */
|
|
__IOM uint32_t PAD9PULL : 1; /*!< [8..8] Pad 9 pullup enable */
|
|
__IOM uint32_t PAD9INPEN : 1; /*!< [9..9] Pad 9 input enable */
|
|
__IOM uint32_t PAD9STRNG : 1; /*!< [10..10] Pad 9 drive strength */
|
|
__IOM uint32_t PAD9FNCSEL : 3; /*!< [13..11] Pad 9 function select */
|
|
__IOM uint32_t PAD9RSEL : 2; /*!< [15..14] Pad 9 pullup resistor selection */
|
|
__IOM uint32_t PAD10PULL : 1; /*!< [16..16] Pad 10 pullup enable */
|
|
__IOM uint32_t PAD10INPEN : 1; /*!< [17..17] Pad 10 input enable */
|
|
__IOM uint32_t PAD10STRNG : 1; /*!< [18..18] Pad 10 drive strength */
|
|
__IOM uint32_t PAD10FNCSEL : 3; /*!< [21..19] Pad 10 function select */
|
|
__IM uint32_t : 2;
|
|
__IOM uint32_t PAD11PULL : 1; /*!< [24..24] Pad 11 pullup enable */
|
|
__IOM uint32_t PAD11INPEN : 1; /*!< [25..25] Pad 11 input enable */
|
|
__IOM uint32_t PAD11STRNG : 1; /*!< [26..26] Pad 11 drive strentgh */
|
|
__IOM uint32_t PAD11FNCSEL : 2; /*!< [28..27] Pad 11 function select */
|
|
__IM uint32_t : 1;
|
|
__IOM uint32_t PAD11PWRDN : 1; /*!< [30..30] Pad 11 lower power switch enable */
|
|
} PADREGC_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t PADREGD; /*!< (@ 0x0000000C) Pad Configuration Register D */
|
|
|
|
struct {
|
|
__IOM uint32_t PAD12PULL : 1; /*!< [0..0] Pad 12 pullup enable */
|
|
__IOM uint32_t PAD12INPEN : 1; /*!< [1..1] Pad 12 input enable */
|
|
__IOM uint32_t PAD12STRNG : 1; /*!< [2..2] Pad 12 drive strength */
|
|
__IOM uint32_t PAD12FNCSEL : 2; /*!< [4..3] Pad 12 function select */
|
|
__IM uint32_t : 3;
|
|
__IOM uint32_t PAD13PULL : 1; /*!< [8..8] Pad 13 pullup enable */
|
|
__IOM uint32_t PAD13INPEN : 1; /*!< [9..9] Pad 13 input enable */
|
|
__IOM uint32_t PAD13STRNG : 1; /*!< [10..10] Pad 13 drive strength */
|
|
__IOM uint32_t PAD13FNCSEL : 3; /*!< [13..11] Pad 13 function select */
|
|
__IM uint32_t : 2;
|
|
__IOM uint32_t PAD14PULL : 1; /*!< [16..16] Pad 14 pullup enable */
|
|
__IOM uint32_t PAD14INPEN : 1; /*!< [17..17] Pad 14 input enable */
|
|
__IOM uint32_t PAD14STRNG : 1; /*!< [18..18] Pad 14 drive strength */
|
|
__IOM uint32_t PAD14FNCSEL : 3; /*!< [21..19] Pad 14 function select */
|
|
__IM uint32_t : 2;
|
|
__IOM uint32_t PAD15PULL : 1; /*!< [24..24] Pad 15 pullup enable */
|
|
__IOM uint32_t PAD15INPEN : 1; /*!< [25..25] Pad 15 input enable */
|
|
__IOM uint32_t PAD15STRNG : 1; /*!< [26..26] Pad 15 drive strentgh */
|
|
__IOM uint32_t PAD15FNCSEL : 3; /*!< [29..27] Pad 15 function select */
|
|
} PADREGD_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t PADREGE; /*!< (@ 0x00000010) Pad Configuration Register E */
|
|
|
|
struct {
|
|
__IOM uint32_t PAD16PULL : 1; /*!< [0..0] Pad 16 pullup enable */
|
|
__IOM uint32_t PAD16INPEN : 1; /*!< [1..1] Pad 16 input enable */
|
|
__IOM uint32_t PAD16STRNG : 1; /*!< [2..2] Pad 16 drive strength */
|
|
__IOM uint32_t PAD16FNCSEL : 2; /*!< [4..3] Pad 16 function select */
|
|
__IM uint32_t : 3;
|
|
__IOM uint32_t PAD17PULL : 1; /*!< [8..8] Pad 17 pullup enable */
|
|
__IOM uint32_t PAD17INPEN : 1; /*!< [9..9] Pad 17 input enable */
|
|
__IOM uint32_t PAD17STRNG : 1; /*!< [10..10] Pad 17 drive strength */
|
|
__IOM uint32_t PAD17FNCSEL : 3; /*!< [13..11] Pad 17 function select */
|
|
__IM uint32_t : 2;
|
|
__IOM uint32_t PAD18PULL : 1; /*!< [16..16] Pad 18 pullup enable */
|
|
__IOM uint32_t PAD18INPEN : 1; /*!< [17..17] Pad 18 input enable */
|
|
__IOM uint32_t PAD18STRNG : 1; /*!< [18..18] Pad 18 drive strength */
|
|
__IOM uint32_t PAD18FNCSEL : 2; /*!< [20..19] Pad 18 function select */
|
|
__IM uint32_t : 3;
|
|
__IOM uint32_t PAD19PULL : 1; /*!< [24..24] Pad 19 pullup enable */
|
|
__IOM uint32_t PAD19INPEN : 1; /*!< [25..25] Pad 19 input enable */
|
|
__IOM uint32_t PAD19STRNG : 1; /*!< [26..26] Pad 19 drive strentgh */
|
|
__IOM uint32_t PAD19FNCSEL : 2; /*!< [28..27] Pad 19 function select */
|
|
} PADREGE_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t PADREGF; /*!< (@ 0x00000014) Pad Configuration Register F */
|
|
|
|
struct {
|
|
__IOM uint32_t PAD20PULL : 1; /*!< [0..0] Pad 20 pulldown enable */
|
|
__IOM uint32_t PAD20INPEN : 1; /*!< [1..1] Pad 20 input enable */
|
|
__IOM uint32_t PAD20STRNG : 1; /*!< [2..2] Pad 20 drive strength */
|
|
__IOM uint32_t PAD20FNCSEL : 2; /*!< [4..3] Pad 20 function select */
|
|
__IM uint32_t : 3;
|
|
__IOM uint32_t PAD21PULL : 1; /*!< [8..8] Pad 21 pullup enable */
|
|
__IOM uint32_t PAD21INPEN : 1; /*!< [9..9] Pad 21 input enable */
|
|
__IOM uint32_t PAD21STRNG : 1; /*!< [10..10] Pad 21 drive strength */
|
|
__IOM uint32_t PAD21FNCSEL : 2; /*!< [12..11] Pad 21 function select */
|
|
__IM uint32_t : 3;
|
|
__IOM uint32_t PAD22PULL : 1; /*!< [16..16] Pad 22 pullup enable */
|
|
__IOM uint32_t PAD22INPEN : 1; /*!< [17..17] Pad 22 input enable */
|
|
__IOM uint32_t PAD22STRNG : 1; /*!< [18..18] Pad 22 drive strength */
|
|
__IOM uint32_t PAD22FNCSEL : 2; /*!< [20..19] Pad 22 function select */
|
|
__IM uint32_t : 3;
|
|
__IOM uint32_t PAD23PULL : 1; /*!< [24..24] Pad 23 pullup enable */
|
|
__IOM uint32_t PAD23INPEN : 1; /*!< [25..25] Pad 23 input enable */
|
|
__IOM uint32_t PAD23STRNG : 1; /*!< [26..26] Pad 23 drive strentgh */
|
|
__IOM uint32_t PAD23FNCSEL : 2; /*!< [28..27] Pad 23 function select */
|
|
} PADREGF_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t PADREGG; /*!< (@ 0x00000018) Pad Configuration Register G */
|
|
|
|
struct {
|
|
__IOM uint32_t PAD24PULL : 1; /*!< [0..0] Pad 24 pullup enable */
|
|
__IOM uint32_t PAD24INPEN : 1; /*!< [1..1] Pad 24 input enable */
|
|
__IOM uint32_t PAD24STRNG : 1; /*!< [2..2] Pad 24 drive strength */
|
|
__IOM uint32_t PAD24FNCSEL : 2; /*!< [4..3] Pad 24 function select */
|
|
__IM uint32_t : 3;
|
|
__IOM uint32_t PAD25PULL : 1; /*!< [8..8] Pad 25 pullup enable */
|
|
__IOM uint32_t PAD25INPEN : 1; /*!< [9..9] Pad 25 input enable */
|
|
__IOM uint32_t PAD25STRNG : 1; /*!< [10..10] Pad 25 drive strength */
|
|
__IOM uint32_t PAD25FNCSEL : 2; /*!< [12..11] Pad 25 function select */
|
|
__IM uint32_t : 3;
|
|
__IOM uint32_t PAD26PULL : 1; /*!< [16..16] Pad 26 pullup enable */
|
|
__IOM uint32_t PAD26INPEN : 1; /*!< [17..17] Pad 26 input enable */
|
|
__IOM uint32_t PAD26STRNG : 1; /*!< [18..18] Pad 26 drive strength */
|
|
__IOM uint32_t PAD26FNCSEL : 2; /*!< [20..19] Pad 26 function select */
|
|
__IM uint32_t : 3;
|
|
__IOM uint32_t PAD27PULL : 1; /*!< [24..24] Pad 27 pullup enable */
|
|
__IOM uint32_t PAD27INPEN : 1; /*!< [25..25] Pad 27 input enable */
|
|
__IOM uint32_t PAD27STRNG : 1; /*!< [26..26] Pad 27 drive strentgh */
|
|
__IOM uint32_t PAD27FNCSEL : 2; /*!< [28..27] Pad 27 function select */
|
|
} PADREGG_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t PADREGH; /*!< (@ 0x0000001C) Pad Configuration Register H */
|
|
|
|
struct {
|
|
__IOM uint32_t PAD28PULL : 1; /*!< [0..0] Pad 28 pullup enable */
|
|
__IOM uint32_t PAD28INPEN : 1; /*!< [1..1] Pad 28 input enable */
|
|
__IOM uint32_t PAD28STRNG : 1; /*!< [2..2] Pad 28 drive strength */
|
|
__IOM uint32_t PAD28FNCSEL : 2; /*!< [4..3] Pad 28 function select */
|
|
__IM uint32_t : 3;
|
|
__IOM uint32_t PAD29PULL : 1; /*!< [8..8] Pad 29 pullup enable */
|
|
__IOM uint32_t PAD29INPEN : 1; /*!< [9..9] Pad 29 input enable */
|
|
__IOM uint32_t PAD29STRNG : 1; /*!< [10..10] Pad 29 drive strength */
|
|
__IOM uint32_t PAD29FNCSEL : 2; /*!< [12..11] Pad 29 function select */
|
|
__IM uint32_t : 3;
|
|
__IOM uint32_t PAD30PULL : 1; /*!< [16..16] Pad 30 pullup enable */
|
|
__IOM uint32_t PAD30INPEN : 1; /*!< [17..17] Pad 30 input enable */
|
|
__IOM uint32_t PAD30STRNG : 1; /*!< [18..18] Pad 30 drive strength */
|
|
__IOM uint32_t PAD30FNCSEL : 2; /*!< [20..19] Pad 30 function select */
|
|
__IM uint32_t : 3;
|
|
__IOM uint32_t PAD31PULL : 1; /*!< [24..24] Pad 31 pullup enable */
|
|
__IOM uint32_t PAD31INPEN : 1; /*!< [25..25] Pad 31 input enable */
|
|
__IOM uint32_t PAD31STRNG : 1; /*!< [26..26] Pad 31 drive strentgh */
|
|
__IOM uint32_t PAD31FNCSEL : 2; /*!< [28..27] Pad 31 function select */
|
|
} PADREGH_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t PADREGI; /*!< (@ 0x00000020) Pad Configuration Register I */
|
|
|
|
struct {
|
|
__IOM uint32_t PAD32PULL : 1; /*!< [0..0] Pad 32 pullup enable */
|
|
__IOM uint32_t PAD32INPEN : 1; /*!< [1..1] Pad 32 input enable */
|
|
__IOM uint32_t PAD32STRNG : 1; /*!< [2..2] Pad 32 drive strength */
|
|
__IOM uint32_t PAD32FNCSEL : 2; /*!< [4..3] Pad 32 function select */
|
|
__IM uint32_t : 3;
|
|
__IOM uint32_t PAD33PULL : 1; /*!< [8..8] Pad 33 pullup enable */
|
|
__IOM uint32_t PAD33INPEN : 1; /*!< [9..9] Pad 33 input enable */
|
|
__IOM uint32_t PAD33STRNG : 1; /*!< [10..10] Pad 33 drive strength */
|
|
__IOM uint32_t PAD33FNCSEL : 2; /*!< [12..11] Pad 33 function select */
|
|
__IM uint32_t : 3;
|
|
__IOM uint32_t PAD34PULL : 1; /*!< [16..16] Pad 34 pullup enable */
|
|
__IOM uint32_t PAD34INPEN : 1; /*!< [17..17] Pad 34 input enable */
|
|
__IOM uint32_t PAD34STRNG : 1; /*!< [18..18] Pad 34 drive strength */
|
|
__IOM uint32_t PAD34FNCSEL : 2; /*!< [20..19] Pad 34 function select */
|
|
__IM uint32_t : 3;
|
|
__IOM uint32_t PAD35PULL : 1; /*!< [24..24] Pad 35 pullup enable */
|
|
__IOM uint32_t PAD35INPEN : 1; /*!< [25..25] Pad 35 input enable */
|
|
__IOM uint32_t PAD35STRNG : 1; /*!< [26..26] Pad 35 drive strentgh */
|
|
__IOM uint32_t PAD35FNCSEL : 2; /*!< [28..27] Pad 35 function select */
|
|
} PADREGI_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t PADREGJ; /*!< (@ 0x00000024) Pad Configuration Register J */
|
|
|
|
struct {
|
|
__IOM uint32_t PAD36PULL : 1; /*!< [0..0] Pad 36 pullup enable */
|
|
__IOM uint32_t PAD36INPEN : 1; /*!< [1..1] Pad 36 input enable */
|
|
__IOM uint32_t PAD36STRNG : 1; /*!< [2..2] Pad 36 drive strength */
|
|
__IOM uint32_t PAD36FNCSEL : 2; /*!< [4..3] Pad 36 function select */
|
|
__IM uint32_t : 3;
|
|
__IOM uint32_t PAD37PULL : 1; /*!< [8..8] Pad 37 pullup enable */
|
|
__IOM uint32_t PAD37INPEN : 1; /*!< [9..9] Pad 37 input enable */
|
|
__IOM uint32_t PAD37STRNG : 1; /*!< [10..10] Pad 37 drive strength */
|
|
__IOM uint32_t PAD37FNCSEL : 2; /*!< [12..11] Pad 37 function select */
|
|
__IM uint32_t : 3;
|
|
__IOM uint32_t PAD38PULL : 1; /*!< [16..16] Pad 38 pullup enable */
|
|
__IOM uint32_t PAD38INPEN : 1; /*!< [17..17] Pad 38 input enable */
|
|
__IOM uint32_t PAD38STRNG : 1; /*!< [18..18] Pad 38 drive strength */
|
|
__IOM uint32_t PAD38FNCSEL : 2; /*!< [20..19] Pad 38 function select */
|
|
__IM uint32_t : 3;
|
|
__IOM uint32_t PAD39PULL : 1; /*!< [24..24] Pad 39 pullup enable */
|
|
__IOM uint32_t PAD39INPEN : 1; /*!< [25..25] Pad 39 input enable */
|
|
__IOM uint32_t PAD39STRNG : 1; /*!< [26..26] Pad 39 drive strentgh */
|
|
__IOM uint32_t PAD39FNCSEL : 2; /*!< [28..27] Pad 39 function select */
|
|
} PADREGJ_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t PADREGK; /*!< (@ 0x00000028) Pad Configuration Register K */
|
|
|
|
struct {
|
|
__IOM uint32_t PAD40PULL : 1; /*!< [0..0] Pad 40 pullup enable */
|
|
__IOM uint32_t PAD40INPEN : 1; /*!< [1..1] Pad 40 input enable */
|
|
__IOM uint32_t PAD40STRNG : 1; /*!< [2..2] Pad 40 drive strength */
|
|
__IOM uint32_t PAD40FNCSEL : 2; /*!< [4..3] Pad 40 function select */
|
|
__IM uint32_t : 3;
|
|
__IOM uint32_t PAD41PULL : 1; /*!< [8..8] Pad 41 pullup enable */
|
|
__IOM uint32_t PAD41INPEN : 1; /*!< [9..9] Pad 41 input enable */
|
|
__IOM uint32_t PAD41STRNG : 1; /*!< [10..10] Pad 41 drive strength */
|
|
__IOM uint32_t PAD41FNCSEL : 2; /*!< [12..11] Pad 41 function select */
|
|
__IM uint32_t : 3;
|
|
__IOM uint32_t PAD42PULL : 1; /*!< [16..16] Pad 42 pullup enable */
|
|
__IOM uint32_t PAD42INPEN : 1; /*!< [17..17] Pad 42 input enable */
|
|
__IOM uint32_t PAD42STRNG : 1; /*!< [18..18] Pad 42 drive strength */
|
|
__IOM uint32_t PAD42FNCSEL : 2; /*!< [20..19] Pad 42 function select */
|
|
__IM uint32_t : 3;
|
|
__IOM uint32_t PAD43PULL : 1; /*!< [24..24] Pad 43 pullup enable */
|
|
__IOM uint32_t PAD43INPEN : 1; /*!< [25..25] Pad 43 input enable */
|
|
__IOM uint32_t PAD43STRNG : 1; /*!< [26..26] Pad 43 drive strentgh */
|
|
__IOM uint32_t PAD43FNCSEL : 2; /*!< [28..27] Pad 43 function select */
|
|
} PADREGK_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t PADREGL; /*!< (@ 0x0000002C) Pad Configuration Register L */
|
|
|
|
struct {
|
|
__IOM uint32_t PAD44PULL : 1; /*!< [0..0] Pad 44 pullup enable */
|
|
__IOM uint32_t PAD44INPEN : 1; /*!< [1..1] Pad 44 input enable */
|
|
__IOM uint32_t PAD44STRNG : 1; /*!< [2..2] Pad 44 drive strength */
|
|
__IOM uint32_t PAD44FNCSEL : 2; /*!< [4..3] Pad 44 function select */
|
|
__IM uint32_t : 3;
|
|
__IOM uint32_t PAD45PULL : 1; /*!< [8..8] Pad 45 pullup enable */
|
|
__IOM uint32_t PAD45INPEN : 1; /*!< [9..9] Pad 45 input enable */
|
|
__IOM uint32_t PAD45STRNG : 1; /*!< [10..10] Pad 45 drive strength */
|
|
__IOM uint32_t PAD45FNCSEL : 2; /*!< [12..11] Pad 45 function select */
|
|
__IM uint32_t : 3;
|
|
__IOM uint32_t PAD46PULL : 1; /*!< [16..16] Pad 46 pullup enable */
|
|
__IOM uint32_t PAD46INPEN : 1; /*!< [17..17] Pad 46 input enable */
|
|
__IOM uint32_t PAD46STRNG : 1; /*!< [18..18] Pad 46 drive strength */
|
|
__IOM uint32_t PAD46FNCSEL : 2; /*!< [20..19] Pad 46 function select */
|
|
__IM uint32_t : 3;
|
|
__IOM uint32_t PAD47PULL : 1; /*!< [24..24] Pad 47 pullup enable */
|
|
__IOM uint32_t PAD47INPEN : 1; /*!< [25..25] Pad 47 input enable */
|
|
__IOM uint32_t PAD47STRNG : 1; /*!< [26..26] Pad 47 drive strentgh */
|
|
__IOM uint32_t PAD47FNCSEL : 2; /*!< [28..27] Pad 47 function select */
|
|
} PADREGL_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t PADREGM; /*!< (@ 0x00000030) Pad Configuration Register M */
|
|
|
|
struct {
|
|
__IOM uint32_t PAD48PULL : 1; /*!< [0..0] Pad 48 pullup enable */
|
|
__IOM uint32_t PAD48INPEN : 1; /*!< [1..1] Pad 48 input enable */
|
|
__IOM uint32_t PAD48STRNG : 1; /*!< [2..2] Pad 48 drive strength */
|
|
__IOM uint32_t PAD48FNCSEL : 2; /*!< [4..3] Pad 48 function select */
|
|
__IM uint32_t : 3;
|
|
__IOM uint32_t PAD49PULL : 1; /*!< [8..8] Pad 49 pullup enable */
|
|
__IOM uint32_t PAD49INPEN : 1; /*!< [9..9] Pad 49 input enable */
|
|
__IOM uint32_t PAD49STRNG : 1; /*!< [10..10] Pad 49 drive strength */
|
|
__IOM uint32_t PAD49FNCSEL : 2; /*!< [12..11] Pad 49 function select */
|
|
} PADREGM_b;
|
|
} ;
|
|
__IM uint32_t RESERVED[3];
|
|
|
|
union {
|
|
__IOM uint32_t CFGA; /*!< (@ 0x00000040) GPIO Configuration Register A */
|
|
|
|
struct {
|
|
__IOM uint32_t GPIO0INCFG : 1; /*!< [0..0] GPIO0 input enable. */
|
|
__IOM uint32_t GPIO0OUTCFG : 2; /*!< [2..1] GPIO0 output configuration. */
|
|
__IOM uint32_t GPIO0INTD : 1; /*!< [3..3] GPIO0 interrupt direction. */
|
|
__IOM uint32_t GPIO1INCFG : 1; /*!< [4..4] GPIO1 input enable. */
|
|
__IOM uint32_t GPIO1OUTCFG : 2; /*!< [6..5] GPIO1 output configuration. */
|
|
__IOM uint32_t GPIO1INTD : 1; /*!< [7..7] GPIO1 interrupt direction. */
|
|
__IOM uint32_t GPIO2INCFG : 1; /*!< [8..8] GPIO2 input enable. */
|
|
__IOM uint32_t GPIO2OUTCFG : 2; /*!< [10..9] GPIO2 output configuration. */
|
|
__IOM uint32_t GPIO2INTD : 1; /*!< [11..11] GPIO2 interrupt direction. */
|
|
__IOM uint32_t GPIO3INCFG : 1; /*!< [12..12] GPIO3 input enable. */
|
|
__IOM uint32_t GPIO3OUTCFG : 2; /*!< [14..13] GPIO3 output configuration. */
|
|
__IOM uint32_t GPIO3INTD : 1; /*!< [15..15] GPIO3 interrupt direction. */
|
|
__IOM uint32_t GPIO4INCFG : 1; /*!< [16..16] GPIO4 input enable. */
|
|
__IOM uint32_t GPIO4OUTCFG : 2; /*!< [18..17] GPIO4 output configuration. */
|
|
__IOM uint32_t GPIO4INTD : 1; /*!< [19..19] GPIO4 interrupt direction. */
|
|
__IOM uint32_t GPIO5INCFG : 1; /*!< [20..20] GPIO5 input enable. */
|
|
__IOM uint32_t GPIO5OUTCFG : 2; /*!< [22..21] GPIO5 output configuration. */
|
|
__IOM uint32_t GPIO5INTD : 1; /*!< [23..23] GPIO5 interrupt direction. */
|
|
__IOM uint32_t GPIO6INCFG : 1; /*!< [24..24] GPIO6 input enable. */
|
|
__IOM uint32_t GPIO6OUTCFG : 2; /*!< [26..25] GPIO6 output configuration. */
|
|
__IOM uint32_t GPIO6INTD : 1; /*!< [27..27] GPIO6 interrupt direction. */
|
|
__IOM uint32_t GPIO7INCFG : 1; /*!< [28..28] GPIO7 input enable. */
|
|
__IOM uint32_t GPIO7OUTCFG : 2; /*!< [30..29] GPIO7 output configuration. */
|
|
__IOM uint32_t GPIO7INTD : 1; /*!< [31..31] GPIO7 interrupt direction. */
|
|
} CFGA_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t CFGB; /*!< (@ 0x00000044) GPIO Configuration Register B */
|
|
|
|
struct {
|
|
__IOM uint32_t GPIO8INCFG : 1; /*!< [0..0] GPIO8 input enable. */
|
|
__IOM uint32_t GPIO8OUTCFG : 2; /*!< [2..1] GPIO8 output configuration. */
|
|
__IOM uint32_t GPIO8INTD : 1; /*!< [3..3] GPIO8 interrupt direction. */
|
|
__IOM uint32_t GPIO9INCFG : 1; /*!< [4..4] GPIO9 input enable. */
|
|
__IOM uint32_t GPIO9OUTCFG : 2; /*!< [6..5] GPIO9 output configuration. */
|
|
__IOM uint32_t GPIO9INTD : 1; /*!< [7..7] GPIO9 interrupt direction. */
|
|
__IOM uint32_t GPIO10INCFG : 1; /*!< [8..8] GPIO10 input enable. */
|
|
__IOM uint32_t GPIO10OUTCFG : 2; /*!< [10..9] GPIO10 output configuration. */
|
|
__IOM uint32_t GPIO10INTD : 1; /*!< [11..11] GPIO10 interrupt direction. */
|
|
__IOM uint32_t GPIO11INCFG : 1; /*!< [12..12] GPIO11 input enable. */
|
|
__IOM uint32_t GPIO11OUTCFG : 2; /*!< [14..13] GPIO11 output configuration. */
|
|
__IOM uint32_t GPIO11INTD : 1; /*!< [15..15] GPIO11 interrupt direction. */
|
|
__IOM uint32_t GPIO12INCFG : 1; /*!< [16..16] GPIO12 input enable. */
|
|
__IOM uint32_t GPIO12OUTCFG : 2; /*!< [18..17] GPIO12 output configuration. */
|
|
__IOM uint32_t GPIO12INTD : 1; /*!< [19..19] GPIO12 interrupt direction. */
|
|
__IOM uint32_t GPIO13INCFG : 1; /*!< [20..20] GPIO13 input enable. */
|
|
__IOM uint32_t GPIO13OUTCFG : 2; /*!< [22..21] GPIO13 output configuration. */
|
|
__IOM uint32_t GPIO13INTD : 1; /*!< [23..23] GPIO13 interrupt direction. */
|
|
__IOM uint32_t GPIO14INCFG : 1; /*!< [24..24] GPIO14 input enable. */
|
|
__IOM uint32_t GPIO14OUTCFG : 2; /*!< [26..25] GPIO14 output configuration. */
|
|
__IOM uint32_t GPIO14INTD : 1; /*!< [27..27] GPIO14 interrupt direction. */
|
|
__IOM uint32_t GPIO15INCFG : 1; /*!< [28..28] GPIO15 input enable. */
|
|
__IOM uint32_t GPIO15OUTCFG : 2; /*!< [30..29] GPIO15 output configuration. */
|
|
__IOM uint32_t GPIO15INTD : 1; /*!< [31..31] GPIO15 interrupt direction. */
|
|
} CFGB_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t CFGC; /*!< (@ 0x00000048) GPIO Configuration Register C */
|
|
|
|
struct {
|
|
__IOM uint32_t GPIO16INCFG : 1; /*!< [0..0] GPIO16 input enable. */
|
|
__IOM uint32_t GPIO16OUTCFG : 2; /*!< [2..1] GPIO16 output configuration. */
|
|
__IOM uint32_t GPIO16INTD : 1; /*!< [3..3] GPIO16 interrupt direction. */
|
|
__IOM uint32_t GPIO17INCFG : 1; /*!< [4..4] GPIO17 input enable. */
|
|
__IOM uint32_t GPIO17OUTCFG : 2; /*!< [6..5] GPIO17 output configuration. */
|
|
__IOM uint32_t GPIO17INTD : 1; /*!< [7..7] GPIO17 interrupt direction. */
|
|
__IOM uint32_t GPIO18INCFG : 1; /*!< [8..8] GPIO18 input enable. */
|
|
__IOM uint32_t GPIO18OUTCFG : 2; /*!< [10..9] GPIO18 output configuration. */
|
|
__IOM uint32_t GPIO18INTD : 1; /*!< [11..11] GPIO18 interrupt direction. */
|
|
__IOM uint32_t GPIO19INCFG : 1; /*!< [12..12] GPIO19 input enable. */
|
|
__IOM uint32_t GPIO19OUTCFG : 2; /*!< [14..13] GPIO19 output configuration. */
|
|
__IOM uint32_t GPIO19INTD : 1; /*!< [15..15] GPIO19 interrupt direction. */
|
|
__IOM uint32_t GPIO20INCFG : 1; /*!< [16..16] GPIO20 input enable. */
|
|
__IOM uint32_t GPIO20OUTCFG : 2; /*!< [18..17] GPIO20 output configuration. */
|
|
__IOM uint32_t GPIO20INTD : 1; /*!< [19..19] GPIO20 interrupt direction. */
|
|
__IOM uint32_t GPIO21INCFG : 1; /*!< [20..20] GPIO21 input enable. */
|
|
__IOM uint32_t GPIO21OUTCFG : 2; /*!< [22..21] GPIO21 output configuration. */
|
|
__IOM uint32_t GPIO21INTD : 1; /*!< [23..23] GPIO21 interrupt direction. */
|
|
__IOM uint32_t GPIO22INCFG : 1; /*!< [24..24] GPIO22 input enable. */
|
|
__IOM uint32_t GPIO22OUTCFG : 2; /*!< [26..25] GPIO22 output configuration. */
|
|
__IOM uint32_t GPIO22INTD : 1; /*!< [27..27] GPIO22 interrupt direction. */
|
|
__IOM uint32_t GPIO23INCFG : 1; /*!< [28..28] GPIO23 input enable. */
|
|
__IOM uint32_t GPIO23OUTCFG : 2; /*!< [30..29] GPIO23 output configuration. */
|
|
__IOM uint32_t GPIO23INTD : 1; /*!< [31..31] GPIO23 interrupt direction. */
|
|
} CFGC_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t CFGD; /*!< (@ 0x0000004C) GPIO Configuration Register D */
|
|
|
|
struct {
|
|
__IOM uint32_t GPIO24INCFG : 1; /*!< [0..0] GPIO24 input enable. */
|
|
__IOM uint32_t GPIO24OUTCFG : 2; /*!< [2..1] GPIO24 output configuration. */
|
|
__IOM uint32_t GPIO24INTD : 1; /*!< [3..3] GPIO24 interrupt direction. */
|
|
__IOM uint32_t GPIO25INCFG : 1; /*!< [4..4] GPIO25 input enable. */
|
|
__IOM uint32_t GPIO25OUTCFG : 2; /*!< [6..5] GPIO25 output configuration. */
|
|
__IOM uint32_t GPIO25INTD : 1; /*!< [7..7] GPIO25 interrupt direction. */
|
|
__IOM uint32_t GPIO26INCFG : 1; /*!< [8..8] GPIO26 input enable. */
|
|
__IOM uint32_t GPIO26OUTCFG : 2; /*!< [10..9] GPIO26 output configuration. */
|
|
__IOM uint32_t GPIO26INTD : 1; /*!< [11..11] GPIO26 interrupt direction. */
|
|
__IOM uint32_t GPIO27INCFG : 1; /*!< [12..12] GPIO27 input enable. */
|
|
__IOM uint32_t GPIO27OUTCFG : 2; /*!< [14..13] GPIO27 output configuration. */
|
|
__IOM uint32_t GPIO27INTD : 1; /*!< [15..15] GPIO27 interrupt direction. */
|
|
__IOM uint32_t GPIO28INCFG : 1; /*!< [16..16] GPIO28 input enable. */
|
|
__IOM uint32_t GPIO28OUTCFG : 2; /*!< [18..17] GPIO28 output configuration. */
|
|
__IOM uint32_t GPIO28INTD : 1; /*!< [19..19] GPIO28 interrupt direction. */
|
|
__IOM uint32_t GPIO29INCFG : 1; /*!< [20..20] GPIO29 input enable. */
|
|
__IOM uint32_t GPIO29OUTCFG : 2; /*!< [22..21] GPIO29 output configuration. */
|
|
__IOM uint32_t GPIO29INTD : 1; /*!< [23..23] GPIO29 interrupt direction. */
|
|
__IOM uint32_t GPIO30INCFG : 1; /*!< [24..24] GPIO30 input enable. */
|
|
__IOM uint32_t GPIO30OUTCFG : 2; /*!< [26..25] GPIO30 output configuration. */
|
|
__IOM uint32_t GPIO30INTD : 1; /*!< [27..27] GPIO30 interrupt direction. */
|
|
__IOM uint32_t GPIO31INCFG : 1; /*!< [28..28] GPIO31 input enable. */
|
|
__IOM uint32_t GPIO31OUTCFG : 2; /*!< [30..29] GPIO31 output configuration. */
|
|
__IOM uint32_t GPIO31INTD : 1; /*!< [31..31] GPIO31 interrupt direction. */
|
|
} CFGD_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t CFGE; /*!< (@ 0x00000050) GPIO Configuration Register E */
|
|
|
|
struct {
|
|
__IOM uint32_t GPIO32INCFG : 1; /*!< [0..0] GPIO32 input enable. */
|
|
__IOM uint32_t GPIO32OUTCFG : 2; /*!< [2..1] GPIO32 output configuration. */
|
|
__IOM uint32_t GPIO32INTD : 1; /*!< [3..3] GPIO32 interrupt direction. */
|
|
__IOM uint32_t GPIO33INCFG : 1; /*!< [4..4] GPIO33 input enable. */
|
|
__IOM uint32_t GPIO33OUTCFG : 2; /*!< [6..5] GPIO33 output configuration. */
|
|
__IOM uint32_t GPIO33INTD : 1; /*!< [7..7] GPIO33 interrupt direction. */
|
|
__IOM uint32_t GPIO34INCFG : 1; /*!< [8..8] GPIO34 input enable. */
|
|
__IOM uint32_t GPIO34OUTCFG : 2; /*!< [10..9] GPIO34 output configuration. */
|
|
__IOM uint32_t GPIO34INTD : 1; /*!< [11..11] GPIO34 interrupt direction. */
|
|
__IOM uint32_t GPIO35INCFG : 1; /*!< [12..12] GPIO35 input enable. */
|
|
__IOM uint32_t GPIO35OUTCFG : 2; /*!< [14..13] GPIO35 output configuration. */
|
|
__IOM uint32_t GPIO35INTD : 1; /*!< [15..15] GPIO35 interrupt direction. */
|
|
__IOM uint32_t GPIO36INCFG : 1; /*!< [16..16] GPIO36 input enable. */
|
|
__IOM uint32_t GPIO36OUTCFG : 2; /*!< [18..17] GPIO36 output configuration. */
|
|
__IOM uint32_t GPIO36INTD : 1; /*!< [19..19] GPIO36 interrupt direction. */
|
|
__IOM uint32_t GPIO37INCFG : 1; /*!< [20..20] GPIO37 input enable. */
|
|
__IOM uint32_t GPIO37OUTCFG : 2; /*!< [22..21] GPIO37 output configuration. */
|
|
__IOM uint32_t GPIO37INTD : 1; /*!< [23..23] GPIO37 interrupt direction. */
|
|
__IOM uint32_t GPIO38INCFG : 1; /*!< [24..24] GPIO38 input enable. */
|
|
__IOM uint32_t GPIO38OUTCFG : 2; /*!< [26..25] GPIO38 output configuration. */
|
|
__IOM uint32_t GPIO38INTD : 1; /*!< [27..27] GPIO38 interrupt direction. */
|
|
__IOM uint32_t GPIO39INCFG : 1; /*!< [28..28] GPIO39 input enable. */
|
|
__IOM uint32_t GPIO39OUTCFG : 2; /*!< [30..29] GPIO39 output configuration. */
|
|
__IOM uint32_t GPIO39INTD : 1; /*!< [31..31] GPIO39 interrupt direction. */
|
|
} CFGE_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t CFGF; /*!< (@ 0x00000054) GPIO Configuration Register F */
|
|
|
|
struct {
|
|
__IOM uint32_t GPIO40INCFG : 1; /*!< [0..0] GPIO40 input enable. */
|
|
__IOM uint32_t GPIO40OUTCFG : 2; /*!< [2..1] GPIO40 output configuration. */
|
|
__IOM uint32_t GPIO40INTD : 1; /*!< [3..3] GPIO40 interrupt direction. */
|
|
__IOM uint32_t GPIO41INCFG : 1; /*!< [4..4] GPIO41 input enable. */
|
|
__IOM uint32_t GPIO41OUTCFG : 2; /*!< [6..5] GPIO41 output configuration. */
|
|
__IOM uint32_t GPIO41INTD : 1; /*!< [7..7] GPIO41 interrupt direction. */
|
|
__IOM uint32_t GPIO42INCFG : 1; /*!< [8..8] GPIO42 input enable. */
|
|
__IOM uint32_t GPIO42OUTCFG : 2; /*!< [10..9] GPIO42 output configuration. */
|
|
__IOM uint32_t GPIO42INTD : 1; /*!< [11..11] GPIO42 interrupt direction. */
|
|
__IOM uint32_t GPIO43INCFG : 1; /*!< [12..12] GPIO43 input enable. */
|
|
__IOM uint32_t GPIO43OUTCFG : 2; /*!< [14..13] GPIO43 output configuration. */
|
|
__IOM uint32_t GPIO43INTD : 1; /*!< [15..15] GPIO43 interrupt direction. */
|
|
__IOM uint32_t GPIO44INCFG : 1; /*!< [16..16] GPIO44 input enable. */
|
|
__IOM uint32_t GPIO44OUTCFG : 2; /*!< [18..17] GPIO44 output configuration. */
|
|
__IOM uint32_t GPIO44INTD : 1; /*!< [19..19] GPIO44 interrupt direction. */
|
|
__IOM uint32_t GPIO45INCFG : 1; /*!< [20..20] GPIO45 input enable. */
|
|
__IOM uint32_t GPIO45OUTCFG : 2; /*!< [22..21] GPIO45 output configuration. */
|
|
__IOM uint32_t GPIO45INTD : 1; /*!< [23..23] GPIO45 interrupt direction. */
|
|
__IOM uint32_t GPIO46INCFG : 1; /*!< [24..24] GPIO46 input enable. */
|
|
__IOM uint32_t GPIO46OUTCFG : 2; /*!< [26..25] GPIO46 output configuration. */
|
|
__IOM uint32_t GPIO46INTD : 1; /*!< [27..27] GPIO46 interrupt direction. */
|
|
__IOM uint32_t GPIO47INCFG : 1; /*!< [28..28] GPIO47 input enable. */
|
|
__IOM uint32_t GPIO47OUTCFG : 2; /*!< [30..29] GPIO47 output configuration. */
|
|
__IOM uint32_t GPIO47INTD : 1; /*!< [31..31] GPIO47 interrupt direction. */
|
|
} CFGF_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t CFGG; /*!< (@ 0x00000058) GPIO Configuration Register G */
|
|
|
|
struct {
|
|
__IOM uint32_t GPIO48INCFG : 1; /*!< [0..0] GPIO48 input enable. */
|
|
__IOM uint32_t GPIO48OUTCFG : 2; /*!< [2..1] GPIO48 output configuration. */
|
|
__IOM uint32_t GPIO48INTD : 1; /*!< [3..3] GPIO48 interrupt direction. */
|
|
__IOM uint32_t GPIO49INCFG : 1; /*!< [4..4] GPIO49 input enable. */
|
|
__IOM uint32_t GPIO49OUTCFG : 2; /*!< [6..5] GPIO49 output configuration. */
|
|
__IOM uint32_t GPIO49INTD : 1; /*!< [7..7] GPIO49 interrupt direction. */
|
|
} CFGG_b;
|
|
} ;
|
|
__IM uint32_t RESERVED1;
|
|
|
|
union {
|
|
__IOM uint32_t PADKEY; /*!< (@ 0x00000060) Key Register for all pad configuration registers */
|
|
|
|
struct {
|
|
__IOM uint32_t PADKEY : 32; /*!< [31..0] Key register value. */
|
|
} PADKEY_b;
|
|
} ;
|
|
__IM uint32_t RESERVED2[7];
|
|
|
|
union {
|
|
__IOM uint32_t RDA; /*!< (@ 0x00000080) GPIO Input Register A */
|
|
|
|
struct {
|
|
__IOM uint32_t RDA : 32; /*!< [31..0] GPIO31-0 read data. */
|
|
} RDA_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t RDB; /*!< (@ 0x00000084) GPIO Input Register B */
|
|
|
|
struct {
|
|
__IOM uint32_t RDB : 18; /*!< [17..0] GPIO49-32 read data. */
|
|
} RDB_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t WTA; /*!< (@ 0x00000088) GPIO Output Register A */
|
|
|
|
struct {
|
|
__IOM uint32_t WTA : 32; /*!< [31..0] GPIO31-0 write data. */
|
|
} WTA_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t WTB; /*!< (@ 0x0000008C) GPIO Output Register B */
|
|
|
|
struct {
|
|
__IOM uint32_t WTB : 18; /*!< [17..0] GPIO49-32 write data. */
|
|
} WTB_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t WTSA; /*!< (@ 0x00000090) GPIO Output Register A Set */
|
|
|
|
struct {
|
|
__IOM uint32_t WTSA : 32; /*!< [31..0] Set the GPIO31-0 write data. */
|
|
} WTSA_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t WTSB; /*!< (@ 0x00000094) GPIO Output Register B Set */
|
|
|
|
struct {
|
|
__IOM uint32_t WTSB : 18; /*!< [17..0] Set the GPIO49-32 write data. */
|
|
} WTSB_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t WTCA; /*!< (@ 0x00000098) GPIO Output Register A Clear */
|
|
|
|
struct {
|
|
__IOM uint32_t WTCA : 32; /*!< [31..0] Clear the GPIO31-0 write data. */
|
|
} WTCA_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t WTCB; /*!< (@ 0x0000009C) GPIO Output Register B Clear */
|
|
|
|
struct {
|
|
__IOM uint32_t WTCB : 18; /*!< [17..0] Clear the GPIO49-32 write data. */
|
|
} WTCB_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t ENA; /*!< (@ 0x000000A0) GPIO Enable Register A */
|
|
|
|
struct {
|
|
__IOM uint32_t ENA : 32; /*!< [31..0] GPIO31-0 output enables */
|
|
} ENA_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t ENB; /*!< (@ 0x000000A4) GPIO Enable Register B */
|
|
|
|
struct {
|
|
__IOM uint32_t ENB : 18; /*!< [17..0] GPIO49-32 output enables */
|
|
} ENB_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t ENSA; /*!< (@ 0x000000A8) GPIO Enable Register A Set */
|
|
|
|
struct {
|
|
__IOM uint32_t ENSA : 32; /*!< [31..0] Set the GPIO31-0 output enables */
|
|
} ENSA_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t ENSB; /*!< (@ 0x000000AC) GPIO Enable Register B Set */
|
|
|
|
struct {
|
|
__IOM uint32_t ENSB : 18; /*!< [17..0] Set the GPIO49-32 output enables */
|
|
} ENSB_b;
|
|
} ;
|
|
__IM uint32_t RESERVED3;
|
|
|
|
union {
|
|
__IOM uint32_t ENCA; /*!< (@ 0x000000B4) GPIO Enable Register A Clear */
|
|
|
|
struct {
|
|
__IOM uint32_t ENCA : 32; /*!< [31..0] Clear the GPIO31-0 output enables */
|
|
} ENCA_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t ENCB; /*!< (@ 0x000000B8) GPIO Enable Register B Clear */
|
|
|
|
struct {
|
|
__IOM uint32_t ENCB : 18; /*!< [17..0] Clear the GPIO49-32 output enables */
|
|
} ENCB_b;
|
|
} ;
|
|
__IM uint32_t RESERVED4[81];
|
|
|
|
union {
|
|
__IOM uint32_t INT0EN; /*!< (@ 0x00000200) GPIO Interrupt Registers 31-0: Enable */
|
|
|
|
struct {
|
|
__IOM uint32_t GPIO0 : 1; /*!< [0..0] GPIO0 interrupt. */
|
|
__IOM uint32_t GPIO1 : 1; /*!< [1..1] GPIO1 interrupt. */
|
|
__IOM uint32_t GPIO2 : 1; /*!< [2..2] GPIO2 interrupt. */
|
|
__IOM uint32_t GPIO3 : 1; /*!< [3..3] GPIO3 interrupt. */
|
|
__IOM uint32_t GPIO4 : 1; /*!< [4..4] GPIO4 interrupt. */
|
|
__IOM uint32_t GPIO5 : 1; /*!< [5..5] GPIO5 interrupt. */
|
|
__IOM uint32_t GPIO6 : 1; /*!< [6..6] GPIO6 interrupt. */
|
|
__IOM uint32_t GPIO7 : 1; /*!< [7..7] GPIO7 interrupt. */
|
|
__IOM uint32_t GPIO8 : 1; /*!< [8..8] GPIO8 interrupt. */
|
|
__IOM uint32_t GPIO9 : 1; /*!< [9..9] GPIO9 interrupt. */
|
|
__IOM uint32_t GPIO10 : 1; /*!< [10..10] GPIO10 interrupt. */
|
|
__IOM uint32_t GPIO11 : 1; /*!< [11..11] GPIO11 interrupt. */
|
|
__IOM uint32_t GPIO12 : 1; /*!< [12..12] GPIO12 interrupt. */
|
|
__IOM uint32_t GPIO13 : 1; /*!< [13..13] GPIO13 interrupt. */
|
|
__IOM uint32_t GPIO14 : 1; /*!< [14..14] GPIO14 interrupt. */
|
|
__IOM uint32_t GPIO15 : 1; /*!< [15..15] GPIO15 interrupt. */
|
|
__IOM uint32_t GPIO16 : 1; /*!< [16..16] GPIO16 interrupt. */
|
|
__IOM uint32_t GPIO17 : 1; /*!< [17..17] GPIO17 interrupt. */
|
|
__IOM uint32_t GPIO18 : 1; /*!< [18..18] GPIO18interrupt. */
|
|
__IOM uint32_t GPIO19 : 1; /*!< [19..19] GPIO19 interrupt. */
|
|
__IOM uint32_t GPIO20 : 1; /*!< [20..20] GPIO20 interrupt. */
|
|
__IOM uint32_t GPIO21 : 1; /*!< [21..21] GPIO21 interrupt. */
|
|
__IOM uint32_t GPIO22 : 1; /*!< [22..22] GPIO22 interrupt. */
|
|
__IOM uint32_t GPIO23 : 1; /*!< [23..23] GPIO23 interrupt. */
|
|
__IOM uint32_t GPIO24 : 1; /*!< [24..24] GPIO24 interrupt. */
|
|
__IOM uint32_t GPIO25 : 1; /*!< [25..25] GPIO25 interrupt. */
|
|
__IOM uint32_t GPIO26 : 1; /*!< [26..26] GPIO26 interrupt. */
|
|
__IOM uint32_t GPIO27 : 1; /*!< [27..27] GPIO27 interrupt. */
|
|
__IOM uint32_t GPIO28 : 1; /*!< [28..28] GPIO28 interrupt. */
|
|
__IOM uint32_t GPIO29 : 1; /*!< [29..29] GPIO29 interrupt. */
|
|
__IOM uint32_t GPIO30 : 1; /*!< [30..30] GPIO30 interrupt. */
|
|
__IOM uint32_t GPIO31 : 1; /*!< [31..31] GPIO31 interrupt. */
|
|
} INT0EN_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t INT0STAT; /*!< (@ 0x00000204) GPIO Interrupt Registers 31-0: Status */
|
|
|
|
struct {
|
|
__IOM uint32_t GPIO0 : 1; /*!< [0..0] GPIO0 interrupt. */
|
|
__IOM uint32_t GPIO1 : 1; /*!< [1..1] GPIO1 interrupt. */
|
|
__IOM uint32_t GPIO2 : 1; /*!< [2..2] GPIO2 interrupt. */
|
|
__IOM uint32_t GPIO3 : 1; /*!< [3..3] GPIO3 interrupt. */
|
|
__IOM uint32_t GPIO4 : 1; /*!< [4..4] GPIO4 interrupt. */
|
|
__IOM uint32_t GPIO5 : 1; /*!< [5..5] GPIO5 interrupt. */
|
|
__IOM uint32_t GPIO6 : 1; /*!< [6..6] GPIO6 interrupt. */
|
|
__IOM uint32_t GPIO7 : 1; /*!< [7..7] GPIO7 interrupt. */
|
|
__IOM uint32_t GPIO8 : 1; /*!< [8..8] GPIO8 interrupt. */
|
|
__IOM uint32_t GPIO9 : 1; /*!< [9..9] GPIO9 interrupt. */
|
|
__IOM uint32_t GPIO10 : 1; /*!< [10..10] GPIO10 interrupt. */
|
|
__IOM uint32_t GPIO11 : 1; /*!< [11..11] GPIO11 interrupt. */
|
|
__IOM uint32_t GPIO12 : 1; /*!< [12..12] GPIO12 interrupt. */
|
|
__IOM uint32_t GPIO13 : 1; /*!< [13..13] GPIO13 interrupt. */
|
|
__IOM uint32_t GPIO14 : 1; /*!< [14..14] GPIO14 interrupt. */
|
|
__IOM uint32_t GPIO15 : 1; /*!< [15..15] GPIO15 interrupt. */
|
|
__IOM uint32_t GPIO16 : 1; /*!< [16..16] GPIO16 interrupt. */
|
|
__IOM uint32_t GPIO17 : 1; /*!< [17..17] GPIO17 interrupt. */
|
|
__IOM uint32_t GPIO18 : 1; /*!< [18..18] GPIO18interrupt. */
|
|
__IOM uint32_t GPIO19 : 1; /*!< [19..19] GPIO19 interrupt. */
|
|
__IOM uint32_t GPIO20 : 1; /*!< [20..20] GPIO20 interrupt. */
|
|
__IOM uint32_t GPIO21 : 1; /*!< [21..21] GPIO21 interrupt. */
|
|
__IOM uint32_t GPIO22 : 1; /*!< [22..22] GPIO22 interrupt. */
|
|
__IOM uint32_t GPIO23 : 1; /*!< [23..23] GPIO23 interrupt. */
|
|
__IOM uint32_t GPIO24 : 1; /*!< [24..24] GPIO24 interrupt. */
|
|
__IOM uint32_t GPIO25 : 1; /*!< [25..25] GPIO25 interrupt. */
|
|
__IOM uint32_t GPIO26 : 1; /*!< [26..26] GPIO26 interrupt. */
|
|
__IOM uint32_t GPIO27 : 1; /*!< [27..27] GPIO27 interrupt. */
|
|
__IOM uint32_t GPIO28 : 1; /*!< [28..28] GPIO28 interrupt. */
|
|
__IOM uint32_t GPIO29 : 1; /*!< [29..29] GPIO29 interrupt. */
|
|
__IOM uint32_t GPIO30 : 1; /*!< [30..30] GPIO30 interrupt. */
|
|
__IOM uint32_t GPIO31 : 1; /*!< [31..31] GPIO31 interrupt. */
|
|
} INT0STAT_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t INT0CLR; /*!< (@ 0x00000208) GPIO Interrupt Registers 31-0: Clear */
|
|
|
|
struct {
|
|
__IOM uint32_t GPIO0 : 1; /*!< [0..0] GPIO0 interrupt. */
|
|
__IOM uint32_t GPIO1 : 1; /*!< [1..1] GPIO1 interrupt. */
|
|
__IOM uint32_t GPIO2 : 1; /*!< [2..2] GPIO2 interrupt. */
|
|
__IOM uint32_t GPIO3 : 1; /*!< [3..3] GPIO3 interrupt. */
|
|
__IOM uint32_t GPIO4 : 1; /*!< [4..4] GPIO4 interrupt. */
|
|
__IOM uint32_t GPIO5 : 1; /*!< [5..5] GPIO5 interrupt. */
|
|
__IOM uint32_t GPIO6 : 1; /*!< [6..6] GPIO6 interrupt. */
|
|
__IOM uint32_t GPIO7 : 1; /*!< [7..7] GPIO7 interrupt. */
|
|
__IOM uint32_t GPIO8 : 1; /*!< [8..8] GPIO8 interrupt. */
|
|
__IOM uint32_t GPIO9 : 1; /*!< [9..9] GPIO9 interrupt. */
|
|
__IOM uint32_t GPIO10 : 1; /*!< [10..10] GPIO10 interrupt. */
|
|
__IOM uint32_t GPIO11 : 1; /*!< [11..11] GPIO11 interrupt. */
|
|
__IOM uint32_t GPIO12 : 1; /*!< [12..12] GPIO12 interrupt. */
|
|
__IOM uint32_t GPIO13 : 1; /*!< [13..13] GPIO13 interrupt. */
|
|
__IOM uint32_t GPIO14 : 1; /*!< [14..14] GPIO14 interrupt. */
|
|
__IOM uint32_t GPIO15 : 1; /*!< [15..15] GPIO15 interrupt. */
|
|
__IOM uint32_t GPIO16 : 1; /*!< [16..16] GPIO16 interrupt. */
|
|
__IOM uint32_t GPIO17 : 1; /*!< [17..17] GPIO17 interrupt. */
|
|
__IOM uint32_t GPIO18 : 1; /*!< [18..18] GPIO18interrupt. */
|
|
__IOM uint32_t GPIO19 : 1; /*!< [19..19] GPIO19 interrupt. */
|
|
__IOM uint32_t GPIO20 : 1; /*!< [20..20] GPIO20 interrupt. */
|
|
__IOM uint32_t GPIO21 : 1; /*!< [21..21] GPIO21 interrupt. */
|
|
__IOM uint32_t GPIO22 : 1; /*!< [22..22] GPIO22 interrupt. */
|
|
__IOM uint32_t GPIO23 : 1; /*!< [23..23] GPIO23 interrupt. */
|
|
__IOM uint32_t GPIO24 : 1; /*!< [24..24] GPIO24 interrupt. */
|
|
__IOM uint32_t GPIO25 : 1; /*!< [25..25] GPIO25 interrupt. */
|
|
__IOM uint32_t GPIO26 : 1; /*!< [26..26] GPIO26 interrupt. */
|
|
__IOM uint32_t GPIO27 : 1; /*!< [27..27] GPIO27 interrupt. */
|
|
__IOM uint32_t GPIO28 : 1; /*!< [28..28] GPIO28 interrupt. */
|
|
__IOM uint32_t GPIO29 : 1; /*!< [29..29] GPIO29 interrupt. */
|
|
__IOM uint32_t GPIO30 : 1; /*!< [30..30] GPIO30 interrupt. */
|
|
__IOM uint32_t GPIO31 : 1; /*!< [31..31] GPIO31 interrupt. */
|
|
} INT0CLR_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t INT0SET; /*!< (@ 0x0000020C) GPIO Interrupt Registers 31-0: Set */
|
|
|
|
struct {
|
|
__IOM uint32_t GPIO0 : 1; /*!< [0..0] GPIO0 interrupt. */
|
|
__IOM uint32_t GPIO1 : 1; /*!< [1..1] GPIO1 interrupt. */
|
|
__IOM uint32_t GPIO2 : 1; /*!< [2..2] GPIO2 interrupt. */
|
|
__IOM uint32_t GPIO3 : 1; /*!< [3..3] GPIO3 interrupt. */
|
|
__IOM uint32_t GPIO4 : 1; /*!< [4..4] GPIO4 interrupt. */
|
|
__IOM uint32_t GPIO5 : 1; /*!< [5..5] GPIO5 interrupt. */
|
|
__IOM uint32_t GPIO6 : 1; /*!< [6..6] GPIO6 interrupt. */
|
|
__IOM uint32_t GPIO7 : 1; /*!< [7..7] GPIO7 interrupt. */
|
|
__IOM uint32_t GPIO8 : 1; /*!< [8..8] GPIO8 interrupt. */
|
|
__IOM uint32_t GPIO9 : 1; /*!< [9..9] GPIO9 interrupt. */
|
|
__IOM uint32_t GPIO10 : 1; /*!< [10..10] GPIO10 interrupt. */
|
|
__IOM uint32_t GPIO11 : 1; /*!< [11..11] GPIO11 interrupt. */
|
|
__IOM uint32_t GPIO12 : 1; /*!< [12..12] GPIO12 interrupt. */
|
|
__IOM uint32_t GPIO13 : 1; /*!< [13..13] GPIO13 interrupt. */
|
|
__IOM uint32_t GPIO14 : 1; /*!< [14..14] GPIO14 interrupt. */
|
|
__IOM uint32_t GPIO15 : 1; /*!< [15..15] GPIO15 interrupt. */
|
|
__IOM uint32_t GPIO16 : 1; /*!< [16..16] GPIO16 interrupt. */
|
|
__IOM uint32_t GPIO17 : 1; /*!< [17..17] GPIO17 interrupt. */
|
|
__IOM uint32_t GPIO18 : 1; /*!< [18..18] GPIO18interrupt. */
|
|
__IOM uint32_t GPIO19 : 1; /*!< [19..19] GPIO19 interrupt. */
|
|
__IOM uint32_t GPIO20 : 1; /*!< [20..20] GPIO20 interrupt. */
|
|
__IOM uint32_t GPIO21 : 1; /*!< [21..21] GPIO21 interrupt. */
|
|
__IOM uint32_t GPIO22 : 1; /*!< [22..22] GPIO22 interrupt. */
|
|
__IOM uint32_t GPIO23 : 1; /*!< [23..23] GPIO23 interrupt. */
|
|
__IOM uint32_t GPIO24 : 1; /*!< [24..24] GPIO24 interrupt. */
|
|
__IOM uint32_t GPIO25 : 1; /*!< [25..25] GPIO25 interrupt. */
|
|
__IOM uint32_t GPIO26 : 1; /*!< [26..26] GPIO26 interrupt. */
|
|
__IOM uint32_t GPIO27 : 1; /*!< [27..27] GPIO27 interrupt. */
|
|
__IOM uint32_t GPIO28 : 1; /*!< [28..28] GPIO28 interrupt. */
|
|
__IOM uint32_t GPIO29 : 1; /*!< [29..29] GPIO29 interrupt. */
|
|
__IOM uint32_t GPIO30 : 1; /*!< [30..30] GPIO30 interrupt. */
|
|
__IOM uint32_t GPIO31 : 1; /*!< [31..31] GPIO31 interrupt. */
|
|
} INT0SET_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t INT1EN; /*!< (@ 0x00000210) GPIO Interrupt Registers 49-32: Enable */
|
|
|
|
struct {
|
|
__IOM uint32_t GPIO32 : 1; /*!< [0..0] GPIO32 interrupt. */
|
|
__IOM uint32_t GPIO33 : 1; /*!< [1..1] GPIO33 interrupt. */
|
|
__IOM uint32_t GPIO34 : 1; /*!< [2..2] GPIO34 interrupt. */
|
|
__IOM uint32_t GPIO35 : 1; /*!< [3..3] GPIO35 interrupt. */
|
|
__IOM uint32_t GPIO36 : 1; /*!< [4..4] GPIO36 interrupt. */
|
|
__IOM uint32_t GPIO37 : 1; /*!< [5..5] GPIO37 interrupt. */
|
|
__IOM uint32_t GPIO38 : 1; /*!< [6..6] GPIO38 interrupt. */
|
|
__IOM uint32_t GPIO39 : 1; /*!< [7..7] GPIO39 interrupt. */
|
|
__IOM uint32_t GPIO40 : 1; /*!< [8..8] GPIO40 interrupt. */
|
|
__IOM uint32_t GPIO41 : 1; /*!< [9..9] GPIO41 interrupt. */
|
|
__IOM uint32_t GPIO42 : 1; /*!< [10..10] GPIO42 interrupt. */
|
|
__IOM uint32_t GPIO43 : 1; /*!< [11..11] GPIO43 interrupt. */
|
|
__IOM uint32_t GPIO44 : 1; /*!< [12..12] GPIO44 interrupt. */
|
|
__IOM uint32_t GPIO45 : 1; /*!< [13..13] GPIO45 interrupt. */
|
|
__IOM uint32_t GPIO46 : 1; /*!< [14..14] GPIO46 interrupt. */
|
|
__IOM uint32_t GPIO47 : 1; /*!< [15..15] GPIO47 interrupt. */
|
|
__IOM uint32_t GPIO48 : 1; /*!< [16..16] GPIO48 interrupt. */
|
|
__IOM uint32_t GPIO49 : 1; /*!< [17..17] GPIO49 interrupt. */
|
|
} INT1EN_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t INT1STAT; /*!< (@ 0x00000214) GPIO Interrupt Registers 49-32: Status */
|
|
|
|
struct {
|
|
__IOM uint32_t GPIO32 : 1; /*!< [0..0] GPIO32 interrupt. */
|
|
__IOM uint32_t GPIO33 : 1; /*!< [1..1] GPIO33 interrupt. */
|
|
__IOM uint32_t GPIO34 : 1; /*!< [2..2] GPIO34 interrupt. */
|
|
__IOM uint32_t GPIO35 : 1; /*!< [3..3] GPIO35 interrupt. */
|
|
__IOM uint32_t GPIO36 : 1; /*!< [4..4] GPIO36 interrupt. */
|
|
__IOM uint32_t GPIO37 : 1; /*!< [5..5] GPIO37 interrupt. */
|
|
__IOM uint32_t GPIO38 : 1; /*!< [6..6] GPIO38 interrupt. */
|
|
__IOM uint32_t GPIO39 : 1; /*!< [7..7] GPIO39 interrupt. */
|
|
__IOM uint32_t GPIO40 : 1; /*!< [8..8] GPIO40 interrupt. */
|
|
__IOM uint32_t GPIO41 : 1; /*!< [9..9] GPIO41 interrupt. */
|
|
__IOM uint32_t GPIO42 : 1; /*!< [10..10] GPIO42 interrupt. */
|
|
__IOM uint32_t GPIO43 : 1; /*!< [11..11] GPIO43 interrupt. */
|
|
__IOM uint32_t GPIO44 : 1; /*!< [12..12] GPIO44 interrupt. */
|
|
__IOM uint32_t GPIO45 : 1; /*!< [13..13] GPIO45 interrupt. */
|
|
__IOM uint32_t GPIO46 : 1; /*!< [14..14] GPIO46 interrupt. */
|
|
__IOM uint32_t GPIO47 : 1; /*!< [15..15] GPIO47 interrupt. */
|
|
__IOM uint32_t GPIO48 : 1; /*!< [16..16] GPIO48 interrupt. */
|
|
__IOM uint32_t GPIO49 : 1; /*!< [17..17] GPIO49 interrupt. */
|
|
} INT1STAT_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t INT1CLR; /*!< (@ 0x00000218) GPIO Interrupt Registers 49-32: Clear */
|
|
|
|
struct {
|
|
__IOM uint32_t GPIO32 : 1; /*!< [0..0] GPIO32 interrupt. */
|
|
__IOM uint32_t GPIO33 : 1; /*!< [1..1] GPIO33 interrupt. */
|
|
__IOM uint32_t GPIO34 : 1; /*!< [2..2] GPIO34 interrupt. */
|
|
__IOM uint32_t GPIO35 : 1; /*!< [3..3] GPIO35 interrupt. */
|
|
__IOM uint32_t GPIO36 : 1; /*!< [4..4] GPIO36 interrupt. */
|
|
__IOM uint32_t GPIO37 : 1; /*!< [5..5] GPIO37 interrupt. */
|
|
__IOM uint32_t GPIO38 : 1; /*!< [6..6] GPIO38 interrupt. */
|
|
__IOM uint32_t GPIO39 : 1; /*!< [7..7] GPIO39 interrupt. */
|
|
__IOM uint32_t GPIO40 : 1; /*!< [8..8] GPIO40 interrupt. */
|
|
__IOM uint32_t GPIO41 : 1; /*!< [9..9] GPIO41 interrupt. */
|
|
__IOM uint32_t GPIO42 : 1; /*!< [10..10] GPIO42 interrupt. */
|
|
__IOM uint32_t GPIO43 : 1; /*!< [11..11] GPIO43 interrupt. */
|
|
__IOM uint32_t GPIO44 : 1; /*!< [12..12] GPIO44 interrupt. */
|
|
__IOM uint32_t GPIO45 : 1; /*!< [13..13] GPIO45 interrupt. */
|
|
__IOM uint32_t GPIO46 : 1; /*!< [14..14] GPIO46 interrupt. */
|
|
__IOM uint32_t GPIO47 : 1; /*!< [15..15] GPIO47 interrupt. */
|
|
__IOM uint32_t GPIO48 : 1; /*!< [16..16] GPIO48 interrupt. */
|
|
__IOM uint32_t GPIO49 : 1; /*!< [17..17] GPIO49 interrupt. */
|
|
} INT1CLR_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t INT1SET; /*!< (@ 0x0000021C) GPIO Interrupt Registers 49-32: Set */
|
|
|
|
struct {
|
|
__IOM uint32_t GPIO32 : 1; /*!< [0..0] GPIO32 interrupt. */
|
|
__IOM uint32_t GPIO33 : 1; /*!< [1..1] GPIO33 interrupt. */
|
|
__IOM uint32_t GPIO34 : 1; /*!< [2..2] GPIO34 interrupt. */
|
|
__IOM uint32_t GPIO35 : 1; /*!< [3..3] GPIO35 interrupt. */
|
|
__IOM uint32_t GPIO36 : 1; /*!< [4..4] GPIO36 interrupt. */
|
|
__IOM uint32_t GPIO37 : 1; /*!< [5..5] GPIO37 interrupt. */
|
|
__IOM uint32_t GPIO38 : 1; /*!< [6..6] GPIO38 interrupt. */
|
|
__IOM uint32_t GPIO39 : 1; /*!< [7..7] GPIO39 interrupt. */
|
|
__IOM uint32_t GPIO40 : 1; /*!< [8..8] GPIO40 interrupt. */
|
|
__IOM uint32_t GPIO41 : 1; /*!< [9..9] GPIO41 interrupt. */
|
|
__IOM uint32_t GPIO42 : 1; /*!< [10..10] GPIO42 interrupt. */
|
|
__IOM uint32_t GPIO43 : 1; /*!< [11..11] GPIO43 interrupt. */
|
|
__IOM uint32_t GPIO44 : 1; /*!< [12..12] GPIO44 interrupt. */
|
|
__IOM uint32_t GPIO45 : 1; /*!< [13..13] GPIO45 interrupt. */
|
|
__IOM uint32_t GPIO46 : 1; /*!< [14..14] GPIO46 interrupt. */
|
|
__IOM uint32_t GPIO47 : 1; /*!< [15..15] GPIO47 interrupt. */
|
|
__IOM uint32_t GPIO48 : 1; /*!< [16..16] GPIO48 interrupt. */
|
|
__IOM uint32_t GPIO49 : 1; /*!< [17..17] GPIO49 interrupt. */
|
|
} INT1SET_b;
|
|
} ;
|
|
} GPIO_Type; /*!< Size = 544 (0x220) */
|
|
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ IOMSTR0 ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/**
|
|
* @brief I2C/SPI Master (IOMSTR0)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x50004000) IOMSTR0 Structure */
|
|
|
|
union {
|
|
__IOM uint32_t FIFO; /*!< (@ 0x00000000) FIFO Access Port */
|
|
|
|
struct {
|
|
__IOM uint32_t FIFO : 32; /*!< [31..0] FIFO access port. */
|
|
} FIFO_b;
|
|
} ;
|
|
__IM uint32_t RESERVED[63];
|
|
|
|
union {
|
|
__IOM uint32_t FIFOPTR; /*!< (@ 0x00000100) Current FIFO Pointers */
|
|
|
|
struct {
|
|
__IOM uint32_t FIFOSIZ : 7; /*!< [6..0] The number of bytes currently in the FIFO. */
|
|
__IM uint32_t : 9;
|
|
__IOM uint32_t FIFOREM : 7; /*!< [22..16] The number of bytes remaining in the FIFO (i.e. 64-FIFOSIZ). */
|
|
} FIFOPTR_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t TLNGTH; /*!< (@ 0x00000104) Transfer Length */
|
|
|
|
struct {
|
|
__IOM uint32_t TLNGTH : 12; /*!< [11..0] Remaining transfer length. */
|
|
} TLNGTH_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t FIFOTHR; /*!< (@ 0x00000108) FIFO Threshold Configuration */
|
|
|
|
struct {
|
|
__IOM uint32_t FIFORTHR : 6; /*!< [5..0] FIFO read threshold. */
|
|
__IM uint32_t : 2;
|
|
__IOM uint32_t FIFOWTHR : 6; /*!< [13..8] FIFO write threshold. */
|
|
} FIFOTHR_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t CLKCFG; /*!< (@ 0x0000010C) I/O Clock Configuration */
|
|
|
|
struct {
|
|
__IM uint32_t : 8;
|
|
__IOM uint32_t FSEL : 3; /*!< [10..8] Select the input clock frequency. */
|
|
__IOM uint32_t DIV3 : 1; /*!< [11..11] Enable divide by 3. */
|
|
__IOM uint32_t DIVEN : 1; /*!< [12..12] Enable clock division by TOTPER. */
|
|
__IM uint32_t : 3;
|
|
__IOM uint32_t LOWPER : 8; /*!< [23..16] Clock low count minus 1. */
|
|
__IOM uint32_t TOTPER : 8; /*!< [31..24] Clock total count minus 1. */
|
|
} CLKCFG_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t CMD; /*!< (@ 0x00000110) Command Register */
|
|
|
|
struct {
|
|
__IOM uint32_t CMD : 32; /*!< [31..0] This register is the I/O Command. */
|
|
} CMD_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t CMDRPT; /*!< (@ 0x00000114) Command Repeat Register */
|
|
|
|
struct {
|
|
__IOM uint32_t CMDRPT : 5; /*!< [4..0] These bits hold the Command repeat count. */
|
|
} CMDRPT_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t STATUS; /*!< (@ 0x00000118) Status Register */
|
|
|
|
struct {
|
|
__IOM uint32_t ERR : 1; /*!< [0..0] This bit indicates if an error interrupt has occurred. */
|
|
__IOM uint32_t CMDACT : 1; /*!< [1..1] This bit indicates if the I/O Command is active. */
|
|
__IOM uint32_t IDLEST : 1; /*!< [2..2] This bit indicates if the I/O state machine is IDLE. */
|
|
} STATUS_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t CFG; /*!< (@ 0x0000011C) I/O Master Configuration */
|
|
|
|
struct {
|
|
__IOM uint32_t IFCSEL : 1; /*!< [0..0] This bit selects the I/O interface. */
|
|
__IOM uint32_t SPOL : 1; /*!< [1..1] This bit selects SPI polarity. */
|
|
__IOM uint32_t SPHA : 1; /*!< [2..2] This bit selects SPI phase. */
|
|
__IM uint32_t : 28;
|
|
__IOM uint32_t IFCEN : 1; /*!< [31..31] This bit enables the IO Master. */
|
|
} CFG_b;
|
|
} ;
|
|
__IM uint32_t RESERVED1[56];
|
|
|
|
union {
|
|
__IOM uint32_t INTEN; /*!< (@ 0x00000200) IO Master Interrupts: Enable */
|
|
|
|
struct {
|
|
__IOM uint32_t CMDCMP : 1; /*!< [0..0] This is the Command Complete interrupt. */
|
|
__IOM uint32_t THR : 1; /*!< [1..1] This is the FIFO Threshold interrupt. */
|
|
__IOM uint32_t FUNDFL : 1; /*!< [2..2] This is the Write FIFO Underflow interrupt. */
|
|
__IOM uint32_t FOVFL : 1; /*!< [3..3] This is the Read FIFO Overflow interrupt. */
|
|
__IOM uint32_t NAK : 1; /*!< [4..4] This is the I2C NAK interrupt. */
|
|
__IOM uint32_t WTLEN : 1; /*!< [5..5] This is the write length mismatch interrupt. */
|
|
__IOM uint32_t IACC : 1; /*!< [6..6] This is the illegal FIFO access interrupt. */
|
|
__IOM uint32_t ICMD : 1; /*!< [7..7] This is the illegal command interrupt. */
|
|
__IOM uint32_t START : 1; /*!< [8..8] This is the START command interrupt. */
|
|
__IOM uint32_t STOP : 1; /*!< [9..9] This is the STOP command interrupt. */
|
|
__IOM uint32_t ARB : 1; /*!< [10..10] This is the arbitration loss interrupt. */
|
|
} INTEN_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t INTSTAT; /*!< (@ 0x00000204) IO Master Interrupts: Status */
|
|
|
|
struct {
|
|
__IOM uint32_t CMDCMP : 1; /*!< [0..0] This is the Command Complete interrupt. */
|
|
__IOM uint32_t THR : 1; /*!< [1..1] This is the FIFO Threshold interrupt. */
|
|
__IOM uint32_t FUNDFL : 1; /*!< [2..2] This is the Write FIFO Underflow interrupt. */
|
|
__IOM uint32_t FOVFL : 1; /*!< [3..3] This is the Read FIFO Overflow interrupt. */
|
|
__IOM uint32_t NAK : 1; /*!< [4..4] This is the I2C NAK interrupt. */
|
|
__IOM uint32_t WTLEN : 1; /*!< [5..5] This is the write length mismatch interrupt. */
|
|
__IOM uint32_t IACC : 1; /*!< [6..6] This is the illegal FIFO access interrupt. */
|
|
__IOM uint32_t ICMD : 1; /*!< [7..7] This is the illegal command interrupt. */
|
|
__IOM uint32_t START : 1; /*!< [8..8] This is the START command interrupt. */
|
|
__IOM uint32_t STOP : 1; /*!< [9..9] This is the STOP command interrupt. */
|
|
__IOM uint32_t ARB : 1; /*!< [10..10] This is the arbitration loss interrupt. */
|
|
} INTSTAT_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t INTCLR; /*!< (@ 0x00000208) IO Master Interrupts: Clear */
|
|
|
|
struct {
|
|
__IOM uint32_t CMDCMP : 1; /*!< [0..0] This is the Command Complete interrupt. */
|
|
__IOM uint32_t THR : 1; /*!< [1..1] This is the FIFO Threshold interrupt. */
|
|
__IOM uint32_t FUNDFL : 1; /*!< [2..2] This is the Write FIFO Underflow interrupt. */
|
|
__IOM uint32_t FOVFL : 1; /*!< [3..3] This is the Read FIFO Overflow interrupt. */
|
|
__IOM uint32_t NAK : 1; /*!< [4..4] This is the I2C NAK interrupt. */
|
|
__IOM uint32_t WTLEN : 1; /*!< [5..5] This is the write length mismatch interrupt. */
|
|
__IOM uint32_t IACC : 1; /*!< [6..6] This is the illegal FIFO access interrupt. */
|
|
__IOM uint32_t ICMD : 1; /*!< [7..7] This is the illegal command interrupt. */
|
|
__IOM uint32_t START : 1; /*!< [8..8] This is the START command interrupt. */
|
|
__IOM uint32_t STOP : 1; /*!< [9..9] This is the STOP command interrupt. */
|
|
__IOM uint32_t ARB : 1; /*!< [10..10] This is the arbitration loss interrupt. */
|
|
} INTCLR_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t INTSET; /*!< (@ 0x0000020C) IO Master Interrupts: Set */
|
|
|
|
struct {
|
|
__IOM uint32_t CMDCMP : 1; /*!< [0..0] This is the Command Complete interrupt. */
|
|
__IOM uint32_t THR : 1; /*!< [1..1] This is the FIFO Threshold interrupt. */
|
|
__IOM uint32_t FUNDFL : 1; /*!< [2..2] This is the Write FIFO Underflow interrupt. */
|
|
__IOM uint32_t FOVFL : 1; /*!< [3..3] This is the Read FIFO Overflow interrupt. */
|
|
__IOM uint32_t NAK : 1; /*!< [4..4] This is the I2C NAK interrupt. */
|
|
__IOM uint32_t WTLEN : 1; /*!< [5..5] This is the write length mismatch interrupt. */
|
|
__IOM uint32_t IACC : 1; /*!< [6..6] This is the illegal FIFO access interrupt. */
|
|
__IOM uint32_t ICMD : 1; /*!< [7..7] This is the illegal command interrupt. */
|
|
__IOM uint32_t START : 1; /*!< [8..8] This is the START command interrupt. */
|
|
__IOM uint32_t STOP : 1; /*!< [9..9] This is the STOP command interrupt. */
|
|
__IOM uint32_t ARB : 1; /*!< [10..10] This is the arbitration loss interrupt. */
|
|
} INTSET_b;
|
|
} ;
|
|
} IOMSTR0_Type; /*!< Size = 528 (0x210) */
|
|
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ IOSLAVE ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/**
|
|
* @brief I2C/SPI Slave (IOSLAVE)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x50000000) IOSLAVE Structure */
|
|
__IM uint32_t RESERVED[64];
|
|
|
|
union {
|
|
__IOM uint32_t FIFOPTR; /*!< (@ 0x00000100) Current FIFO Pointer */
|
|
|
|
struct {
|
|
__IOM uint32_t FIFOPTR : 8; /*!< [7..0] Current FIFO pointer. */
|
|
__IOM uint32_t FIFOSIZ : 8; /*!< [15..8] The number of bytes currently in the hardware FIFO. */
|
|
} FIFOPTR_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t FIFOCFG; /*!< (@ 0x00000104) FIFO Configuration */
|
|
|
|
struct {
|
|
__IOM uint32_t FIFOBASE : 5; /*!< [4..0] These bits hold the base address of the I/O FIFO in 8
|
|
byte segments. The IO Slave FIFO is situated in LRAM at
|
|
(FIFOBASE*8) to (FIFOMAX*8-1). */
|
|
__IM uint32_t : 3;
|
|
__IOM uint32_t FIFOMAX : 6; /*!< [13..8] These bits hold the maximum FIFO address in 8 byte segments.
|
|
It is also the beginning of the RAM area of the LRAM. Note
|
|
that no RAM area is configured if FIFOMAX is set to 0x1F. */
|
|
__IM uint32_t : 10;
|
|
__IOM uint32_t ROBASE : 6; /*!< [29..24] Defines the read-only area. The IO Slave read-only
|
|
area is situated in LRAM at (ROBASE*8) to (FIFOOBASE*8-1) */
|
|
} FIFOCFG_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t FIFOTHR; /*!< (@ 0x00000108) FIFO Threshold Configuration */
|
|
|
|
struct {
|
|
__IOM uint32_t FIFOTHR : 8; /*!< [7..0] FIFO size interrupt threshold. */
|
|
} FIFOTHR_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t FUPD; /*!< (@ 0x0000010C) FIFO Update Status */
|
|
|
|
struct {
|
|
__IOM uint32_t FIFOUPD : 1; /*!< [0..0] This bit indicates that a FIFO update is underway. */
|
|
__IOM uint32_t IOREAD : 1; /*!< [1..1] This bitfield indicates an IO read is active. */
|
|
} FUPD_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t FIFOCTR; /*!< (@ 0x00000110) Overall FIFO Counter */
|
|
|
|
struct {
|
|
__IOM uint32_t FIFOCTR : 10; /*!< [9..0] Virtual FIFO byte count */
|
|
} FIFOCTR_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t FIFOINC; /*!< (@ 0x00000114) Overall FIFO Counter Increment */
|
|
|
|
struct {
|
|
__IOM uint32_t FIFOINC : 10; /*!< [9..0] Increment the Overall FIFO Counter by this value on a
|
|
write */
|
|
} FIFOINC_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t CFG; /*!< (@ 0x00000118) I/O Slave Configuration */
|
|
|
|
struct {
|
|
__IOM uint32_t IFCSEL : 1; /*!< [0..0] This bit selects the I/O interface. */
|
|
__IOM uint32_t SPOL : 1; /*!< [1..1] This bit selects SPI polarity. */
|
|
__IOM uint32_t LSB : 1; /*!< [2..2] This bit selects the transfer bit ordering. */
|
|
__IM uint32_t : 1;
|
|
__IOM uint32_t STARTRD : 1; /*!< [4..4] This bit holds the cycle to initiate an I/O RAM read. */
|
|
__IM uint32_t : 3;
|
|
__IOM uint32_t I2CADDR : 12; /*!< [19..8] 7-bit or 10-bit I2C device address. */
|
|
__IM uint32_t : 11;
|
|
__IOM uint32_t IFCEN : 1; /*!< [31..31] IOSLAVE interface enable. */
|
|
} CFG_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t PRENC; /*!< (@ 0x0000011C) I/O Slave Interrupt Priority Encode */
|
|
|
|
struct {
|
|
__IOM uint32_t PRENC : 5; /*!< [4..0] These bits hold the priority encode of the REGACC interrupts. */
|
|
} PRENC_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t IOINTCTL; /*!< (@ 0x00000120) I/O Interrupt Control */
|
|
|
|
struct {
|
|
__IOM uint32_t IOINTEN : 8; /*!< [7..0] These bits setread the IOINT interrupt enables. */
|
|
__IOM uint32_t IOINT : 8; /*!< [15..8] These bits read the IOINT interrupts. */
|
|
__IOM uint32_t IOINTCLR : 1; /*!< [16..16] This bit clears all of the IOINT interrupts when written
|
|
with a 1. */
|
|
__IM uint32_t : 7;
|
|
__IOM uint32_t IOINTSET : 8; /*!< [31..24] These bits set the IOINT interrupts when written with
|
|
a 1. */
|
|
} IOINTCTL_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t GENADD; /*!< (@ 0x00000124) General Address Data */
|
|
|
|
struct {
|
|
__IOM uint32_t GADATA : 8; /*!< [7..0] The data supplied on the last General Address reference. */
|
|
} GENADD_b;
|
|
} ;
|
|
__IM uint32_t RESERVED1[54];
|
|
|
|
union {
|
|
__IOM uint32_t INTEN; /*!< (@ 0x00000200) IO Slave Interrupts: Enable */
|
|
|
|
struct {
|
|
__IOM uint32_t FSIZE : 1; /*!< [0..0] FIFO Size interrupt. */
|
|
__IOM uint32_t FOVFL : 1; /*!< [1..1] FIFO Overflow interrupt. */
|
|
__IOM uint32_t FUNDFL : 1; /*!< [2..2] FIFO Underflow interrupt. */
|
|
__IOM uint32_t FRDERR : 1; /*!< [3..3] FIFO Read Error interrupt. */
|
|
__IOM uint32_t GENAD : 1; /*!< [4..4] I2C General Address interrupt. */
|
|
__IOM uint32_t IOINTW : 1; /*!< [5..5] I2C Interrupt Write interrupt. */
|
|
} INTEN_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t INTSTAT; /*!< (@ 0x00000204) IO Slave Interrupts: Status */
|
|
|
|
struct {
|
|
__IOM uint32_t FSIZE : 1; /*!< [0..0] FIFO Size interrupt. */
|
|
__IOM uint32_t FOVFL : 1; /*!< [1..1] FIFO Overflow interrupt. */
|
|
__IOM uint32_t FUNDFL : 1; /*!< [2..2] FIFO Underflow interrupt. */
|
|
__IOM uint32_t FRDERR : 1; /*!< [3..3] FIFO Read Error interrupt. */
|
|
__IOM uint32_t GENAD : 1; /*!< [4..4] I2C General Address interrupt. */
|
|
__IOM uint32_t IOINTW : 1; /*!< [5..5] I2C Interrupt Write interrupt. */
|
|
} INTSTAT_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t INTCLR; /*!< (@ 0x00000208) IO Slave Interrupts: Clear */
|
|
|
|
struct {
|
|
__IOM uint32_t FSIZE : 1; /*!< [0..0] FIFO Size interrupt. */
|
|
__IOM uint32_t FOVFL : 1; /*!< [1..1] FIFO Overflow interrupt. */
|
|
__IOM uint32_t FUNDFL : 1; /*!< [2..2] FIFO Underflow interrupt. */
|
|
__IOM uint32_t FRDERR : 1; /*!< [3..3] FIFO Read Error interrupt. */
|
|
__IOM uint32_t GENAD : 1; /*!< [4..4] I2C General Address interrupt. */
|
|
__IOM uint32_t IOINTW : 1; /*!< [5..5] I2C Interrupt Write interrupt. */
|
|
} INTCLR_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t INTSET; /*!< (@ 0x0000020C) IO Slave Interrupts: Set */
|
|
|
|
struct {
|
|
__IOM uint32_t FSIZE : 1; /*!< [0..0] FIFO Size interrupt. */
|
|
__IOM uint32_t FOVFL : 1; /*!< [1..1] FIFO Overflow interrupt. */
|
|
__IOM uint32_t FUNDFL : 1; /*!< [2..2] FIFO Underflow interrupt. */
|
|
__IOM uint32_t FRDERR : 1; /*!< [3..3] FIFO Read Error interrupt. */
|
|
__IOM uint32_t GENAD : 1; /*!< [4..4] I2C General Address interrupt. */
|
|
__IOM uint32_t IOINTW : 1; /*!< [5..5] I2C Interrupt Write interrupt. */
|
|
} INTSET_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t REGACCINTEN; /*!< (@ 0x00000210) Register Access Interrupts: Enable */
|
|
|
|
struct {
|
|
__IOM uint32_t REGACC : 32; /*!< [31..0] Register access interrupts. */
|
|
} REGACCINTEN_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t REGACCINTSTAT; /*!< (@ 0x00000214) Register Access Interrupts: Status */
|
|
|
|
struct {
|
|
__IOM uint32_t REGACC : 32; /*!< [31..0] Register access interrupts. */
|
|
} REGACCINTSTAT_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t REGACCINTCLR; /*!< (@ 0x00000218) Register Access Interrupts: Clear */
|
|
|
|
struct {
|
|
__IOM uint32_t REGACC : 32; /*!< [31..0] Register access interrupts. */
|
|
} REGACCINTCLR_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t REGACCINTSET; /*!< (@ 0x0000021C) Register Access Interrupts: Set */
|
|
|
|
struct {
|
|
__IOM uint32_t REGACC : 32; /*!< [31..0] Register access interrupts. */
|
|
} REGACCINTSET_b;
|
|
} ;
|
|
} IOSLAVE_Type; /*!< Size = 544 (0x220) */
|
|
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ MCUCTRL ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/**
|
|
* @brief MCU Miscellaneous Control Logic (MCUCTRL)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x40020000) MCUCTRL Structure */
|
|
|
|
union {
|
|
__IOM uint32_t CHIP_INFO; /*!< (@ 0x00000000) Chip Information Register */
|
|
|
|
struct {
|
|
__IOM uint32_t QUAL : 1; /*!< [0..0] Device qualified. */
|
|
__IOM uint32_t TEMP : 2; /*!< [2..1] Device temperature range. */
|
|
__IOM uint32_t PINS : 3; /*!< [5..3] Number of pins. */
|
|
__IOM uint32_t PKG : 2; /*!< [7..6] Device package type. */
|
|
__IOM uint32_t MINORREV : 4; /*!< [11..8] Minor device revision number. */
|
|
__IOM uint32_t MAJORREV : 4; /*!< [15..12] Major device revision number. */
|
|
__IOM uint32_t RAM : 4; /*!< [19..16] Device RAM size. */
|
|
__IOM uint32_t FLASH : 4; /*!< [23..20] Device flash size. */
|
|
__IOM uint32_t CLASS : 8; /*!< [31..24] Device class. */
|
|
} CHIP_INFO_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t CHIPID0; /*!< (@ 0x00000004) Unique Chip ID 0 */
|
|
|
|
struct {
|
|
__IOM uint32_t VALUE : 32; /*!< [31..0] Unique chip ID 0. */
|
|
} CHIPID0_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t CHIPID1; /*!< (@ 0x00000008) Unique Chip ID 1 */
|
|
|
|
struct {
|
|
__IOM uint32_t VALUE : 32; /*!< [31..0] Unique chip ID 1. */
|
|
} CHIPID1_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t CHIPREV; /*!< (@ 0x0000000C) Chip Revision */
|
|
|
|
struct {
|
|
__IOM uint32_t REVISION : 8; /*!< [7..0] Chip Revision Number. */
|
|
} CHIPREV_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t SUPPLYSRC; /*!< (@ 0x00000010) Memory and Core Voltage Supply Source Select
|
|
Register */
|
|
|
|
struct {
|
|
__IOM uint32_t MEMBUCKEN : 1; /*!< [0..0] Enables and select the Memory Buck as the supply for
|
|
the Flash and SRAM power domain. */
|
|
__IOM uint32_t COREBUCKEN : 1; /*!< [1..1] Enables and Selects the Core Buck as the supply for the
|
|
low-voltage power domain. */
|
|
} SUPPLYSRC_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t SUPPLYSTATUS; /*!< (@ 0x00000014) Memory and Core Voltage Supply Source Status
|
|
Register */
|
|
|
|
struct {
|
|
__IOM uint32_t MEMBUCKON : 1; /*!< [0..0] Indicate whether the Memory power domain is supplied
|
|
from the LDO or the Buck. */
|
|
__IOM uint32_t COREBUCKON : 1; /*!< [1..1] Indicates whether the Core low-voltage domain is supplied
|
|
from the LDO or the Buck. */
|
|
} SUPPLYSTATUS_b;
|
|
} ;
|
|
__IM uint32_t RESERVED[57];
|
|
|
|
union {
|
|
__IOM uint32_t BANDGAPEN; /*!< (@ 0x000000FC) Band Gap Enable */
|
|
|
|
struct {
|
|
__IOM uint32_t BGPEN : 1; /*!< [0..0] Bandgap Enable */
|
|
} BANDGAPEN_b;
|
|
} ;
|
|
__IM uint32_t RESERVED1[16];
|
|
|
|
union {
|
|
__IOM uint32_t SRAMPWDINSLEEP; /*!< (@ 0x00000140) Powerdown an SRAM Bank in Deep Sleep mode */
|
|
|
|
struct {
|
|
__IOM uint32_t BANK0 : 1; /*!< [0..0] Force SRAM Bank 0 to powerdown in deep sleep mode, causing
|
|
the contents of the bank to be lost. */
|
|
__IOM uint32_t BANK1 : 1; /*!< [1..1] Force SRAM Bank 1 to powerdown in deep sleep mode, causing
|
|
the contents of the bank to be lost. */
|
|
__IOM uint32_t BANK2 : 1; /*!< [2..2] Force SRAM Bank 2 to powerdown in deep sleep mode, causing
|
|
the contents of the bank to be lost. */
|
|
__IOM uint32_t BANK3 : 1; /*!< [3..3] Force SRAM Bank 3 to powerdown in deep sleep mode, causing
|
|
the contents of the bank to be lost. */
|
|
__IOM uint32_t BANK4 : 1; /*!< [4..4] Force SRAM Bank 4 to powerdown in deep sleep mode, causing
|
|
the contents of the bank to be lost. */
|
|
__IOM uint32_t BANK5 : 1; /*!< [5..5] Force SRAM Bank 5 to powerdown in deep sleep mode, causing
|
|
the contents of the bank to be lost. */
|
|
__IOM uint32_t BANK6 : 1; /*!< [6..6] Force SRAM Bank 6 to powerdown in deep sleep mode, causing
|
|
the contents of the bank to be lost. */
|
|
__IOM uint32_t BANK7 : 1; /*!< [7..7] Force SRAM Bank 7 to powerdown in deep sleep mode, causing
|
|
the contents of the bank to be lost. */
|
|
} SRAMPWDINSLEEP_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t SRAMPWRDIS; /*!< (@ 0x00000144) Disables individual banks of the SRAM array */
|
|
|
|
struct {
|
|
__IOM uint32_t BANK0 : 1; /*!< [0..0] Remove power from SRAM Bank 0 which will cause an access
|
|
to its address space to generate a Hard Fault. */
|
|
__IOM uint32_t BANK1 : 1; /*!< [1..1] Remove power from SRAM Bank 1 which will cause an access
|
|
to its address space to generate a Hard Fault. */
|
|
__IOM uint32_t BANK2 : 1; /*!< [2..2] Remove power from SRAM Bank 2 which will cause an access
|
|
to its address space to generate a Hard Fault. */
|
|
__IOM uint32_t BANK3 : 1; /*!< [3..3] Remove power from SRAM Bank 3 which will cause an access
|
|
to its address space to generate a Hard Fault. */
|
|
__IOM uint32_t BANK4 : 1; /*!< [4..4] Remove power from SRAM Bank 4 which will cause an access
|
|
to its address space to generate a Hard Fault. */
|
|
__IOM uint32_t BANK5 : 1; /*!< [5..5] Remove power from SRAM Bank 5 which will cause an access
|
|
to its address space to generate a Hard Fault. */
|
|
__IOM uint32_t BANK6 : 1; /*!< [6..6] Remove power from SRAM Bank 6 which will cause an access
|
|
to its address space to generate a Hard Fault. */
|
|
__IOM uint32_t BANK7 : 1; /*!< [7..7] Remove power from SRAM Bank 7 which will cause an access
|
|
to its address space to generate a Hard Fault. */
|
|
} SRAMPWRDIS_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t FLASHPWRDIS; /*!< (@ 0x00000148) Disables individual banks of the Flash array */
|
|
|
|
struct {
|
|
__IOM uint32_t BANK0 : 1; /*!< [0..0] Remove power from Flash Bank 0 which will cause an access
|
|
to its address space to generate a Hard Fault. */
|
|
__IOM uint32_t BANK1 : 1; /*!< [1..1] Remove power from Flash Bank 1 which will cause an access
|
|
to its address space to generate a Hard Fault. */
|
|
} FLASHPWRDIS_b;
|
|
} ;
|
|
__IM uint32_t RESERVED2[29];
|
|
|
|
union {
|
|
__IOM uint32_t ICODEFAULTADDR; /*!< (@ 0x000001C0) ICODE bus address which was present when a bus
|
|
fault occurred. */
|
|
|
|
struct {
|
|
__IOM uint32_t ADDR : 32; /*!< [31..0] The ICODE bus address observed when a Bus Fault occurred.
|
|
Once an address is captured in this field, it is held until
|
|
the corresponding Fault Observed bit is cleared in the
|
|
FAULTSTATUS register. */
|
|
} ICODEFAULTADDR_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t DCODEFAULTADDR; /*!< (@ 0x000001C4) DCODE bus address which was present when a bus
|
|
fault occurred. */
|
|
|
|
struct {
|
|
__IOM uint32_t ADDR : 32; /*!< [31..0] The DCODE bus address observed when a Bus Fault occurred.
|
|
Once an address is captured in this field, it is held until
|
|
the corresponding Fault Observed bit is cleared in the
|
|
FAULTSTATUS register. */
|
|
} DCODEFAULTADDR_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t SYSFAULTADDR; /*!< (@ 0x000001C8) System bus address which was present when a bus
|
|
fault occurred. */
|
|
|
|
struct {
|
|
__IOM uint32_t ADDR : 32; /*!< [31..0] SYS bus address observed when a Bus Fault occurred.
|
|
Once an address is captured in this field, it is held until
|
|
the corresponding Fault Observed bit is cleared in the
|
|
FAULTSTATUS register. */
|
|
} SYSFAULTADDR_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t FAULTSTATUS; /*!< (@ 0x000001CC) Reflects the status of the bus decoders' fault
|
|
detection. Any write to this register will
|
|
clear all of the status bits within the
|
|
register. */
|
|
|
|
struct {
|
|
__IOM uint32_t ICODE : 1; /*!< [0..0] The ICODE Bus Decoder Fault Detected bit. When set, a
|
|
fault has been detected, and the ICODEFAULTADDR register
|
|
will contain the bus address which generated the fault. */
|
|
__IOM uint32_t DCODE : 1; /*!< [1..1] DCODE Bus Decoder Fault Detected bit. When set, a fault
|
|
has been detected, and the DCODEFAULTADDR register will
|
|
contain the bus address which generated the fault. */
|
|
__IOM uint32_t SYS : 1; /*!< [2..2] SYS Bus Decoder Fault Detected bit. When set, a fault
|
|
has been detected, and the SYSFAULTADDR register will contain
|
|
the bus address which generated the fault. */
|
|
} FAULTSTATUS_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t FAULTCAPTUREEN; /*!< (@ 0x000001D0) Enable the fault capture registers */
|
|
|
|
struct {
|
|
__IOM uint32_t ENABLE : 1; /*!< [0..0] Fault Capture Enable field. When set, the Fault Capture
|
|
monitors are enabled and addresses which generate a hard
|
|
fault are captured into the FAULTADDR registers. */
|
|
} FAULTCAPTUREEN_b;
|
|
} ;
|
|
__IM uint32_t RESERVED3[31];
|
|
|
|
union {
|
|
__IOM uint32_t TPIUCTRL; /*!< (@ 0x00000250) TPIU Control Register. Determines the clock enable
|
|
and frequency for the M4's TPIU interface. */
|
|
|
|
struct {
|
|
__IOM uint32_t ENABLE : 1; /*!< [0..0] TPIU Enable field. When set, the ARM M4 TPIU is enabled
|
|
and data can be streamed out of the MCU's SWO port using
|
|
the ARM ITM and TPIU modules. */
|
|
__IM uint32_t : 7;
|
|
__IOM uint32_t CLKSEL : 2; /*!< [9..8] This field selects the frequency of the ARM M4 TPIU port. */
|
|
} TPIUCTRL_b;
|
|
} ;
|
|
} MCUCTRL_Type; /*!< Size = 596 (0x254) */
|
|
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ RSTGEN ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/**
|
|
* @brief MCU Reset Generator (RSTGEN)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x40000000) RSTGEN Structure */
|
|
|
|
union {
|
|
__IOM uint32_t CFG; /*!< (@ 0x00000000) Configuration Register */
|
|
|
|
struct {
|
|
__IOM uint32_t BODHREN : 1; /*!< [0..0] Brown out high (2.1v) reset enable. */
|
|
__IOM uint32_t WDREN : 1; /*!< [1..1] Watchdog Timer Reset Enable. NOTE: The WDT module must
|
|
also be configured for WDT reset. */
|
|
} CFG_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t SWPOI; /*!< (@ 0x00000004) Software POI Reset */
|
|
|
|
struct {
|
|
__IOM uint32_t SWPOIKEY : 8; /*!< [7..0] 0x1B generates a software POI reset. */
|
|
} SWPOI_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t SWPOR; /*!< (@ 0x00000008) Software POR Reset */
|
|
|
|
struct {
|
|
__IOM uint32_t SWPORKEY : 8; /*!< [7..0] 0xD4 generates a software POR reset. */
|
|
} SWPOR_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t STAT; /*!< (@ 0x0000000C) Status Register */
|
|
|
|
struct {
|
|
__IOM uint32_t EXRSTAT : 1; /*!< [0..0] Reset was initiated by an External Reset. */
|
|
__IOM uint32_t PORSTAT : 1; /*!< [1..1] Reset was initiated by a Power-On Reset. */
|
|
__IOM uint32_t BORSTAT : 1; /*!< [2..2] Reset was initiated by a Brown-Out Reset. */
|
|
__IOM uint32_t SWRSTAT : 1; /*!< [3..3] Reset was a initiated by SW POR or AIRCR Reset. */
|
|
__IOM uint32_t POIRSTAT : 1; /*!< [4..4] Reset was a initiated by Software POI Reset. */
|
|
__IOM uint32_t DBGRSTAT : 1; /*!< [5..5] Reset was a initiated by Debugger Reset. */
|
|
__IOM uint32_t WDRSTAT : 1; /*!< [6..6] Reset was initiated by a Watchdog Timer Reset. */
|
|
} STAT_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t CLRSTAT; /*!< (@ 0x00000010) Clear the status register */
|
|
|
|
struct {
|
|
__IOM uint32_t CLRSTAT : 1; /*!< [0..0] Writing a 1 to this bit clears all bits in the RST_STAT. */
|
|
} CLRSTAT_b;
|
|
} ;
|
|
__IM uint32_t RESERVED[123];
|
|
|
|
union {
|
|
__IOM uint32_t INTEN; /*!< (@ 0x00000200) Reset Interrupt register: Enable */
|
|
|
|
struct {
|
|
__IOM uint32_t BODH : 1; /*!< [0..0] Enables an interrupt that triggers when VCC is below
|
|
BODH level. */
|
|
} INTEN_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t INTSTAT; /*!< (@ 0x00000204) Reset Interrupt register: Status */
|
|
|
|
struct {
|
|
__IOM uint32_t BODH : 1; /*!< [0..0] Enables an interrupt that triggers when VCC is below
|
|
BODH level. */
|
|
} INTSTAT_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t INTCLR; /*!< (@ 0x00000208) Reset Interrupt register: Clear */
|
|
|
|
struct {
|
|
__IOM uint32_t BODH : 1; /*!< [0..0] Enables an interrupt that triggers when VCC is below
|
|
BODH level. */
|
|
} INTCLR_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t INTSET; /*!< (@ 0x0000020C) Reset Interrupt register: Set */
|
|
|
|
struct {
|
|
__IOM uint32_t BODH : 1; /*!< [0..0] Enables an interrupt that triggers when VCC is below
|
|
BODH level. */
|
|
} INTSET_b;
|
|
} ;
|
|
} RSTGEN_Type; /*!< Size = 528 (0x210) */
|
|
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ RTC ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/**
|
|
* @brief Real Time Clock (RTC)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x40004040) RTC Structure */
|
|
|
|
union {
|
|
__IOM uint32_t CTRLOW; /*!< (@ 0x00000000) RTC Counters Lower */
|
|
|
|
struct {
|
|
__IOM uint32_t CTR100 : 8; /*!< [7..0] 100ths of a second Counter */
|
|
__IOM uint32_t CTRSEC : 7; /*!< [14..8] Seconds Counter */
|
|
__IM uint32_t : 1;
|
|
__IOM uint32_t CTRMIN : 7; /*!< [22..16] Minutes Counter */
|
|
__IM uint32_t : 1;
|
|
__IOM uint32_t CTRHR : 6; /*!< [29..24] Hours Counter */
|
|
} CTRLOW_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t CTRUP; /*!< (@ 0x00000004) RTC Counters Upper */
|
|
|
|
struct {
|
|
__IOM uint32_t CTRDATE : 6; /*!< [5..0] Date Counter */
|
|
__IM uint32_t : 2;
|
|
__IOM uint32_t CTRMO : 5; /*!< [12..8] Months Counter */
|
|
__IM uint32_t : 3;
|
|
__IOM uint32_t CTRYR : 8; /*!< [23..16] Years Counter */
|
|
__IOM uint32_t CTRWKDY : 3; /*!< [26..24] Weekdays Counter */
|
|
__IOM uint32_t CB : 1; /*!< [27..27] Century */
|
|
__IOM uint32_t CEB : 1; /*!< [28..28] Century enable */
|
|
__IM uint32_t : 2;
|
|
__IOM uint32_t CTERR : 1; /*!< [31..31] Counter read error status */
|
|
} CTRUP_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t ALMLOW; /*!< (@ 0x00000008) RTC Alarms Lower */
|
|
|
|
struct {
|
|
__IOM uint32_t ALM100 : 8; /*!< [7..0] 100ths of a second Alarm */
|
|
__IOM uint32_t ALMSEC : 7; /*!< [14..8] Seconds Alarm */
|
|
__IM uint32_t : 1;
|
|
__IOM uint32_t ALMMIN : 7; /*!< [22..16] Minutes Alarm */
|
|
__IM uint32_t : 1;
|
|
__IOM uint32_t ALMHR : 6; /*!< [29..24] Hours Alarm */
|
|
} ALMLOW_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t ALMUP; /*!< (@ 0x0000000C) RTC Alarms Upper */
|
|
|
|
struct {
|
|
__IOM uint32_t ALMDATE : 6; /*!< [5..0] Date Alarm */
|
|
__IM uint32_t : 2;
|
|
__IOM uint32_t ALMMO : 5; /*!< [12..8] Months Alarm */
|
|
__IM uint32_t : 3;
|
|
__IOM uint32_t ALMWKDY : 3; /*!< [18..16] Weekdays Alarm */
|
|
} ALMUP_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t RTCCTL; /*!< (@ 0x00000010) RTC Control Register */
|
|
|
|
struct {
|
|
__IOM uint32_t WRTC : 1; /*!< [0..0] Counter write control */
|
|
__IOM uint32_t RPT : 3; /*!< [3..1] Alarm repeat interval */
|
|
__IOM uint32_t RSTOP : 1; /*!< [4..4] RTC input clock control */
|
|
__IOM uint32_t HR1224 : 1; /*!< [5..5] Hours Counter mode */
|
|
} RTCCTL_b;
|
|
} ;
|
|
__IM uint32_t RESERVED[43];
|
|
|
|
union {
|
|
__IOM uint32_t INTEN; /*!< (@ 0x000000C0) CLK_GEN Interrupt Register: Enable */
|
|
|
|
struct {
|
|
__IOM uint32_t ACF : 1; /*!< [0..0] Autocalibration Fail interrupt */
|
|
__IOM uint32_t ACC : 1; /*!< [1..1] Autocalibration Complete interrupt */
|
|
__IOM uint32_t OF : 1; /*!< [2..2] XT Oscillator Fail interrupt */
|
|
__IOM uint32_t ALM : 1; /*!< [3..3] RTC Alarm interrupt */
|
|
} INTEN_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t INTSTAT; /*!< (@ 0x000000C4) CLK_GEN Interrupt Register: Status */
|
|
|
|
struct {
|
|
__IOM uint32_t ACF : 1; /*!< [0..0] Autocalibration Fail interrupt */
|
|
__IOM uint32_t ACC : 1; /*!< [1..1] Autocalibration Complete interrupt */
|
|
__IOM uint32_t OF : 1; /*!< [2..2] XT Oscillator Fail interrupt */
|
|
__IOM uint32_t ALM : 1; /*!< [3..3] RTC Alarm interrupt */
|
|
} INTSTAT_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t INTCLR; /*!< (@ 0x000000C8) CLK_GEN Interrupt Register: Clear */
|
|
|
|
struct {
|
|
__IOM uint32_t ACF : 1; /*!< [0..0] Autocalibration Fail interrupt */
|
|
__IOM uint32_t ACC : 1; /*!< [1..1] Autocalibration Complete interrupt */
|
|
__IOM uint32_t OF : 1; /*!< [2..2] XT Oscillator Fail interrupt */
|
|
__IOM uint32_t ALM : 1; /*!< [3..3] RTC Alarm interrupt */
|
|
} INTCLR_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t INTSET; /*!< (@ 0x000000CC) CLK_GEN Interrupt Register: Set */
|
|
|
|
struct {
|
|
__IOM uint32_t ACF : 1; /*!< [0..0] Autocalibration Fail interrupt */
|
|
__IOM uint32_t ACC : 1; /*!< [1..1] Autocalibration Complete interrupt */
|
|
__IOM uint32_t OF : 1; /*!< [2..2] XT Oscillator Fail interrupt */
|
|
__IOM uint32_t ALM : 1; /*!< [3..3] RTC Alarm interrupt */
|
|
} INTSET_b;
|
|
} ;
|
|
} RTC_Type; /*!< Size = 208 (0xd0) */
|
|
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ UART ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/**
|
|
* @brief Serial UART (UART)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x4001C000) UART Structure */
|
|
|
|
union {
|
|
__IOM uint32_t DR; /*!< (@ 0x00000000) UART Data Register */
|
|
|
|
struct {
|
|
__IOM uint32_t DATA : 8; /*!< [7..0] This is the UART data port. */
|
|
__IOM uint32_t FEDATA : 1; /*!< [8..8] This is the framing error indicator. */
|
|
__IOM uint32_t PEDATA : 1; /*!< [9..9] This is the parity error indicator. */
|
|
__IOM uint32_t BEDATA : 1; /*!< [10..10] This is the break error indicator. */
|
|
__IOM uint32_t OEDATA : 1; /*!< [11..11] This is the overrun error indicator. */
|
|
} DR_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t RSR; /*!< (@ 0x00000004) UART Status Register */
|
|
|
|
struct {
|
|
__IOM uint32_t FESTAT : 1; /*!< [0..0] This is the framing error indicator. */
|
|
__IOM uint32_t PESTAT : 1; /*!< [1..1] This is the parity error indicator. */
|
|
__IOM uint32_t BESTAT : 1; /*!< [2..2] This is the break error indicator. */
|
|
__IOM uint32_t OESTAT : 1; /*!< [3..3] This is the overrun error indicator. */
|
|
} RSR_b;
|
|
} ;
|
|
__IM uint32_t RESERVED[4];
|
|
|
|
union {
|
|
__IOM uint32_t FR; /*!< (@ 0x00000018) Flag Register */
|
|
|
|
struct {
|
|
__IOM uint32_t CTS : 1; /*!< [0..0] This bit holds the clear to send indicator. */
|
|
__IOM uint32_t DSR : 1; /*!< [1..1] This bit holds the data set ready indicator. */
|
|
__IOM uint32_t DCD : 1; /*!< [2..2] This bit holds the data carrier detect indicator. */
|
|
__IOM uint32_t BUSY : 1; /*!< [3..3] This bit holds the busy indicator. */
|
|
__IOM uint32_t RXFE : 1; /*!< [4..4] This bit holds the receive FIFO empty indicator. */
|
|
__IOM uint32_t TXFF : 1; /*!< [5..5] This bit holds the transmit FIFO full indicator. */
|
|
__IOM uint32_t RXFF : 1; /*!< [6..6] This bit holds the receive FIFO full indicator. */
|
|
__IOM uint32_t TXFE : 1; /*!< [7..7] This bit holds the transmit FIFO empty indicator. */
|
|
__IOM uint32_t RI : 1; /*!< [8..8] This bit holds the ring indicator. */
|
|
} FR_b;
|
|
} ;
|
|
__IM uint32_t RESERVED1;
|
|
|
|
union {
|
|
__IOM uint32_t ILPR; /*!< (@ 0x00000020) IrDA Counter */
|
|
|
|
struct {
|
|
__IOM uint32_t ILPDVSR : 8; /*!< [7..0] These bits hold the IrDA counter divisor. */
|
|
} ILPR_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t IBRD; /*!< (@ 0x00000024) Integer Baud Rate Divisor */
|
|
|
|
struct {
|
|
__IOM uint32_t DIVINT : 16; /*!< [15..0] These bits hold the baud integer divisor. */
|
|
} IBRD_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t FBRD; /*!< (@ 0x00000028) Fractional Baud Rate Divisor */
|
|
|
|
struct {
|
|
__IOM uint32_t DIVFRAC : 6; /*!< [5..0] These bits hold the baud fractional divisor. */
|
|
} FBRD_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t LCRH; /*!< (@ 0x0000002C) Line Control High */
|
|
|
|
struct {
|
|
__IOM uint32_t BRK : 1; /*!< [0..0] This bit holds the break set. */
|
|
__IOM uint32_t PEN : 1; /*!< [1..1] This bit holds the parity enable. */
|
|
__IOM uint32_t EPS : 1; /*!< [2..2] This bit holds the even parity select. */
|
|
__IOM uint32_t STP2 : 1; /*!< [3..3] This bit holds the two stop bits select. */
|
|
__IOM uint32_t FEN : 1; /*!< [4..4] This bit holds the FIFO enable. */
|
|
__IOM uint32_t WLEN : 2; /*!< [6..5] These bits hold the write length. */
|
|
__IOM uint32_t SPS : 1; /*!< [7..7] This bit holds the stick parity select. */
|
|
} LCRH_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t CR; /*!< (@ 0x00000030) Control Register */
|
|
|
|
struct {
|
|
__IOM uint32_t UARTEN : 1; /*!< [0..0] This bit is the UART enable. */
|
|
__IOM uint32_t SIREN : 1; /*!< [1..1] This bit is the SIR ENDEC enable. */
|
|
__IOM uint32_t SIRLP : 1; /*!< [2..2] This bit is the SIR low power select. */
|
|
__IOM uint32_t CLKEN : 1; /*!< [3..3] This bit is the UART clock enable. */
|
|
__IOM uint32_t CLKSEL : 3; /*!< [6..4] This bitfield is the UART clock select. */
|
|
__IOM uint32_t LBE : 1; /*!< [7..7] This bit is the loopback enable. */
|
|
__IOM uint32_t TXE : 1; /*!< [8..8] This bit is the transmit enable. */
|
|
__IOM uint32_t RXE : 1; /*!< [9..9] This bit is the receive enable. */
|
|
__IOM uint32_t DTR : 1; /*!< [10..10] This bit enables data transmit ready. */
|
|
__IOM uint32_t RTS : 1; /*!< [11..11] This bit enables request to send. */
|
|
__IOM uint32_t OUT1 : 1; /*!< [12..12] This bit holds modem Out1. */
|
|
__IOM uint32_t OUT2 : 1; /*!< [13..13] This bit holds modem Out2. */
|
|
__IOM uint32_t RTSEN : 1; /*!< [14..14] This bit enables RTS hardware flow control. */
|
|
__IOM uint32_t CTSEN : 1; /*!< [15..15] This bit enables CTS hardware flow control. */
|
|
} CR_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t IFLS; /*!< (@ 0x00000034) FIFO Interrupt Level Select */
|
|
|
|
struct {
|
|
__IOM uint32_t TXIFLSEL : 3; /*!< [2..0] These bits hold the transmit FIFO interrupt level. */
|
|
__IOM uint32_t RXIFLSEL : 3; /*!< [5..3] These bits hold the receive FIFO interrupt level. */
|
|
} IFLS_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t IER; /*!< (@ 0x00000038) Interrupt Enable */
|
|
|
|
struct {
|
|
__IOM uint32_t RIMIM : 1; /*!< [0..0] This bit holds the modem RI interrupt enable. */
|
|
__IOM uint32_t CTSMIM : 1; /*!< [1..1] This bit holds the modem CTS interrupt enable. */
|
|
__IOM uint32_t DCDMIM : 1; /*!< [2..2] This bit holds the modem DCD interrupt enable. */
|
|
__IOM uint32_t DSRMIM : 1; /*!< [3..3] This bit holds the modem DSR interrupt enable. */
|
|
__IOM uint32_t RXIM : 1; /*!< [4..4] This bit holds the receive interrupt enable. */
|
|
__IOM uint32_t TXIM : 1; /*!< [5..5] This bit holds the transmit interrupt enable. */
|
|
__IOM uint32_t RTIM : 1; /*!< [6..6] This bit holds the receive timeout interrupt enable. */
|
|
__IOM uint32_t FEIM : 1; /*!< [7..7] This bit holds the framing error interrupt enable. */
|
|
__IOM uint32_t PEIM : 1; /*!< [8..8] This bit holds the parity error interrupt enable. */
|
|
__IOM uint32_t BEIM : 1; /*!< [9..9] This bit holds the break error interrupt enable. */
|
|
__IOM uint32_t OEIM : 1; /*!< [10..10] This bit holds the overflow interrupt enable. */
|
|
} IER_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t IES; /*!< (@ 0x0000003C) Interrupt Status */
|
|
|
|
struct {
|
|
__IOM uint32_t RIMRIS : 1; /*!< [0..0] This bit holds the modem RI interrupt status. */
|
|
__IOM uint32_t CTSMRIS : 1; /*!< [1..1] This bit holds the modem CTS interrupt status. */
|
|
__IOM uint32_t DCDMRIS : 1; /*!< [2..2] This bit holds the modem DCD interrupt status. */
|
|
__IOM uint32_t DSRMRIS : 1; /*!< [3..3] This bit holds the modem DSR interrupt status. */
|
|
__IOM uint32_t RXRIS : 1; /*!< [4..4] This bit holds the receive interrupt status. */
|
|
__IOM uint32_t TXRIS : 1; /*!< [5..5] This bit holds the transmit interrupt status. */
|
|
__IOM uint32_t RTRIS : 1; /*!< [6..6] This bit holds the receive timeout interrupt status. */
|
|
__IOM uint32_t FERIS : 1; /*!< [7..7] This bit holds the framing error interrupt status. */
|
|
__IOM uint32_t PERIS : 1; /*!< [8..8] This bit holds the parity error interrupt status. */
|
|
__IOM uint32_t BERIS : 1; /*!< [9..9] This bit holds the break error interrupt status. */
|
|
__IOM uint32_t OERIS : 1; /*!< [10..10] This bit holds the overflow interrupt status. */
|
|
} IES_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t MIS; /*!< (@ 0x00000040) Masked Interrupt Status */
|
|
|
|
struct {
|
|
__IOM uint32_t RIMMIS : 1; /*!< [0..0] This bit holds the modem RI interrupt status masked. */
|
|
__IOM uint32_t CTSMMIS : 1; /*!< [1..1] This bit holds the modem CTS interrupt status masked. */
|
|
__IOM uint32_t DCDMMIS : 1; /*!< [2..2] This bit holds the modem DCD interrupt status masked. */
|
|
__IOM uint32_t DSRMMIS : 1; /*!< [3..3] This bit holds the modem DSR interrupt status masked. */
|
|
__IOM uint32_t RXMIS : 1; /*!< [4..4] This bit holds the receive interrupt status masked. */
|
|
__IOM uint32_t TXMIS : 1; /*!< [5..5] This bit holds the transmit interrupt status masked. */
|
|
__IOM uint32_t RTMIS : 1; /*!< [6..6] This bit holds the receive timeout interrupt status masked. */
|
|
__IOM uint32_t FEMIS : 1; /*!< [7..7] This bit holds the framing error interrupt status masked. */
|
|
__IOM uint32_t PEMIS : 1; /*!< [8..8] This bit holds the parity error interrupt status masked. */
|
|
__IOM uint32_t BEMIS : 1; /*!< [9..9] This bit holds the break error interrupt status masked. */
|
|
__IOM uint32_t OEMIS : 1; /*!< [10..10] This bit holds the overflow interrupt status masked. */
|
|
} MIS_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t IEC; /*!< (@ 0x00000044) Interrupt Clear */
|
|
|
|
struct {
|
|
__IOM uint32_t RIMIC : 1; /*!< [0..0] This bit holds the modem RI interrupt clear. */
|
|
__IOM uint32_t CTSMIC : 1; /*!< [1..1] This bit holds the modem CTS interrupt clear. */
|
|
__IOM uint32_t DCDMIC : 1; /*!< [2..2] This bit holds the modem DCD interrupt clear. */
|
|
__IOM uint32_t DSRMIC : 1; /*!< [3..3] This bit holds the modem DSR interrupt clear. */
|
|
__IOM uint32_t RXIC : 1; /*!< [4..4] This bit holds the receive interrupt clear. */
|
|
__IOM uint32_t TXIC : 1; /*!< [5..5] This bit holds the transmit interrupt clear. */
|
|
__IOM uint32_t RTIC : 1; /*!< [6..6] This bit holds the receive timeout interrupt clear. */
|
|
__IOM uint32_t FEIC : 1; /*!< [7..7] This bit holds the framing error interrupt clear. */
|
|
__IOM uint32_t PEIC : 1; /*!< [8..8] This bit holds the parity error interrupt clear. */
|
|
__IOM uint32_t BEIC : 1; /*!< [9..9] This bit holds the break error interrupt clear. */
|
|
__IOM uint32_t OEIC : 1; /*!< [10..10] This bit holds the overflow interrupt clear. */
|
|
} IEC_b;
|
|
} ;
|
|
} UART_Type; /*!< Size = 72 (0x48) */
|
|
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ VCOMP ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/**
|
|
* @brief Voltage Comparator (VCOMP)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x4000C000) VCOMP Structure */
|
|
|
|
union {
|
|
__IOM uint32_t CFG; /*!< (@ 0x00000000) Configuration Register */
|
|
|
|
struct {
|
|
__IOM uint32_t PSEL : 2; /*!< [1..0] This bitfield selects the positive input to the comparator. */
|
|
__IM uint32_t : 6;
|
|
__IOM uint32_t NSEL : 2; /*!< [9..8] This bitfield selects the negative input to the comparator. */
|
|
__IM uint32_t : 6;
|
|
__IOM uint32_t LVLSEL : 4; /*!< [19..16] When the reference input NSEL is set to NSEL_DAC, this
|
|
bitfield selects the voltage level for the negative input
|
|
to the comparator. */
|
|
} CFG_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t STAT; /*!< (@ 0x00000004) Status Register */
|
|
|
|
struct {
|
|
__IOM uint32_t CMPOUT : 1; /*!< [0..0] This bit is 1 if the positive input of the comparator
|
|
is greater than the negative input. */
|
|
__IOM uint32_t PWDSTAT : 1; /*!< [1..1] This bit indicates the power down state of the voltage
|
|
comparator. */
|
|
} STAT_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t PWDKEY; /*!< (@ 0x00000008) Key Register for Powering Down the Voltage Comparator */
|
|
|
|
struct {
|
|
__IOM uint32_t PWDKEY : 32; /*!< [31..0] Key register value. */
|
|
} PWDKEY_b;
|
|
} ;
|
|
__IM uint32_t RESERVED[125];
|
|
|
|
union {
|
|
__IOM uint32_t INTEN; /*!< (@ 0x00000200) Voltage Comparator Interrupt registers: Enable */
|
|
|
|
struct {
|
|
__IOM uint32_t OUTLOW : 1; /*!< [0..0] This bit is the vcompout low interrupt. */
|
|
__IOM uint32_t OUTHI : 1; /*!< [1..1] This bit is the vcompout high interrupt. */
|
|
} INTEN_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t INTSTAT; /*!< (@ 0x00000204) Voltage Comparator Interrupt registers: Status */
|
|
|
|
struct {
|
|
__IOM uint32_t OUTLOW : 1; /*!< [0..0] This bit is the vcompout low interrupt. */
|
|
__IOM uint32_t OUTHI : 1; /*!< [1..1] This bit is the vcompout high interrupt. */
|
|
} INTSTAT_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t INTCLR; /*!< (@ 0x00000208) Voltage Comparator Interrupt registers: Clear */
|
|
|
|
struct {
|
|
__IOM uint32_t OUTLOW : 1; /*!< [0..0] This bit is the vcompout low interrupt. */
|
|
__IOM uint32_t OUTHI : 1; /*!< [1..1] This bit is the vcompout high interrupt. */
|
|
} INTCLR_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t INTSET; /*!< (@ 0x0000020C) Voltage Comparator Interrupt registers: Set */
|
|
|
|
struct {
|
|
__IOM uint32_t OUTLOW : 1; /*!< [0..0] This bit is the vcompout low interrupt. */
|
|
__IOM uint32_t OUTHI : 1; /*!< [1..1] This bit is the vcompout high interrupt. */
|
|
} INTSET_b;
|
|
} ;
|
|
} VCOMP_Type; /*!< Size = 528 (0x210) */
|
|
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ WDT ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/**
|
|
* @brief Watchdog Timer (WDT)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x40024000) WDT Structure */
|
|
|
|
union {
|
|
__IOM uint32_t CFG; /*!< (@ 0x00000000) Configuration Register */
|
|
|
|
struct {
|
|
__IOM uint32_t WDTEN : 1; /*!< [0..0] This bitfield enables the WDT. */
|
|
__IOM uint32_t INTEN : 1; /*!< [1..1] This bitfield enables the WDT interrupt. Note : This
|
|
bit must be set before the interrupt status bit will reflect
|
|
a watchdog timer expiration. The IER interrupt register
|
|
must also be enabled for a WDT interrupt to be sent to
|
|
the NVIC. */
|
|
__IOM uint32_t RESEN : 1; /*!< [2..2] This bitfield enables the WDT reset. */
|
|
__IM uint32_t : 5;
|
|
__IOM uint32_t RESVAL : 8; /*!< [15..8] This bitfield is the compare value for counter bits
|
|
7:0 to generate a watchdog reset. */
|
|
__IOM uint32_t INTVAL : 8; /*!< [23..16] This bitfield is the compare value for counter bits
|
|
7:0 to generate a watchdog interrupt. */
|
|
} CFG_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t RSTRT; /*!< (@ 0x00000004) Restart the watchdog timer */
|
|
|
|
struct {
|
|
__IOM uint32_t RSTRT : 8; /*!< [7..0] Writing 0xB2 to WDTRSTRT restarts the watchdog timer. */
|
|
} RSTRT_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t LOCK; /*!< (@ 0x00000008) Locks the WDT */
|
|
|
|
struct {
|
|
__IOM uint32_t LOCK : 8; /*!< [7..0] Writing 0x3A locks the watchdog timer. Once locked, the
|
|
WDTCFG reg cannot be written and WDTEN is set. */
|
|
} LOCK_b;
|
|
} ;
|
|
__IM uint32_t RESERVED[125];
|
|
|
|
union {
|
|
__IOM uint32_t INTEN; /*!< (@ 0x00000200) WDT Interrupt register: Enable */
|
|
|
|
struct {
|
|
__IOM uint32_t WDTINT : 1; /*!< [0..0] Watchdog Timer Interrupt. */
|
|
} INTEN_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t INTSTAT; /*!< (@ 0x00000204) WDT Interrupt register: Status */
|
|
|
|
struct {
|
|
__IOM uint32_t WDTINT : 1; /*!< [0..0] Watchdog Timer Interrupt. */
|
|
} INTSTAT_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t INTCLR; /*!< (@ 0x00000208) WDT Interrupt register: Clear */
|
|
|
|
struct {
|
|
__IOM uint32_t WDTINT : 1; /*!< [0..0] Watchdog Timer Interrupt. */
|
|
} INTCLR_b;
|
|
} ;
|
|
|
|
union {
|
|
__IOM uint32_t INTSET; /*!< (@ 0x0000020C) WDT Interrupt register: Set */
|
|
|
|
struct {
|
|
__IOM uint32_t WDTINT : 1; /*!< [0..0] Watchdog Timer Interrupt. */
|
|
} INTSET_b;
|
|
} ;
|
|
} WDT_Type; /*!< Size = 528 (0x210) */
|
|
|
|
|
|
/** @} */ /* End of group Device_Peripheral_peripherals */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ Device Specific Peripheral Address Map ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/** @addtogroup Device_Peripheral_peripheralAddr
|
|
* @{
|
|
*/
|
|
|
|
#define ADC_BASE 0x50008000UL
|
|
#define CLKGEN_BASE 0x40004000UL
|
|
#define CTIMER_BASE 0x40008000UL
|
|
#define GPIO_BASE 0x40010000UL
|
|
#define IOMSTR0_BASE 0x50004000UL
|
|
#define IOMSTR1_BASE 0x50005000UL
|
|
#define IOSLAVE_BASE 0x50000000UL
|
|
#define MCUCTRL_BASE 0x40020000UL
|
|
#define RSTGEN_BASE 0x40000000UL
|
|
#define RTC_BASE 0x40004040UL
|
|
#define UART_BASE 0x4001C000UL
|
|
#define VCOMP_BASE 0x4000C000UL
|
|
#define WDT_BASE 0x40024000UL
|
|
|
|
/** @} */ /* End of group Device_Peripheral_peripheralAddr */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ Peripheral declaration ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/** @addtogroup Device_Peripheral_declaration
|
|
* @{
|
|
*/
|
|
|
|
#define ADC ((ADC_Type*) ADC_BASE)
|
|
#define CLKGEN ((CLKGEN_Type*) CLKGEN_BASE)
|
|
#define CTIMER ((CTIMER_Type*) CTIMER_BASE)
|
|
#define GPIO ((GPIO_Type*) GPIO_BASE)
|
|
#define IOMSTR0 ((IOMSTR0_Type*) IOMSTR0_BASE)
|
|
#define IOMSTR1 ((IOMSTR0_Type*) IOMSTR1_BASE)
|
|
#define IOSLAVE ((IOSLAVE_Type*) IOSLAVE_BASE)
|
|
#define MCUCTRL ((MCUCTRL_Type*) MCUCTRL_BASE)
|
|
#define RSTGEN ((RSTGEN_Type*) RSTGEN_BASE)
|
|
#define RTC ((RTC_Type*) RTC_BASE)
|
|
#define UART ((UART_Type*) UART_BASE)
|
|
#define VCOMP ((VCOMP_Type*) VCOMP_BASE)
|
|
#define WDT ((WDT_Type*) WDT_BASE)
|
|
|
|
/** @} */ /* End of group Device_Peripheral_declaration */
|
|
|
|
|
|
/* ========================================= End of section using anonymous unions ========================================= */
|
|
#if defined (__CC_ARM)
|
|
#pragma pop
|
|
#elif defined (__ICCARM__)
|
|
/* leave anonymous unions enabled */
|
|
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
|
#pragma clang diagnostic pop
|
|
#elif defined (__GNUC__)
|
|
/* anonymous unions are enabled by default */
|
|
#elif defined (__TMS470__)
|
|
/* anonymous unions are enabled by default */
|
|
#elif defined (__TASKING__)
|
|
#pragma warning restore
|
|
#elif defined (__CSMC__)
|
|
/* anonymous unions are enabled by default */
|
|
#endif
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ Pos/Mask Peripheral Section ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/** @addtogroup PosMask_peripherals
|
|
* @{
|
|
*/
|
|
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ ADC ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
/* ========================================================== CFG ========================================================== */
|
|
#define ADC_CFG_CLKSEL_Pos (24UL) /*!< CLKSEL (Bit 24) */
|
|
#define ADC_CFG_CLKSEL_Msk (0x7000000UL) /*!< CLKSEL (Bitfield-Mask: 0x07) */
|
|
#define ADC_CFG_TRIGPOL_Pos (20UL) /*!< TRIGPOL (Bit 20) */
|
|
#define ADC_CFG_TRIGPOL_Msk (0x100000UL) /*!< TRIGPOL (Bitfield-Mask: 0x01) */
|
|
#define ADC_CFG_TRIGSEL_Pos (16UL) /*!< TRIGSEL (Bit 16) */
|
|
#define ADC_CFG_TRIGSEL_Msk (0xf0000UL) /*!< TRIGSEL (Bitfield-Mask: 0x0f) */
|
|
#define ADC_CFG_REFSEL_Pos (8UL) /*!< REFSEL (Bit 8) */
|
|
#define ADC_CFG_REFSEL_Msk (0x300UL) /*!< REFSEL (Bitfield-Mask: 0x03) */
|
|
#define ADC_CFG_BATTLOAD_Pos (7UL) /*!< BATTLOAD (Bit 7) */
|
|
#define ADC_CFG_BATTLOAD_Msk (0x80UL) /*!< BATTLOAD (Bitfield-Mask: 0x01) */
|
|
#define ADC_CFG_OPMODE_Pos (5UL) /*!< OPMODE (Bit 5) */
|
|
#define ADC_CFG_OPMODE_Msk (0x60UL) /*!< OPMODE (Bitfield-Mask: 0x03) */
|
|
#define ADC_CFG_LPMODE_Pos (3UL) /*!< LPMODE (Bit 3) */
|
|
#define ADC_CFG_LPMODE_Msk (0x18UL) /*!< LPMODE (Bitfield-Mask: 0x03) */
|
|
#define ADC_CFG_RPTEN_Pos (2UL) /*!< RPTEN (Bit 2) */
|
|
#define ADC_CFG_RPTEN_Msk (0x4UL) /*!< RPTEN (Bitfield-Mask: 0x01) */
|
|
#define ADC_CFG_TMPSPWR_Pos (1UL) /*!< TMPSPWR (Bit 1) */
|
|
#define ADC_CFG_TMPSPWR_Msk (0x2UL) /*!< TMPSPWR (Bitfield-Mask: 0x01) */
|
|
#define ADC_CFG_ADCEN_Pos (0UL) /*!< ADCEN (Bit 0) */
|
|
#define ADC_CFG_ADCEN_Msk (0x1UL) /*!< ADCEN (Bitfield-Mask: 0x01) */
|
|
/* ========================================================= STAT ========================================================== */
|
|
#define ADC_STAT_PWDSTAT_Pos (0UL) /*!< PWDSTAT (Bit 0) */
|
|
#define ADC_STAT_PWDSTAT_Msk (0x3UL) /*!< PWDSTAT (Bitfield-Mask: 0x03) */
|
|
/* ========================================================== SWT ========================================================== */
|
|
#define ADC_SWT_SWT_Pos (0UL) /*!< SWT (Bit 0) */
|
|
#define ADC_SWT_SWT_Msk (0xffUL) /*!< SWT (Bitfield-Mask: 0xff) */
|
|
/* ======================================================== SL0CFG ========================================================= */
|
|
#define ADC_SL0CFG_ADSEL0_Pos (24UL) /*!< ADSEL0 (Bit 24) */
|
|
#define ADC_SL0CFG_ADSEL0_Msk (0x7000000UL) /*!< ADSEL0 (Bitfield-Mask: 0x07) */
|
|
#define ADC_SL0CFG_THSEL0_Pos (16UL) /*!< THSEL0 (Bit 16) */
|
|
#define ADC_SL0CFG_THSEL0_Msk (0x70000UL) /*!< THSEL0 (Bitfield-Mask: 0x07) */
|
|
#define ADC_SL0CFG_CHSEL0_Pos (8UL) /*!< CHSEL0 (Bit 8) */
|
|
#define ADC_SL0CFG_CHSEL0_Msk (0xf00UL) /*!< CHSEL0 (Bitfield-Mask: 0x0f) */
|
|
#define ADC_SL0CFG_WCEN0_Pos (1UL) /*!< WCEN0 (Bit 1) */
|
|
#define ADC_SL0CFG_WCEN0_Msk (0x2UL) /*!< WCEN0 (Bitfield-Mask: 0x01) */
|
|
#define ADC_SL0CFG_SLEN0_Pos (0UL) /*!< SLEN0 (Bit 0) */
|
|
#define ADC_SL0CFG_SLEN0_Msk (0x1UL) /*!< SLEN0 (Bitfield-Mask: 0x01) */
|
|
/* ======================================================== SL1CFG ========================================================= */
|
|
#define ADC_SL1CFG_ADSEL1_Pos (24UL) /*!< ADSEL1 (Bit 24) */
|
|
#define ADC_SL1CFG_ADSEL1_Msk (0x7000000UL) /*!< ADSEL1 (Bitfield-Mask: 0x07) */
|
|
#define ADC_SL1CFG_THSEL1_Pos (16UL) /*!< THSEL1 (Bit 16) */
|
|
#define ADC_SL1CFG_THSEL1_Msk (0x70000UL) /*!< THSEL1 (Bitfield-Mask: 0x07) */
|
|
#define ADC_SL1CFG_CHSEL1_Pos (8UL) /*!< CHSEL1 (Bit 8) */
|
|
#define ADC_SL1CFG_CHSEL1_Msk (0xf00UL) /*!< CHSEL1 (Bitfield-Mask: 0x0f) */
|
|
#define ADC_SL1CFG_WCEN1_Pos (1UL) /*!< WCEN1 (Bit 1) */
|
|
#define ADC_SL1CFG_WCEN1_Msk (0x2UL) /*!< WCEN1 (Bitfield-Mask: 0x01) */
|
|
#define ADC_SL1CFG_SLEN1_Pos (0UL) /*!< SLEN1 (Bit 0) */
|
|
#define ADC_SL1CFG_SLEN1_Msk (0x1UL) /*!< SLEN1 (Bitfield-Mask: 0x01) */
|
|
/* ======================================================== SL2CFG ========================================================= */
|
|
#define ADC_SL2CFG_ADSEL2_Pos (24UL) /*!< ADSEL2 (Bit 24) */
|
|
#define ADC_SL2CFG_ADSEL2_Msk (0x7000000UL) /*!< ADSEL2 (Bitfield-Mask: 0x07) */
|
|
#define ADC_SL2CFG_THSEL2_Pos (16UL) /*!< THSEL2 (Bit 16) */
|
|
#define ADC_SL2CFG_THSEL2_Msk (0x70000UL) /*!< THSEL2 (Bitfield-Mask: 0x07) */
|
|
#define ADC_SL2CFG_CHSEL2_Pos (8UL) /*!< CHSEL2 (Bit 8) */
|
|
#define ADC_SL2CFG_CHSEL2_Msk (0xf00UL) /*!< CHSEL2 (Bitfield-Mask: 0x0f) */
|
|
#define ADC_SL2CFG_WCEN2_Pos (1UL) /*!< WCEN2 (Bit 1) */
|
|
#define ADC_SL2CFG_WCEN2_Msk (0x2UL) /*!< WCEN2 (Bitfield-Mask: 0x01) */
|
|
#define ADC_SL2CFG_SLEN2_Pos (0UL) /*!< SLEN2 (Bit 0) */
|
|
#define ADC_SL2CFG_SLEN2_Msk (0x1UL) /*!< SLEN2 (Bitfield-Mask: 0x01) */
|
|
/* ======================================================== SL3CFG ========================================================= */
|
|
#define ADC_SL3CFG_ADSEL3_Pos (24UL) /*!< ADSEL3 (Bit 24) */
|
|
#define ADC_SL3CFG_ADSEL3_Msk (0x7000000UL) /*!< ADSEL3 (Bitfield-Mask: 0x07) */
|
|
#define ADC_SL3CFG_THSEL3_Pos (16UL) /*!< THSEL3 (Bit 16) */
|
|
#define ADC_SL3CFG_THSEL3_Msk (0x70000UL) /*!< THSEL3 (Bitfield-Mask: 0x07) */
|
|
#define ADC_SL3CFG_CHSEL3_Pos (8UL) /*!< CHSEL3 (Bit 8) */
|
|
#define ADC_SL3CFG_CHSEL3_Msk (0xf00UL) /*!< CHSEL3 (Bitfield-Mask: 0x0f) */
|
|
#define ADC_SL3CFG_WCEN3_Pos (1UL) /*!< WCEN3 (Bit 1) */
|
|
#define ADC_SL3CFG_WCEN3_Msk (0x2UL) /*!< WCEN3 (Bitfield-Mask: 0x01) */
|
|
#define ADC_SL3CFG_SLEN3_Pos (0UL) /*!< SLEN3 (Bit 0) */
|
|
#define ADC_SL3CFG_SLEN3_Msk (0x1UL) /*!< SLEN3 (Bitfield-Mask: 0x01) */
|
|
/* ======================================================== SL4CFG ========================================================= */
|
|
#define ADC_SL4CFG_ADSEL4_Pos (24UL) /*!< ADSEL4 (Bit 24) */
|
|
#define ADC_SL4CFG_ADSEL4_Msk (0x7000000UL) /*!< ADSEL4 (Bitfield-Mask: 0x07) */
|
|
#define ADC_SL4CFG_THSEL4_Pos (16UL) /*!< THSEL4 (Bit 16) */
|
|
#define ADC_SL4CFG_THSEL4_Msk (0x70000UL) /*!< THSEL4 (Bitfield-Mask: 0x07) */
|
|
#define ADC_SL4CFG_CHSEL4_Pos (8UL) /*!< CHSEL4 (Bit 8) */
|
|
#define ADC_SL4CFG_CHSEL4_Msk (0xf00UL) /*!< CHSEL4 (Bitfield-Mask: 0x0f) */
|
|
#define ADC_SL4CFG_WCEN4_Pos (1UL) /*!< WCEN4 (Bit 1) */
|
|
#define ADC_SL4CFG_WCEN4_Msk (0x2UL) /*!< WCEN4 (Bitfield-Mask: 0x01) */
|
|
#define ADC_SL4CFG_SLEN4_Pos (0UL) /*!< SLEN4 (Bit 0) */
|
|
#define ADC_SL4CFG_SLEN4_Msk (0x1UL) /*!< SLEN4 (Bitfield-Mask: 0x01) */
|
|
/* ======================================================== SL5CFG ========================================================= */
|
|
#define ADC_SL5CFG_ADSEL5_Pos (24UL) /*!< ADSEL5 (Bit 24) */
|
|
#define ADC_SL5CFG_ADSEL5_Msk (0x7000000UL) /*!< ADSEL5 (Bitfield-Mask: 0x07) */
|
|
#define ADC_SL5CFG_THSEL5_Pos (16UL) /*!< THSEL5 (Bit 16) */
|
|
#define ADC_SL5CFG_THSEL5_Msk (0x70000UL) /*!< THSEL5 (Bitfield-Mask: 0x07) */
|
|
#define ADC_SL5CFG_CHSEL5_Pos (8UL) /*!< CHSEL5 (Bit 8) */
|
|
#define ADC_SL5CFG_CHSEL5_Msk (0xf00UL) /*!< CHSEL5 (Bitfield-Mask: 0x0f) */
|
|
#define ADC_SL5CFG_WCEN5_Pos (1UL) /*!< WCEN5 (Bit 1) */
|
|
#define ADC_SL5CFG_WCEN5_Msk (0x2UL) /*!< WCEN5 (Bitfield-Mask: 0x01) */
|
|
#define ADC_SL5CFG_SLEN5_Pos (0UL) /*!< SLEN5 (Bit 0) */
|
|
#define ADC_SL5CFG_SLEN5_Msk (0x1UL) /*!< SLEN5 (Bitfield-Mask: 0x01) */
|
|
/* ======================================================== SL6CFG ========================================================= */
|
|
#define ADC_SL6CFG_ADSEL6_Pos (24UL) /*!< ADSEL6 (Bit 24) */
|
|
#define ADC_SL6CFG_ADSEL6_Msk (0x7000000UL) /*!< ADSEL6 (Bitfield-Mask: 0x07) */
|
|
#define ADC_SL6CFG_THSEL6_Pos (16UL) /*!< THSEL6 (Bit 16) */
|
|
#define ADC_SL6CFG_THSEL6_Msk (0x70000UL) /*!< THSEL6 (Bitfield-Mask: 0x07) */
|
|
#define ADC_SL6CFG_CHSEL6_Pos (8UL) /*!< CHSEL6 (Bit 8) */
|
|
#define ADC_SL6CFG_CHSEL6_Msk (0xf00UL) /*!< CHSEL6 (Bitfield-Mask: 0x0f) */
|
|
#define ADC_SL6CFG_WCEN6_Pos (1UL) /*!< WCEN6 (Bit 1) */
|
|
#define ADC_SL6CFG_WCEN6_Msk (0x2UL) /*!< WCEN6 (Bitfield-Mask: 0x01) */
|
|
#define ADC_SL6CFG_SLEN6_Pos (0UL) /*!< SLEN6 (Bit 0) */
|
|
#define ADC_SL6CFG_SLEN6_Msk (0x1UL) /*!< SLEN6 (Bitfield-Mask: 0x01) */
|
|
/* ======================================================== SL7CFG ========================================================= */
|
|
#define ADC_SL7CFG_ADSEL7_Pos (24UL) /*!< ADSEL7 (Bit 24) */
|
|
#define ADC_SL7CFG_ADSEL7_Msk (0x7000000UL) /*!< ADSEL7 (Bitfield-Mask: 0x07) */
|
|
#define ADC_SL7CFG_THSEL7_Pos (16UL) /*!< THSEL7 (Bit 16) */
|
|
#define ADC_SL7CFG_THSEL7_Msk (0x70000UL) /*!< THSEL7 (Bitfield-Mask: 0x07) */
|
|
#define ADC_SL7CFG_CHSEL7_Pos (8UL) /*!< CHSEL7 (Bit 8) */
|
|
#define ADC_SL7CFG_CHSEL7_Msk (0xf00UL) /*!< CHSEL7 (Bitfield-Mask: 0x0f) */
|
|
#define ADC_SL7CFG_WCEN7_Pos (1UL) /*!< WCEN7 (Bit 1) */
|
|
#define ADC_SL7CFG_WCEN7_Msk (0x2UL) /*!< WCEN7 (Bitfield-Mask: 0x01) */
|
|
#define ADC_SL7CFG_SLEN7_Pos (0UL) /*!< SLEN7 (Bit 0) */
|
|
#define ADC_SL7CFG_SLEN7_Msk (0x1UL) /*!< SLEN7 (Bitfield-Mask: 0x01) */
|
|
/* ========================================================= WLIM ========================================================== */
|
|
#define ADC_WLIM_ULIM_Pos (16UL) /*!< ULIM (Bit 16) */
|
|
#define ADC_WLIM_ULIM_Msk (0xffff0000UL) /*!< ULIM (Bitfield-Mask: 0xffff) */
|
|
#define ADC_WLIM_LLIM_Pos (0UL) /*!< LLIM (Bit 0) */
|
|
#define ADC_WLIM_LLIM_Msk (0xffffUL) /*!< LLIM (Bitfield-Mask: 0xffff) */
|
|
/* ========================================================= FIFO ========================================================== */
|
|
#define ADC_FIFO_RSVD_27_Pos (27UL) /*!< RSVD_27 (Bit 27) */
|
|
#define ADC_FIFO_RSVD_27_Msk (0xf8000000UL) /*!< RSVD_27 (Bitfield-Mask: 0x1f) */
|
|
#define ADC_FIFO_SLOTNUM_Pos (24UL) /*!< SLOTNUM (Bit 24) */
|
|
#define ADC_FIFO_SLOTNUM_Msk (0x7000000UL) /*!< SLOTNUM (Bitfield-Mask: 0x07) */
|
|
#define ADC_FIFO_RSVD_20_Pos (20UL) /*!< RSVD_20 (Bit 20) */
|
|
#define ADC_FIFO_RSVD_20_Msk (0xf00000UL) /*!< RSVD_20 (Bitfield-Mask: 0x0f) */
|
|
#define ADC_FIFO_COUNT_Pos (16UL) /*!< COUNT (Bit 16) */
|
|
#define ADC_FIFO_COUNT_Msk (0xf0000UL) /*!< COUNT (Bitfield-Mask: 0x0f) */
|
|
#define ADC_FIFO_DATA_Pos (0UL) /*!< DATA (Bit 0) */
|
|
#define ADC_FIFO_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */
|
|
/* ========================================================= INTEN ========================================================= */
|
|
#define ADC_INTEN_WCINC_Pos (5UL) /*!< WCINC (Bit 5) */
|
|
#define ADC_INTEN_WCINC_Msk (0x20UL) /*!< WCINC (Bitfield-Mask: 0x01) */
|
|
#define ADC_INTEN_WCEXC_Pos (4UL) /*!< WCEXC (Bit 4) */
|
|
#define ADC_INTEN_WCEXC_Msk (0x10UL) /*!< WCEXC (Bitfield-Mask: 0x01) */
|
|
#define ADC_INTEN_FIFOOVR2_Pos (3UL) /*!< FIFOOVR2 (Bit 3) */
|
|
#define ADC_INTEN_FIFOOVR2_Msk (0x8UL) /*!< FIFOOVR2 (Bitfield-Mask: 0x01) */
|
|
#define ADC_INTEN_FIFOOVR1_Pos (2UL) /*!< FIFOOVR1 (Bit 2) */
|
|
#define ADC_INTEN_FIFOOVR1_Msk (0x4UL) /*!< FIFOOVR1 (Bitfield-Mask: 0x01) */
|
|
#define ADC_INTEN_SCNCMP_Pos (1UL) /*!< SCNCMP (Bit 1) */
|
|
#define ADC_INTEN_SCNCMP_Msk (0x2UL) /*!< SCNCMP (Bitfield-Mask: 0x01) */
|
|
#define ADC_INTEN_CNVCMP_Pos (0UL) /*!< CNVCMP (Bit 0) */
|
|
#define ADC_INTEN_CNVCMP_Msk (0x1UL) /*!< CNVCMP (Bitfield-Mask: 0x01) */
|
|
/* ======================================================== INTSTAT ======================================================== */
|
|
#define ADC_INTSTAT_WCINC_Pos (5UL) /*!< WCINC (Bit 5) */
|
|
#define ADC_INTSTAT_WCINC_Msk (0x20UL) /*!< WCINC (Bitfield-Mask: 0x01) */
|
|
#define ADC_INTSTAT_WCEXC_Pos (4UL) /*!< WCEXC (Bit 4) */
|
|
#define ADC_INTSTAT_WCEXC_Msk (0x10UL) /*!< WCEXC (Bitfield-Mask: 0x01) */
|
|
#define ADC_INTSTAT_FIFOOVR2_Pos (3UL) /*!< FIFOOVR2 (Bit 3) */
|
|
#define ADC_INTSTAT_FIFOOVR2_Msk (0x8UL) /*!< FIFOOVR2 (Bitfield-Mask: 0x01) */
|
|
#define ADC_INTSTAT_FIFOOVR1_Pos (2UL) /*!< FIFOOVR1 (Bit 2) */
|
|
#define ADC_INTSTAT_FIFOOVR1_Msk (0x4UL) /*!< FIFOOVR1 (Bitfield-Mask: 0x01) */
|
|
#define ADC_INTSTAT_SCNCMP_Pos (1UL) /*!< SCNCMP (Bit 1) */
|
|
#define ADC_INTSTAT_SCNCMP_Msk (0x2UL) /*!< SCNCMP (Bitfield-Mask: 0x01) */
|
|
#define ADC_INTSTAT_CNVCMP_Pos (0UL) /*!< CNVCMP (Bit 0) */
|
|
#define ADC_INTSTAT_CNVCMP_Msk (0x1UL) /*!< CNVCMP (Bitfield-Mask: 0x01) */
|
|
/* ======================================================== INTCLR ========================================================= */
|
|
#define ADC_INTCLR_WCINC_Pos (5UL) /*!< WCINC (Bit 5) */
|
|
#define ADC_INTCLR_WCINC_Msk (0x20UL) /*!< WCINC (Bitfield-Mask: 0x01) */
|
|
#define ADC_INTCLR_WCEXC_Pos (4UL) /*!< WCEXC (Bit 4) */
|
|
#define ADC_INTCLR_WCEXC_Msk (0x10UL) /*!< WCEXC (Bitfield-Mask: 0x01) */
|
|
#define ADC_INTCLR_FIFOOVR2_Pos (3UL) /*!< FIFOOVR2 (Bit 3) */
|
|
#define ADC_INTCLR_FIFOOVR2_Msk (0x8UL) /*!< FIFOOVR2 (Bitfield-Mask: 0x01) */
|
|
#define ADC_INTCLR_FIFOOVR1_Pos (2UL) /*!< FIFOOVR1 (Bit 2) */
|
|
#define ADC_INTCLR_FIFOOVR1_Msk (0x4UL) /*!< FIFOOVR1 (Bitfield-Mask: 0x01) */
|
|
#define ADC_INTCLR_SCNCMP_Pos (1UL) /*!< SCNCMP (Bit 1) */
|
|
#define ADC_INTCLR_SCNCMP_Msk (0x2UL) /*!< SCNCMP (Bitfield-Mask: 0x01) */
|
|
#define ADC_INTCLR_CNVCMP_Pos (0UL) /*!< CNVCMP (Bit 0) */
|
|
#define ADC_INTCLR_CNVCMP_Msk (0x1UL) /*!< CNVCMP (Bitfield-Mask: 0x01) */
|
|
/* ======================================================== INTSET ========================================================= */
|
|
#define ADC_INTSET_WCINC_Pos (5UL) /*!< WCINC (Bit 5) */
|
|
#define ADC_INTSET_WCINC_Msk (0x20UL) /*!< WCINC (Bitfield-Mask: 0x01) */
|
|
#define ADC_INTSET_WCEXC_Pos (4UL) /*!< WCEXC (Bit 4) */
|
|
#define ADC_INTSET_WCEXC_Msk (0x10UL) /*!< WCEXC (Bitfield-Mask: 0x01) */
|
|
#define ADC_INTSET_FIFOOVR2_Pos (3UL) /*!< FIFOOVR2 (Bit 3) */
|
|
#define ADC_INTSET_FIFOOVR2_Msk (0x8UL) /*!< FIFOOVR2 (Bitfield-Mask: 0x01) */
|
|
#define ADC_INTSET_FIFOOVR1_Pos (2UL) /*!< FIFOOVR1 (Bit 2) */
|
|
#define ADC_INTSET_FIFOOVR1_Msk (0x4UL) /*!< FIFOOVR1 (Bitfield-Mask: 0x01) */
|
|
#define ADC_INTSET_SCNCMP_Pos (1UL) /*!< SCNCMP (Bit 1) */
|
|
#define ADC_INTSET_SCNCMP_Msk (0x2UL) /*!< SCNCMP (Bitfield-Mask: 0x01) */
|
|
#define ADC_INTSET_CNVCMP_Pos (0UL) /*!< CNVCMP (Bit 0) */
|
|
#define ADC_INTSET_CNVCMP_Msk (0x1UL) /*!< CNVCMP (Bitfield-Mask: 0x01) */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ CLKGEN ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
/* ========================================================= CALXT ========================================================= */
|
|
#define CLKGEN_CALXT_CALXT_Pos (0UL) /*!< CALXT (Bit 0) */
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#define CLKGEN_CALXT_CALXT_Msk (0x7ffUL) /*!< CALXT (Bitfield-Mask: 0x7ff) */
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/* ========================================================= CALRC ========================================================= */
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#define CLKGEN_CALRC_CALRC_Pos (0UL) /*!< CALRC (Bit 0) */
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#define CLKGEN_CALRC_CALRC_Msk (0x3ffffUL) /*!< CALRC (Bitfield-Mask: 0x3ffff) */
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/* ======================================================== ACALCTR ======================================================== */
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#define CLKGEN_ACALCTR_ACALCTR_Pos (0UL) /*!< ACALCTR (Bit 0) */
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#define CLKGEN_ACALCTR_ACALCTR_Msk (0xffffffUL) /*!< ACALCTR (Bitfield-Mask: 0xffffff) */
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/* ========================================================= OCTRL ========================================================= */
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#define CLKGEN_OCTRL_ACAL_Pos (8UL) /*!< ACAL (Bit 8) */
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#define CLKGEN_OCTRL_ACAL_Msk (0x700UL) /*!< ACAL (Bitfield-Mask: 0x07) */
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#define CLKGEN_OCTRL_OSEL_Pos (7UL) /*!< OSEL (Bit 7) */
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#define CLKGEN_OCTRL_OSEL_Msk (0x80UL) /*!< OSEL (Bitfield-Mask: 0x01) */
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#define CLKGEN_OCTRL_FOS_Pos (6UL) /*!< FOS (Bit 6) */
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#define CLKGEN_OCTRL_FOS_Msk (0x40UL) /*!< FOS (Bitfield-Mask: 0x01) */
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#define CLKGEN_OCTRL_STOPRC_Pos (1UL) /*!< STOPRC (Bit 1) */
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#define CLKGEN_OCTRL_STOPRC_Msk (0x2UL) /*!< STOPRC (Bitfield-Mask: 0x01) */
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#define CLKGEN_OCTRL_STOPXT_Pos (0UL) /*!< STOPXT (Bit 0) */
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#define CLKGEN_OCTRL_STOPXT_Msk (0x1UL) /*!< STOPXT (Bitfield-Mask: 0x01) */
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/* ======================================================== CLKOUT ========================================================= */
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#define CLKGEN_CLKOUT_CKEN_Pos (7UL) /*!< CKEN (Bit 7) */
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#define CLKGEN_CLKOUT_CKEN_Msk (0x80UL) /*!< CKEN (Bitfield-Mask: 0x01) */
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#define CLKGEN_CLKOUT_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */
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#define CLKGEN_CLKOUT_CKSEL_Msk (0x3fUL) /*!< CKSEL (Bitfield-Mask: 0x3f) */
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/* ======================================================== CLKKEY ========================================================= */
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#define CLKGEN_CLKKEY_CLKKEY_Pos (0UL) /*!< CLKKEY (Bit 0) */
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#define CLKGEN_CLKKEY_CLKKEY_Msk (0xffffffffUL) /*!< CLKKEY (Bitfield-Mask: 0xffffffff) */
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/* ========================================================= CCTRL ========================================================= */
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#define CLKGEN_CCTRL_MEMSEL_Pos (3UL) /*!< MEMSEL (Bit 3) */
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#define CLKGEN_CCTRL_MEMSEL_Msk (0x8UL) /*!< MEMSEL (Bitfield-Mask: 0x01) */
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#define CLKGEN_CCTRL_CORESEL_Pos (0UL) /*!< CORESEL (Bit 0) */
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#define CLKGEN_CCTRL_CORESEL_Msk (0x7UL) /*!< CORESEL (Bitfield-Mask: 0x07) */
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/* ======================================================== STATUS ========================================================= */
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#define CLKGEN_STATUS_OSCF_Pos (1UL) /*!< OSCF (Bit 1) */
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#define CLKGEN_STATUS_OSCF_Msk (0x2UL) /*!< OSCF (Bitfield-Mask: 0x01) */
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#define CLKGEN_STATUS_OMODE_Pos (0UL) /*!< OMODE (Bit 0) */
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#define CLKGEN_STATUS_OMODE_Msk (0x1UL) /*!< OMODE (Bitfield-Mask: 0x01) */
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/* ========================================================= HFADJ ========================================================= */
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#define CLKGEN_HFADJ_HFWARMUP_Pos (19UL) /*!< HFWARMUP (Bit 19) */
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#define CLKGEN_HFADJ_HFWARMUP_Msk (0x80000UL) /*!< HFWARMUP (Bitfield-Mask: 0x01) */
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#define CLKGEN_HFADJ_HFXTADJ_Pos (8UL) /*!< HFXTADJ (Bit 8) */
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#define CLKGEN_HFADJ_HFXTADJ_Msk (0x7ff00UL) /*!< HFXTADJ (Bitfield-Mask: 0x7ff) */
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#define CLKGEN_HFADJ_HFADJCK_Pos (1UL) /*!< HFADJCK (Bit 1) */
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#define CLKGEN_HFADJ_HFADJCK_Msk (0xeUL) /*!< HFADJCK (Bitfield-Mask: 0x07) */
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#define CLKGEN_HFADJ_HFADJEN_Pos (0UL) /*!< HFADJEN (Bit 0) */
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#define CLKGEN_HFADJ_HFADJEN_Msk (0x1UL) /*!< HFADJEN (Bitfield-Mask: 0x01) */
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/* ========================================================= HFVAL ========================================================= */
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#define CLKGEN_HFVAL_HFTUNERB_Pos (0UL) /*!< HFTUNERB (Bit 0) */
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#define CLKGEN_HFVAL_HFTUNERB_Msk (0x7ffUL) /*!< HFTUNERB (Bitfield-Mask: 0x7ff) */
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/* ======================================================== CLOCKEN ======================================================== */
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#define CLKGEN_CLOCKEN_CLOCKEN_Pos (0UL) /*!< CLOCKEN (Bit 0) */
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#define CLKGEN_CLOCKEN_CLOCKEN_Msk (0xffffffffUL) /*!< CLOCKEN (Bitfield-Mask: 0xffffffff) */
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/* ======================================================== UARTEN ========================================================= */
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#define CLKGEN_UARTEN_UARTEN_Pos (0UL) /*!< UARTEN (Bit 0) */
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#define CLKGEN_UARTEN_UARTEN_Msk (0x1UL) /*!< UARTEN (Bitfield-Mask: 0x01) */
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/* ========================================================= INTEN ========================================================= */
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#define CLKGEN_INTEN_ALM_Pos (3UL) /*!< ALM (Bit 3) */
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#define CLKGEN_INTEN_ALM_Msk (0x8UL) /*!< ALM (Bitfield-Mask: 0x01) */
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#define CLKGEN_INTEN_OF_Pos (2UL) /*!< OF (Bit 2) */
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#define CLKGEN_INTEN_OF_Msk (0x4UL) /*!< OF (Bitfield-Mask: 0x01) */
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#define CLKGEN_INTEN_ACC_Pos (1UL) /*!< ACC (Bit 1) */
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#define CLKGEN_INTEN_ACC_Msk (0x2UL) /*!< ACC (Bitfield-Mask: 0x01) */
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#define CLKGEN_INTEN_ACF_Pos (0UL) /*!< ACF (Bit 0) */
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#define CLKGEN_INTEN_ACF_Msk (0x1UL) /*!< ACF (Bitfield-Mask: 0x01) */
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/* ======================================================== INTSTAT ======================================================== */
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#define CLKGEN_INTSTAT_ALM_Pos (3UL) /*!< ALM (Bit 3) */
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#define CLKGEN_INTSTAT_ALM_Msk (0x8UL) /*!< ALM (Bitfield-Mask: 0x01) */
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#define CLKGEN_INTSTAT_OF_Pos (2UL) /*!< OF (Bit 2) */
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#define CLKGEN_INTSTAT_OF_Msk (0x4UL) /*!< OF (Bitfield-Mask: 0x01) */
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#define CLKGEN_INTSTAT_ACC_Pos (1UL) /*!< ACC (Bit 1) */
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#define CLKGEN_INTSTAT_ACC_Msk (0x2UL) /*!< ACC (Bitfield-Mask: 0x01) */
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#define CLKGEN_INTSTAT_ACF_Pos (0UL) /*!< ACF (Bit 0) */
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#define CLKGEN_INTSTAT_ACF_Msk (0x1UL) /*!< ACF (Bitfield-Mask: 0x01) */
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/* ======================================================== INTCLR ========================================================= */
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#define CLKGEN_INTCLR_ALM_Pos (3UL) /*!< ALM (Bit 3) */
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#define CLKGEN_INTCLR_ALM_Msk (0x8UL) /*!< ALM (Bitfield-Mask: 0x01) */
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#define CLKGEN_INTCLR_OF_Pos (2UL) /*!< OF (Bit 2) */
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#define CLKGEN_INTCLR_OF_Msk (0x4UL) /*!< OF (Bitfield-Mask: 0x01) */
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#define CLKGEN_INTCLR_ACC_Pos (1UL) /*!< ACC (Bit 1) */
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#define CLKGEN_INTCLR_ACC_Msk (0x2UL) /*!< ACC (Bitfield-Mask: 0x01) */
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#define CLKGEN_INTCLR_ACF_Pos (0UL) /*!< ACF (Bit 0) */
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#define CLKGEN_INTCLR_ACF_Msk (0x1UL) /*!< ACF (Bitfield-Mask: 0x01) */
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/* ======================================================== INTSET ========================================================= */
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#define CLKGEN_INTSET_ALM_Pos (3UL) /*!< ALM (Bit 3) */
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#define CLKGEN_INTSET_ALM_Msk (0x8UL) /*!< ALM (Bitfield-Mask: 0x01) */
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#define CLKGEN_INTSET_OF_Pos (2UL) /*!< OF (Bit 2) */
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#define CLKGEN_INTSET_OF_Msk (0x4UL) /*!< OF (Bitfield-Mask: 0x01) */
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#define CLKGEN_INTSET_ACC_Pos (1UL) /*!< ACC (Bit 1) */
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#define CLKGEN_INTSET_ACC_Msk (0x2UL) /*!< ACC (Bitfield-Mask: 0x01) */
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#define CLKGEN_INTSET_ACF_Pos (0UL) /*!< ACF (Bit 0) */
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#define CLKGEN_INTSET_ACF_Msk (0x1UL) /*!< ACF (Bitfield-Mask: 0x01) */
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/* =========================================================================================================================== */
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/* ================ CTIMER ================ */
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/* =========================================================================================================================== */
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/* ========================================================= TMR0 ========================================================== */
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#define CTIMER_TMR0_CTTMRB0_Pos (16UL) /*!< CTTMRB0 (Bit 16) */
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#define CTIMER_TMR0_CTTMRB0_Msk (0xffff0000UL) /*!< CTTMRB0 (Bitfield-Mask: 0xffff) */
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#define CTIMER_TMR0_CTTMRA0_Pos (0UL) /*!< CTTMRA0 (Bit 0) */
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#define CTIMER_TMR0_CTTMRA0_Msk (0xffffUL) /*!< CTTMRA0 (Bitfield-Mask: 0xffff) */
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/* ======================================================== CMPRA0 ========================================================= */
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#define CTIMER_CMPRA0_CMPR1A0_Pos (16UL) /*!< CMPR1A0 (Bit 16) */
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#define CTIMER_CMPRA0_CMPR1A0_Msk (0xffff0000UL) /*!< CMPR1A0 (Bitfield-Mask: 0xffff) */
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#define CTIMER_CMPRA0_CMPR0A0_Pos (0UL) /*!< CMPR0A0 (Bit 0) */
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#define CTIMER_CMPRA0_CMPR0A0_Msk (0xffffUL) /*!< CMPR0A0 (Bitfield-Mask: 0xffff) */
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/* ======================================================== CMPRB0 ========================================================= */
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#define CTIMER_CMPRB0_CMPR1B0_Pos (16UL) /*!< CMPR1B0 (Bit 16) */
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#define CTIMER_CMPRB0_CMPR1B0_Msk (0xffff0000UL) /*!< CMPR1B0 (Bitfield-Mask: 0xffff) */
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#define CTIMER_CMPRB0_CMPR0B0_Pos (0UL) /*!< CMPR0B0 (Bit 0) */
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#define CTIMER_CMPRB0_CMPR0B0_Msk (0xffffUL) /*!< CMPR0B0 (Bitfield-Mask: 0xffff) */
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/* ========================================================= CTRL0 ========================================================= */
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#define CTIMER_CTRL0_CTLINK0_Pos (31UL) /*!< CTLINK0 (Bit 31) */
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#define CTIMER_CTRL0_CTLINK0_Msk (0x80000000UL) /*!< CTLINK0 (Bitfield-Mask: 0x01) */
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#define CTIMER_CTRL0_TMRB0POL_Pos (28UL) /*!< TMRB0POL (Bit 28) */
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#define CTIMER_CTRL0_TMRB0POL_Msk (0x10000000UL) /*!< TMRB0POL (Bitfield-Mask: 0x01) */
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#define CTIMER_CTRL0_TMRB0CLR_Pos (27UL) /*!< TMRB0CLR (Bit 27) */
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#define CTIMER_CTRL0_TMRB0CLR_Msk (0x8000000UL) /*!< TMRB0CLR (Bitfield-Mask: 0x01) */
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#define CTIMER_CTRL0_TMRB0PE_Pos (26UL) /*!< TMRB0PE (Bit 26) */
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#define CTIMER_CTRL0_TMRB0PE_Msk (0x4000000UL) /*!< TMRB0PE (Bitfield-Mask: 0x01) */
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#define CTIMER_CTRL0_TMRB0IE_Pos (25UL) /*!< TMRB0IE (Bit 25) */
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#define CTIMER_CTRL0_TMRB0IE_Msk (0x2000000UL) /*!< TMRB0IE (Bitfield-Mask: 0x01) */
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#define CTIMER_CTRL0_TMRB0FN_Pos (22UL) /*!< TMRB0FN (Bit 22) */
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#define CTIMER_CTRL0_TMRB0FN_Msk (0x1c00000UL) /*!< TMRB0FN (Bitfield-Mask: 0x07) */
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#define CTIMER_CTRL0_TMRB0CLK_Pos (17UL) /*!< TMRB0CLK (Bit 17) */
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#define CTIMER_CTRL0_TMRB0CLK_Msk (0x3e0000UL) /*!< TMRB0CLK (Bitfield-Mask: 0x1f) */
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#define CTIMER_CTRL0_TMRB0EN_Pos (16UL) /*!< TMRB0EN (Bit 16) */
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#define CTIMER_CTRL0_TMRB0EN_Msk (0x10000UL) /*!< TMRB0EN (Bitfield-Mask: 0x01) */
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#define CTIMER_CTRL0_TMRA0POL_Pos (12UL) /*!< TMRA0POL (Bit 12) */
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#define CTIMER_CTRL0_TMRA0POL_Msk (0x1000UL) /*!< TMRA0POL (Bitfield-Mask: 0x01) */
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#define CTIMER_CTRL0_TMRA0CLR_Pos (11UL) /*!< TMRA0CLR (Bit 11) */
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#define CTIMER_CTRL0_TMRA0CLR_Msk (0x800UL) /*!< TMRA0CLR (Bitfield-Mask: 0x01) */
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#define CTIMER_CTRL0_TMRA0PE_Pos (10UL) /*!< TMRA0PE (Bit 10) */
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#define CTIMER_CTRL0_TMRA0PE_Msk (0x400UL) /*!< TMRA0PE (Bitfield-Mask: 0x01) */
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#define CTIMER_CTRL0_TMRA0IE_Pos (9UL) /*!< TMRA0IE (Bit 9) */
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#define CTIMER_CTRL0_TMRA0IE_Msk (0x200UL) /*!< TMRA0IE (Bitfield-Mask: 0x01) */
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#define CTIMER_CTRL0_TMRA0FN_Pos (6UL) /*!< TMRA0FN (Bit 6) */
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#define CTIMER_CTRL0_TMRA0FN_Msk (0x1c0UL) /*!< TMRA0FN (Bitfield-Mask: 0x07) */
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#define CTIMER_CTRL0_TMRA0CLK_Pos (1UL) /*!< TMRA0CLK (Bit 1) */
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#define CTIMER_CTRL0_TMRA0CLK_Msk (0x3eUL) /*!< TMRA0CLK (Bitfield-Mask: 0x1f) */
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#define CTIMER_CTRL0_TMRA0EN_Pos (0UL) /*!< TMRA0EN (Bit 0) */
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#define CTIMER_CTRL0_TMRA0EN_Msk (0x1UL) /*!< TMRA0EN (Bitfield-Mask: 0x01) */
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/* ========================================================= TMR1 ========================================================== */
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#define CTIMER_TMR1_CTTMRB1_Pos (16UL) /*!< CTTMRB1 (Bit 16) */
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#define CTIMER_TMR1_CTTMRB1_Msk (0xffff0000UL) /*!< CTTMRB1 (Bitfield-Mask: 0xffff) */
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#define CTIMER_TMR1_CTTMRA1_Pos (0UL) /*!< CTTMRA1 (Bit 0) */
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#define CTIMER_TMR1_CTTMRA1_Msk (0xffffUL) /*!< CTTMRA1 (Bitfield-Mask: 0xffff) */
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/* ======================================================== CMPRA1 ========================================================= */
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#define CTIMER_CMPRA1_CMPR1A1_Pos (16UL) /*!< CMPR1A1 (Bit 16) */
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#define CTIMER_CMPRA1_CMPR1A1_Msk (0xffff0000UL) /*!< CMPR1A1 (Bitfield-Mask: 0xffff) */
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#define CTIMER_CMPRA1_CMPR0A1_Pos (0UL) /*!< CMPR0A1 (Bit 0) */
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#define CTIMER_CMPRA1_CMPR0A1_Msk (0xffffUL) /*!< CMPR0A1 (Bitfield-Mask: 0xffff) */
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/* ======================================================== CMPRB1 ========================================================= */
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#define CTIMER_CMPRB1_CMPR1B1_Pos (16UL) /*!< CMPR1B1 (Bit 16) */
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#define CTIMER_CMPRB1_CMPR1B1_Msk (0xffff0000UL) /*!< CMPR1B1 (Bitfield-Mask: 0xffff) */
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#define CTIMER_CMPRB1_CMPR0B1_Pos (0UL) /*!< CMPR0B1 (Bit 0) */
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#define CTIMER_CMPRB1_CMPR0B1_Msk (0xffffUL) /*!< CMPR0B1 (Bitfield-Mask: 0xffff) */
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/* ========================================================= CTRL1 ========================================================= */
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#define CTIMER_CTRL1_CTLINK1_Pos (31UL) /*!< CTLINK1 (Bit 31) */
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#define CTIMER_CTRL1_CTLINK1_Msk (0x80000000UL) /*!< CTLINK1 (Bitfield-Mask: 0x01) */
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#define CTIMER_CTRL1_TMRB1POL_Pos (28UL) /*!< TMRB1POL (Bit 28) */
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#define CTIMER_CTRL1_TMRB1POL_Msk (0x10000000UL) /*!< TMRB1POL (Bitfield-Mask: 0x01) */
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#define CTIMER_CTRL1_TMRB1CLR_Pos (27UL) /*!< TMRB1CLR (Bit 27) */
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#define CTIMER_CTRL1_TMRB1CLR_Msk (0x8000000UL) /*!< TMRB1CLR (Bitfield-Mask: 0x01) */
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#define CTIMER_CTRL1_TMRB1PE_Pos (26UL) /*!< TMRB1PE (Bit 26) */
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#define CTIMER_CTRL1_TMRB1PE_Msk (0x4000000UL) /*!< TMRB1PE (Bitfield-Mask: 0x01) */
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#define CTIMER_CTRL1_TMRB1IE_Pos (25UL) /*!< TMRB1IE (Bit 25) */
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#define CTIMER_CTRL1_TMRB1IE_Msk (0x2000000UL) /*!< TMRB1IE (Bitfield-Mask: 0x01) */
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#define CTIMER_CTRL1_TMRB1FN_Pos (22UL) /*!< TMRB1FN (Bit 22) */
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#define CTIMER_CTRL1_TMRB1FN_Msk (0x1c00000UL) /*!< TMRB1FN (Bitfield-Mask: 0x07) */
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#define CTIMER_CTRL1_TMRB1CLK_Pos (17UL) /*!< TMRB1CLK (Bit 17) */
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#define CTIMER_CTRL1_TMRB1CLK_Msk (0x3e0000UL) /*!< TMRB1CLK (Bitfield-Mask: 0x1f) */
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#define CTIMER_CTRL1_TMRB1EN_Pos (16UL) /*!< TMRB1EN (Bit 16) */
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#define CTIMER_CTRL1_TMRB1EN_Msk (0x10000UL) /*!< TMRB1EN (Bitfield-Mask: 0x01) */
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|
#define CTIMER_CTRL1_TMRA1POL_Pos (12UL) /*!< TMRA1POL (Bit 12) */
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#define CTIMER_CTRL1_TMRA1POL_Msk (0x1000UL) /*!< TMRA1POL (Bitfield-Mask: 0x01) */
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#define CTIMER_CTRL1_TMRA1CLR_Pos (11UL) /*!< TMRA1CLR (Bit 11) */
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#define CTIMER_CTRL1_TMRA1CLR_Msk (0x800UL) /*!< TMRA1CLR (Bitfield-Mask: 0x01) */
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#define CTIMER_CTRL1_TMRA1PE_Pos (10UL) /*!< TMRA1PE (Bit 10) */
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#define CTIMER_CTRL1_TMRA1PE_Msk (0x400UL) /*!< TMRA1PE (Bitfield-Mask: 0x01) */
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|
#define CTIMER_CTRL1_TMRA1IE_Pos (9UL) /*!< TMRA1IE (Bit 9) */
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|
#define CTIMER_CTRL1_TMRA1IE_Msk (0x200UL) /*!< TMRA1IE (Bitfield-Mask: 0x01) */
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|
#define CTIMER_CTRL1_TMRA1FN_Pos (6UL) /*!< TMRA1FN (Bit 6) */
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|
#define CTIMER_CTRL1_TMRA1FN_Msk (0x1c0UL) /*!< TMRA1FN (Bitfield-Mask: 0x07) */
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|
#define CTIMER_CTRL1_TMRA1CLK_Pos (1UL) /*!< TMRA1CLK (Bit 1) */
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#define CTIMER_CTRL1_TMRA1CLK_Msk (0x3eUL) /*!< TMRA1CLK (Bitfield-Mask: 0x1f) */
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|
#define CTIMER_CTRL1_TMRA1EN_Pos (0UL) /*!< TMRA1EN (Bit 0) */
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|
#define CTIMER_CTRL1_TMRA1EN_Msk (0x1UL) /*!< TMRA1EN (Bitfield-Mask: 0x01) */
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|
/* ========================================================= TMR2 ========================================================== */
|
|
#define CTIMER_TMR2_CTTMRB2_Pos (16UL) /*!< CTTMRB2 (Bit 16) */
|
|
#define CTIMER_TMR2_CTTMRB2_Msk (0xffff0000UL) /*!< CTTMRB2 (Bitfield-Mask: 0xffff) */
|
|
#define CTIMER_TMR2_CTTMRA2_Pos (0UL) /*!< CTTMRA2 (Bit 0) */
|
|
#define CTIMER_TMR2_CTTMRA2_Msk (0xffffUL) /*!< CTTMRA2 (Bitfield-Mask: 0xffff) */
|
|
/* ======================================================== CMPRA2 ========================================================= */
|
|
#define CTIMER_CMPRA2_CMPR1A2_Pos (16UL) /*!< CMPR1A2 (Bit 16) */
|
|
#define CTIMER_CMPRA2_CMPR1A2_Msk (0xffff0000UL) /*!< CMPR1A2 (Bitfield-Mask: 0xffff) */
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|
#define CTIMER_CMPRA2_CMPR0A2_Pos (0UL) /*!< CMPR0A2 (Bit 0) */
|
|
#define CTIMER_CMPRA2_CMPR0A2_Msk (0xffffUL) /*!< CMPR0A2 (Bitfield-Mask: 0xffff) */
|
|
/* ======================================================== CMPRB2 ========================================================= */
|
|
#define CTIMER_CMPRB2_CMPR1B2_Pos (16UL) /*!< CMPR1B2 (Bit 16) */
|
|
#define CTIMER_CMPRB2_CMPR1B2_Msk (0xffff0000UL) /*!< CMPR1B2 (Bitfield-Mask: 0xffff) */
|
|
#define CTIMER_CMPRB2_CMPR0B2_Pos (0UL) /*!< CMPR0B2 (Bit 0) */
|
|
#define CTIMER_CMPRB2_CMPR0B2_Msk (0xffffUL) /*!< CMPR0B2 (Bitfield-Mask: 0xffff) */
|
|
/* ========================================================= CTRL2 ========================================================= */
|
|
#define CTIMER_CTRL2_CTLINK2_Pos (31UL) /*!< CTLINK2 (Bit 31) */
|
|
#define CTIMER_CTRL2_CTLINK2_Msk (0x80000000UL) /*!< CTLINK2 (Bitfield-Mask: 0x01) */
|
|
#define CTIMER_CTRL2_TMRB2POL_Pos (28UL) /*!< TMRB2POL (Bit 28) */
|
|
#define CTIMER_CTRL2_TMRB2POL_Msk (0x10000000UL) /*!< TMRB2POL (Bitfield-Mask: 0x01) */
|
|
#define CTIMER_CTRL2_TMRB2CLR_Pos (27UL) /*!< TMRB2CLR (Bit 27) */
|
|
#define CTIMER_CTRL2_TMRB2CLR_Msk (0x8000000UL) /*!< TMRB2CLR (Bitfield-Mask: 0x01) */
|
|
#define CTIMER_CTRL2_TMRB2PE_Pos (26UL) /*!< TMRB2PE (Bit 26) */
|
|
#define CTIMER_CTRL2_TMRB2PE_Msk (0x4000000UL) /*!< TMRB2PE (Bitfield-Mask: 0x01) */
|
|
#define CTIMER_CTRL2_TMRB2IE_Pos (25UL) /*!< TMRB2IE (Bit 25) */
|
|
#define CTIMER_CTRL2_TMRB2IE_Msk (0x2000000UL) /*!< TMRB2IE (Bitfield-Mask: 0x01) */
|
|
#define CTIMER_CTRL2_TMRB2FN_Pos (22UL) /*!< TMRB2FN (Bit 22) */
|
|
#define CTIMER_CTRL2_TMRB2FN_Msk (0x1c00000UL) /*!< TMRB2FN (Bitfield-Mask: 0x07) */
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#define CTIMER_CTRL2_TMRB2CLK_Pos (17UL) /*!< TMRB2CLK (Bit 17) */
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#define CTIMER_CTRL2_TMRB2CLK_Msk (0x3e0000UL) /*!< TMRB2CLK (Bitfield-Mask: 0x1f) */
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#define CTIMER_CTRL2_TMRB2EN_Pos (16UL) /*!< TMRB2EN (Bit 16) */
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#define CTIMER_CTRL2_TMRB2EN_Msk (0x10000UL) /*!< TMRB2EN (Bitfield-Mask: 0x01) */
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#define CTIMER_CTRL2_TMRA2POL_Pos (12UL) /*!< TMRA2POL (Bit 12) */
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#define CTIMER_CTRL2_TMRA2POL_Msk (0x1000UL) /*!< TMRA2POL (Bitfield-Mask: 0x01) */
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#define CTIMER_CTRL2_TMRA2CLR_Pos (11UL) /*!< TMRA2CLR (Bit 11) */
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#define CTIMER_CTRL2_TMRA2CLR_Msk (0x800UL) /*!< TMRA2CLR (Bitfield-Mask: 0x01) */
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#define CTIMER_CTRL2_TMRA2PE_Pos (10UL) /*!< TMRA2PE (Bit 10) */
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#define CTIMER_CTRL2_TMRA2PE_Msk (0x400UL) /*!< TMRA2PE (Bitfield-Mask: 0x01) */
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#define CTIMER_CTRL2_TMRA2IE_Pos (9UL) /*!< TMRA2IE (Bit 9) */
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#define CTIMER_CTRL2_TMRA2IE_Msk (0x200UL) /*!< TMRA2IE (Bitfield-Mask: 0x01) */
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#define CTIMER_CTRL2_TMRA2FN_Pos (6UL) /*!< TMRA2FN (Bit 6) */
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#define CTIMER_CTRL2_TMRA2FN_Msk (0x1c0UL) /*!< TMRA2FN (Bitfield-Mask: 0x07) */
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#define CTIMER_CTRL2_TMRA2CLK_Pos (1UL) /*!< TMRA2CLK (Bit 1) */
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#define CTIMER_CTRL2_TMRA2CLK_Msk (0x3eUL) /*!< TMRA2CLK (Bitfield-Mask: 0x1f) */
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#define CTIMER_CTRL2_TMRA2EN_Pos (0UL) /*!< TMRA2EN (Bit 0) */
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#define CTIMER_CTRL2_TMRA2EN_Msk (0x1UL) /*!< TMRA2EN (Bitfield-Mask: 0x01) */
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/* ========================================================= TMR3 ========================================================== */
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#define CTIMER_TMR3_CTTMRB3_Pos (16UL) /*!< CTTMRB3 (Bit 16) */
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#define CTIMER_TMR3_CTTMRB3_Msk (0xffff0000UL) /*!< CTTMRB3 (Bitfield-Mask: 0xffff) */
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#define CTIMER_TMR3_CTTMRA3_Pos (0UL) /*!< CTTMRA3 (Bit 0) */
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#define CTIMER_TMR3_CTTMRA3_Msk (0xffffUL) /*!< CTTMRA3 (Bitfield-Mask: 0xffff) */
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/* ======================================================== CMPRA3 ========================================================= */
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#define CTIMER_CMPRA3_CMPR1A3_Pos (16UL) /*!< CMPR1A3 (Bit 16) */
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#define CTIMER_CMPRA3_CMPR1A3_Msk (0xffff0000UL) /*!< CMPR1A3 (Bitfield-Mask: 0xffff) */
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#define CTIMER_CMPRA3_CMPR0A3_Pos (0UL) /*!< CMPR0A3 (Bit 0) */
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#define CTIMER_CMPRA3_CMPR0A3_Msk (0xffffUL) /*!< CMPR0A3 (Bitfield-Mask: 0xffff) */
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/* ======================================================== CMPRB3 ========================================================= */
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#define CTIMER_CMPRB3_CMPR1B3_Pos (16UL) /*!< CMPR1B3 (Bit 16) */
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#define CTIMER_CMPRB3_CMPR1B3_Msk (0xffff0000UL) /*!< CMPR1B3 (Bitfield-Mask: 0xffff) */
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#define CTIMER_CMPRB3_CMPR0B3_Pos (0UL) /*!< CMPR0B3 (Bit 0) */
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#define CTIMER_CMPRB3_CMPR0B3_Msk (0xffffUL) /*!< CMPR0B3 (Bitfield-Mask: 0xffff) */
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/* ========================================================= CTRL3 ========================================================= */
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#define CTIMER_CTRL3_CTLINK3_Pos (31UL) /*!< CTLINK3 (Bit 31) */
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#define CTIMER_CTRL3_CTLINK3_Msk (0x80000000UL) /*!< CTLINK3 (Bitfield-Mask: 0x01) */
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#define CTIMER_CTRL3_TMRB3POL_Pos (28UL) /*!< TMRB3POL (Bit 28) */
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#define CTIMER_CTRL3_TMRB3POL_Msk (0x10000000UL) /*!< TMRB3POL (Bitfield-Mask: 0x01) */
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#define CTIMER_CTRL3_TMRB3CLR_Pos (27UL) /*!< TMRB3CLR (Bit 27) */
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#define CTIMER_CTRL3_TMRB3CLR_Msk (0x8000000UL) /*!< TMRB3CLR (Bitfield-Mask: 0x01) */
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#define CTIMER_CTRL3_TMRB3PE_Pos (26UL) /*!< TMRB3PE (Bit 26) */
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#define CTIMER_CTRL3_TMRB3PE_Msk (0x4000000UL) /*!< TMRB3PE (Bitfield-Mask: 0x01) */
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#define CTIMER_CTRL3_TMRB3IE_Pos (25UL) /*!< TMRB3IE (Bit 25) */
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#define CTIMER_CTRL3_TMRB3IE_Msk (0x2000000UL) /*!< TMRB3IE (Bitfield-Mask: 0x01) */
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#define CTIMER_CTRL3_TMRB3FN_Pos (22UL) /*!< TMRB3FN (Bit 22) */
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#define CTIMER_CTRL3_TMRB3FN_Msk (0x1c00000UL) /*!< TMRB3FN (Bitfield-Mask: 0x07) */
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#define CTIMER_CTRL3_TMRB3CLK_Pos (17UL) /*!< TMRB3CLK (Bit 17) */
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#define CTIMER_CTRL3_TMRB3CLK_Msk (0x3e0000UL) /*!< TMRB3CLK (Bitfield-Mask: 0x1f) */
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#define CTIMER_CTRL3_TMRB3EN_Pos (16UL) /*!< TMRB3EN (Bit 16) */
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#define CTIMER_CTRL3_TMRB3EN_Msk (0x10000UL) /*!< TMRB3EN (Bitfield-Mask: 0x01) */
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#define CTIMER_CTRL3_ADCEN_Pos (15UL) /*!< ADCEN (Bit 15) */
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#define CTIMER_CTRL3_ADCEN_Msk (0x8000UL) /*!< ADCEN (Bitfield-Mask: 0x01) */
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#define CTIMER_CTRL3_TMRA3POL_Pos (12UL) /*!< TMRA3POL (Bit 12) */
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#define CTIMER_CTRL3_TMRA3POL_Msk (0x1000UL) /*!< TMRA3POL (Bitfield-Mask: 0x01) */
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#define CTIMER_CTRL3_TMRA3CLR_Pos (11UL) /*!< TMRA3CLR (Bit 11) */
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#define CTIMER_CTRL3_TMRA3CLR_Msk (0x800UL) /*!< TMRA3CLR (Bitfield-Mask: 0x01) */
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#define CTIMER_CTRL3_TMRA3PE_Pos (10UL) /*!< TMRA3PE (Bit 10) */
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#define CTIMER_CTRL3_TMRA3PE_Msk (0x400UL) /*!< TMRA3PE (Bitfield-Mask: 0x01) */
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#define CTIMER_CTRL3_TMRA3IE_Pos (9UL) /*!< TMRA3IE (Bit 9) */
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#define CTIMER_CTRL3_TMRA3IE_Msk (0x200UL) /*!< TMRA3IE (Bitfield-Mask: 0x01) */
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#define CTIMER_CTRL3_TMRA3FN_Pos (6UL) /*!< TMRA3FN (Bit 6) */
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#define CTIMER_CTRL3_TMRA3FN_Msk (0x1c0UL) /*!< TMRA3FN (Bitfield-Mask: 0x07) */
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#define CTIMER_CTRL3_TMRA3CLK_Pos (1UL) /*!< TMRA3CLK (Bit 1) */
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#define CTIMER_CTRL3_TMRA3CLK_Msk (0x3eUL) /*!< TMRA3CLK (Bitfield-Mask: 0x1f) */
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#define CTIMER_CTRL3_TMRA3EN_Pos (0UL) /*!< TMRA3EN (Bit 0) */
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#define CTIMER_CTRL3_TMRA3EN_Msk (0x1UL) /*!< TMRA3EN (Bitfield-Mask: 0x01) */
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/* ========================================================= INTEN ========================================================= */
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#define CTIMER_INTEN_CTMRB3INT_Pos (7UL) /*!< CTMRB3INT (Bit 7) */
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#define CTIMER_INTEN_CTMRB3INT_Msk (0x80UL) /*!< CTMRB3INT (Bitfield-Mask: 0x01) */
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#define CTIMER_INTEN_CTMRA3INT_Pos (6UL) /*!< CTMRA3INT (Bit 6) */
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#define CTIMER_INTEN_CTMRA3INT_Msk (0x40UL) /*!< CTMRA3INT (Bitfield-Mask: 0x01) */
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#define CTIMER_INTEN_CTMRB2INT_Pos (5UL) /*!< CTMRB2INT (Bit 5) */
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#define CTIMER_INTEN_CTMRB2INT_Msk (0x20UL) /*!< CTMRB2INT (Bitfield-Mask: 0x01) */
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#define CTIMER_INTEN_CTMRA2INT_Pos (4UL) /*!< CTMRA2INT (Bit 4) */
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#define CTIMER_INTEN_CTMRA2INT_Msk (0x10UL) /*!< CTMRA2INT (Bitfield-Mask: 0x01) */
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#define CTIMER_INTEN_CTMRB1INT_Pos (3UL) /*!< CTMRB1INT (Bit 3) */
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#define CTIMER_INTEN_CTMRB1INT_Msk (0x8UL) /*!< CTMRB1INT (Bitfield-Mask: 0x01) */
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#define CTIMER_INTEN_CTMRA1INT_Pos (2UL) /*!< CTMRA1INT (Bit 2) */
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#define CTIMER_INTEN_CTMRA1INT_Msk (0x4UL) /*!< CTMRA1INT (Bitfield-Mask: 0x01) */
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#define CTIMER_INTEN_CTMRB0INT_Pos (1UL) /*!< CTMRB0INT (Bit 1) */
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#define CTIMER_INTEN_CTMRB0INT_Msk (0x2UL) /*!< CTMRB0INT (Bitfield-Mask: 0x01) */
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#define CTIMER_INTEN_CTMRA0INT_Pos (0UL) /*!< CTMRA0INT (Bit 0) */
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#define CTIMER_INTEN_CTMRA0INT_Msk (0x1UL) /*!< CTMRA0INT (Bitfield-Mask: 0x01) */
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/* ======================================================== INTSTAT ======================================================== */
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#define CTIMER_INTSTAT_CTMRB3INT_Pos (7UL) /*!< CTMRB3INT (Bit 7) */
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#define CTIMER_INTSTAT_CTMRB3INT_Msk (0x80UL) /*!< CTMRB3INT (Bitfield-Mask: 0x01) */
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#define CTIMER_INTSTAT_CTMRA3INT_Pos (6UL) /*!< CTMRA3INT (Bit 6) */
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#define CTIMER_INTSTAT_CTMRA3INT_Msk (0x40UL) /*!< CTMRA3INT (Bitfield-Mask: 0x01) */
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#define CTIMER_INTSTAT_CTMRB2INT_Pos (5UL) /*!< CTMRB2INT (Bit 5) */
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#define CTIMER_INTSTAT_CTMRB2INT_Msk (0x20UL) /*!< CTMRB2INT (Bitfield-Mask: 0x01) */
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#define CTIMER_INTSTAT_CTMRA2INT_Pos (4UL) /*!< CTMRA2INT (Bit 4) */
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#define CTIMER_INTSTAT_CTMRA2INT_Msk (0x10UL) /*!< CTMRA2INT (Bitfield-Mask: 0x01) */
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#define CTIMER_INTSTAT_CTMRB1INT_Pos (3UL) /*!< CTMRB1INT (Bit 3) */
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#define CTIMER_INTSTAT_CTMRB1INT_Msk (0x8UL) /*!< CTMRB1INT (Bitfield-Mask: 0x01) */
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#define CTIMER_INTSTAT_CTMRA1INT_Pos (2UL) /*!< CTMRA1INT (Bit 2) */
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#define CTIMER_INTSTAT_CTMRA1INT_Msk (0x4UL) /*!< CTMRA1INT (Bitfield-Mask: 0x01) */
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#define CTIMER_INTSTAT_CTMRB0INT_Pos (1UL) /*!< CTMRB0INT (Bit 1) */
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#define CTIMER_INTSTAT_CTMRB0INT_Msk (0x2UL) /*!< CTMRB0INT (Bitfield-Mask: 0x01) */
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#define CTIMER_INTSTAT_CTMRA0INT_Pos (0UL) /*!< CTMRA0INT (Bit 0) */
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#define CTIMER_INTSTAT_CTMRA0INT_Msk (0x1UL) /*!< CTMRA0INT (Bitfield-Mask: 0x01) */
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/* ======================================================== INTCLR ========================================================= */
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#define CTIMER_INTCLR_CTMRB3INT_Pos (7UL) /*!< CTMRB3INT (Bit 7) */
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#define CTIMER_INTCLR_CTMRB3INT_Msk (0x80UL) /*!< CTMRB3INT (Bitfield-Mask: 0x01) */
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#define CTIMER_INTCLR_CTMRA3INT_Pos (6UL) /*!< CTMRA3INT (Bit 6) */
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#define CTIMER_INTCLR_CTMRA3INT_Msk (0x40UL) /*!< CTMRA3INT (Bitfield-Mask: 0x01) */
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#define CTIMER_INTCLR_CTMRB2INT_Pos (5UL) /*!< CTMRB2INT (Bit 5) */
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#define CTIMER_INTCLR_CTMRB2INT_Msk (0x20UL) /*!< CTMRB2INT (Bitfield-Mask: 0x01) */
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#define CTIMER_INTCLR_CTMRA2INT_Pos (4UL) /*!< CTMRA2INT (Bit 4) */
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#define CTIMER_INTCLR_CTMRA2INT_Msk (0x10UL) /*!< CTMRA2INT (Bitfield-Mask: 0x01) */
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#define CTIMER_INTCLR_CTMRB1INT_Pos (3UL) /*!< CTMRB1INT (Bit 3) */
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#define CTIMER_INTCLR_CTMRB1INT_Msk (0x8UL) /*!< CTMRB1INT (Bitfield-Mask: 0x01) */
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#define CTIMER_INTCLR_CTMRA1INT_Pos (2UL) /*!< CTMRA1INT (Bit 2) */
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#define CTIMER_INTCLR_CTMRA1INT_Msk (0x4UL) /*!< CTMRA1INT (Bitfield-Mask: 0x01) */
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#define CTIMER_INTCLR_CTMRB0INT_Pos (1UL) /*!< CTMRB0INT (Bit 1) */
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#define CTIMER_INTCLR_CTMRB0INT_Msk (0x2UL) /*!< CTMRB0INT (Bitfield-Mask: 0x01) */
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#define CTIMER_INTCLR_CTMRA0INT_Pos (0UL) /*!< CTMRA0INT (Bit 0) */
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#define CTIMER_INTCLR_CTMRA0INT_Msk (0x1UL) /*!< CTMRA0INT (Bitfield-Mask: 0x01) */
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/* ======================================================== INTSET ========================================================= */
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#define CTIMER_INTSET_CTMRB3INT_Pos (7UL) /*!< CTMRB3INT (Bit 7) */
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#define CTIMER_INTSET_CTMRB3INT_Msk (0x80UL) /*!< CTMRB3INT (Bitfield-Mask: 0x01) */
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#define CTIMER_INTSET_CTMRA3INT_Pos (6UL) /*!< CTMRA3INT (Bit 6) */
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#define CTIMER_INTSET_CTMRA3INT_Msk (0x40UL) /*!< CTMRA3INT (Bitfield-Mask: 0x01) */
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#define CTIMER_INTSET_CTMRB2INT_Pos (5UL) /*!< CTMRB2INT (Bit 5) */
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#define CTIMER_INTSET_CTMRB2INT_Msk (0x20UL) /*!< CTMRB2INT (Bitfield-Mask: 0x01) */
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#define CTIMER_INTSET_CTMRA2INT_Pos (4UL) /*!< CTMRA2INT (Bit 4) */
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#define CTIMER_INTSET_CTMRA2INT_Msk (0x10UL) /*!< CTMRA2INT (Bitfield-Mask: 0x01) */
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#define CTIMER_INTSET_CTMRB1INT_Pos (3UL) /*!< CTMRB1INT (Bit 3) */
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#define CTIMER_INTSET_CTMRB1INT_Msk (0x8UL) /*!< CTMRB1INT (Bitfield-Mask: 0x01) */
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#define CTIMER_INTSET_CTMRA1INT_Pos (2UL) /*!< CTMRA1INT (Bit 2) */
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#define CTIMER_INTSET_CTMRA1INT_Msk (0x4UL) /*!< CTMRA1INT (Bitfield-Mask: 0x01) */
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#define CTIMER_INTSET_CTMRB0INT_Pos (1UL) /*!< CTMRB0INT (Bit 1) */
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#define CTIMER_INTSET_CTMRB0INT_Msk (0x2UL) /*!< CTMRB0INT (Bitfield-Mask: 0x01) */
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#define CTIMER_INTSET_CTMRA0INT_Pos (0UL) /*!< CTMRA0INT (Bit 0) */
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#define CTIMER_INTSET_CTMRA0INT_Msk (0x1UL) /*!< CTMRA0INT (Bitfield-Mask: 0x01) */
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/* =========================================================================================================================== */
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/* ================ GPIO ================ */
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/* =========================================================================================================================== */
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/* ======================================================== PADREGA ======================================================== */
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#define GPIO_PADREGA_PAD3PWRUP_Pos (31UL) /*!< PAD3PWRUP (Bit 31) */
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#define GPIO_PADREGA_PAD3PWRUP_Msk (0x80000000UL) /*!< PAD3PWRUP (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGA_PAD3FNCSEL_Pos (27UL) /*!< PAD3FNCSEL (Bit 27) */
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#define GPIO_PADREGA_PAD3FNCSEL_Msk (0x38000000UL) /*!< PAD3FNCSEL (Bitfield-Mask: 0x07) */
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#define GPIO_PADREGA_PAD3STRNG_Pos (26UL) /*!< PAD3STRNG (Bit 26) */
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#define GPIO_PADREGA_PAD3STRNG_Msk (0x4000000UL) /*!< PAD3STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGA_PAD3INPEN_Pos (25UL) /*!< PAD3INPEN (Bit 25) */
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#define GPIO_PADREGA_PAD3INPEN_Msk (0x2000000UL) /*!< PAD3INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGA_PAD3PULL_Pos (24UL) /*!< PAD3PULL (Bit 24) */
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#define GPIO_PADREGA_PAD3PULL_Msk (0x1000000UL) /*!< PAD3PULL (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGA_PAD2FNCSEL_Pos (19UL) /*!< PAD2FNCSEL (Bit 19) */
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#define GPIO_PADREGA_PAD2FNCSEL_Msk (0x380000UL) /*!< PAD2FNCSEL (Bitfield-Mask: 0x07) */
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#define GPIO_PADREGA_PAD2STRNG_Pos (18UL) /*!< PAD2STRNG (Bit 18) */
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#define GPIO_PADREGA_PAD2STRNG_Msk (0x40000UL) /*!< PAD2STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGA_PAD2INPEN_Pos (17UL) /*!< PAD2INPEN (Bit 17) */
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#define GPIO_PADREGA_PAD2INPEN_Msk (0x20000UL) /*!< PAD2INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGA_PAD2PULL_Pos (16UL) /*!< PAD2PULL (Bit 16) */
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#define GPIO_PADREGA_PAD2PULL_Msk (0x10000UL) /*!< PAD2PULL (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGA_PAD1FNCSEL_Pos (11UL) /*!< PAD1FNCSEL (Bit 11) */
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#define GPIO_PADREGA_PAD1FNCSEL_Msk (0x3800UL) /*!< PAD1FNCSEL (Bitfield-Mask: 0x07) */
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#define GPIO_PADREGA_PAD1STRNG_Pos (10UL) /*!< PAD1STRNG (Bit 10) */
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#define GPIO_PADREGA_PAD1STRNG_Msk (0x400UL) /*!< PAD1STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGA_PAD1INPEN_Pos (9UL) /*!< PAD1INPEN (Bit 9) */
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#define GPIO_PADREGA_PAD1INPEN_Msk (0x200UL) /*!< PAD1INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGA_PAD1PULL_Pos (8UL) /*!< PAD1PULL (Bit 8) */
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#define GPIO_PADREGA_PAD1PULL_Msk (0x100UL) /*!< PAD1PULL (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGA_PAD0FNCSEL_Pos (3UL) /*!< PAD0FNCSEL (Bit 3) */
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#define GPIO_PADREGA_PAD0FNCSEL_Msk (0x38UL) /*!< PAD0FNCSEL (Bitfield-Mask: 0x07) */
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#define GPIO_PADREGA_PAD0STRNG_Pos (2UL) /*!< PAD0STRNG (Bit 2) */
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#define GPIO_PADREGA_PAD0STRNG_Msk (0x4UL) /*!< PAD0STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGA_PAD0INPEN_Pos (1UL) /*!< PAD0INPEN (Bit 1) */
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#define GPIO_PADREGA_PAD0INPEN_Msk (0x2UL) /*!< PAD0INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGA_PAD0PULL_Pos (0UL) /*!< PAD0PULL (Bit 0) */
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#define GPIO_PADREGA_PAD0PULL_Msk (0x1UL) /*!< PAD0PULL (Bitfield-Mask: 0x01) */
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/* ======================================================== PADREGB ======================================================== */
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#define GPIO_PADREGB_PAD7FNCSEL_Pos (27UL) /*!< PAD7FNCSEL (Bit 27) */
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#define GPIO_PADREGB_PAD7FNCSEL_Msk (0x38000000UL) /*!< PAD7FNCSEL (Bitfield-Mask: 0x07) */
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#define GPIO_PADREGB_PAD7STRNG_Pos (26UL) /*!< PAD7STRNG (Bit 26) */
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#define GPIO_PADREGB_PAD7STRNG_Msk (0x4000000UL) /*!< PAD7STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGB_PAD7INPEN_Pos (25UL) /*!< PAD7INPEN (Bit 25) */
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#define GPIO_PADREGB_PAD7INPEN_Msk (0x2000000UL) /*!< PAD7INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGB_PAD7PULL_Pos (24UL) /*!< PAD7PULL (Bit 24) */
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#define GPIO_PADREGB_PAD7PULL_Msk (0x1000000UL) /*!< PAD7PULL (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGB_PAD6RSEL_Pos (22UL) /*!< PAD6RSEL (Bit 22) */
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#define GPIO_PADREGB_PAD6RSEL_Msk (0xc00000UL) /*!< PAD6RSEL (Bitfield-Mask: 0x03) */
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#define GPIO_PADREGB_PAD6FNCSEL_Pos (19UL) /*!< PAD6FNCSEL (Bit 19) */
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#define GPIO_PADREGB_PAD6FNCSEL_Msk (0x380000UL) /*!< PAD6FNCSEL (Bitfield-Mask: 0x07) */
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#define GPIO_PADREGB_PAD6STRNG_Pos (18UL) /*!< PAD6STRNG (Bit 18) */
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#define GPIO_PADREGB_PAD6STRNG_Msk (0x40000UL) /*!< PAD6STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGB_PAD6INPEN_Pos (17UL) /*!< PAD6INPEN (Bit 17) */
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#define GPIO_PADREGB_PAD6INPEN_Msk (0x20000UL) /*!< PAD6INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGB_PAD6PULL_Pos (16UL) /*!< PAD6PULL (Bit 16) */
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#define GPIO_PADREGB_PAD6PULL_Msk (0x10000UL) /*!< PAD6PULL (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGB_PAD5RSEL_Pos (14UL) /*!< PAD5RSEL (Bit 14) */
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#define GPIO_PADREGB_PAD5RSEL_Msk (0xc000UL) /*!< PAD5RSEL (Bitfield-Mask: 0x03) */
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#define GPIO_PADREGB_PAD5FNCSEL_Pos (11UL) /*!< PAD5FNCSEL (Bit 11) */
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#define GPIO_PADREGB_PAD5FNCSEL_Msk (0x3800UL) /*!< PAD5FNCSEL (Bitfield-Mask: 0x07) */
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#define GPIO_PADREGB_PAD5STRNG_Pos (10UL) /*!< PAD5STRNG (Bit 10) */
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#define GPIO_PADREGB_PAD5STRNG_Msk (0x400UL) /*!< PAD5STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGB_PAD5INPEN_Pos (9UL) /*!< PAD5INPEN (Bit 9) */
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#define GPIO_PADREGB_PAD5INPEN_Msk (0x200UL) /*!< PAD5INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGB_PAD5PULL_Pos (8UL) /*!< PAD5PULL (Bit 8) */
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#define GPIO_PADREGB_PAD5PULL_Msk (0x100UL) /*!< PAD5PULL (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGB_PAD4PWRUP_Pos (7UL) /*!< PAD4PWRUP (Bit 7) */
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#define GPIO_PADREGB_PAD4PWRUP_Msk (0x80UL) /*!< PAD4PWRUP (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGB_PAD4FNCSEL_Pos (3UL) /*!< PAD4FNCSEL (Bit 3) */
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#define GPIO_PADREGB_PAD4FNCSEL_Msk (0x38UL) /*!< PAD4FNCSEL (Bitfield-Mask: 0x07) */
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#define GPIO_PADREGB_PAD4STRNG_Pos (2UL) /*!< PAD4STRNG (Bit 2) */
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#define GPIO_PADREGB_PAD4STRNG_Msk (0x4UL) /*!< PAD4STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGB_PAD4INPEN_Pos (1UL) /*!< PAD4INPEN (Bit 1) */
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#define GPIO_PADREGB_PAD4INPEN_Msk (0x2UL) /*!< PAD4INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGB_PAD4PULL_Pos (0UL) /*!< PAD4PULL (Bit 0) */
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#define GPIO_PADREGB_PAD4PULL_Msk (0x1UL) /*!< PAD4PULL (Bitfield-Mask: 0x01) */
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/* ======================================================== PADREGC ======================================================== */
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#define GPIO_PADREGC_PAD11PWRDN_Pos (30UL) /*!< PAD11PWRDN (Bit 30) */
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#define GPIO_PADREGC_PAD11PWRDN_Msk (0x40000000UL) /*!< PAD11PWRDN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGC_PAD11FNCSEL_Pos (27UL) /*!< PAD11FNCSEL (Bit 27) */
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#define GPIO_PADREGC_PAD11FNCSEL_Msk (0x18000000UL) /*!< PAD11FNCSEL (Bitfield-Mask: 0x03) */
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#define GPIO_PADREGC_PAD11STRNG_Pos (26UL) /*!< PAD11STRNG (Bit 26) */
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#define GPIO_PADREGC_PAD11STRNG_Msk (0x4000000UL) /*!< PAD11STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGC_PAD11INPEN_Pos (25UL) /*!< PAD11INPEN (Bit 25) */
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#define GPIO_PADREGC_PAD11INPEN_Msk (0x2000000UL) /*!< PAD11INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGC_PAD11PULL_Pos (24UL) /*!< PAD11PULL (Bit 24) */
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#define GPIO_PADREGC_PAD11PULL_Msk (0x1000000UL) /*!< PAD11PULL (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGC_PAD10FNCSEL_Pos (19UL) /*!< PAD10FNCSEL (Bit 19) */
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#define GPIO_PADREGC_PAD10FNCSEL_Msk (0x380000UL) /*!< PAD10FNCSEL (Bitfield-Mask: 0x07) */
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#define GPIO_PADREGC_PAD10STRNG_Pos (18UL) /*!< PAD10STRNG (Bit 18) */
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#define GPIO_PADREGC_PAD10STRNG_Msk (0x40000UL) /*!< PAD10STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGC_PAD10INPEN_Pos (17UL) /*!< PAD10INPEN (Bit 17) */
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#define GPIO_PADREGC_PAD10INPEN_Msk (0x20000UL) /*!< PAD10INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGC_PAD10PULL_Pos (16UL) /*!< PAD10PULL (Bit 16) */
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#define GPIO_PADREGC_PAD10PULL_Msk (0x10000UL) /*!< PAD10PULL (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGC_PAD9RSEL_Pos (14UL) /*!< PAD9RSEL (Bit 14) */
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#define GPIO_PADREGC_PAD9RSEL_Msk (0xc000UL) /*!< PAD9RSEL (Bitfield-Mask: 0x03) */
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#define GPIO_PADREGC_PAD9FNCSEL_Pos (11UL) /*!< PAD9FNCSEL (Bit 11) */
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#define GPIO_PADREGC_PAD9FNCSEL_Msk (0x3800UL) /*!< PAD9FNCSEL (Bitfield-Mask: 0x07) */
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#define GPIO_PADREGC_PAD9STRNG_Pos (10UL) /*!< PAD9STRNG (Bit 10) */
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#define GPIO_PADREGC_PAD9STRNG_Msk (0x400UL) /*!< PAD9STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGC_PAD9INPEN_Pos (9UL) /*!< PAD9INPEN (Bit 9) */
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#define GPIO_PADREGC_PAD9INPEN_Msk (0x200UL) /*!< PAD9INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGC_PAD9PULL_Pos (8UL) /*!< PAD9PULL (Bit 8) */
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#define GPIO_PADREGC_PAD9PULL_Msk (0x100UL) /*!< PAD9PULL (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGC_PAD8RSEL_Pos (6UL) /*!< PAD8RSEL (Bit 6) */
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#define GPIO_PADREGC_PAD8RSEL_Msk (0xc0UL) /*!< PAD8RSEL (Bitfield-Mask: 0x03) */
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#define GPIO_PADREGC_PAD8FNCSEL_Pos (3UL) /*!< PAD8FNCSEL (Bit 3) */
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#define GPIO_PADREGC_PAD8FNCSEL_Msk (0x38UL) /*!< PAD8FNCSEL (Bitfield-Mask: 0x07) */
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#define GPIO_PADREGC_PAD8STRNG_Pos (2UL) /*!< PAD8STRNG (Bit 2) */
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#define GPIO_PADREGC_PAD8STRNG_Msk (0x4UL) /*!< PAD8STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGC_PAD8INPEN_Pos (1UL) /*!< PAD8INPEN (Bit 1) */
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#define GPIO_PADREGC_PAD8INPEN_Msk (0x2UL) /*!< PAD8INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGC_PAD8PULL_Pos (0UL) /*!< PAD8PULL (Bit 0) */
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#define GPIO_PADREGC_PAD8PULL_Msk (0x1UL) /*!< PAD8PULL (Bitfield-Mask: 0x01) */
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/* ======================================================== PADREGD ======================================================== */
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#define GPIO_PADREGD_PAD15FNCSEL_Pos (27UL) /*!< PAD15FNCSEL (Bit 27) */
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#define GPIO_PADREGD_PAD15FNCSEL_Msk (0x38000000UL) /*!< PAD15FNCSEL (Bitfield-Mask: 0x07) */
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#define GPIO_PADREGD_PAD15STRNG_Pos (26UL) /*!< PAD15STRNG (Bit 26) */
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#define GPIO_PADREGD_PAD15STRNG_Msk (0x4000000UL) /*!< PAD15STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGD_PAD15INPEN_Pos (25UL) /*!< PAD15INPEN (Bit 25) */
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#define GPIO_PADREGD_PAD15INPEN_Msk (0x2000000UL) /*!< PAD15INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGD_PAD15PULL_Pos (24UL) /*!< PAD15PULL (Bit 24) */
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#define GPIO_PADREGD_PAD15PULL_Msk (0x1000000UL) /*!< PAD15PULL (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGD_PAD14FNCSEL_Pos (19UL) /*!< PAD14FNCSEL (Bit 19) */
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#define GPIO_PADREGD_PAD14FNCSEL_Msk (0x380000UL) /*!< PAD14FNCSEL (Bitfield-Mask: 0x07) */
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#define GPIO_PADREGD_PAD14STRNG_Pos (18UL) /*!< PAD14STRNG (Bit 18) */
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#define GPIO_PADREGD_PAD14STRNG_Msk (0x40000UL) /*!< PAD14STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGD_PAD14INPEN_Pos (17UL) /*!< PAD14INPEN (Bit 17) */
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#define GPIO_PADREGD_PAD14INPEN_Msk (0x20000UL) /*!< PAD14INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGD_PAD14PULL_Pos (16UL) /*!< PAD14PULL (Bit 16) */
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#define GPIO_PADREGD_PAD14PULL_Msk (0x10000UL) /*!< PAD14PULL (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGD_PAD13FNCSEL_Pos (11UL) /*!< PAD13FNCSEL (Bit 11) */
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#define GPIO_PADREGD_PAD13FNCSEL_Msk (0x3800UL) /*!< PAD13FNCSEL (Bitfield-Mask: 0x07) */
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#define GPIO_PADREGD_PAD13STRNG_Pos (10UL) /*!< PAD13STRNG (Bit 10) */
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#define GPIO_PADREGD_PAD13STRNG_Msk (0x400UL) /*!< PAD13STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGD_PAD13INPEN_Pos (9UL) /*!< PAD13INPEN (Bit 9) */
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#define GPIO_PADREGD_PAD13INPEN_Msk (0x200UL) /*!< PAD13INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGD_PAD13PULL_Pos (8UL) /*!< PAD13PULL (Bit 8) */
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#define GPIO_PADREGD_PAD13PULL_Msk (0x100UL) /*!< PAD13PULL (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGD_PAD12FNCSEL_Pos (3UL) /*!< PAD12FNCSEL (Bit 3) */
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#define GPIO_PADREGD_PAD12FNCSEL_Msk (0x18UL) /*!< PAD12FNCSEL (Bitfield-Mask: 0x03) */
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#define GPIO_PADREGD_PAD12STRNG_Pos (2UL) /*!< PAD12STRNG (Bit 2) */
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#define GPIO_PADREGD_PAD12STRNG_Msk (0x4UL) /*!< PAD12STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGD_PAD12INPEN_Pos (1UL) /*!< PAD12INPEN (Bit 1) */
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#define GPIO_PADREGD_PAD12INPEN_Msk (0x2UL) /*!< PAD12INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGD_PAD12PULL_Pos (0UL) /*!< PAD12PULL (Bit 0) */
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#define GPIO_PADREGD_PAD12PULL_Msk (0x1UL) /*!< PAD12PULL (Bitfield-Mask: 0x01) */
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/* ======================================================== PADREGE ======================================================== */
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#define GPIO_PADREGE_PAD19FNCSEL_Pos (27UL) /*!< PAD19FNCSEL (Bit 27) */
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#define GPIO_PADREGE_PAD19FNCSEL_Msk (0x18000000UL) /*!< PAD19FNCSEL (Bitfield-Mask: 0x03) */
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#define GPIO_PADREGE_PAD19STRNG_Pos (26UL) /*!< PAD19STRNG (Bit 26) */
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#define GPIO_PADREGE_PAD19STRNG_Msk (0x4000000UL) /*!< PAD19STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGE_PAD19INPEN_Pos (25UL) /*!< PAD19INPEN (Bit 25) */
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#define GPIO_PADREGE_PAD19INPEN_Msk (0x2000000UL) /*!< PAD19INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGE_PAD19PULL_Pos (24UL) /*!< PAD19PULL (Bit 24) */
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#define GPIO_PADREGE_PAD19PULL_Msk (0x1000000UL) /*!< PAD19PULL (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGE_PAD18FNCSEL_Pos (19UL) /*!< PAD18FNCSEL (Bit 19) */
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#define GPIO_PADREGE_PAD18FNCSEL_Msk (0x180000UL) /*!< PAD18FNCSEL (Bitfield-Mask: 0x03) */
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#define GPIO_PADREGE_PAD18STRNG_Pos (18UL) /*!< PAD18STRNG (Bit 18) */
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#define GPIO_PADREGE_PAD18STRNG_Msk (0x40000UL) /*!< PAD18STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGE_PAD18INPEN_Pos (17UL) /*!< PAD18INPEN (Bit 17) */
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#define GPIO_PADREGE_PAD18INPEN_Msk (0x20000UL) /*!< PAD18INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGE_PAD18PULL_Pos (16UL) /*!< PAD18PULL (Bit 16) */
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#define GPIO_PADREGE_PAD18PULL_Msk (0x10000UL) /*!< PAD18PULL (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGE_PAD17FNCSEL_Pos (11UL) /*!< PAD17FNCSEL (Bit 11) */
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#define GPIO_PADREGE_PAD17FNCSEL_Msk (0x3800UL) /*!< PAD17FNCSEL (Bitfield-Mask: 0x07) */
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#define GPIO_PADREGE_PAD17STRNG_Pos (10UL) /*!< PAD17STRNG (Bit 10) */
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#define GPIO_PADREGE_PAD17STRNG_Msk (0x400UL) /*!< PAD17STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGE_PAD17INPEN_Pos (9UL) /*!< PAD17INPEN (Bit 9) */
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#define GPIO_PADREGE_PAD17INPEN_Msk (0x200UL) /*!< PAD17INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGE_PAD17PULL_Pos (8UL) /*!< PAD17PULL (Bit 8) */
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#define GPIO_PADREGE_PAD17PULL_Msk (0x100UL) /*!< PAD17PULL (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGE_PAD16FNCSEL_Pos (3UL) /*!< PAD16FNCSEL (Bit 3) */
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#define GPIO_PADREGE_PAD16FNCSEL_Msk (0x18UL) /*!< PAD16FNCSEL (Bitfield-Mask: 0x03) */
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#define GPIO_PADREGE_PAD16STRNG_Pos (2UL) /*!< PAD16STRNG (Bit 2) */
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#define GPIO_PADREGE_PAD16STRNG_Msk (0x4UL) /*!< PAD16STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGE_PAD16INPEN_Pos (1UL) /*!< PAD16INPEN (Bit 1) */
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#define GPIO_PADREGE_PAD16INPEN_Msk (0x2UL) /*!< PAD16INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGE_PAD16PULL_Pos (0UL) /*!< PAD16PULL (Bit 0) */
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#define GPIO_PADREGE_PAD16PULL_Msk (0x1UL) /*!< PAD16PULL (Bitfield-Mask: 0x01) */
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/* ======================================================== PADREGF ======================================================== */
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#define GPIO_PADREGF_PAD23FNCSEL_Pos (27UL) /*!< PAD23FNCSEL (Bit 27) */
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#define GPIO_PADREGF_PAD23FNCSEL_Msk (0x18000000UL) /*!< PAD23FNCSEL (Bitfield-Mask: 0x03) */
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#define GPIO_PADREGF_PAD23STRNG_Pos (26UL) /*!< PAD23STRNG (Bit 26) */
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#define GPIO_PADREGF_PAD23STRNG_Msk (0x4000000UL) /*!< PAD23STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGF_PAD23INPEN_Pos (25UL) /*!< PAD23INPEN (Bit 25) */
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#define GPIO_PADREGF_PAD23INPEN_Msk (0x2000000UL) /*!< PAD23INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGF_PAD23PULL_Pos (24UL) /*!< PAD23PULL (Bit 24) */
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#define GPIO_PADREGF_PAD23PULL_Msk (0x1000000UL) /*!< PAD23PULL (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGF_PAD22FNCSEL_Pos (19UL) /*!< PAD22FNCSEL (Bit 19) */
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#define GPIO_PADREGF_PAD22FNCSEL_Msk (0x180000UL) /*!< PAD22FNCSEL (Bitfield-Mask: 0x03) */
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#define GPIO_PADREGF_PAD22STRNG_Pos (18UL) /*!< PAD22STRNG (Bit 18) */
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#define GPIO_PADREGF_PAD22STRNG_Msk (0x40000UL) /*!< PAD22STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGF_PAD22INPEN_Pos (17UL) /*!< PAD22INPEN (Bit 17) */
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#define GPIO_PADREGF_PAD22INPEN_Msk (0x20000UL) /*!< PAD22INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGF_PAD22PULL_Pos (16UL) /*!< PAD22PULL (Bit 16) */
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#define GPIO_PADREGF_PAD22PULL_Msk (0x10000UL) /*!< PAD22PULL (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGF_PAD21FNCSEL_Pos (11UL) /*!< PAD21FNCSEL (Bit 11) */
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#define GPIO_PADREGF_PAD21FNCSEL_Msk (0x1800UL) /*!< PAD21FNCSEL (Bitfield-Mask: 0x03) */
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#define GPIO_PADREGF_PAD21STRNG_Pos (10UL) /*!< PAD21STRNG (Bit 10) */
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#define GPIO_PADREGF_PAD21STRNG_Msk (0x400UL) /*!< PAD21STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGF_PAD21INPEN_Pos (9UL) /*!< PAD21INPEN (Bit 9) */
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#define GPIO_PADREGF_PAD21INPEN_Msk (0x200UL) /*!< PAD21INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGF_PAD21PULL_Pos (8UL) /*!< PAD21PULL (Bit 8) */
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#define GPIO_PADREGF_PAD21PULL_Msk (0x100UL) /*!< PAD21PULL (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGF_PAD20FNCSEL_Pos (3UL) /*!< PAD20FNCSEL (Bit 3) */
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#define GPIO_PADREGF_PAD20FNCSEL_Msk (0x18UL) /*!< PAD20FNCSEL (Bitfield-Mask: 0x03) */
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#define GPIO_PADREGF_PAD20STRNG_Pos (2UL) /*!< PAD20STRNG (Bit 2) */
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#define GPIO_PADREGF_PAD20STRNG_Msk (0x4UL) /*!< PAD20STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGF_PAD20INPEN_Pos (1UL) /*!< PAD20INPEN (Bit 1) */
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#define GPIO_PADREGF_PAD20INPEN_Msk (0x2UL) /*!< PAD20INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGF_PAD20PULL_Pos (0UL) /*!< PAD20PULL (Bit 0) */
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#define GPIO_PADREGF_PAD20PULL_Msk (0x1UL) /*!< PAD20PULL (Bitfield-Mask: 0x01) */
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/* ======================================================== PADREGG ======================================================== */
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#define GPIO_PADREGG_PAD27FNCSEL_Pos (27UL) /*!< PAD27FNCSEL (Bit 27) */
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#define GPIO_PADREGG_PAD27FNCSEL_Msk (0x18000000UL) /*!< PAD27FNCSEL (Bitfield-Mask: 0x03) */
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#define GPIO_PADREGG_PAD27STRNG_Pos (26UL) /*!< PAD27STRNG (Bit 26) */
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#define GPIO_PADREGG_PAD27STRNG_Msk (0x4000000UL) /*!< PAD27STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGG_PAD27INPEN_Pos (25UL) /*!< PAD27INPEN (Bit 25) */
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#define GPIO_PADREGG_PAD27INPEN_Msk (0x2000000UL) /*!< PAD27INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGG_PAD27PULL_Pos (24UL) /*!< PAD27PULL (Bit 24) */
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#define GPIO_PADREGG_PAD27PULL_Msk (0x1000000UL) /*!< PAD27PULL (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGG_PAD26FNCSEL_Pos (19UL) /*!< PAD26FNCSEL (Bit 19) */
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#define GPIO_PADREGG_PAD26FNCSEL_Msk (0x180000UL) /*!< PAD26FNCSEL (Bitfield-Mask: 0x03) */
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#define GPIO_PADREGG_PAD26STRNG_Pos (18UL) /*!< PAD26STRNG (Bit 18) */
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#define GPIO_PADREGG_PAD26STRNG_Msk (0x40000UL) /*!< PAD26STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGG_PAD26INPEN_Pos (17UL) /*!< PAD26INPEN (Bit 17) */
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#define GPIO_PADREGG_PAD26INPEN_Msk (0x20000UL) /*!< PAD26INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGG_PAD26PULL_Pos (16UL) /*!< PAD26PULL (Bit 16) */
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#define GPIO_PADREGG_PAD26PULL_Msk (0x10000UL) /*!< PAD26PULL (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGG_PAD25FNCSEL_Pos (11UL) /*!< PAD25FNCSEL (Bit 11) */
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#define GPIO_PADREGG_PAD25FNCSEL_Msk (0x1800UL) /*!< PAD25FNCSEL (Bitfield-Mask: 0x03) */
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#define GPIO_PADREGG_PAD25STRNG_Pos (10UL) /*!< PAD25STRNG (Bit 10) */
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#define GPIO_PADREGG_PAD25STRNG_Msk (0x400UL) /*!< PAD25STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGG_PAD25INPEN_Pos (9UL) /*!< PAD25INPEN (Bit 9) */
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#define GPIO_PADREGG_PAD25INPEN_Msk (0x200UL) /*!< PAD25INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGG_PAD25PULL_Pos (8UL) /*!< PAD25PULL (Bit 8) */
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#define GPIO_PADREGG_PAD25PULL_Msk (0x100UL) /*!< PAD25PULL (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGG_PAD24FNCSEL_Pos (3UL) /*!< PAD24FNCSEL (Bit 3) */
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#define GPIO_PADREGG_PAD24FNCSEL_Msk (0x18UL) /*!< PAD24FNCSEL (Bitfield-Mask: 0x03) */
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#define GPIO_PADREGG_PAD24STRNG_Pos (2UL) /*!< PAD24STRNG (Bit 2) */
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#define GPIO_PADREGG_PAD24STRNG_Msk (0x4UL) /*!< PAD24STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGG_PAD24INPEN_Pos (1UL) /*!< PAD24INPEN (Bit 1) */
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#define GPIO_PADREGG_PAD24INPEN_Msk (0x2UL) /*!< PAD24INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGG_PAD24PULL_Pos (0UL) /*!< PAD24PULL (Bit 0) */
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#define GPIO_PADREGG_PAD24PULL_Msk (0x1UL) /*!< PAD24PULL (Bitfield-Mask: 0x01) */
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/* ======================================================== PADREGH ======================================================== */
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#define GPIO_PADREGH_PAD31FNCSEL_Pos (27UL) /*!< PAD31FNCSEL (Bit 27) */
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#define GPIO_PADREGH_PAD31FNCSEL_Msk (0x18000000UL) /*!< PAD31FNCSEL (Bitfield-Mask: 0x03) */
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#define GPIO_PADREGH_PAD31STRNG_Pos (26UL) /*!< PAD31STRNG (Bit 26) */
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#define GPIO_PADREGH_PAD31STRNG_Msk (0x4000000UL) /*!< PAD31STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGH_PAD31INPEN_Pos (25UL) /*!< PAD31INPEN (Bit 25) */
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#define GPIO_PADREGH_PAD31INPEN_Msk (0x2000000UL) /*!< PAD31INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGH_PAD31PULL_Pos (24UL) /*!< PAD31PULL (Bit 24) */
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#define GPIO_PADREGH_PAD31PULL_Msk (0x1000000UL) /*!< PAD31PULL (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGH_PAD30FNCSEL_Pos (19UL) /*!< PAD30FNCSEL (Bit 19) */
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#define GPIO_PADREGH_PAD30FNCSEL_Msk (0x180000UL) /*!< PAD30FNCSEL (Bitfield-Mask: 0x03) */
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#define GPIO_PADREGH_PAD30STRNG_Pos (18UL) /*!< PAD30STRNG (Bit 18) */
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#define GPIO_PADREGH_PAD30STRNG_Msk (0x40000UL) /*!< PAD30STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGH_PAD30INPEN_Pos (17UL) /*!< PAD30INPEN (Bit 17) */
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#define GPIO_PADREGH_PAD30INPEN_Msk (0x20000UL) /*!< PAD30INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGH_PAD30PULL_Pos (16UL) /*!< PAD30PULL (Bit 16) */
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#define GPIO_PADREGH_PAD30PULL_Msk (0x10000UL) /*!< PAD30PULL (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGH_PAD29FNCSEL_Pos (11UL) /*!< PAD29FNCSEL (Bit 11) */
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#define GPIO_PADREGH_PAD29FNCSEL_Msk (0x1800UL) /*!< PAD29FNCSEL (Bitfield-Mask: 0x03) */
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#define GPIO_PADREGH_PAD29STRNG_Pos (10UL) /*!< PAD29STRNG (Bit 10) */
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#define GPIO_PADREGH_PAD29STRNG_Msk (0x400UL) /*!< PAD29STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGH_PAD29INPEN_Pos (9UL) /*!< PAD29INPEN (Bit 9) */
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#define GPIO_PADREGH_PAD29INPEN_Msk (0x200UL) /*!< PAD29INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGH_PAD29PULL_Pos (8UL) /*!< PAD29PULL (Bit 8) */
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#define GPIO_PADREGH_PAD29PULL_Msk (0x100UL) /*!< PAD29PULL (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGH_PAD28FNCSEL_Pos (3UL) /*!< PAD28FNCSEL (Bit 3) */
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#define GPIO_PADREGH_PAD28FNCSEL_Msk (0x18UL) /*!< PAD28FNCSEL (Bitfield-Mask: 0x03) */
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#define GPIO_PADREGH_PAD28STRNG_Pos (2UL) /*!< PAD28STRNG (Bit 2) */
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#define GPIO_PADREGH_PAD28STRNG_Msk (0x4UL) /*!< PAD28STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGH_PAD28INPEN_Pos (1UL) /*!< PAD28INPEN (Bit 1) */
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#define GPIO_PADREGH_PAD28INPEN_Msk (0x2UL) /*!< PAD28INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGH_PAD28PULL_Pos (0UL) /*!< PAD28PULL (Bit 0) */
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#define GPIO_PADREGH_PAD28PULL_Msk (0x1UL) /*!< PAD28PULL (Bitfield-Mask: 0x01) */
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/* ======================================================== PADREGI ======================================================== */
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#define GPIO_PADREGI_PAD35FNCSEL_Pos (27UL) /*!< PAD35FNCSEL (Bit 27) */
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#define GPIO_PADREGI_PAD35FNCSEL_Msk (0x18000000UL) /*!< PAD35FNCSEL (Bitfield-Mask: 0x03) */
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#define GPIO_PADREGI_PAD35STRNG_Pos (26UL) /*!< PAD35STRNG (Bit 26) */
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#define GPIO_PADREGI_PAD35STRNG_Msk (0x4000000UL) /*!< PAD35STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGI_PAD35INPEN_Pos (25UL) /*!< PAD35INPEN (Bit 25) */
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#define GPIO_PADREGI_PAD35INPEN_Msk (0x2000000UL) /*!< PAD35INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGI_PAD35PULL_Pos (24UL) /*!< PAD35PULL (Bit 24) */
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#define GPIO_PADREGI_PAD35PULL_Msk (0x1000000UL) /*!< PAD35PULL (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGI_PAD34FNCSEL_Pos (19UL) /*!< PAD34FNCSEL (Bit 19) */
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#define GPIO_PADREGI_PAD34FNCSEL_Msk (0x180000UL) /*!< PAD34FNCSEL (Bitfield-Mask: 0x03) */
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#define GPIO_PADREGI_PAD34STRNG_Pos (18UL) /*!< PAD34STRNG (Bit 18) */
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#define GPIO_PADREGI_PAD34STRNG_Msk (0x40000UL) /*!< PAD34STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGI_PAD34INPEN_Pos (17UL) /*!< PAD34INPEN (Bit 17) */
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#define GPIO_PADREGI_PAD34INPEN_Msk (0x20000UL) /*!< PAD34INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGI_PAD34PULL_Pos (16UL) /*!< PAD34PULL (Bit 16) */
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#define GPIO_PADREGI_PAD34PULL_Msk (0x10000UL) /*!< PAD34PULL (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGI_PAD33FNCSEL_Pos (11UL) /*!< PAD33FNCSEL (Bit 11) */
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#define GPIO_PADREGI_PAD33FNCSEL_Msk (0x1800UL) /*!< PAD33FNCSEL (Bitfield-Mask: 0x03) */
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#define GPIO_PADREGI_PAD33STRNG_Pos (10UL) /*!< PAD33STRNG (Bit 10) */
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#define GPIO_PADREGI_PAD33STRNG_Msk (0x400UL) /*!< PAD33STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGI_PAD33INPEN_Pos (9UL) /*!< PAD33INPEN (Bit 9) */
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#define GPIO_PADREGI_PAD33INPEN_Msk (0x200UL) /*!< PAD33INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGI_PAD33PULL_Pos (8UL) /*!< PAD33PULL (Bit 8) */
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#define GPIO_PADREGI_PAD33PULL_Msk (0x100UL) /*!< PAD33PULL (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGI_PAD32FNCSEL_Pos (3UL) /*!< PAD32FNCSEL (Bit 3) */
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#define GPIO_PADREGI_PAD32FNCSEL_Msk (0x18UL) /*!< PAD32FNCSEL (Bitfield-Mask: 0x03) */
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#define GPIO_PADREGI_PAD32STRNG_Pos (2UL) /*!< PAD32STRNG (Bit 2) */
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#define GPIO_PADREGI_PAD32STRNG_Msk (0x4UL) /*!< PAD32STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGI_PAD32INPEN_Pos (1UL) /*!< PAD32INPEN (Bit 1) */
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#define GPIO_PADREGI_PAD32INPEN_Msk (0x2UL) /*!< PAD32INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGI_PAD32PULL_Pos (0UL) /*!< PAD32PULL (Bit 0) */
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#define GPIO_PADREGI_PAD32PULL_Msk (0x1UL) /*!< PAD32PULL (Bitfield-Mask: 0x01) */
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/* ======================================================== PADREGJ ======================================================== */
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#define GPIO_PADREGJ_PAD39FNCSEL_Pos (27UL) /*!< PAD39FNCSEL (Bit 27) */
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#define GPIO_PADREGJ_PAD39FNCSEL_Msk (0x18000000UL) /*!< PAD39FNCSEL (Bitfield-Mask: 0x03) */
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#define GPIO_PADREGJ_PAD39STRNG_Pos (26UL) /*!< PAD39STRNG (Bit 26) */
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#define GPIO_PADREGJ_PAD39STRNG_Msk (0x4000000UL) /*!< PAD39STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGJ_PAD39INPEN_Pos (25UL) /*!< PAD39INPEN (Bit 25) */
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#define GPIO_PADREGJ_PAD39INPEN_Msk (0x2000000UL) /*!< PAD39INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGJ_PAD39PULL_Pos (24UL) /*!< PAD39PULL (Bit 24) */
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#define GPIO_PADREGJ_PAD39PULL_Msk (0x1000000UL) /*!< PAD39PULL (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGJ_PAD38FNCSEL_Pos (19UL) /*!< PAD38FNCSEL (Bit 19) */
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#define GPIO_PADREGJ_PAD38FNCSEL_Msk (0x180000UL) /*!< PAD38FNCSEL (Bitfield-Mask: 0x03) */
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#define GPIO_PADREGJ_PAD38STRNG_Pos (18UL) /*!< PAD38STRNG (Bit 18) */
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#define GPIO_PADREGJ_PAD38STRNG_Msk (0x40000UL) /*!< PAD38STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGJ_PAD38INPEN_Pos (17UL) /*!< PAD38INPEN (Bit 17) */
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#define GPIO_PADREGJ_PAD38INPEN_Msk (0x20000UL) /*!< PAD38INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGJ_PAD38PULL_Pos (16UL) /*!< PAD38PULL (Bit 16) */
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#define GPIO_PADREGJ_PAD38PULL_Msk (0x10000UL) /*!< PAD38PULL (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGJ_PAD37FNCSEL_Pos (11UL) /*!< PAD37FNCSEL (Bit 11) */
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#define GPIO_PADREGJ_PAD37FNCSEL_Msk (0x1800UL) /*!< PAD37FNCSEL (Bitfield-Mask: 0x03) */
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#define GPIO_PADREGJ_PAD37STRNG_Pos (10UL) /*!< PAD37STRNG (Bit 10) */
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#define GPIO_PADREGJ_PAD37STRNG_Msk (0x400UL) /*!< PAD37STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGJ_PAD37INPEN_Pos (9UL) /*!< PAD37INPEN (Bit 9) */
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#define GPIO_PADREGJ_PAD37INPEN_Msk (0x200UL) /*!< PAD37INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGJ_PAD37PULL_Pos (8UL) /*!< PAD37PULL (Bit 8) */
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#define GPIO_PADREGJ_PAD37PULL_Msk (0x100UL) /*!< PAD37PULL (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGJ_PAD36FNCSEL_Pos (3UL) /*!< PAD36FNCSEL (Bit 3) */
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#define GPIO_PADREGJ_PAD36FNCSEL_Msk (0x18UL) /*!< PAD36FNCSEL (Bitfield-Mask: 0x03) */
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#define GPIO_PADREGJ_PAD36STRNG_Pos (2UL) /*!< PAD36STRNG (Bit 2) */
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#define GPIO_PADREGJ_PAD36STRNG_Msk (0x4UL) /*!< PAD36STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGJ_PAD36INPEN_Pos (1UL) /*!< PAD36INPEN (Bit 1) */
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#define GPIO_PADREGJ_PAD36INPEN_Msk (0x2UL) /*!< PAD36INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGJ_PAD36PULL_Pos (0UL) /*!< PAD36PULL (Bit 0) */
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#define GPIO_PADREGJ_PAD36PULL_Msk (0x1UL) /*!< PAD36PULL (Bitfield-Mask: 0x01) */
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/* ======================================================== PADREGK ======================================================== */
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#define GPIO_PADREGK_PAD43FNCSEL_Pos (27UL) /*!< PAD43FNCSEL (Bit 27) */
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#define GPIO_PADREGK_PAD43FNCSEL_Msk (0x18000000UL) /*!< PAD43FNCSEL (Bitfield-Mask: 0x03) */
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#define GPIO_PADREGK_PAD43STRNG_Pos (26UL) /*!< PAD43STRNG (Bit 26) */
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#define GPIO_PADREGK_PAD43STRNG_Msk (0x4000000UL) /*!< PAD43STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGK_PAD43INPEN_Pos (25UL) /*!< PAD43INPEN (Bit 25) */
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#define GPIO_PADREGK_PAD43INPEN_Msk (0x2000000UL) /*!< PAD43INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGK_PAD43PULL_Pos (24UL) /*!< PAD43PULL (Bit 24) */
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#define GPIO_PADREGK_PAD43PULL_Msk (0x1000000UL) /*!< PAD43PULL (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGK_PAD42FNCSEL_Pos (19UL) /*!< PAD42FNCSEL (Bit 19) */
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#define GPIO_PADREGK_PAD42FNCSEL_Msk (0x180000UL) /*!< PAD42FNCSEL (Bitfield-Mask: 0x03) */
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#define GPIO_PADREGK_PAD42STRNG_Pos (18UL) /*!< PAD42STRNG (Bit 18) */
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#define GPIO_PADREGK_PAD42STRNG_Msk (0x40000UL) /*!< PAD42STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGK_PAD42INPEN_Pos (17UL) /*!< PAD42INPEN (Bit 17) */
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#define GPIO_PADREGK_PAD42INPEN_Msk (0x20000UL) /*!< PAD42INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGK_PAD42PULL_Pos (16UL) /*!< PAD42PULL (Bit 16) */
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#define GPIO_PADREGK_PAD42PULL_Msk (0x10000UL) /*!< PAD42PULL (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGK_PAD41FNCSEL_Pos (11UL) /*!< PAD41FNCSEL (Bit 11) */
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#define GPIO_PADREGK_PAD41FNCSEL_Msk (0x1800UL) /*!< PAD41FNCSEL (Bitfield-Mask: 0x03) */
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#define GPIO_PADREGK_PAD41STRNG_Pos (10UL) /*!< PAD41STRNG (Bit 10) */
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#define GPIO_PADREGK_PAD41STRNG_Msk (0x400UL) /*!< PAD41STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGK_PAD41INPEN_Pos (9UL) /*!< PAD41INPEN (Bit 9) */
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#define GPIO_PADREGK_PAD41INPEN_Msk (0x200UL) /*!< PAD41INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGK_PAD41PULL_Pos (8UL) /*!< PAD41PULL (Bit 8) */
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#define GPIO_PADREGK_PAD41PULL_Msk (0x100UL) /*!< PAD41PULL (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGK_PAD40FNCSEL_Pos (3UL) /*!< PAD40FNCSEL (Bit 3) */
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#define GPIO_PADREGK_PAD40FNCSEL_Msk (0x18UL) /*!< PAD40FNCSEL (Bitfield-Mask: 0x03) */
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#define GPIO_PADREGK_PAD40STRNG_Pos (2UL) /*!< PAD40STRNG (Bit 2) */
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#define GPIO_PADREGK_PAD40STRNG_Msk (0x4UL) /*!< PAD40STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGK_PAD40INPEN_Pos (1UL) /*!< PAD40INPEN (Bit 1) */
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#define GPIO_PADREGK_PAD40INPEN_Msk (0x2UL) /*!< PAD40INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGK_PAD40PULL_Pos (0UL) /*!< PAD40PULL (Bit 0) */
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#define GPIO_PADREGK_PAD40PULL_Msk (0x1UL) /*!< PAD40PULL (Bitfield-Mask: 0x01) */
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/* ======================================================== PADREGL ======================================================== */
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#define GPIO_PADREGL_PAD47FNCSEL_Pos (27UL) /*!< PAD47FNCSEL (Bit 27) */
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#define GPIO_PADREGL_PAD47FNCSEL_Msk (0x18000000UL) /*!< PAD47FNCSEL (Bitfield-Mask: 0x03) */
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#define GPIO_PADREGL_PAD47STRNG_Pos (26UL) /*!< PAD47STRNG (Bit 26) */
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#define GPIO_PADREGL_PAD47STRNG_Msk (0x4000000UL) /*!< PAD47STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGL_PAD47INPEN_Pos (25UL) /*!< PAD47INPEN (Bit 25) */
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#define GPIO_PADREGL_PAD47INPEN_Msk (0x2000000UL) /*!< PAD47INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGL_PAD47PULL_Pos (24UL) /*!< PAD47PULL (Bit 24) */
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#define GPIO_PADREGL_PAD47PULL_Msk (0x1000000UL) /*!< PAD47PULL (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGL_PAD46FNCSEL_Pos (19UL) /*!< PAD46FNCSEL (Bit 19) */
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#define GPIO_PADREGL_PAD46FNCSEL_Msk (0x180000UL) /*!< PAD46FNCSEL (Bitfield-Mask: 0x03) */
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#define GPIO_PADREGL_PAD46STRNG_Pos (18UL) /*!< PAD46STRNG (Bit 18) */
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#define GPIO_PADREGL_PAD46STRNG_Msk (0x40000UL) /*!< PAD46STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGL_PAD46INPEN_Pos (17UL) /*!< PAD46INPEN (Bit 17) */
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#define GPIO_PADREGL_PAD46INPEN_Msk (0x20000UL) /*!< PAD46INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGL_PAD46PULL_Pos (16UL) /*!< PAD46PULL (Bit 16) */
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#define GPIO_PADREGL_PAD46PULL_Msk (0x10000UL) /*!< PAD46PULL (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGL_PAD45FNCSEL_Pos (11UL) /*!< PAD45FNCSEL (Bit 11) */
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#define GPIO_PADREGL_PAD45FNCSEL_Msk (0x1800UL) /*!< PAD45FNCSEL (Bitfield-Mask: 0x03) */
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#define GPIO_PADREGL_PAD45STRNG_Pos (10UL) /*!< PAD45STRNG (Bit 10) */
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#define GPIO_PADREGL_PAD45STRNG_Msk (0x400UL) /*!< PAD45STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGL_PAD45INPEN_Pos (9UL) /*!< PAD45INPEN (Bit 9) */
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#define GPIO_PADREGL_PAD45INPEN_Msk (0x200UL) /*!< PAD45INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGL_PAD45PULL_Pos (8UL) /*!< PAD45PULL (Bit 8) */
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#define GPIO_PADREGL_PAD45PULL_Msk (0x100UL) /*!< PAD45PULL (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGL_PAD44FNCSEL_Pos (3UL) /*!< PAD44FNCSEL (Bit 3) */
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#define GPIO_PADREGL_PAD44FNCSEL_Msk (0x18UL) /*!< PAD44FNCSEL (Bitfield-Mask: 0x03) */
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#define GPIO_PADREGL_PAD44STRNG_Pos (2UL) /*!< PAD44STRNG (Bit 2) */
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#define GPIO_PADREGL_PAD44STRNG_Msk (0x4UL) /*!< PAD44STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGL_PAD44INPEN_Pos (1UL) /*!< PAD44INPEN (Bit 1) */
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#define GPIO_PADREGL_PAD44INPEN_Msk (0x2UL) /*!< PAD44INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGL_PAD44PULL_Pos (0UL) /*!< PAD44PULL (Bit 0) */
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#define GPIO_PADREGL_PAD44PULL_Msk (0x1UL) /*!< PAD44PULL (Bitfield-Mask: 0x01) */
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/* ======================================================== PADREGM ======================================================== */
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#define GPIO_PADREGM_PAD49FNCSEL_Pos (11UL) /*!< PAD49FNCSEL (Bit 11) */
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#define GPIO_PADREGM_PAD49FNCSEL_Msk (0x1800UL) /*!< PAD49FNCSEL (Bitfield-Mask: 0x03) */
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#define GPIO_PADREGM_PAD49STRNG_Pos (10UL) /*!< PAD49STRNG (Bit 10) */
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#define GPIO_PADREGM_PAD49STRNG_Msk (0x400UL) /*!< PAD49STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGM_PAD49INPEN_Pos (9UL) /*!< PAD49INPEN (Bit 9) */
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#define GPIO_PADREGM_PAD49INPEN_Msk (0x200UL) /*!< PAD49INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGM_PAD49PULL_Pos (8UL) /*!< PAD49PULL (Bit 8) */
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#define GPIO_PADREGM_PAD49PULL_Msk (0x100UL) /*!< PAD49PULL (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGM_PAD48FNCSEL_Pos (3UL) /*!< PAD48FNCSEL (Bit 3) */
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#define GPIO_PADREGM_PAD48FNCSEL_Msk (0x18UL) /*!< PAD48FNCSEL (Bitfield-Mask: 0x03) */
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#define GPIO_PADREGM_PAD48STRNG_Pos (2UL) /*!< PAD48STRNG (Bit 2) */
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#define GPIO_PADREGM_PAD48STRNG_Msk (0x4UL) /*!< PAD48STRNG (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGM_PAD48INPEN_Pos (1UL) /*!< PAD48INPEN (Bit 1) */
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#define GPIO_PADREGM_PAD48INPEN_Msk (0x2UL) /*!< PAD48INPEN (Bitfield-Mask: 0x01) */
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#define GPIO_PADREGM_PAD48PULL_Pos (0UL) /*!< PAD48PULL (Bit 0) */
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#define GPIO_PADREGM_PAD48PULL_Msk (0x1UL) /*!< PAD48PULL (Bitfield-Mask: 0x01) */
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/* ========================================================= CFGA ========================================================== */
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#define GPIO_CFGA_GPIO7INTD_Pos (31UL) /*!< GPIO7INTD (Bit 31) */
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#define GPIO_CFGA_GPIO7INTD_Msk (0x80000000UL) /*!< GPIO7INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGA_GPIO7OUTCFG_Pos (29UL) /*!< GPIO7OUTCFG (Bit 29) */
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#define GPIO_CFGA_GPIO7OUTCFG_Msk (0x60000000UL) /*!< GPIO7OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGA_GPIO7INCFG_Pos (28UL) /*!< GPIO7INCFG (Bit 28) */
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#define GPIO_CFGA_GPIO7INCFG_Msk (0x10000000UL) /*!< GPIO7INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGA_GPIO6INTD_Pos (27UL) /*!< GPIO6INTD (Bit 27) */
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#define GPIO_CFGA_GPIO6INTD_Msk (0x8000000UL) /*!< GPIO6INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGA_GPIO6OUTCFG_Pos (25UL) /*!< GPIO6OUTCFG (Bit 25) */
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#define GPIO_CFGA_GPIO6OUTCFG_Msk (0x6000000UL) /*!< GPIO6OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGA_GPIO6INCFG_Pos (24UL) /*!< GPIO6INCFG (Bit 24) */
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#define GPIO_CFGA_GPIO6INCFG_Msk (0x1000000UL) /*!< GPIO6INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGA_GPIO5INTD_Pos (23UL) /*!< GPIO5INTD (Bit 23) */
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#define GPIO_CFGA_GPIO5INTD_Msk (0x800000UL) /*!< GPIO5INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGA_GPIO5OUTCFG_Pos (21UL) /*!< GPIO5OUTCFG (Bit 21) */
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#define GPIO_CFGA_GPIO5OUTCFG_Msk (0x600000UL) /*!< GPIO5OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGA_GPIO5INCFG_Pos (20UL) /*!< GPIO5INCFG (Bit 20) */
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#define GPIO_CFGA_GPIO5INCFG_Msk (0x100000UL) /*!< GPIO5INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGA_GPIO4INTD_Pos (19UL) /*!< GPIO4INTD (Bit 19) */
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#define GPIO_CFGA_GPIO4INTD_Msk (0x80000UL) /*!< GPIO4INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGA_GPIO4OUTCFG_Pos (17UL) /*!< GPIO4OUTCFG (Bit 17) */
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#define GPIO_CFGA_GPIO4OUTCFG_Msk (0x60000UL) /*!< GPIO4OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGA_GPIO4INCFG_Pos (16UL) /*!< GPIO4INCFG (Bit 16) */
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#define GPIO_CFGA_GPIO4INCFG_Msk (0x10000UL) /*!< GPIO4INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGA_GPIO3INTD_Pos (15UL) /*!< GPIO3INTD (Bit 15) */
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#define GPIO_CFGA_GPIO3INTD_Msk (0x8000UL) /*!< GPIO3INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGA_GPIO3OUTCFG_Pos (13UL) /*!< GPIO3OUTCFG (Bit 13) */
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#define GPIO_CFGA_GPIO3OUTCFG_Msk (0x6000UL) /*!< GPIO3OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGA_GPIO3INCFG_Pos (12UL) /*!< GPIO3INCFG (Bit 12) */
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#define GPIO_CFGA_GPIO3INCFG_Msk (0x1000UL) /*!< GPIO3INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGA_GPIO2INTD_Pos (11UL) /*!< GPIO2INTD (Bit 11) */
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#define GPIO_CFGA_GPIO2INTD_Msk (0x800UL) /*!< GPIO2INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGA_GPIO2OUTCFG_Pos (9UL) /*!< GPIO2OUTCFG (Bit 9) */
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#define GPIO_CFGA_GPIO2OUTCFG_Msk (0x600UL) /*!< GPIO2OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGA_GPIO2INCFG_Pos (8UL) /*!< GPIO2INCFG (Bit 8) */
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#define GPIO_CFGA_GPIO2INCFG_Msk (0x100UL) /*!< GPIO2INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGA_GPIO1INTD_Pos (7UL) /*!< GPIO1INTD (Bit 7) */
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#define GPIO_CFGA_GPIO1INTD_Msk (0x80UL) /*!< GPIO1INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGA_GPIO1OUTCFG_Pos (5UL) /*!< GPIO1OUTCFG (Bit 5) */
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#define GPIO_CFGA_GPIO1OUTCFG_Msk (0x60UL) /*!< GPIO1OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGA_GPIO1INCFG_Pos (4UL) /*!< GPIO1INCFG (Bit 4) */
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#define GPIO_CFGA_GPIO1INCFG_Msk (0x10UL) /*!< GPIO1INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGA_GPIO0INTD_Pos (3UL) /*!< GPIO0INTD (Bit 3) */
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#define GPIO_CFGA_GPIO0INTD_Msk (0x8UL) /*!< GPIO0INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGA_GPIO0OUTCFG_Pos (1UL) /*!< GPIO0OUTCFG (Bit 1) */
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#define GPIO_CFGA_GPIO0OUTCFG_Msk (0x6UL) /*!< GPIO0OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGA_GPIO0INCFG_Pos (0UL) /*!< GPIO0INCFG (Bit 0) */
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#define GPIO_CFGA_GPIO0INCFG_Msk (0x1UL) /*!< GPIO0INCFG (Bitfield-Mask: 0x01) */
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/* ========================================================= CFGB ========================================================== */
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#define GPIO_CFGB_GPIO15INTD_Pos (31UL) /*!< GPIO15INTD (Bit 31) */
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#define GPIO_CFGB_GPIO15INTD_Msk (0x80000000UL) /*!< GPIO15INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGB_GPIO15OUTCFG_Pos (29UL) /*!< GPIO15OUTCFG (Bit 29) */
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#define GPIO_CFGB_GPIO15OUTCFG_Msk (0x60000000UL) /*!< GPIO15OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGB_GPIO15INCFG_Pos (28UL) /*!< GPIO15INCFG (Bit 28) */
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#define GPIO_CFGB_GPIO15INCFG_Msk (0x10000000UL) /*!< GPIO15INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGB_GPIO14INTD_Pos (27UL) /*!< GPIO14INTD (Bit 27) */
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#define GPIO_CFGB_GPIO14INTD_Msk (0x8000000UL) /*!< GPIO14INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGB_GPIO14OUTCFG_Pos (25UL) /*!< GPIO14OUTCFG (Bit 25) */
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#define GPIO_CFGB_GPIO14OUTCFG_Msk (0x6000000UL) /*!< GPIO14OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGB_GPIO14INCFG_Pos (24UL) /*!< GPIO14INCFG (Bit 24) */
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#define GPIO_CFGB_GPIO14INCFG_Msk (0x1000000UL) /*!< GPIO14INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGB_GPIO13INTD_Pos (23UL) /*!< GPIO13INTD (Bit 23) */
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#define GPIO_CFGB_GPIO13INTD_Msk (0x800000UL) /*!< GPIO13INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGB_GPIO13OUTCFG_Pos (21UL) /*!< GPIO13OUTCFG (Bit 21) */
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#define GPIO_CFGB_GPIO13OUTCFG_Msk (0x600000UL) /*!< GPIO13OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGB_GPIO13INCFG_Pos (20UL) /*!< GPIO13INCFG (Bit 20) */
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#define GPIO_CFGB_GPIO13INCFG_Msk (0x100000UL) /*!< GPIO13INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGB_GPIO12INTD_Pos (19UL) /*!< GPIO12INTD (Bit 19) */
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#define GPIO_CFGB_GPIO12INTD_Msk (0x80000UL) /*!< GPIO12INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGB_GPIO12OUTCFG_Pos (17UL) /*!< GPIO12OUTCFG (Bit 17) */
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#define GPIO_CFGB_GPIO12OUTCFG_Msk (0x60000UL) /*!< GPIO12OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGB_GPIO12INCFG_Pos (16UL) /*!< GPIO12INCFG (Bit 16) */
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#define GPIO_CFGB_GPIO12INCFG_Msk (0x10000UL) /*!< GPIO12INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGB_GPIO11INTD_Pos (15UL) /*!< GPIO11INTD (Bit 15) */
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#define GPIO_CFGB_GPIO11INTD_Msk (0x8000UL) /*!< GPIO11INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGB_GPIO11OUTCFG_Pos (13UL) /*!< GPIO11OUTCFG (Bit 13) */
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#define GPIO_CFGB_GPIO11OUTCFG_Msk (0x6000UL) /*!< GPIO11OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGB_GPIO11INCFG_Pos (12UL) /*!< GPIO11INCFG (Bit 12) */
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#define GPIO_CFGB_GPIO11INCFG_Msk (0x1000UL) /*!< GPIO11INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGB_GPIO10INTD_Pos (11UL) /*!< GPIO10INTD (Bit 11) */
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#define GPIO_CFGB_GPIO10INTD_Msk (0x800UL) /*!< GPIO10INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGB_GPIO10OUTCFG_Pos (9UL) /*!< GPIO10OUTCFG (Bit 9) */
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#define GPIO_CFGB_GPIO10OUTCFG_Msk (0x600UL) /*!< GPIO10OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGB_GPIO10INCFG_Pos (8UL) /*!< GPIO10INCFG (Bit 8) */
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#define GPIO_CFGB_GPIO10INCFG_Msk (0x100UL) /*!< GPIO10INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGB_GPIO9INTD_Pos (7UL) /*!< GPIO9INTD (Bit 7) */
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#define GPIO_CFGB_GPIO9INTD_Msk (0x80UL) /*!< GPIO9INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGB_GPIO9OUTCFG_Pos (5UL) /*!< GPIO9OUTCFG (Bit 5) */
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#define GPIO_CFGB_GPIO9OUTCFG_Msk (0x60UL) /*!< GPIO9OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGB_GPIO9INCFG_Pos (4UL) /*!< GPIO9INCFG (Bit 4) */
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#define GPIO_CFGB_GPIO9INCFG_Msk (0x10UL) /*!< GPIO9INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGB_GPIO8INTD_Pos (3UL) /*!< GPIO8INTD (Bit 3) */
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#define GPIO_CFGB_GPIO8INTD_Msk (0x8UL) /*!< GPIO8INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGB_GPIO8OUTCFG_Pos (1UL) /*!< GPIO8OUTCFG (Bit 1) */
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#define GPIO_CFGB_GPIO8OUTCFG_Msk (0x6UL) /*!< GPIO8OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGB_GPIO8INCFG_Pos (0UL) /*!< GPIO8INCFG (Bit 0) */
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#define GPIO_CFGB_GPIO8INCFG_Msk (0x1UL) /*!< GPIO8INCFG (Bitfield-Mask: 0x01) */
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/* ========================================================= CFGC ========================================================== */
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#define GPIO_CFGC_GPIO23INTD_Pos (31UL) /*!< GPIO23INTD (Bit 31) */
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#define GPIO_CFGC_GPIO23INTD_Msk (0x80000000UL) /*!< GPIO23INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGC_GPIO23OUTCFG_Pos (29UL) /*!< GPIO23OUTCFG (Bit 29) */
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#define GPIO_CFGC_GPIO23OUTCFG_Msk (0x60000000UL) /*!< GPIO23OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGC_GPIO23INCFG_Pos (28UL) /*!< GPIO23INCFG (Bit 28) */
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#define GPIO_CFGC_GPIO23INCFG_Msk (0x10000000UL) /*!< GPIO23INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGC_GPIO22INTD_Pos (27UL) /*!< GPIO22INTD (Bit 27) */
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#define GPIO_CFGC_GPIO22INTD_Msk (0x8000000UL) /*!< GPIO22INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGC_GPIO22OUTCFG_Pos (25UL) /*!< GPIO22OUTCFG (Bit 25) */
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#define GPIO_CFGC_GPIO22OUTCFG_Msk (0x6000000UL) /*!< GPIO22OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGC_GPIO22INCFG_Pos (24UL) /*!< GPIO22INCFG (Bit 24) */
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#define GPIO_CFGC_GPIO22INCFG_Msk (0x1000000UL) /*!< GPIO22INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGC_GPIO21INTD_Pos (23UL) /*!< GPIO21INTD (Bit 23) */
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#define GPIO_CFGC_GPIO21INTD_Msk (0x800000UL) /*!< GPIO21INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGC_GPIO21OUTCFG_Pos (21UL) /*!< GPIO21OUTCFG (Bit 21) */
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#define GPIO_CFGC_GPIO21OUTCFG_Msk (0x600000UL) /*!< GPIO21OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGC_GPIO21INCFG_Pos (20UL) /*!< GPIO21INCFG (Bit 20) */
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#define GPIO_CFGC_GPIO21INCFG_Msk (0x100000UL) /*!< GPIO21INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGC_GPIO20INTD_Pos (19UL) /*!< GPIO20INTD (Bit 19) */
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#define GPIO_CFGC_GPIO20INTD_Msk (0x80000UL) /*!< GPIO20INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGC_GPIO20OUTCFG_Pos (17UL) /*!< GPIO20OUTCFG (Bit 17) */
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#define GPIO_CFGC_GPIO20OUTCFG_Msk (0x60000UL) /*!< GPIO20OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGC_GPIO20INCFG_Pos (16UL) /*!< GPIO20INCFG (Bit 16) */
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#define GPIO_CFGC_GPIO20INCFG_Msk (0x10000UL) /*!< GPIO20INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGC_GPIO19INTD_Pos (15UL) /*!< GPIO19INTD (Bit 15) */
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#define GPIO_CFGC_GPIO19INTD_Msk (0x8000UL) /*!< GPIO19INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGC_GPIO19OUTCFG_Pos (13UL) /*!< GPIO19OUTCFG (Bit 13) */
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#define GPIO_CFGC_GPIO19OUTCFG_Msk (0x6000UL) /*!< GPIO19OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGC_GPIO19INCFG_Pos (12UL) /*!< GPIO19INCFG (Bit 12) */
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#define GPIO_CFGC_GPIO19INCFG_Msk (0x1000UL) /*!< GPIO19INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGC_GPIO18INTD_Pos (11UL) /*!< GPIO18INTD (Bit 11) */
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#define GPIO_CFGC_GPIO18INTD_Msk (0x800UL) /*!< GPIO18INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGC_GPIO18OUTCFG_Pos (9UL) /*!< GPIO18OUTCFG (Bit 9) */
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#define GPIO_CFGC_GPIO18OUTCFG_Msk (0x600UL) /*!< GPIO18OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGC_GPIO18INCFG_Pos (8UL) /*!< GPIO18INCFG (Bit 8) */
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#define GPIO_CFGC_GPIO18INCFG_Msk (0x100UL) /*!< GPIO18INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGC_GPIO17INTD_Pos (7UL) /*!< GPIO17INTD (Bit 7) */
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#define GPIO_CFGC_GPIO17INTD_Msk (0x80UL) /*!< GPIO17INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGC_GPIO17OUTCFG_Pos (5UL) /*!< GPIO17OUTCFG (Bit 5) */
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#define GPIO_CFGC_GPIO17OUTCFG_Msk (0x60UL) /*!< GPIO17OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGC_GPIO17INCFG_Pos (4UL) /*!< GPIO17INCFG (Bit 4) */
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#define GPIO_CFGC_GPIO17INCFG_Msk (0x10UL) /*!< GPIO17INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGC_GPIO16INTD_Pos (3UL) /*!< GPIO16INTD (Bit 3) */
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#define GPIO_CFGC_GPIO16INTD_Msk (0x8UL) /*!< GPIO16INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGC_GPIO16OUTCFG_Pos (1UL) /*!< GPIO16OUTCFG (Bit 1) */
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#define GPIO_CFGC_GPIO16OUTCFG_Msk (0x6UL) /*!< GPIO16OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGC_GPIO16INCFG_Pos (0UL) /*!< GPIO16INCFG (Bit 0) */
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#define GPIO_CFGC_GPIO16INCFG_Msk (0x1UL) /*!< GPIO16INCFG (Bitfield-Mask: 0x01) */
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/* ========================================================= CFGD ========================================================== */
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#define GPIO_CFGD_GPIO31INTD_Pos (31UL) /*!< GPIO31INTD (Bit 31) */
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#define GPIO_CFGD_GPIO31INTD_Msk (0x80000000UL) /*!< GPIO31INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGD_GPIO31OUTCFG_Pos (29UL) /*!< GPIO31OUTCFG (Bit 29) */
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#define GPIO_CFGD_GPIO31OUTCFG_Msk (0x60000000UL) /*!< GPIO31OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGD_GPIO31INCFG_Pos (28UL) /*!< GPIO31INCFG (Bit 28) */
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#define GPIO_CFGD_GPIO31INCFG_Msk (0x10000000UL) /*!< GPIO31INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGD_GPIO30INTD_Pos (27UL) /*!< GPIO30INTD (Bit 27) */
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#define GPIO_CFGD_GPIO30INTD_Msk (0x8000000UL) /*!< GPIO30INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGD_GPIO30OUTCFG_Pos (25UL) /*!< GPIO30OUTCFG (Bit 25) */
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#define GPIO_CFGD_GPIO30OUTCFG_Msk (0x6000000UL) /*!< GPIO30OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGD_GPIO30INCFG_Pos (24UL) /*!< GPIO30INCFG (Bit 24) */
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#define GPIO_CFGD_GPIO30INCFG_Msk (0x1000000UL) /*!< GPIO30INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGD_GPIO29INTD_Pos (23UL) /*!< GPIO29INTD (Bit 23) */
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#define GPIO_CFGD_GPIO29INTD_Msk (0x800000UL) /*!< GPIO29INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGD_GPIO29OUTCFG_Pos (21UL) /*!< GPIO29OUTCFG (Bit 21) */
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#define GPIO_CFGD_GPIO29OUTCFG_Msk (0x600000UL) /*!< GPIO29OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGD_GPIO29INCFG_Pos (20UL) /*!< GPIO29INCFG (Bit 20) */
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#define GPIO_CFGD_GPIO29INCFG_Msk (0x100000UL) /*!< GPIO29INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGD_GPIO28INTD_Pos (19UL) /*!< GPIO28INTD (Bit 19) */
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#define GPIO_CFGD_GPIO28INTD_Msk (0x80000UL) /*!< GPIO28INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGD_GPIO28OUTCFG_Pos (17UL) /*!< GPIO28OUTCFG (Bit 17) */
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#define GPIO_CFGD_GPIO28OUTCFG_Msk (0x60000UL) /*!< GPIO28OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGD_GPIO28INCFG_Pos (16UL) /*!< GPIO28INCFG (Bit 16) */
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#define GPIO_CFGD_GPIO28INCFG_Msk (0x10000UL) /*!< GPIO28INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGD_GPIO27INTD_Pos (15UL) /*!< GPIO27INTD (Bit 15) */
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#define GPIO_CFGD_GPIO27INTD_Msk (0x8000UL) /*!< GPIO27INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGD_GPIO27OUTCFG_Pos (13UL) /*!< GPIO27OUTCFG (Bit 13) */
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#define GPIO_CFGD_GPIO27OUTCFG_Msk (0x6000UL) /*!< GPIO27OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGD_GPIO27INCFG_Pos (12UL) /*!< GPIO27INCFG (Bit 12) */
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#define GPIO_CFGD_GPIO27INCFG_Msk (0x1000UL) /*!< GPIO27INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGD_GPIO26INTD_Pos (11UL) /*!< GPIO26INTD (Bit 11) */
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#define GPIO_CFGD_GPIO26INTD_Msk (0x800UL) /*!< GPIO26INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGD_GPIO26OUTCFG_Pos (9UL) /*!< GPIO26OUTCFG (Bit 9) */
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#define GPIO_CFGD_GPIO26OUTCFG_Msk (0x600UL) /*!< GPIO26OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGD_GPIO26INCFG_Pos (8UL) /*!< GPIO26INCFG (Bit 8) */
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#define GPIO_CFGD_GPIO26INCFG_Msk (0x100UL) /*!< GPIO26INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGD_GPIO25INTD_Pos (7UL) /*!< GPIO25INTD (Bit 7) */
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#define GPIO_CFGD_GPIO25INTD_Msk (0x80UL) /*!< GPIO25INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGD_GPIO25OUTCFG_Pos (5UL) /*!< GPIO25OUTCFG (Bit 5) */
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#define GPIO_CFGD_GPIO25OUTCFG_Msk (0x60UL) /*!< GPIO25OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGD_GPIO25INCFG_Pos (4UL) /*!< GPIO25INCFG (Bit 4) */
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#define GPIO_CFGD_GPIO25INCFG_Msk (0x10UL) /*!< GPIO25INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGD_GPIO24INTD_Pos (3UL) /*!< GPIO24INTD (Bit 3) */
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#define GPIO_CFGD_GPIO24INTD_Msk (0x8UL) /*!< GPIO24INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGD_GPIO24OUTCFG_Pos (1UL) /*!< GPIO24OUTCFG (Bit 1) */
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#define GPIO_CFGD_GPIO24OUTCFG_Msk (0x6UL) /*!< GPIO24OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGD_GPIO24INCFG_Pos (0UL) /*!< GPIO24INCFG (Bit 0) */
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#define GPIO_CFGD_GPIO24INCFG_Msk (0x1UL) /*!< GPIO24INCFG (Bitfield-Mask: 0x01) */
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/* ========================================================= CFGE ========================================================== */
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#define GPIO_CFGE_GPIO39INTD_Pos (31UL) /*!< GPIO39INTD (Bit 31) */
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#define GPIO_CFGE_GPIO39INTD_Msk (0x80000000UL) /*!< GPIO39INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGE_GPIO39OUTCFG_Pos (29UL) /*!< GPIO39OUTCFG (Bit 29) */
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#define GPIO_CFGE_GPIO39OUTCFG_Msk (0x60000000UL) /*!< GPIO39OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGE_GPIO39INCFG_Pos (28UL) /*!< GPIO39INCFG (Bit 28) */
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#define GPIO_CFGE_GPIO39INCFG_Msk (0x10000000UL) /*!< GPIO39INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGE_GPIO38INTD_Pos (27UL) /*!< GPIO38INTD (Bit 27) */
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#define GPIO_CFGE_GPIO38INTD_Msk (0x8000000UL) /*!< GPIO38INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGE_GPIO38OUTCFG_Pos (25UL) /*!< GPIO38OUTCFG (Bit 25) */
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#define GPIO_CFGE_GPIO38OUTCFG_Msk (0x6000000UL) /*!< GPIO38OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGE_GPIO38INCFG_Pos (24UL) /*!< GPIO38INCFG (Bit 24) */
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#define GPIO_CFGE_GPIO38INCFG_Msk (0x1000000UL) /*!< GPIO38INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGE_GPIO37INTD_Pos (23UL) /*!< GPIO37INTD (Bit 23) */
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#define GPIO_CFGE_GPIO37INTD_Msk (0x800000UL) /*!< GPIO37INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGE_GPIO37OUTCFG_Pos (21UL) /*!< GPIO37OUTCFG (Bit 21) */
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#define GPIO_CFGE_GPIO37OUTCFG_Msk (0x600000UL) /*!< GPIO37OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGE_GPIO37INCFG_Pos (20UL) /*!< GPIO37INCFG (Bit 20) */
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#define GPIO_CFGE_GPIO37INCFG_Msk (0x100000UL) /*!< GPIO37INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGE_GPIO36INTD_Pos (19UL) /*!< GPIO36INTD (Bit 19) */
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#define GPIO_CFGE_GPIO36INTD_Msk (0x80000UL) /*!< GPIO36INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGE_GPIO36OUTCFG_Pos (17UL) /*!< GPIO36OUTCFG (Bit 17) */
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#define GPIO_CFGE_GPIO36OUTCFG_Msk (0x60000UL) /*!< GPIO36OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGE_GPIO36INCFG_Pos (16UL) /*!< GPIO36INCFG (Bit 16) */
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#define GPIO_CFGE_GPIO36INCFG_Msk (0x10000UL) /*!< GPIO36INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGE_GPIO35INTD_Pos (15UL) /*!< GPIO35INTD (Bit 15) */
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#define GPIO_CFGE_GPIO35INTD_Msk (0x8000UL) /*!< GPIO35INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGE_GPIO35OUTCFG_Pos (13UL) /*!< GPIO35OUTCFG (Bit 13) */
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#define GPIO_CFGE_GPIO35OUTCFG_Msk (0x6000UL) /*!< GPIO35OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGE_GPIO35INCFG_Pos (12UL) /*!< GPIO35INCFG (Bit 12) */
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#define GPIO_CFGE_GPIO35INCFG_Msk (0x1000UL) /*!< GPIO35INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGE_GPIO34INTD_Pos (11UL) /*!< GPIO34INTD (Bit 11) */
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#define GPIO_CFGE_GPIO34INTD_Msk (0x800UL) /*!< GPIO34INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGE_GPIO34OUTCFG_Pos (9UL) /*!< GPIO34OUTCFG (Bit 9) */
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#define GPIO_CFGE_GPIO34OUTCFG_Msk (0x600UL) /*!< GPIO34OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGE_GPIO34INCFG_Pos (8UL) /*!< GPIO34INCFG (Bit 8) */
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#define GPIO_CFGE_GPIO34INCFG_Msk (0x100UL) /*!< GPIO34INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGE_GPIO33INTD_Pos (7UL) /*!< GPIO33INTD (Bit 7) */
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#define GPIO_CFGE_GPIO33INTD_Msk (0x80UL) /*!< GPIO33INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGE_GPIO33OUTCFG_Pos (5UL) /*!< GPIO33OUTCFG (Bit 5) */
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#define GPIO_CFGE_GPIO33OUTCFG_Msk (0x60UL) /*!< GPIO33OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGE_GPIO33INCFG_Pos (4UL) /*!< GPIO33INCFG (Bit 4) */
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#define GPIO_CFGE_GPIO33INCFG_Msk (0x10UL) /*!< GPIO33INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGE_GPIO32INTD_Pos (3UL) /*!< GPIO32INTD (Bit 3) */
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#define GPIO_CFGE_GPIO32INTD_Msk (0x8UL) /*!< GPIO32INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGE_GPIO32OUTCFG_Pos (1UL) /*!< GPIO32OUTCFG (Bit 1) */
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#define GPIO_CFGE_GPIO32OUTCFG_Msk (0x6UL) /*!< GPIO32OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGE_GPIO32INCFG_Pos (0UL) /*!< GPIO32INCFG (Bit 0) */
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#define GPIO_CFGE_GPIO32INCFG_Msk (0x1UL) /*!< GPIO32INCFG (Bitfield-Mask: 0x01) */
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/* ========================================================= CFGF ========================================================== */
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#define GPIO_CFGF_GPIO47INTD_Pos (31UL) /*!< GPIO47INTD (Bit 31) */
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#define GPIO_CFGF_GPIO47INTD_Msk (0x80000000UL) /*!< GPIO47INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGF_GPIO47OUTCFG_Pos (29UL) /*!< GPIO47OUTCFG (Bit 29) */
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#define GPIO_CFGF_GPIO47OUTCFG_Msk (0x60000000UL) /*!< GPIO47OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGF_GPIO47INCFG_Pos (28UL) /*!< GPIO47INCFG (Bit 28) */
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#define GPIO_CFGF_GPIO47INCFG_Msk (0x10000000UL) /*!< GPIO47INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGF_GPIO46INTD_Pos (27UL) /*!< GPIO46INTD (Bit 27) */
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#define GPIO_CFGF_GPIO46INTD_Msk (0x8000000UL) /*!< GPIO46INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGF_GPIO46OUTCFG_Pos (25UL) /*!< GPIO46OUTCFG (Bit 25) */
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#define GPIO_CFGF_GPIO46OUTCFG_Msk (0x6000000UL) /*!< GPIO46OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGF_GPIO46INCFG_Pos (24UL) /*!< GPIO46INCFG (Bit 24) */
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#define GPIO_CFGF_GPIO46INCFG_Msk (0x1000000UL) /*!< GPIO46INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGF_GPIO45INTD_Pos (23UL) /*!< GPIO45INTD (Bit 23) */
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#define GPIO_CFGF_GPIO45INTD_Msk (0x800000UL) /*!< GPIO45INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGF_GPIO45OUTCFG_Pos (21UL) /*!< GPIO45OUTCFG (Bit 21) */
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#define GPIO_CFGF_GPIO45OUTCFG_Msk (0x600000UL) /*!< GPIO45OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGF_GPIO45INCFG_Pos (20UL) /*!< GPIO45INCFG (Bit 20) */
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#define GPIO_CFGF_GPIO45INCFG_Msk (0x100000UL) /*!< GPIO45INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGF_GPIO44INTD_Pos (19UL) /*!< GPIO44INTD (Bit 19) */
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#define GPIO_CFGF_GPIO44INTD_Msk (0x80000UL) /*!< GPIO44INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGF_GPIO44OUTCFG_Pos (17UL) /*!< GPIO44OUTCFG (Bit 17) */
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#define GPIO_CFGF_GPIO44OUTCFG_Msk (0x60000UL) /*!< GPIO44OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGF_GPIO44INCFG_Pos (16UL) /*!< GPIO44INCFG (Bit 16) */
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#define GPIO_CFGF_GPIO44INCFG_Msk (0x10000UL) /*!< GPIO44INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGF_GPIO43INTD_Pos (15UL) /*!< GPIO43INTD (Bit 15) */
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#define GPIO_CFGF_GPIO43INTD_Msk (0x8000UL) /*!< GPIO43INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGF_GPIO43OUTCFG_Pos (13UL) /*!< GPIO43OUTCFG (Bit 13) */
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#define GPIO_CFGF_GPIO43OUTCFG_Msk (0x6000UL) /*!< GPIO43OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGF_GPIO43INCFG_Pos (12UL) /*!< GPIO43INCFG (Bit 12) */
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#define GPIO_CFGF_GPIO43INCFG_Msk (0x1000UL) /*!< GPIO43INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGF_GPIO42INTD_Pos (11UL) /*!< GPIO42INTD (Bit 11) */
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#define GPIO_CFGF_GPIO42INTD_Msk (0x800UL) /*!< GPIO42INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGF_GPIO42OUTCFG_Pos (9UL) /*!< GPIO42OUTCFG (Bit 9) */
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#define GPIO_CFGF_GPIO42OUTCFG_Msk (0x600UL) /*!< GPIO42OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGF_GPIO42INCFG_Pos (8UL) /*!< GPIO42INCFG (Bit 8) */
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#define GPIO_CFGF_GPIO42INCFG_Msk (0x100UL) /*!< GPIO42INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGF_GPIO41INTD_Pos (7UL) /*!< GPIO41INTD (Bit 7) */
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#define GPIO_CFGF_GPIO41INTD_Msk (0x80UL) /*!< GPIO41INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGF_GPIO41OUTCFG_Pos (5UL) /*!< GPIO41OUTCFG (Bit 5) */
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#define GPIO_CFGF_GPIO41OUTCFG_Msk (0x60UL) /*!< GPIO41OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGF_GPIO41INCFG_Pos (4UL) /*!< GPIO41INCFG (Bit 4) */
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#define GPIO_CFGF_GPIO41INCFG_Msk (0x10UL) /*!< GPIO41INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGF_GPIO40INTD_Pos (3UL) /*!< GPIO40INTD (Bit 3) */
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#define GPIO_CFGF_GPIO40INTD_Msk (0x8UL) /*!< GPIO40INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGF_GPIO40OUTCFG_Pos (1UL) /*!< GPIO40OUTCFG (Bit 1) */
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#define GPIO_CFGF_GPIO40OUTCFG_Msk (0x6UL) /*!< GPIO40OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGF_GPIO40INCFG_Pos (0UL) /*!< GPIO40INCFG (Bit 0) */
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#define GPIO_CFGF_GPIO40INCFG_Msk (0x1UL) /*!< GPIO40INCFG (Bitfield-Mask: 0x01) */
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/* ========================================================= CFGG ========================================================== */
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#define GPIO_CFGG_GPIO49INTD_Pos (7UL) /*!< GPIO49INTD (Bit 7) */
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#define GPIO_CFGG_GPIO49INTD_Msk (0x80UL) /*!< GPIO49INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGG_GPIO49OUTCFG_Pos (5UL) /*!< GPIO49OUTCFG (Bit 5) */
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#define GPIO_CFGG_GPIO49OUTCFG_Msk (0x60UL) /*!< GPIO49OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGG_GPIO49INCFG_Pos (4UL) /*!< GPIO49INCFG (Bit 4) */
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#define GPIO_CFGG_GPIO49INCFG_Msk (0x10UL) /*!< GPIO49INCFG (Bitfield-Mask: 0x01) */
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#define GPIO_CFGG_GPIO48INTD_Pos (3UL) /*!< GPIO48INTD (Bit 3) */
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#define GPIO_CFGG_GPIO48INTD_Msk (0x8UL) /*!< GPIO48INTD (Bitfield-Mask: 0x01) */
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#define GPIO_CFGG_GPIO48OUTCFG_Pos (1UL) /*!< GPIO48OUTCFG (Bit 1) */
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#define GPIO_CFGG_GPIO48OUTCFG_Msk (0x6UL) /*!< GPIO48OUTCFG (Bitfield-Mask: 0x03) */
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#define GPIO_CFGG_GPIO48INCFG_Pos (0UL) /*!< GPIO48INCFG (Bit 0) */
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#define GPIO_CFGG_GPIO48INCFG_Msk (0x1UL) /*!< GPIO48INCFG (Bitfield-Mask: 0x01) */
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/* ======================================================== PADKEY ========================================================= */
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#define GPIO_PADKEY_PADKEY_Pos (0UL) /*!< PADKEY (Bit 0) */
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#define GPIO_PADKEY_PADKEY_Msk (0xffffffffUL) /*!< PADKEY (Bitfield-Mask: 0xffffffff) */
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/* ========================================================== RDA ========================================================== */
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#define GPIO_RDA_RDA_Pos (0UL) /*!< RDA (Bit 0) */
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#define GPIO_RDA_RDA_Msk (0xffffffffUL) /*!< RDA (Bitfield-Mask: 0xffffffff) */
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/* ========================================================== RDB ========================================================== */
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#define GPIO_RDB_RDB_Pos (0UL) /*!< RDB (Bit 0) */
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#define GPIO_RDB_RDB_Msk (0x3ffffUL) /*!< RDB (Bitfield-Mask: 0x3ffff) */
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/* ========================================================== WTA ========================================================== */
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#define GPIO_WTA_WTA_Pos (0UL) /*!< WTA (Bit 0) */
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#define GPIO_WTA_WTA_Msk (0xffffffffUL) /*!< WTA (Bitfield-Mask: 0xffffffff) */
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/* ========================================================== WTB ========================================================== */
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#define GPIO_WTB_WTB_Pos (0UL) /*!< WTB (Bit 0) */
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#define GPIO_WTB_WTB_Msk (0x3ffffUL) /*!< WTB (Bitfield-Mask: 0x3ffff) */
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/* ========================================================= WTSA ========================================================== */
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#define GPIO_WTSA_WTSA_Pos (0UL) /*!< WTSA (Bit 0) */
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#define GPIO_WTSA_WTSA_Msk (0xffffffffUL) /*!< WTSA (Bitfield-Mask: 0xffffffff) */
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/* ========================================================= WTSB ========================================================== */
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#define GPIO_WTSB_WTSB_Pos (0UL) /*!< WTSB (Bit 0) */
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#define GPIO_WTSB_WTSB_Msk (0x3ffffUL) /*!< WTSB (Bitfield-Mask: 0x3ffff) */
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/* ========================================================= WTCA ========================================================== */
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#define GPIO_WTCA_WTCA_Pos (0UL) /*!< WTCA (Bit 0) */
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#define GPIO_WTCA_WTCA_Msk (0xffffffffUL) /*!< WTCA (Bitfield-Mask: 0xffffffff) */
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/* ========================================================= WTCB ========================================================== */
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#define GPIO_WTCB_WTCB_Pos (0UL) /*!< WTCB (Bit 0) */
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#define GPIO_WTCB_WTCB_Msk (0x3ffffUL) /*!< WTCB (Bitfield-Mask: 0x3ffff) */
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/* ========================================================== ENA ========================================================== */
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#define GPIO_ENA_ENA_Pos (0UL) /*!< ENA (Bit 0) */
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#define GPIO_ENA_ENA_Msk (0xffffffffUL) /*!< ENA (Bitfield-Mask: 0xffffffff) */
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/* ========================================================== ENB ========================================================== */
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#define GPIO_ENB_ENB_Pos (0UL) /*!< ENB (Bit 0) */
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#define GPIO_ENB_ENB_Msk (0x3ffffUL) /*!< ENB (Bitfield-Mask: 0x3ffff) */
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/* ========================================================= ENSA ========================================================== */
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#define GPIO_ENSA_ENSA_Pos (0UL) /*!< ENSA (Bit 0) */
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#define GPIO_ENSA_ENSA_Msk (0xffffffffUL) /*!< ENSA (Bitfield-Mask: 0xffffffff) */
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/* ========================================================= ENSB ========================================================== */
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#define GPIO_ENSB_ENSB_Pos (0UL) /*!< ENSB (Bit 0) */
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#define GPIO_ENSB_ENSB_Msk (0x3ffffUL) /*!< ENSB (Bitfield-Mask: 0x3ffff) */
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/* ========================================================= ENCA ========================================================== */
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#define GPIO_ENCA_ENCA_Pos (0UL) /*!< ENCA (Bit 0) */
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#define GPIO_ENCA_ENCA_Msk (0xffffffffUL) /*!< ENCA (Bitfield-Mask: 0xffffffff) */
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/* ========================================================= ENCB ========================================================== */
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#define GPIO_ENCB_ENCB_Pos (0UL) /*!< ENCB (Bit 0) */
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#define GPIO_ENCB_ENCB_Msk (0x3ffffUL) /*!< ENCB (Bitfield-Mask: 0x3ffff) */
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/* ======================================================== INT0EN ========================================================= */
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#define GPIO_INT0EN_GPIO31_Pos (31UL) /*!< GPIO31 (Bit 31) */
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#define GPIO_INT0EN_GPIO31_Msk (0x80000000UL) /*!< GPIO31 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0EN_GPIO30_Pos (30UL) /*!< GPIO30 (Bit 30) */
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#define GPIO_INT0EN_GPIO30_Msk (0x40000000UL) /*!< GPIO30 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0EN_GPIO29_Pos (29UL) /*!< GPIO29 (Bit 29) */
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#define GPIO_INT0EN_GPIO29_Msk (0x20000000UL) /*!< GPIO29 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0EN_GPIO28_Pos (28UL) /*!< GPIO28 (Bit 28) */
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#define GPIO_INT0EN_GPIO28_Msk (0x10000000UL) /*!< GPIO28 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0EN_GPIO27_Pos (27UL) /*!< GPIO27 (Bit 27) */
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#define GPIO_INT0EN_GPIO27_Msk (0x8000000UL) /*!< GPIO27 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0EN_GPIO26_Pos (26UL) /*!< GPIO26 (Bit 26) */
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#define GPIO_INT0EN_GPIO26_Msk (0x4000000UL) /*!< GPIO26 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0EN_GPIO25_Pos (25UL) /*!< GPIO25 (Bit 25) */
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#define GPIO_INT0EN_GPIO25_Msk (0x2000000UL) /*!< GPIO25 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0EN_GPIO24_Pos (24UL) /*!< GPIO24 (Bit 24) */
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#define GPIO_INT0EN_GPIO24_Msk (0x1000000UL) /*!< GPIO24 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0EN_GPIO23_Pos (23UL) /*!< GPIO23 (Bit 23) */
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#define GPIO_INT0EN_GPIO23_Msk (0x800000UL) /*!< GPIO23 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0EN_GPIO22_Pos (22UL) /*!< GPIO22 (Bit 22) */
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#define GPIO_INT0EN_GPIO22_Msk (0x400000UL) /*!< GPIO22 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0EN_GPIO21_Pos (21UL) /*!< GPIO21 (Bit 21) */
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#define GPIO_INT0EN_GPIO21_Msk (0x200000UL) /*!< GPIO21 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0EN_GPIO20_Pos (20UL) /*!< GPIO20 (Bit 20) */
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#define GPIO_INT0EN_GPIO20_Msk (0x100000UL) /*!< GPIO20 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0EN_GPIO19_Pos (19UL) /*!< GPIO19 (Bit 19) */
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#define GPIO_INT0EN_GPIO19_Msk (0x80000UL) /*!< GPIO19 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0EN_GPIO18_Pos (18UL) /*!< GPIO18 (Bit 18) */
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#define GPIO_INT0EN_GPIO18_Msk (0x40000UL) /*!< GPIO18 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0EN_GPIO17_Pos (17UL) /*!< GPIO17 (Bit 17) */
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#define GPIO_INT0EN_GPIO17_Msk (0x20000UL) /*!< GPIO17 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0EN_GPIO16_Pos (16UL) /*!< GPIO16 (Bit 16) */
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#define GPIO_INT0EN_GPIO16_Msk (0x10000UL) /*!< GPIO16 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0EN_GPIO15_Pos (15UL) /*!< GPIO15 (Bit 15) */
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#define GPIO_INT0EN_GPIO15_Msk (0x8000UL) /*!< GPIO15 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0EN_GPIO14_Pos (14UL) /*!< GPIO14 (Bit 14) */
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#define GPIO_INT0EN_GPIO14_Msk (0x4000UL) /*!< GPIO14 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0EN_GPIO13_Pos (13UL) /*!< GPIO13 (Bit 13) */
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#define GPIO_INT0EN_GPIO13_Msk (0x2000UL) /*!< GPIO13 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0EN_GPIO12_Pos (12UL) /*!< GPIO12 (Bit 12) */
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#define GPIO_INT0EN_GPIO12_Msk (0x1000UL) /*!< GPIO12 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0EN_GPIO11_Pos (11UL) /*!< GPIO11 (Bit 11) */
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#define GPIO_INT0EN_GPIO11_Msk (0x800UL) /*!< GPIO11 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0EN_GPIO10_Pos (10UL) /*!< GPIO10 (Bit 10) */
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#define GPIO_INT0EN_GPIO10_Msk (0x400UL) /*!< GPIO10 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0EN_GPIO9_Pos (9UL) /*!< GPIO9 (Bit 9) */
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#define GPIO_INT0EN_GPIO9_Msk (0x200UL) /*!< GPIO9 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0EN_GPIO8_Pos (8UL) /*!< GPIO8 (Bit 8) */
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#define GPIO_INT0EN_GPIO8_Msk (0x100UL) /*!< GPIO8 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0EN_GPIO7_Pos (7UL) /*!< GPIO7 (Bit 7) */
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#define GPIO_INT0EN_GPIO7_Msk (0x80UL) /*!< GPIO7 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0EN_GPIO6_Pos (6UL) /*!< GPIO6 (Bit 6) */
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#define GPIO_INT0EN_GPIO6_Msk (0x40UL) /*!< GPIO6 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0EN_GPIO5_Pos (5UL) /*!< GPIO5 (Bit 5) */
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#define GPIO_INT0EN_GPIO5_Msk (0x20UL) /*!< GPIO5 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0EN_GPIO4_Pos (4UL) /*!< GPIO4 (Bit 4) */
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#define GPIO_INT0EN_GPIO4_Msk (0x10UL) /*!< GPIO4 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0EN_GPIO3_Pos (3UL) /*!< GPIO3 (Bit 3) */
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#define GPIO_INT0EN_GPIO3_Msk (0x8UL) /*!< GPIO3 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0EN_GPIO2_Pos (2UL) /*!< GPIO2 (Bit 2) */
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#define GPIO_INT0EN_GPIO2_Msk (0x4UL) /*!< GPIO2 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0EN_GPIO1_Pos (1UL) /*!< GPIO1 (Bit 1) */
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#define GPIO_INT0EN_GPIO1_Msk (0x2UL) /*!< GPIO1 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0EN_GPIO0_Pos (0UL) /*!< GPIO0 (Bit 0) */
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#define GPIO_INT0EN_GPIO0_Msk (0x1UL) /*!< GPIO0 (Bitfield-Mask: 0x01) */
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/* ======================================================= INT0STAT ======================================================== */
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#define GPIO_INT0STAT_GPIO31_Pos (31UL) /*!< GPIO31 (Bit 31) */
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#define GPIO_INT0STAT_GPIO31_Msk (0x80000000UL) /*!< GPIO31 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0STAT_GPIO30_Pos (30UL) /*!< GPIO30 (Bit 30) */
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#define GPIO_INT0STAT_GPIO30_Msk (0x40000000UL) /*!< GPIO30 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0STAT_GPIO29_Pos (29UL) /*!< GPIO29 (Bit 29) */
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#define GPIO_INT0STAT_GPIO29_Msk (0x20000000UL) /*!< GPIO29 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0STAT_GPIO28_Pos (28UL) /*!< GPIO28 (Bit 28) */
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#define GPIO_INT0STAT_GPIO28_Msk (0x10000000UL) /*!< GPIO28 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0STAT_GPIO27_Pos (27UL) /*!< GPIO27 (Bit 27) */
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#define GPIO_INT0STAT_GPIO27_Msk (0x8000000UL) /*!< GPIO27 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0STAT_GPIO26_Pos (26UL) /*!< GPIO26 (Bit 26) */
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#define GPIO_INT0STAT_GPIO26_Msk (0x4000000UL) /*!< GPIO26 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0STAT_GPIO25_Pos (25UL) /*!< GPIO25 (Bit 25) */
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#define GPIO_INT0STAT_GPIO25_Msk (0x2000000UL) /*!< GPIO25 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0STAT_GPIO24_Pos (24UL) /*!< GPIO24 (Bit 24) */
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#define GPIO_INT0STAT_GPIO24_Msk (0x1000000UL) /*!< GPIO24 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0STAT_GPIO23_Pos (23UL) /*!< GPIO23 (Bit 23) */
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#define GPIO_INT0STAT_GPIO23_Msk (0x800000UL) /*!< GPIO23 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0STAT_GPIO22_Pos (22UL) /*!< GPIO22 (Bit 22) */
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#define GPIO_INT0STAT_GPIO22_Msk (0x400000UL) /*!< GPIO22 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0STAT_GPIO21_Pos (21UL) /*!< GPIO21 (Bit 21) */
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#define GPIO_INT0STAT_GPIO21_Msk (0x200000UL) /*!< GPIO21 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0STAT_GPIO20_Pos (20UL) /*!< GPIO20 (Bit 20) */
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#define GPIO_INT0STAT_GPIO20_Msk (0x100000UL) /*!< GPIO20 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0STAT_GPIO19_Pos (19UL) /*!< GPIO19 (Bit 19) */
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#define GPIO_INT0STAT_GPIO19_Msk (0x80000UL) /*!< GPIO19 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0STAT_GPIO18_Pos (18UL) /*!< GPIO18 (Bit 18) */
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#define GPIO_INT0STAT_GPIO18_Msk (0x40000UL) /*!< GPIO18 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0STAT_GPIO17_Pos (17UL) /*!< GPIO17 (Bit 17) */
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#define GPIO_INT0STAT_GPIO17_Msk (0x20000UL) /*!< GPIO17 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0STAT_GPIO16_Pos (16UL) /*!< GPIO16 (Bit 16) */
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#define GPIO_INT0STAT_GPIO16_Msk (0x10000UL) /*!< GPIO16 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0STAT_GPIO15_Pos (15UL) /*!< GPIO15 (Bit 15) */
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#define GPIO_INT0STAT_GPIO15_Msk (0x8000UL) /*!< GPIO15 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0STAT_GPIO14_Pos (14UL) /*!< GPIO14 (Bit 14) */
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#define GPIO_INT0STAT_GPIO14_Msk (0x4000UL) /*!< GPIO14 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0STAT_GPIO13_Pos (13UL) /*!< GPIO13 (Bit 13) */
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#define GPIO_INT0STAT_GPIO13_Msk (0x2000UL) /*!< GPIO13 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0STAT_GPIO12_Pos (12UL) /*!< GPIO12 (Bit 12) */
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#define GPIO_INT0STAT_GPIO12_Msk (0x1000UL) /*!< GPIO12 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0STAT_GPIO11_Pos (11UL) /*!< GPIO11 (Bit 11) */
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#define GPIO_INT0STAT_GPIO11_Msk (0x800UL) /*!< GPIO11 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0STAT_GPIO10_Pos (10UL) /*!< GPIO10 (Bit 10) */
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#define GPIO_INT0STAT_GPIO10_Msk (0x400UL) /*!< GPIO10 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0STAT_GPIO9_Pos (9UL) /*!< GPIO9 (Bit 9) */
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#define GPIO_INT0STAT_GPIO9_Msk (0x200UL) /*!< GPIO9 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0STAT_GPIO8_Pos (8UL) /*!< GPIO8 (Bit 8) */
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#define GPIO_INT0STAT_GPIO8_Msk (0x100UL) /*!< GPIO8 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0STAT_GPIO7_Pos (7UL) /*!< GPIO7 (Bit 7) */
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#define GPIO_INT0STAT_GPIO7_Msk (0x80UL) /*!< GPIO7 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0STAT_GPIO6_Pos (6UL) /*!< GPIO6 (Bit 6) */
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#define GPIO_INT0STAT_GPIO6_Msk (0x40UL) /*!< GPIO6 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0STAT_GPIO5_Pos (5UL) /*!< GPIO5 (Bit 5) */
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#define GPIO_INT0STAT_GPIO5_Msk (0x20UL) /*!< GPIO5 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0STAT_GPIO4_Pos (4UL) /*!< GPIO4 (Bit 4) */
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#define GPIO_INT0STAT_GPIO4_Msk (0x10UL) /*!< GPIO4 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0STAT_GPIO3_Pos (3UL) /*!< GPIO3 (Bit 3) */
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#define GPIO_INT0STAT_GPIO3_Msk (0x8UL) /*!< GPIO3 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0STAT_GPIO2_Pos (2UL) /*!< GPIO2 (Bit 2) */
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#define GPIO_INT0STAT_GPIO2_Msk (0x4UL) /*!< GPIO2 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0STAT_GPIO1_Pos (1UL) /*!< GPIO1 (Bit 1) */
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#define GPIO_INT0STAT_GPIO1_Msk (0x2UL) /*!< GPIO1 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0STAT_GPIO0_Pos (0UL) /*!< GPIO0 (Bit 0) */
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#define GPIO_INT0STAT_GPIO0_Msk (0x1UL) /*!< GPIO0 (Bitfield-Mask: 0x01) */
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/* ======================================================== INT0CLR ======================================================== */
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#define GPIO_INT0CLR_GPIO31_Pos (31UL) /*!< GPIO31 (Bit 31) */
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#define GPIO_INT0CLR_GPIO31_Msk (0x80000000UL) /*!< GPIO31 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0CLR_GPIO30_Pos (30UL) /*!< GPIO30 (Bit 30) */
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#define GPIO_INT0CLR_GPIO30_Msk (0x40000000UL) /*!< GPIO30 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0CLR_GPIO29_Pos (29UL) /*!< GPIO29 (Bit 29) */
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#define GPIO_INT0CLR_GPIO29_Msk (0x20000000UL) /*!< GPIO29 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0CLR_GPIO28_Pos (28UL) /*!< GPIO28 (Bit 28) */
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#define GPIO_INT0CLR_GPIO28_Msk (0x10000000UL) /*!< GPIO28 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0CLR_GPIO27_Pos (27UL) /*!< GPIO27 (Bit 27) */
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#define GPIO_INT0CLR_GPIO27_Msk (0x8000000UL) /*!< GPIO27 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0CLR_GPIO26_Pos (26UL) /*!< GPIO26 (Bit 26) */
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#define GPIO_INT0CLR_GPIO26_Msk (0x4000000UL) /*!< GPIO26 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0CLR_GPIO25_Pos (25UL) /*!< GPIO25 (Bit 25) */
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#define GPIO_INT0CLR_GPIO25_Msk (0x2000000UL) /*!< GPIO25 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0CLR_GPIO24_Pos (24UL) /*!< GPIO24 (Bit 24) */
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#define GPIO_INT0CLR_GPIO24_Msk (0x1000000UL) /*!< GPIO24 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0CLR_GPIO23_Pos (23UL) /*!< GPIO23 (Bit 23) */
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#define GPIO_INT0CLR_GPIO23_Msk (0x800000UL) /*!< GPIO23 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0CLR_GPIO22_Pos (22UL) /*!< GPIO22 (Bit 22) */
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#define GPIO_INT0CLR_GPIO22_Msk (0x400000UL) /*!< GPIO22 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0CLR_GPIO21_Pos (21UL) /*!< GPIO21 (Bit 21) */
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#define GPIO_INT0CLR_GPIO21_Msk (0x200000UL) /*!< GPIO21 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0CLR_GPIO20_Pos (20UL) /*!< GPIO20 (Bit 20) */
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#define GPIO_INT0CLR_GPIO20_Msk (0x100000UL) /*!< GPIO20 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0CLR_GPIO19_Pos (19UL) /*!< GPIO19 (Bit 19) */
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#define GPIO_INT0CLR_GPIO19_Msk (0x80000UL) /*!< GPIO19 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0CLR_GPIO18_Pos (18UL) /*!< GPIO18 (Bit 18) */
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#define GPIO_INT0CLR_GPIO18_Msk (0x40000UL) /*!< GPIO18 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0CLR_GPIO17_Pos (17UL) /*!< GPIO17 (Bit 17) */
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#define GPIO_INT0CLR_GPIO17_Msk (0x20000UL) /*!< GPIO17 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0CLR_GPIO16_Pos (16UL) /*!< GPIO16 (Bit 16) */
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#define GPIO_INT0CLR_GPIO16_Msk (0x10000UL) /*!< GPIO16 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0CLR_GPIO15_Pos (15UL) /*!< GPIO15 (Bit 15) */
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#define GPIO_INT0CLR_GPIO15_Msk (0x8000UL) /*!< GPIO15 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0CLR_GPIO14_Pos (14UL) /*!< GPIO14 (Bit 14) */
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#define GPIO_INT0CLR_GPIO14_Msk (0x4000UL) /*!< GPIO14 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0CLR_GPIO13_Pos (13UL) /*!< GPIO13 (Bit 13) */
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#define GPIO_INT0CLR_GPIO13_Msk (0x2000UL) /*!< GPIO13 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0CLR_GPIO12_Pos (12UL) /*!< GPIO12 (Bit 12) */
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#define GPIO_INT0CLR_GPIO12_Msk (0x1000UL) /*!< GPIO12 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0CLR_GPIO11_Pos (11UL) /*!< GPIO11 (Bit 11) */
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#define GPIO_INT0CLR_GPIO11_Msk (0x800UL) /*!< GPIO11 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0CLR_GPIO10_Pos (10UL) /*!< GPIO10 (Bit 10) */
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#define GPIO_INT0CLR_GPIO10_Msk (0x400UL) /*!< GPIO10 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0CLR_GPIO9_Pos (9UL) /*!< GPIO9 (Bit 9) */
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#define GPIO_INT0CLR_GPIO9_Msk (0x200UL) /*!< GPIO9 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0CLR_GPIO8_Pos (8UL) /*!< GPIO8 (Bit 8) */
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#define GPIO_INT0CLR_GPIO8_Msk (0x100UL) /*!< GPIO8 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0CLR_GPIO7_Pos (7UL) /*!< GPIO7 (Bit 7) */
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#define GPIO_INT0CLR_GPIO7_Msk (0x80UL) /*!< GPIO7 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0CLR_GPIO6_Pos (6UL) /*!< GPIO6 (Bit 6) */
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#define GPIO_INT0CLR_GPIO6_Msk (0x40UL) /*!< GPIO6 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0CLR_GPIO5_Pos (5UL) /*!< GPIO5 (Bit 5) */
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#define GPIO_INT0CLR_GPIO5_Msk (0x20UL) /*!< GPIO5 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0CLR_GPIO4_Pos (4UL) /*!< GPIO4 (Bit 4) */
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#define GPIO_INT0CLR_GPIO4_Msk (0x10UL) /*!< GPIO4 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0CLR_GPIO3_Pos (3UL) /*!< GPIO3 (Bit 3) */
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#define GPIO_INT0CLR_GPIO3_Msk (0x8UL) /*!< GPIO3 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0CLR_GPIO2_Pos (2UL) /*!< GPIO2 (Bit 2) */
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#define GPIO_INT0CLR_GPIO2_Msk (0x4UL) /*!< GPIO2 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0CLR_GPIO1_Pos (1UL) /*!< GPIO1 (Bit 1) */
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#define GPIO_INT0CLR_GPIO1_Msk (0x2UL) /*!< GPIO1 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0CLR_GPIO0_Pos (0UL) /*!< GPIO0 (Bit 0) */
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#define GPIO_INT0CLR_GPIO0_Msk (0x1UL) /*!< GPIO0 (Bitfield-Mask: 0x01) */
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/* ======================================================== INT0SET ======================================================== */
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#define GPIO_INT0SET_GPIO31_Pos (31UL) /*!< GPIO31 (Bit 31) */
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#define GPIO_INT0SET_GPIO31_Msk (0x80000000UL) /*!< GPIO31 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0SET_GPIO30_Pos (30UL) /*!< GPIO30 (Bit 30) */
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#define GPIO_INT0SET_GPIO30_Msk (0x40000000UL) /*!< GPIO30 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0SET_GPIO29_Pos (29UL) /*!< GPIO29 (Bit 29) */
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#define GPIO_INT0SET_GPIO29_Msk (0x20000000UL) /*!< GPIO29 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0SET_GPIO28_Pos (28UL) /*!< GPIO28 (Bit 28) */
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#define GPIO_INT0SET_GPIO28_Msk (0x10000000UL) /*!< GPIO28 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0SET_GPIO27_Pos (27UL) /*!< GPIO27 (Bit 27) */
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#define GPIO_INT0SET_GPIO27_Msk (0x8000000UL) /*!< GPIO27 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0SET_GPIO26_Pos (26UL) /*!< GPIO26 (Bit 26) */
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#define GPIO_INT0SET_GPIO26_Msk (0x4000000UL) /*!< GPIO26 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0SET_GPIO25_Pos (25UL) /*!< GPIO25 (Bit 25) */
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#define GPIO_INT0SET_GPIO25_Msk (0x2000000UL) /*!< GPIO25 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0SET_GPIO24_Pos (24UL) /*!< GPIO24 (Bit 24) */
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#define GPIO_INT0SET_GPIO24_Msk (0x1000000UL) /*!< GPIO24 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0SET_GPIO23_Pos (23UL) /*!< GPIO23 (Bit 23) */
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#define GPIO_INT0SET_GPIO23_Msk (0x800000UL) /*!< GPIO23 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0SET_GPIO22_Pos (22UL) /*!< GPIO22 (Bit 22) */
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#define GPIO_INT0SET_GPIO22_Msk (0x400000UL) /*!< GPIO22 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0SET_GPIO21_Pos (21UL) /*!< GPIO21 (Bit 21) */
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#define GPIO_INT0SET_GPIO21_Msk (0x200000UL) /*!< GPIO21 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0SET_GPIO20_Pos (20UL) /*!< GPIO20 (Bit 20) */
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#define GPIO_INT0SET_GPIO20_Msk (0x100000UL) /*!< GPIO20 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0SET_GPIO19_Pos (19UL) /*!< GPIO19 (Bit 19) */
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#define GPIO_INT0SET_GPIO19_Msk (0x80000UL) /*!< GPIO19 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0SET_GPIO18_Pos (18UL) /*!< GPIO18 (Bit 18) */
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#define GPIO_INT0SET_GPIO18_Msk (0x40000UL) /*!< GPIO18 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0SET_GPIO17_Pos (17UL) /*!< GPIO17 (Bit 17) */
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#define GPIO_INT0SET_GPIO17_Msk (0x20000UL) /*!< GPIO17 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0SET_GPIO16_Pos (16UL) /*!< GPIO16 (Bit 16) */
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#define GPIO_INT0SET_GPIO16_Msk (0x10000UL) /*!< GPIO16 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0SET_GPIO15_Pos (15UL) /*!< GPIO15 (Bit 15) */
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#define GPIO_INT0SET_GPIO15_Msk (0x8000UL) /*!< GPIO15 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0SET_GPIO14_Pos (14UL) /*!< GPIO14 (Bit 14) */
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#define GPIO_INT0SET_GPIO14_Msk (0x4000UL) /*!< GPIO14 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0SET_GPIO13_Pos (13UL) /*!< GPIO13 (Bit 13) */
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#define GPIO_INT0SET_GPIO13_Msk (0x2000UL) /*!< GPIO13 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0SET_GPIO12_Pos (12UL) /*!< GPIO12 (Bit 12) */
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#define GPIO_INT0SET_GPIO12_Msk (0x1000UL) /*!< GPIO12 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0SET_GPIO11_Pos (11UL) /*!< GPIO11 (Bit 11) */
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#define GPIO_INT0SET_GPIO11_Msk (0x800UL) /*!< GPIO11 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0SET_GPIO10_Pos (10UL) /*!< GPIO10 (Bit 10) */
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#define GPIO_INT0SET_GPIO10_Msk (0x400UL) /*!< GPIO10 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0SET_GPIO9_Pos (9UL) /*!< GPIO9 (Bit 9) */
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#define GPIO_INT0SET_GPIO9_Msk (0x200UL) /*!< GPIO9 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0SET_GPIO8_Pos (8UL) /*!< GPIO8 (Bit 8) */
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#define GPIO_INT0SET_GPIO8_Msk (0x100UL) /*!< GPIO8 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0SET_GPIO7_Pos (7UL) /*!< GPIO7 (Bit 7) */
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#define GPIO_INT0SET_GPIO7_Msk (0x80UL) /*!< GPIO7 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0SET_GPIO6_Pos (6UL) /*!< GPIO6 (Bit 6) */
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#define GPIO_INT0SET_GPIO6_Msk (0x40UL) /*!< GPIO6 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0SET_GPIO5_Pos (5UL) /*!< GPIO5 (Bit 5) */
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#define GPIO_INT0SET_GPIO5_Msk (0x20UL) /*!< GPIO5 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0SET_GPIO4_Pos (4UL) /*!< GPIO4 (Bit 4) */
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#define GPIO_INT0SET_GPIO4_Msk (0x10UL) /*!< GPIO4 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0SET_GPIO3_Pos (3UL) /*!< GPIO3 (Bit 3) */
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#define GPIO_INT0SET_GPIO3_Msk (0x8UL) /*!< GPIO3 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0SET_GPIO2_Pos (2UL) /*!< GPIO2 (Bit 2) */
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#define GPIO_INT0SET_GPIO2_Msk (0x4UL) /*!< GPIO2 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0SET_GPIO1_Pos (1UL) /*!< GPIO1 (Bit 1) */
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#define GPIO_INT0SET_GPIO1_Msk (0x2UL) /*!< GPIO1 (Bitfield-Mask: 0x01) */
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#define GPIO_INT0SET_GPIO0_Pos (0UL) /*!< GPIO0 (Bit 0) */
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#define GPIO_INT0SET_GPIO0_Msk (0x1UL) /*!< GPIO0 (Bitfield-Mask: 0x01) */
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/* ======================================================== INT1EN ========================================================= */
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#define GPIO_INT1EN_GPIO49_Pos (17UL) /*!< GPIO49 (Bit 17) */
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#define GPIO_INT1EN_GPIO49_Msk (0x20000UL) /*!< GPIO49 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1EN_GPIO48_Pos (16UL) /*!< GPIO48 (Bit 16) */
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#define GPIO_INT1EN_GPIO48_Msk (0x10000UL) /*!< GPIO48 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1EN_GPIO47_Pos (15UL) /*!< GPIO47 (Bit 15) */
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#define GPIO_INT1EN_GPIO47_Msk (0x8000UL) /*!< GPIO47 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1EN_GPIO46_Pos (14UL) /*!< GPIO46 (Bit 14) */
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#define GPIO_INT1EN_GPIO46_Msk (0x4000UL) /*!< GPIO46 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1EN_GPIO45_Pos (13UL) /*!< GPIO45 (Bit 13) */
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#define GPIO_INT1EN_GPIO45_Msk (0x2000UL) /*!< GPIO45 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1EN_GPIO44_Pos (12UL) /*!< GPIO44 (Bit 12) */
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#define GPIO_INT1EN_GPIO44_Msk (0x1000UL) /*!< GPIO44 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1EN_GPIO43_Pos (11UL) /*!< GPIO43 (Bit 11) */
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#define GPIO_INT1EN_GPIO43_Msk (0x800UL) /*!< GPIO43 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1EN_GPIO42_Pos (10UL) /*!< GPIO42 (Bit 10) */
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#define GPIO_INT1EN_GPIO42_Msk (0x400UL) /*!< GPIO42 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1EN_GPIO41_Pos (9UL) /*!< GPIO41 (Bit 9) */
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#define GPIO_INT1EN_GPIO41_Msk (0x200UL) /*!< GPIO41 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1EN_GPIO40_Pos (8UL) /*!< GPIO40 (Bit 8) */
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#define GPIO_INT1EN_GPIO40_Msk (0x100UL) /*!< GPIO40 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1EN_GPIO39_Pos (7UL) /*!< GPIO39 (Bit 7) */
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#define GPIO_INT1EN_GPIO39_Msk (0x80UL) /*!< GPIO39 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1EN_GPIO38_Pos (6UL) /*!< GPIO38 (Bit 6) */
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#define GPIO_INT1EN_GPIO38_Msk (0x40UL) /*!< GPIO38 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1EN_GPIO37_Pos (5UL) /*!< GPIO37 (Bit 5) */
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#define GPIO_INT1EN_GPIO37_Msk (0x20UL) /*!< GPIO37 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1EN_GPIO36_Pos (4UL) /*!< GPIO36 (Bit 4) */
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#define GPIO_INT1EN_GPIO36_Msk (0x10UL) /*!< GPIO36 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1EN_GPIO35_Pos (3UL) /*!< GPIO35 (Bit 3) */
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#define GPIO_INT1EN_GPIO35_Msk (0x8UL) /*!< GPIO35 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1EN_GPIO34_Pos (2UL) /*!< GPIO34 (Bit 2) */
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#define GPIO_INT1EN_GPIO34_Msk (0x4UL) /*!< GPIO34 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1EN_GPIO33_Pos (1UL) /*!< GPIO33 (Bit 1) */
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#define GPIO_INT1EN_GPIO33_Msk (0x2UL) /*!< GPIO33 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1EN_GPIO32_Pos (0UL) /*!< GPIO32 (Bit 0) */
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#define GPIO_INT1EN_GPIO32_Msk (0x1UL) /*!< GPIO32 (Bitfield-Mask: 0x01) */
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/* ======================================================= INT1STAT ======================================================== */
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#define GPIO_INT1STAT_GPIO49_Pos (17UL) /*!< GPIO49 (Bit 17) */
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#define GPIO_INT1STAT_GPIO49_Msk (0x20000UL) /*!< GPIO49 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1STAT_GPIO48_Pos (16UL) /*!< GPIO48 (Bit 16) */
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#define GPIO_INT1STAT_GPIO48_Msk (0x10000UL) /*!< GPIO48 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1STAT_GPIO47_Pos (15UL) /*!< GPIO47 (Bit 15) */
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#define GPIO_INT1STAT_GPIO47_Msk (0x8000UL) /*!< GPIO47 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1STAT_GPIO46_Pos (14UL) /*!< GPIO46 (Bit 14) */
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#define GPIO_INT1STAT_GPIO46_Msk (0x4000UL) /*!< GPIO46 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1STAT_GPIO45_Pos (13UL) /*!< GPIO45 (Bit 13) */
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#define GPIO_INT1STAT_GPIO45_Msk (0x2000UL) /*!< GPIO45 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1STAT_GPIO44_Pos (12UL) /*!< GPIO44 (Bit 12) */
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#define GPIO_INT1STAT_GPIO44_Msk (0x1000UL) /*!< GPIO44 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1STAT_GPIO43_Pos (11UL) /*!< GPIO43 (Bit 11) */
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#define GPIO_INT1STAT_GPIO43_Msk (0x800UL) /*!< GPIO43 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1STAT_GPIO42_Pos (10UL) /*!< GPIO42 (Bit 10) */
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#define GPIO_INT1STAT_GPIO42_Msk (0x400UL) /*!< GPIO42 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1STAT_GPIO41_Pos (9UL) /*!< GPIO41 (Bit 9) */
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#define GPIO_INT1STAT_GPIO41_Msk (0x200UL) /*!< GPIO41 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1STAT_GPIO40_Pos (8UL) /*!< GPIO40 (Bit 8) */
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#define GPIO_INT1STAT_GPIO40_Msk (0x100UL) /*!< GPIO40 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1STAT_GPIO39_Pos (7UL) /*!< GPIO39 (Bit 7) */
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#define GPIO_INT1STAT_GPIO39_Msk (0x80UL) /*!< GPIO39 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1STAT_GPIO38_Pos (6UL) /*!< GPIO38 (Bit 6) */
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#define GPIO_INT1STAT_GPIO38_Msk (0x40UL) /*!< GPIO38 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1STAT_GPIO37_Pos (5UL) /*!< GPIO37 (Bit 5) */
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#define GPIO_INT1STAT_GPIO37_Msk (0x20UL) /*!< GPIO37 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1STAT_GPIO36_Pos (4UL) /*!< GPIO36 (Bit 4) */
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#define GPIO_INT1STAT_GPIO36_Msk (0x10UL) /*!< GPIO36 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1STAT_GPIO35_Pos (3UL) /*!< GPIO35 (Bit 3) */
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#define GPIO_INT1STAT_GPIO35_Msk (0x8UL) /*!< GPIO35 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1STAT_GPIO34_Pos (2UL) /*!< GPIO34 (Bit 2) */
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#define GPIO_INT1STAT_GPIO34_Msk (0x4UL) /*!< GPIO34 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1STAT_GPIO33_Pos (1UL) /*!< GPIO33 (Bit 1) */
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#define GPIO_INT1STAT_GPIO33_Msk (0x2UL) /*!< GPIO33 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1STAT_GPIO32_Pos (0UL) /*!< GPIO32 (Bit 0) */
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#define GPIO_INT1STAT_GPIO32_Msk (0x1UL) /*!< GPIO32 (Bitfield-Mask: 0x01) */
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/* ======================================================== INT1CLR ======================================================== */
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#define GPIO_INT1CLR_GPIO49_Pos (17UL) /*!< GPIO49 (Bit 17) */
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#define GPIO_INT1CLR_GPIO49_Msk (0x20000UL) /*!< GPIO49 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1CLR_GPIO48_Pos (16UL) /*!< GPIO48 (Bit 16) */
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#define GPIO_INT1CLR_GPIO48_Msk (0x10000UL) /*!< GPIO48 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1CLR_GPIO47_Pos (15UL) /*!< GPIO47 (Bit 15) */
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#define GPIO_INT1CLR_GPIO47_Msk (0x8000UL) /*!< GPIO47 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1CLR_GPIO46_Pos (14UL) /*!< GPIO46 (Bit 14) */
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#define GPIO_INT1CLR_GPIO46_Msk (0x4000UL) /*!< GPIO46 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1CLR_GPIO45_Pos (13UL) /*!< GPIO45 (Bit 13) */
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#define GPIO_INT1CLR_GPIO45_Msk (0x2000UL) /*!< GPIO45 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1CLR_GPIO44_Pos (12UL) /*!< GPIO44 (Bit 12) */
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#define GPIO_INT1CLR_GPIO44_Msk (0x1000UL) /*!< GPIO44 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1CLR_GPIO43_Pos (11UL) /*!< GPIO43 (Bit 11) */
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#define GPIO_INT1CLR_GPIO43_Msk (0x800UL) /*!< GPIO43 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1CLR_GPIO42_Pos (10UL) /*!< GPIO42 (Bit 10) */
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#define GPIO_INT1CLR_GPIO42_Msk (0x400UL) /*!< GPIO42 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1CLR_GPIO41_Pos (9UL) /*!< GPIO41 (Bit 9) */
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#define GPIO_INT1CLR_GPIO41_Msk (0x200UL) /*!< GPIO41 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1CLR_GPIO40_Pos (8UL) /*!< GPIO40 (Bit 8) */
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#define GPIO_INT1CLR_GPIO40_Msk (0x100UL) /*!< GPIO40 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1CLR_GPIO39_Pos (7UL) /*!< GPIO39 (Bit 7) */
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#define GPIO_INT1CLR_GPIO39_Msk (0x80UL) /*!< GPIO39 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1CLR_GPIO38_Pos (6UL) /*!< GPIO38 (Bit 6) */
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#define GPIO_INT1CLR_GPIO38_Msk (0x40UL) /*!< GPIO38 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1CLR_GPIO37_Pos (5UL) /*!< GPIO37 (Bit 5) */
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#define GPIO_INT1CLR_GPIO37_Msk (0x20UL) /*!< GPIO37 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1CLR_GPIO36_Pos (4UL) /*!< GPIO36 (Bit 4) */
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#define GPIO_INT1CLR_GPIO36_Msk (0x10UL) /*!< GPIO36 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1CLR_GPIO35_Pos (3UL) /*!< GPIO35 (Bit 3) */
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#define GPIO_INT1CLR_GPIO35_Msk (0x8UL) /*!< GPIO35 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1CLR_GPIO34_Pos (2UL) /*!< GPIO34 (Bit 2) */
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#define GPIO_INT1CLR_GPIO34_Msk (0x4UL) /*!< GPIO34 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1CLR_GPIO33_Pos (1UL) /*!< GPIO33 (Bit 1) */
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#define GPIO_INT1CLR_GPIO33_Msk (0x2UL) /*!< GPIO33 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1CLR_GPIO32_Pos (0UL) /*!< GPIO32 (Bit 0) */
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#define GPIO_INT1CLR_GPIO32_Msk (0x1UL) /*!< GPIO32 (Bitfield-Mask: 0x01) */
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/* ======================================================== INT1SET ======================================================== */
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#define GPIO_INT1SET_GPIO49_Pos (17UL) /*!< GPIO49 (Bit 17) */
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#define GPIO_INT1SET_GPIO49_Msk (0x20000UL) /*!< GPIO49 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1SET_GPIO48_Pos (16UL) /*!< GPIO48 (Bit 16) */
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#define GPIO_INT1SET_GPIO48_Msk (0x10000UL) /*!< GPIO48 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1SET_GPIO47_Pos (15UL) /*!< GPIO47 (Bit 15) */
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#define GPIO_INT1SET_GPIO47_Msk (0x8000UL) /*!< GPIO47 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1SET_GPIO46_Pos (14UL) /*!< GPIO46 (Bit 14) */
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#define GPIO_INT1SET_GPIO46_Msk (0x4000UL) /*!< GPIO46 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1SET_GPIO45_Pos (13UL) /*!< GPIO45 (Bit 13) */
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#define GPIO_INT1SET_GPIO45_Msk (0x2000UL) /*!< GPIO45 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1SET_GPIO44_Pos (12UL) /*!< GPIO44 (Bit 12) */
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#define GPIO_INT1SET_GPIO44_Msk (0x1000UL) /*!< GPIO44 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1SET_GPIO43_Pos (11UL) /*!< GPIO43 (Bit 11) */
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#define GPIO_INT1SET_GPIO43_Msk (0x800UL) /*!< GPIO43 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1SET_GPIO42_Pos (10UL) /*!< GPIO42 (Bit 10) */
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#define GPIO_INT1SET_GPIO42_Msk (0x400UL) /*!< GPIO42 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1SET_GPIO41_Pos (9UL) /*!< GPIO41 (Bit 9) */
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#define GPIO_INT1SET_GPIO41_Msk (0x200UL) /*!< GPIO41 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1SET_GPIO40_Pos (8UL) /*!< GPIO40 (Bit 8) */
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#define GPIO_INT1SET_GPIO40_Msk (0x100UL) /*!< GPIO40 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1SET_GPIO39_Pos (7UL) /*!< GPIO39 (Bit 7) */
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#define GPIO_INT1SET_GPIO39_Msk (0x80UL) /*!< GPIO39 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1SET_GPIO38_Pos (6UL) /*!< GPIO38 (Bit 6) */
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#define GPIO_INT1SET_GPIO38_Msk (0x40UL) /*!< GPIO38 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1SET_GPIO37_Pos (5UL) /*!< GPIO37 (Bit 5) */
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#define GPIO_INT1SET_GPIO37_Msk (0x20UL) /*!< GPIO37 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1SET_GPIO36_Pos (4UL) /*!< GPIO36 (Bit 4) */
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#define GPIO_INT1SET_GPIO36_Msk (0x10UL) /*!< GPIO36 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1SET_GPIO35_Pos (3UL) /*!< GPIO35 (Bit 3) */
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#define GPIO_INT1SET_GPIO35_Msk (0x8UL) /*!< GPIO35 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1SET_GPIO34_Pos (2UL) /*!< GPIO34 (Bit 2) */
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#define GPIO_INT1SET_GPIO34_Msk (0x4UL) /*!< GPIO34 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1SET_GPIO33_Pos (1UL) /*!< GPIO33 (Bit 1) */
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#define GPIO_INT1SET_GPIO33_Msk (0x2UL) /*!< GPIO33 (Bitfield-Mask: 0x01) */
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#define GPIO_INT1SET_GPIO32_Pos (0UL) /*!< GPIO32 (Bit 0) */
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#define GPIO_INT1SET_GPIO32_Msk (0x1UL) /*!< GPIO32 (Bitfield-Mask: 0x01) */
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/* =========================================================================================================================== */
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/* ================ IOMSTR0 ================ */
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/* =========================================================================================================================== */
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/* ========================================================= FIFO ========================================================== */
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#define IOMSTR0_FIFO_FIFO_Pos (0UL) /*!< FIFO (Bit 0) */
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#define IOMSTR0_FIFO_FIFO_Msk (0xffffffffUL) /*!< FIFO (Bitfield-Mask: 0xffffffff) */
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/* ======================================================== FIFOPTR ======================================================== */
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#define IOMSTR0_FIFOPTR_FIFOREM_Pos (16UL) /*!< FIFOREM (Bit 16) */
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#define IOMSTR0_FIFOPTR_FIFOREM_Msk (0x7f0000UL) /*!< FIFOREM (Bitfield-Mask: 0x7f) */
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#define IOMSTR0_FIFOPTR_FIFOSIZ_Pos (0UL) /*!< FIFOSIZ (Bit 0) */
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#define IOMSTR0_FIFOPTR_FIFOSIZ_Msk (0x7fUL) /*!< FIFOSIZ (Bitfield-Mask: 0x7f) */
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/* ======================================================== TLNGTH ========================================================= */
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#define IOMSTR0_TLNGTH_TLNGTH_Pos (0UL) /*!< TLNGTH (Bit 0) */
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#define IOMSTR0_TLNGTH_TLNGTH_Msk (0xfffUL) /*!< TLNGTH (Bitfield-Mask: 0xfff) */
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/* ======================================================== FIFOTHR ======================================================== */
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#define IOMSTR0_FIFOTHR_FIFOWTHR_Pos (8UL) /*!< FIFOWTHR (Bit 8) */
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#define IOMSTR0_FIFOTHR_FIFOWTHR_Msk (0x3f00UL) /*!< FIFOWTHR (Bitfield-Mask: 0x3f) */
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#define IOMSTR0_FIFOTHR_FIFORTHR_Pos (0UL) /*!< FIFORTHR (Bit 0) */
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#define IOMSTR0_FIFOTHR_FIFORTHR_Msk (0x3fUL) /*!< FIFORTHR (Bitfield-Mask: 0x3f) */
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/* ======================================================== CLKCFG ========================================================= */
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#define IOMSTR0_CLKCFG_TOTPER_Pos (24UL) /*!< TOTPER (Bit 24) */
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#define IOMSTR0_CLKCFG_TOTPER_Msk (0xff000000UL) /*!< TOTPER (Bitfield-Mask: 0xff) */
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#define IOMSTR0_CLKCFG_LOWPER_Pos (16UL) /*!< LOWPER (Bit 16) */
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#define IOMSTR0_CLKCFG_LOWPER_Msk (0xff0000UL) /*!< LOWPER (Bitfield-Mask: 0xff) */
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#define IOMSTR0_CLKCFG_DIVEN_Pos (12UL) /*!< DIVEN (Bit 12) */
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#define IOMSTR0_CLKCFG_DIVEN_Msk (0x1000UL) /*!< DIVEN (Bitfield-Mask: 0x01) */
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#define IOMSTR0_CLKCFG_DIV3_Pos (11UL) /*!< DIV3 (Bit 11) */
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#define IOMSTR0_CLKCFG_DIV3_Msk (0x800UL) /*!< DIV3 (Bitfield-Mask: 0x01) */
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#define IOMSTR0_CLKCFG_FSEL_Pos (8UL) /*!< FSEL (Bit 8) */
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#define IOMSTR0_CLKCFG_FSEL_Msk (0x700UL) /*!< FSEL (Bitfield-Mask: 0x07) */
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/* ========================================================== CMD ========================================================== */
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#define IOMSTR0_CMD_CMD_Pos (0UL) /*!< CMD (Bit 0) */
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#define IOMSTR0_CMD_CMD_Msk (0xffffffffUL) /*!< CMD (Bitfield-Mask: 0xffffffff) */
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/* ======================================================== CMDRPT ========================================================= */
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#define IOMSTR0_CMDRPT_CMDRPT_Pos (0UL) /*!< CMDRPT (Bit 0) */
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#define IOMSTR0_CMDRPT_CMDRPT_Msk (0x1fUL) /*!< CMDRPT (Bitfield-Mask: 0x1f) */
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/* ======================================================== STATUS ========================================================= */
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#define IOMSTR0_STATUS_IDLEST_Pos (2UL) /*!< IDLEST (Bit 2) */
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#define IOMSTR0_STATUS_IDLEST_Msk (0x4UL) /*!< IDLEST (Bitfield-Mask: 0x01) */
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#define IOMSTR0_STATUS_CMDACT_Pos (1UL) /*!< CMDACT (Bit 1) */
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#define IOMSTR0_STATUS_CMDACT_Msk (0x2UL) /*!< CMDACT (Bitfield-Mask: 0x01) */
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#define IOMSTR0_STATUS_ERR_Pos (0UL) /*!< ERR (Bit 0) */
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#define IOMSTR0_STATUS_ERR_Msk (0x1UL) /*!< ERR (Bitfield-Mask: 0x01) */
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/* ========================================================== CFG ========================================================== */
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#define IOMSTR0_CFG_IFCEN_Pos (31UL) /*!< IFCEN (Bit 31) */
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#define IOMSTR0_CFG_IFCEN_Msk (0x80000000UL) /*!< IFCEN (Bitfield-Mask: 0x01) */
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#define IOMSTR0_CFG_SPHA_Pos (2UL) /*!< SPHA (Bit 2) */
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#define IOMSTR0_CFG_SPHA_Msk (0x4UL) /*!< SPHA (Bitfield-Mask: 0x01) */
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#define IOMSTR0_CFG_SPOL_Pos (1UL) /*!< SPOL (Bit 1) */
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#define IOMSTR0_CFG_SPOL_Msk (0x2UL) /*!< SPOL (Bitfield-Mask: 0x01) */
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#define IOMSTR0_CFG_IFCSEL_Pos (0UL) /*!< IFCSEL (Bit 0) */
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#define IOMSTR0_CFG_IFCSEL_Msk (0x1UL) /*!< IFCSEL (Bitfield-Mask: 0x01) */
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/* ========================================================= INTEN ========================================================= */
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#define IOMSTR0_INTEN_ARB_Pos (10UL) /*!< ARB (Bit 10) */
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#define IOMSTR0_INTEN_ARB_Msk (0x400UL) /*!< ARB (Bitfield-Mask: 0x01) */
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#define IOMSTR0_INTEN_STOP_Pos (9UL) /*!< STOP (Bit 9) */
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#define IOMSTR0_INTEN_STOP_Msk (0x200UL) /*!< STOP (Bitfield-Mask: 0x01) */
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#define IOMSTR0_INTEN_START_Pos (8UL) /*!< START (Bit 8) */
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#define IOMSTR0_INTEN_START_Msk (0x100UL) /*!< START (Bitfield-Mask: 0x01) */
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#define IOMSTR0_INTEN_ICMD_Pos (7UL) /*!< ICMD (Bit 7) */
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#define IOMSTR0_INTEN_ICMD_Msk (0x80UL) /*!< ICMD (Bitfield-Mask: 0x01) */
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#define IOMSTR0_INTEN_IACC_Pos (6UL) /*!< IACC (Bit 6) */
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#define IOMSTR0_INTEN_IACC_Msk (0x40UL) /*!< IACC (Bitfield-Mask: 0x01) */
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#define IOMSTR0_INTEN_WTLEN_Pos (5UL) /*!< WTLEN (Bit 5) */
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#define IOMSTR0_INTEN_WTLEN_Msk (0x20UL) /*!< WTLEN (Bitfield-Mask: 0x01) */
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#define IOMSTR0_INTEN_NAK_Pos (4UL) /*!< NAK (Bit 4) */
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#define IOMSTR0_INTEN_NAK_Msk (0x10UL) /*!< NAK (Bitfield-Mask: 0x01) */
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#define IOMSTR0_INTEN_FOVFL_Pos (3UL) /*!< FOVFL (Bit 3) */
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#define IOMSTR0_INTEN_FOVFL_Msk (0x8UL) /*!< FOVFL (Bitfield-Mask: 0x01) */
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#define IOMSTR0_INTEN_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */
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#define IOMSTR0_INTEN_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */
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#define IOMSTR0_INTEN_THR_Pos (1UL) /*!< THR (Bit 1) */
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#define IOMSTR0_INTEN_THR_Msk (0x2UL) /*!< THR (Bitfield-Mask: 0x01) */
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#define IOMSTR0_INTEN_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */
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#define IOMSTR0_INTEN_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */
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/* ======================================================== INTSTAT ======================================================== */
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#define IOMSTR0_INTSTAT_ARB_Pos (10UL) /*!< ARB (Bit 10) */
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#define IOMSTR0_INTSTAT_ARB_Msk (0x400UL) /*!< ARB (Bitfield-Mask: 0x01) */
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#define IOMSTR0_INTSTAT_STOP_Pos (9UL) /*!< STOP (Bit 9) */
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#define IOMSTR0_INTSTAT_STOP_Msk (0x200UL) /*!< STOP (Bitfield-Mask: 0x01) */
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#define IOMSTR0_INTSTAT_START_Pos (8UL) /*!< START (Bit 8) */
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#define IOMSTR0_INTSTAT_START_Msk (0x100UL) /*!< START (Bitfield-Mask: 0x01) */
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#define IOMSTR0_INTSTAT_ICMD_Pos (7UL) /*!< ICMD (Bit 7) */
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#define IOMSTR0_INTSTAT_ICMD_Msk (0x80UL) /*!< ICMD (Bitfield-Mask: 0x01) */
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#define IOMSTR0_INTSTAT_IACC_Pos (6UL) /*!< IACC (Bit 6) */
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#define IOMSTR0_INTSTAT_IACC_Msk (0x40UL) /*!< IACC (Bitfield-Mask: 0x01) */
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#define IOMSTR0_INTSTAT_WTLEN_Pos (5UL) /*!< WTLEN (Bit 5) */
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#define IOMSTR0_INTSTAT_WTLEN_Msk (0x20UL) /*!< WTLEN (Bitfield-Mask: 0x01) */
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#define IOMSTR0_INTSTAT_NAK_Pos (4UL) /*!< NAK (Bit 4) */
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#define IOMSTR0_INTSTAT_NAK_Msk (0x10UL) /*!< NAK (Bitfield-Mask: 0x01) */
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#define IOMSTR0_INTSTAT_FOVFL_Pos (3UL) /*!< FOVFL (Bit 3) */
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#define IOMSTR0_INTSTAT_FOVFL_Msk (0x8UL) /*!< FOVFL (Bitfield-Mask: 0x01) */
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#define IOMSTR0_INTSTAT_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */
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#define IOMSTR0_INTSTAT_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */
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#define IOMSTR0_INTSTAT_THR_Pos (1UL) /*!< THR (Bit 1) */
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#define IOMSTR0_INTSTAT_THR_Msk (0x2UL) /*!< THR (Bitfield-Mask: 0x01) */
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#define IOMSTR0_INTSTAT_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */
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#define IOMSTR0_INTSTAT_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */
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/* ======================================================== INTCLR ========================================================= */
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#define IOMSTR0_INTCLR_ARB_Pos (10UL) /*!< ARB (Bit 10) */
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#define IOMSTR0_INTCLR_ARB_Msk (0x400UL) /*!< ARB (Bitfield-Mask: 0x01) */
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#define IOMSTR0_INTCLR_STOP_Pos (9UL) /*!< STOP (Bit 9) */
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#define IOMSTR0_INTCLR_STOP_Msk (0x200UL) /*!< STOP (Bitfield-Mask: 0x01) */
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#define IOMSTR0_INTCLR_START_Pos (8UL) /*!< START (Bit 8) */
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#define IOMSTR0_INTCLR_START_Msk (0x100UL) /*!< START (Bitfield-Mask: 0x01) */
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#define IOMSTR0_INTCLR_ICMD_Pos (7UL) /*!< ICMD (Bit 7) */
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#define IOMSTR0_INTCLR_ICMD_Msk (0x80UL) /*!< ICMD (Bitfield-Mask: 0x01) */
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#define IOMSTR0_INTCLR_IACC_Pos (6UL) /*!< IACC (Bit 6) */
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#define IOMSTR0_INTCLR_IACC_Msk (0x40UL) /*!< IACC (Bitfield-Mask: 0x01) */
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#define IOMSTR0_INTCLR_WTLEN_Pos (5UL) /*!< WTLEN (Bit 5) */
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#define IOMSTR0_INTCLR_WTLEN_Msk (0x20UL) /*!< WTLEN (Bitfield-Mask: 0x01) */
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#define IOMSTR0_INTCLR_NAK_Pos (4UL) /*!< NAK (Bit 4) */
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#define IOMSTR0_INTCLR_NAK_Msk (0x10UL) /*!< NAK (Bitfield-Mask: 0x01) */
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#define IOMSTR0_INTCLR_FOVFL_Pos (3UL) /*!< FOVFL (Bit 3) */
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#define IOMSTR0_INTCLR_FOVFL_Msk (0x8UL) /*!< FOVFL (Bitfield-Mask: 0x01) */
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#define IOMSTR0_INTCLR_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */
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#define IOMSTR0_INTCLR_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */
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#define IOMSTR0_INTCLR_THR_Pos (1UL) /*!< THR (Bit 1) */
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#define IOMSTR0_INTCLR_THR_Msk (0x2UL) /*!< THR (Bitfield-Mask: 0x01) */
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#define IOMSTR0_INTCLR_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */
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#define IOMSTR0_INTCLR_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */
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/* ======================================================== INTSET ========================================================= */
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#define IOMSTR0_INTSET_ARB_Pos (10UL) /*!< ARB (Bit 10) */
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#define IOMSTR0_INTSET_ARB_Msk (0x400UL) /*!< ARB (Bitfield-Mask: 0x01) */
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#define IOMSTR0_INTSET_STOP_Pos (9UL) /*!< STOP (Bit 9) */
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#define IOMSTR0_INTSET_STOP_Msk (0x200UL) /*!< STOP (Bitfield-Mask: 0x01) */
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#define IOMSTR0_INTSET_START_Pos (8UL) /*!< START (Bit 8) */
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#define IOMSTR0_INTSET_START_Msk (0x100UL) /*!< START (Bitfield-Mask: 0x01) */
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#define IOMSTR0_INTSET_ICMD_Pos (7UL) /*!< ICMD (Bit 7) */
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#define IOMSTR0_INTSET_ICMD_Msk (0x80UL) /*!< ICMD (Bitfield-Mask: 0x01) */
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#define IOMSTR0_INTSET_IACC_Pos (6UL) /*!< IACC (Bit 6) */
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#define IOMSTR0_INTSET_IACC_Msk (0x40UL) /*!< IACC (Bitfield-Mask: 0x01) */
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#define IOMSTR0_INTSET_WTLEN_Pos (5UL) /*!< WTLEN (Bit 5) */
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#define IOMSTR0_INTSET_WTLEN_Msk (0x20UL) /*!< WTLEN (Bitfield-Mask: 0x01) */
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#define IOMSTR0_INTSET_NAK_Pos (4UL) /*!< NAK (Bit 4) */
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#define IOMSTR0_INTSET_NAK_Msk (0x10UL) /*!< NAK (Bitfield-Mask: 0x01) */
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#define IOMSTR0_INTSET_FOVFL_Pos (3UL) /*!< FOVFL (Bit 3) */
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#define IOMSTR0_INTSET_FOVFL_Msk (0x8UL) /*!< FOVFL (Bitfield-Mask: 0x01) */
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#define IOMSTR0_INTSET_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */
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#define IOMSTR0_INTSET_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */
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#define IOMSTR0_INTSET_THR_Pos (1UL) /*!< THR (Bit 1) */
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#define IOMSTR0_INTSET_THR_Msk (0x2UL) /*!< THR (Bitfield-Mask: 0x01) */
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#define IOMSTR0_INTSET_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */
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#define IOMSTR0_INTSET_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */
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/* =========================================================================================================================== */
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/* ================ IOSLAVE ================ */
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/* =========================================================================================================================== */
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/* ======================================================== FIFOPTR ======================================================== */
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#define IOSLAVE_FIFOPTR_FIFOSIZ_Pos (8UL) /*!< FIFOSIZ (Bit 8) */
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#define IOSLAVE_FIFOPTR_FIFOSIZ_Msk (0xff00UL) /*!< FIFOSIZ (Bitfield-Mask: 0xff) */
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#define IOSLAVE_FIFOPTR_FIFOPTR_Pos (0UL) /*!< FIFOPTR (Bit 0) */
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#define IOSLAVE_FIFOPTR_FIFOPTR_Msk (0xffUL) /*!< FIFOPTR (Bitfield-Mask: 0xff) */
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/* ======================================================== FIFOCFG ======================================================== */
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#define IOSLAVE_FIFOCFG_ROBASE_Pos (24UL) /*!< ROBASE (Bit 24) */
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#define IOSLAVE_FIFOCFG_ROBASE_Msk (0x3f000000UL) /*!< ROBASE (Bitfield-Mask: 0x3f) */
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#define IOSLAVE_FIFOCFG_FIFOMAX_Pos (8UL) /*!< FIFOMAX (Bit 8) */
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#define IOSLAVE_FIFOCFG_FIFOMAX_Msk (0x3f00UL) /*!< FIFOMAX (Bitfield-Mask: 0x3f) */
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#define IOSLAVE_FIFOCFG_FIFOBASE_Pos (0UL) /*!< FIFOBASE (Bit 0) */
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#define IOSLAVE_FIFOCFG_FIFOBASE_Msk (0x1fUL) /*!< FIFOBASE (Bitfield-Mask: 0x1f) */
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/* ======================================================== FIFOTHR ======================================================== */
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#define IOSLAVE_FIFOTHR_FIFOTHR_Pos (0UL) /*!< FIFOTHR (Bit 0) */
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#define IOSLAVE_FIFOTHR_FIFOTHR_Msk (0xffUL) /*!< FIFOTHR (Bitfield-Mask: 0xff) */
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/* ========================================================= FUPD ========================================================== */
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#define IOSLAVE_FUPD_IOREAD_Pos (1UL) /*!< IOREAD (Bit 1) */
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#define IOSLAVE_FUPD_IOREAD_Msk (0x2UL) /*!< IOREAD (Bitfield-Mask: 0x01) */
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#define IOSLAVE_FUPD_FIFOUPD_Pos (0UL) /*!< FIFOUPD (Bit 0) */
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#define IOSLAVE_FUPD_FIFOUPD_Msk (0x1UL) /*!< FIFOUPD (Bitfield-Mask: 0x01) */
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/* ======================================================== FIFOCTR ======================================================== */
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#define IOSLAVE_FIFOCTR_FIFOCTR_Pos (0UL) /*!< FIFOCTR (Bit 0) */
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#define IOSLAVE_FIFOCTR_FIFOCTR_Msk (0x3ffUL) /*!< FIFOCTR (Bitfield-Mask: 0x3ff) */
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/* ======================================================== FIFOINC ======================================================== */
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#define IOSLAVE_FIFOINC_FIFOINC_Pos (0UL) /*!< FIFOINC (Bit 0) */
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#define IOSLAVE_FIFOINC_FIFOINC_Msk (0x3ffUL) /*!< FIFOINC (Bitfield-Mask: 0x3ff) */
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/* ========================================================== CFG ========================================================== */
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#define IOSLAVE_CFG_IFCEN_Pos (31UL) /*!< IFCEN (Bit 31) */
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#define IOSLAVE_CFG_IFCEN_Msk (0x80000000UL) /*!< IFCEN (Bitfield-Mask: 0x01) */
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#define IOSLAVE_CFG_I2CADDR_Pos (8UL) /*!< I2CADDR (Bit 8) */
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#define IOSLAVE_CFG_I2CADDR_Msk (0xfff00UL) /*!< I2CADDR (Bitfield-Mask: 0xfff) */
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#define IOSLAVE_CFG_STARTRD_Pos (4UL) /*!< STARTRD (Bit 4) */
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#define IOSLAVE_CFG_STARTRD_Msk (0x10UL) /*!< STARTRD (Bitfield-Mask: 0x01) */
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#define IOSLAVE_CFG_LSB_Pos (2UL) /*!< LSB (Bit 2) */
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#define IOSLAVE_CFG_LSB_Msk (0x4UL) /*!< LSB (Bitfield-Mask: 0x01) */
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#define IOSLAVE_CFG_SPOL_Pos (1UL) /*!< SPOL (Bit 1) */
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#define IOSLAVE_CFG_SPOL_Msk (0x2UL) /*!< SPOL (Bitfield-Mask: 0x01) */
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#define IOSLAVE_CFG_IFCSEL_Pos (0UL) /*!< IFCSEL (Bit 0) */
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#define IOSLAVE_CFG_IFCSEL_Msk (0x1UL) /*!< IFCSEL (Bitfield-Mask: 0x01) */
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/* ========================================================= PRENC ========================================================= */
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#define IOSLAVE_PRENC_PRENC_Pos (0UL) /*!< PRENC (Bit 0) */
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#define IOSLAVE_PRENC_PRENC_Msk (0x1fUL) /*!< PRENC (Bitfield-Mask: 0x1f) */
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/* ======================================================= IOINTCTL ======================================================== */
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#define IOSLAVE_IOINTCTL_IOINTSET_Pos (24UL) /*!< IOINTSET (Bit 24) */
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#define IOSLAVE_IOINTCTL_IOINTSET_Msk (0xff000000UL) /*!< IOINTSET (Bitfield-Mask: 0xff) */
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#define IOSLAVE_IOINTCTL_IOINTCLR_Pos (16UL) /*!< IOINTCLR (Bit 16) */
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#define IOSLAVE_IOINTCTL_IOINTCLR_Msk (0x10000UL) /*!< IOINTCLR (Bitfield-Mask: 0x01) */
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#define IOSLAVE_IOINTCTL_IOINT_Pos (8UL) /*!< IOINT (Bit 8) */
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#define IOSLAVE_IOINTCTL_IOINT_Msk (0xff00UL) /*!< IOINT (Bitfield-Mask: 0xff) */
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#define IOSLAVE_IOINTCTL_IOINTEN_Pos (0UL) /*!< IOINTEN (Bit 0) */
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#define IOSLAVE_IOINTCTL_IOINTEN_Msk (0xffUL) /*!< IOINTEN (Bitfield-Mask: 0xff) */
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/* ======================================================== GENADD ========================================================= */
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#define IOSLAVE_GENADD_GADATA_Pos (0UL) /*!< GADATA (Bit 0) */
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#define IOSLAVE_GENADD_GADATA_Msk (0xffUL) /*!< GADATA (Bitfield-Mask: 0xff) */
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/* ========================================================= INTEN ========================================================= */
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#define IOSLAVE_INTEN_IOINTW_Pos (5UL) /*!< IOINTW (Bit 5) */
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#define IOSLAVE_INTEN_IOINTW_Msk (0x20UL) /*!< IOINTW (Bitfield-Mask: 0x01) */
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#define IOSLAVE_INTEN_GENAD_Pos (4UL) /*!< GENAD (Bit 4) */
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#define IOSLAVE_INTEN_GENAD_Msk (0x10UL) /*!< GENAD (Bitfield-Mask: 0x01) */
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#define IOSLAVE_INTEN_FRDERR_Pos (3UL) /*!< FRDERR (Bit 3) */
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#define IOSLAVE_INTEN_FRDERR_Msk (0x8UL) /*!< FRDERR (Bitfield-Mask: 0x01) */
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#define IOSLAVE_INTEN_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */
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#define IOSLAVE_INTEN_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */
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#define IOSLAVE_INTEN_FOVFL_Pos (1UL) /*!< FOVFL (Bit 1) */
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#define IOSLAVE_INTEN_FOVFL_Msk (0x2UL) /*!< FOVFL (Bitfield-Mask: 0x01) */
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#define IOSLAVE_INTEN_FSIZE_Pos (0UL) /*!< FSIZE (Bit 0) */
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#define IOSLAVE_INTEN_FSIZE_Msk (0x1UL) /*!< FSIZE (Bitfield-Mask: 0x01) */
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/* ======================================================== INTSTAT ======================================================== */
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#define IOSLAVE_INTSTAT_IOINTW_Pos (5UL) /*!< IOINTW (Bit 5) */
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#define IOSLAVE_INTSTAT_IOINTW_Msk (0x20UL) /*!< IOINTW (Bitfield-Mask: 0x01) */
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#define IOSLAVE_INTSTAT_GENAD_Pos (4UL) /*!< GENAD (Bit 4) */
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#define IOSLAVE_INTSTAT_GENAD_Msk (0x10UL) /*!< GENAD (Bitfield-Mask: 0x01) */
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#define IOSLAVE_INTSTAT_FRDERR_Pos (3UL) /*!< FRDERR (Bit 3) */
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#define IOSLAVE_INTSTAT_FRDERR_Msk (0x8UL) /*!< FRDERR (Bitfield-Mask: 0x01) */
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#define IOSLAVE_INTSTAT_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */
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#define IOSLAVE_INTSTAT_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */
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#define IOSLAVE_INTSTAT_FOVFL_Pos (1UL) /*!< FOVFL (Bit 1) */
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#define IOSLAVE_INTSTAT_FOVFL_Msk (0x2UL) /*!< FOVFL (Bitfield-Mask: 0x01) */
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#define IOSLAVE_INTSTAT_FSIZE_Pos (0UL) /*!< FSIZE (Bit 0) */
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#define IOSLAVE_INTSTAT_FSIZE_Msk (0x1UL) /*!< FSIZE (Bitfield-Mask: 0x01) */
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/* ======================================================== INTCLR ========================================================= */
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#define IOSLAVE_INTCLR_IOINTW_Pos (5UL) /*!< IOINTW (Bit 5) */
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#define IOSLAVE_INTCLR_IOINTW_Msk (0x20UL) /*!< IOINTW (Bitfield-Mask: 0x01) */
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#define IOSLAVE_INTCLR_GENAD_Pos (4UL) /*!< GENAD (Bit 4) */
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#define IOSLAVE_INTCLR_GENAD_Msk (0x10UL) /*!< GENAD (Bitfield-Mask: 0x01) */
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#define IOSLAVE_INTCLR_FRDERR_Pos (3UL) /*!< FRDERR (Bit 3) */
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#define IOSLAVE_INTCLR_FRDERR_Msk (0x8UL) /*!< FRDERR (Bitfield-Mask: 0x01) */
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#define IOSLAVE_INTCLR_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */
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#define IOSLAVE_INTCLR_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */
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#define IOSLAVE_INTCLR_FOVFL_Pos (1UL) /*!< FOVFL (Bit 1) */
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#define IOSLAVE_INTCLR_FOVFL_Msk (0x2UL) /*!< FOVFL (Bitfield-Mask: 0x01) */
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#define IOSLAVE_INTCLR_FSIZE_Pos (0UL) /*!< FSIZE (Bit 0) */
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#define IOSLAVE_INTCLR_FSIZE_Msk (0x1UL) /*!< FSIZE (Bitfield-Mask: 0x01) */
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/* ======================================================== INTSET ========================================================= */
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#define IOSLAVE_INTSET_IOINTW_Pos (5UL) /*!< IOINTW (Bit 5) */
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#define IOSLAVE_INTSET_IOINTW_Msk (0x20UL) /*!< IOINTW (Bitfield-Mask: 0x01) */
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#define IOSLAVE_INTSET_GENAD_Pos (4UL) /*!< GENAD (Bit 4) */
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#define IOSLAVE_INTSET_GENAD_Msk (0x10UL) /*!< GENAD (Bitfield-Mask: 0x01) */
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#define IOSLAVE_INTSET_FRDERR_Pos (3UL) /*!< FRDERR (Bit 3) */
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#define IOSLAVE_INTSET_FRDERR_Msk (0x8UL) /*!< FRDERR (Bitfield-Mask: 0x01) */
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#define IOSLAVE_INTSET_FUNDFL_Pos (2UL) /*!< FUNDFL (Bit 2) */
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#define IOSLAVE_INTSET_FUNDFL_Msk (0x4UL) /*!< FUNDFL (Bitfield-Mask: 0x01) */
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#define IOSLAVE_INTSET_FOVFL_Pos (1UL) /*!< FOVFL (Bit 1) */
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#define IOSLAVE_INTSET_FOVFL_Msk (0x2UL) /*!< FOVFL (Bitfield-Mask: 0x01) */
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#define IOSLAVE_INTSET_FSIZE_Pos (0UL) /*!< FSIZE (Bit 0) */
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#define IOSLAVE_INTSET_FSIZE_Msk (0x1UL) /*!< FSIZE (Bitfield-Mask: 0x01) */
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/* ====================================================== REGACCINTEN ====================================================== */
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#define IOSLAVE_REGACCINTEN_REGACC_Pos (0UL) /*!< REGACC (Bit 0) */
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#define IOSLAVE_REGACCINTEN_REGACC_Msk (0xffffffffUL) /*!< REGACC (Bitfield-Mask: 0xffffffff) */
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/* ===================================================== REGACCINTSTAT ===================================================== */
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#define IOSLAVE_REGACCINTSTAT_REGACC_Pos (0UL) /*!< REGACC (Bit 0) */
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#define IOSLAVE_REGACCINTSTAT_REGACC_Msk (0xffffffffUL) /*!< REGACC (Bitfield-Mask: 0xffffffff) */
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/* ===================================================== REGACCINTCLR ====================================================== */
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#define IOSLAVE_REGACCINTCLR_REGACC_Pos (0UL) /*!< REGACC (Bit 0) */
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#define IOSLAVE_REGACCINTCLR_REGACC_Msk (0xffffffffUL) /*!< REGACC (Bitfield-Mask: 0xffffffff) */
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/* ===================================================== REGACCINTSET ====================================================== */
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#define IOSLAVE_REGACCINTSET_REGACC_Pos (0UL) /*!< REGACC (Bit 0) */
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#define IOSLAVE_REGACCINTSET_REGACC_Msk (0xffffffffUL) /*!< REGACC (Bitfield-Mask: 0xffffffff) */
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/* =========================================================================================================================== */
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/* ================ MCUCTRL ================ */
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/* =========================================================================================================================== */
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/* ======================================================= CHIP_INFO ======================================================= */
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#define MCUCTRL_CHIP_INFO_CLASS_Pos (24UL) /*!< CLASS (Bit 24) */
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#define MCUCTRL_CHIP_INFO_CLASS_Msk (0xff000000UL) /*!< CLASS (Bitfield-Mask: 0xff) */
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#define MCUCTRL_CHIP_INFO_FLASH_Pos (20UL) /*!< FLASH (Bit 20) */
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#define MCUCTRL_CHIP_INFO_FLASH_Msk (0xf00000UL) /*!< FLASH (Bitfield-Mask: 0x0f) */
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#define MCUCTRL_CHIP_INFO_RAM_Pos (16UL) /*!< RAM (Bit 16) */
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#define MCUCTRL_CHIP_INFO_RAM_Msk (0xf0000UL) /*!< RAM (Bitfield-Mask: 0x0f) */
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#define MCUCTRL_CHIP_INFO_MAJORREV_Pos (12UL) /*!< MAJORREV (Bit 12) */
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#define MCUCTRL_CHIP_INFO_MAJORREV_Msk (0xf000UL) /*!< MAJORREV (Bitfield-Mask: 0x0f) */
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#define MCUCTRL_CHIP_INFO_MINORREV_Pos (8UL) /*!< MINORREV (Bit 8) */
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#define MCUCTRL_CHIP_INFO_MINORREV_Msk (0xf00UL) /*!< MINORREV (Bitfield-Mask: 0x0f) */
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#define MCUCTRL_CHIP_INFO_PKG_Pos (6UL) /*!< PKG (Bit 6) */
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#define MCUCTRL_CHIP_INFO_PKG_Msk (0xc0UL) /*!< PKG (Bitfield-Mask: 0x03) */
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#define MCUCTRL_CHIP_INFO_PINS_Pos (3UL) /*!< PINS (Bit 3) */
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#define MCUCTRL_CHIP_INFO_PINS_Msk (0x38UL) /*!< PINS (Bitfield-Mask: 0x07) */
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#define MCUCTRL_CHIP_INFO_TEMP_Pos (1UL) /*!< TEMP (Bit 1) */
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#define MCUCTRL_CHIP_INFO_TEMP_Msk (0x6UL) /*!< TEMP (Bitfield-Mask: 0x03) */
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#define MCUCTRL_CHIP_INFO_QUAL_Pos (0UL) /*!< QUAL (Bit 0) */
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#define MCUCTRL_CHIP_INFO_QUAL_Msk (0x1UL) /*!< QUAL (Bitfield-Mask: 0x01) */
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/* ======================================================== CHIPID0 ======================================================== */
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#define MCUCTRL_CHIPID0_VALUE_Pos (0UL) /*!< VALUE (Bit 0) */
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#define MCUCTRL_CHIPID0_VALUE_Msk (0xffffffffUL) /*!< VALUE (Bitfield-Mask: 0xffffffff) */
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/* ======================================================== CHIPID1 ======================================================== */
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#define MCUCTRL_CHIPID1_VALUE_Pos (0UL) /*!< VALUE (Bit 0) */
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#define MCUCTRL_CHIPID1_VALUE_Msk (0xffffffffUL) /*!< VALUE (Bitfield-Mask: 0xffffffff) */
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/* ======================================================== CHIPREV ======================================================== */
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#define MCUCTRL_CHIPREV_REVISION_Pos (0UL) /*!< REVISION (Bit 0) */
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#define MCUCTRL_CHIPREV_REVISION_Msk (0xffUL) /*!< REVISION (Bitfield-Mask: 0xff) */
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/* ======================================================= SUPPLYSRC ======================================================= */
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#define MCUCTRL_SUPPLYSRC_COREBUCKEN_Pos (1UL) /*!< COREBUCKEN (Bit 1) */
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#define MCUCTRL_SUPPLYSRC_COREBUCKEN_Msk (0x2UL) /*!< COREBUCKEN (Bitfield-Mask: 0x01) */
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#define MCUCTRL_SUPPLYSRC_MEMBUCKEN_Pos (0UL) /*!< MEMBUCKEN (Bit 0) */
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#define MCUCTRL_SUPPLYSRC_MEMBUCKEN_Msk (0x1UL) /*!< MEMBUCKEN (Bitfield-Mask: 0x01) */
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/* ===================================================== SUPPLYSTATUS ====================================================== */
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#define MCUCTRL_SUPPLYSTATUS_COREBUCKON_Pos (1UL) /*!< COREBUCKON (Bit 1) */
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#define MCUCTRL_SUPPLYSTATUS_COREBUCKON_Msk (0x2UL) /*!< COREBUCKON (Bitfield-Mask: 0x01) */
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#define MCUCTRL_SUPPLYSTATUS_MEMBUCKON_Pos (0UL) /*!< MEMBUCKON (Bit 0) */
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#define MCUCTRL_SUPPLYSTATUS_MEMBUCKON_Msk (0x1UL) /*!< MEMBUCKON (Bitfield-Mask: 0x01) */
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/* ======================================================= BANDGAPEN ======================================================= */
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#define MCUCTRL_BANDGAPEN_BGPEN_Pos (0UL) /*!< BGPEN (Bit 0) */
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#define MCUCTRL_BANDGAPEN_BGPEN_Msk (0x1UL) /*!< BGPEN (Bitfield-Mask: 0x01) */
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/* ==================================================== SRAMPWDINSLEEP ===================================================== */
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#define MCUCTRL_SRAMPWDINSLEEP_BANK7_Pos (7UL) /*!< BANK7 (Bit 7) */
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#define MCUCTRL_SRAMPWDINSLEEP_BANK7_Msk (0x80UL) /*!< BANK7 (Bitfield-Mask: 0x01) */
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#define MCUCTRL_SRAMPWDINSLEEP_BANK6_Pos (6UL) /*!< BANK6 (Bit 6) */
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#define MCUCTRL_SRAMPWDINSLEEP_BANK6_Msk (0x40UL) /*!< BANK6 (Bitfield-Mask: 0x01) */
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#define MCUCTRL_SRAMPWDINSLEEP_BANK5_Pos (5UL) /*!< BANK5 (Bit 5) */
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#define MCUCTRL_SRAMPWDINSLEEP_BANK5_Msk (0x20UL) /*!< BANK5 (Bitfield-Mask: 0x01) */
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#define MCUCTRL_SRAMPWDINSLEEP_BANK4_Pos (4UL) /*!< BANK4 (Bit 4) */
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#define MCUCTRL_SRAMPWDINSLEEP_BANK4_Msk (0x10UL) /*!< BANK4 (Bitfield-Mask: 0x01) */
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#define MCUCTRL_SRAMPWDINSLEEP_BANK3_Pos (3UL) /*!< BANK3 (Bit 3) */
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#define MCUCTRL_SRAMPWDINSLEEP_BANK3_Msk (0x8UL) /*!< BANK3 (Bitfield-Mask: 0x01) */
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#define MCUCTRL_SRAMPWDINSLEEP_BANK2_Pos (2UL) /*!< BANK2 (Bit 2) */
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#define MCUCTRL_SRAMPWDINSLEEP_BANK2_Msk (0x4UL) /*!< BANK2 (Bitfield-Mask: 0x01) */
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#define MCUCTRL_SRAMPWDINSLEEP_BANK1_Pos (1UL) /*!< BANK1 (Bit 1) */
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#define MCUCTRL_SRAMPWDINSLEEP_BANK1_Msk (0x2UL) /*!< BANK1 (Bitfield-Mask: 0x01) */
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#define MCUCTRL_SRAMPWDINSLEEP_BANK0_Pos (0UL) /*!< BANK0 (Bit 0) */
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#define MCUCTRL_SRAMPWDINSLEEP_BANK0_Msk (0x1UL) /*!< BANK0 (Bitfield-Mask: 0x01) */
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/* ====================================================== SRAMPWRDIS ======================================================= */
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#define MCUCTRL_SRAMPWRDIS_BANK7_Pos (7UL) /*!< BANK7 (Bit 7) */
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#define MCUCTRL_SRAMPWRDIS_BANK7_Msk (0x80UL) /*!< BANK7 (Bitfield-Mask: 0x01) */
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#define MCUCTRL_SRAMPWRDIS_BANK6_Pos (6UL) /*!< BANK6 (Bit 6) */
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#define MCUCTRL_SRAMPWRDIS_BANK6_Msk (0x40UL) /*!< BANK6 (Bitfield-Mask: 0x01) */
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#define MCUCTRL_SRAMPWRDIS_BANK5_Pos (5UL) /*!< BANK5 (Bit 5) */
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#define MCUCTRL_SRAMPWRDIS_BANK5_Msk (0x20UL) /*!< BANK5 (Bitfield-Mask: 0x01) */
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#define MCUCTRL_SRAMPWRDIS_BANK4_Pos (4UL) /*!< BANK4 (Bit 4) */
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#define MCUCTRL_SRAMPWRDIS_BANK4_Msk (0x10UL) /*!< BANK4 (Bitfield-Mask: 0x01) */
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#define MCUCTRL_SRAMPWRDIS_BANK3_Pos (3UL) /*!< BANK3 (Bit 3) */
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#define MCUCTRL_SRAMPWRDIS_BANK3_Msk (0x8UL) /*!< BANK3 (Bitfield-Mask: 0x01) */
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#define MCUCTRL_SRAMPWRDIS_BANK2_Pos (2UL) /*!< BANK2 (Bit 2) */
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#define MCUCTRL_SRAMPWRDIS_BANK2_Msk (0x4UL) /*!< BANK2 (Bitfield-Mask: 0x01) */
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#define MCUCTRL_SRAMPWRDIS_BANK1_Pos (1UL) /*!< BANK1 (Bit 1) */
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#define MCUCTRL_SRAMPWRDIS_BANK1_Msk (0x2UL) /*!< BANK1 (Bitfield-Mask: 0x01) */
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#define MCUCTRL_SRAMPWRDIS_BANK0_Pos (0UL) /*!< BANK0 (Bit 0) */
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#define MCUCTRL_SRAMPWRDIS_BANK0_Msk (0x1UL) /*!< BANK0 (Bitfield-Mask: 0x01) */
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/* ====================================================== FLASHPWRDIS ====================================================== */
|
|
#define MCUCTRL_FLASHPWRDIS_BANK1_Pos (1UL) /*!< BANK1 (Bit 1) */
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#define MCUCTRL_FLASHPWRDIS_BANK1_Msk (0x2UL) /*!< BANK1 (Bitfield-Mask: 0x01) */
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#define MCUCTRL_FLASHPWRDIS_BANK0_Pos (0UL) /*!< BANK0 (Bit 0) */
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|
#define MCUCTRL_FLASHPWRDIS_BANK0_Msk (0x1UL) /*!< BANK0 (Bitfield-Mask: 0x01) */
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|
/* ==================================================== ICODEFAULTADDR ===================================================== */
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|
#define MCUCTRL_ICODEFAULTADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
|
|
#define MCUCTRL_ICODEFAULTADDR_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
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|
/* ==================================================== DCODEFAULTADDR ===================================================== */
|
|
#define MCUCTRL_DCODEFAULTADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
|
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#define MCUCTRL_DCODEFAULTADDR_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
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/* ===================================================== SYSFAULTADDR ====================================================== */
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#define MCUCTRL_SYSFAULTADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
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#define MCUCTRL_SYSFAULTADDR_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
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/* ====================================================== FAULTSTATUS ====================================================== */
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#define MCUCTRL_FAULTSTATUS_SYS_Pos (2UL) /*!< SYS (Bit 2) */
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#define MCUCTRL_FAULTSTATUS_SYS_Msk (0x4UL) /*!< SYS (Bitfield-Mask: 0x01) */
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#define MCUCTRL_FAULTSTATUS_DCODE_Pos (1UL) /*!< DCODE (Bit 1) */
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#define MCUCTRL_FAULTSTATUS_DCODE_Msk (0x2UL) /*!< DCODE (Bitfield-Mask: 0x01) */
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#define MCUCTRL_FAULTSTATUS_ICODE_Pos (0UL) /*!< ICODE (Bit 0) */
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#define MCUCTRL_FAULTSTATUS_ICODE_Msk (0x1UL) /*!< ICODE (Bitfield-Mask: 0x01) */
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/* ==================================================== FAULTCAPTUREEN ===================================================== */
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#define MCUCTRL_FAULTCAPTUREEN_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */
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#define MCUCTRL_FAULTCAPTUREEN_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
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/* ======================================================= TPIUCTRL ======================================================== */
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#define MCUCTRL_TPIUCTRL_CLKSEL_Pos (8UL) /*!< CLKSEL (Bit 8) */
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#define MCUCTRL_TPIUCTRL_CLKSEL_Msk (0x300UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */
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#define MCUCTRL_TPIUCTRL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */
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#define MCUCTRL_TPIUCTRL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
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/* =========================================================================================================================== */
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/* ================ RSTGEN ================ */
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/* =========================================================================================================================== */
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/* ========================================================== CFG ========================================================== */
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#define RSTGEN_CFG_WDREN_Pos (1UL) /*!< WDREN (Bit 1) */
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#define RSTGEN_CFG_WDREN_Msk (0x2UL) /*!< WDREN (Bitfield-Mask: 0x01) */
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#define RSTGEN_CFG_BODHREN_Pos (0UL) /*!< BODHREN (Bit 0) */
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#define RSTGEN_CFG_BODHREN_Msk (0x1UL) /*!< BODHREN (Bitfield-Mask: 0x01) */
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/* ========================================================= SWPOI ========================================================= */
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#define RSTGEN_SWPOI_SWPOIKEY_Pos (0UL) /*!< SWPOIKEY (Bit 0) */
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#define RSTGEN_SWPOI_SWPOIKEY_Msk (0xffUL) /*!< SWPOIKEY (Bitfield-Mask: 0xff) */
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/* ========================================================= SWPOR ========================================================= */
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#define RSTGEN_SWPOR_SWPORKEY_Pos (0UL) /*!< SWPORKEY (Bit 0) */
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#define RSTGEN_SWPOR_SWPORKEY_Msk (0xffUL) /*!< SWPORKEY (Bitfield-Mask: 0xff) */
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/* ========================================================= STAT ========================================================== */
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#define RSTGEN_STAT_WDRSTAT_Pos (6UL) /*!< WDRSTAT (Bit 6) */
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#define RSTGEN_STAT_WDRSTAT_Msk (0x40UL) /*!< WDRSTAT (Bitfield-Mask: 0x01) */
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#define RSTGEN_STAT_DBGRSTAT_Pos (5UL) /*!< DBGRSTAT (Bit 5) */
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#define RSTGEN_STAT_DBGRSTAT_Msk (0x20UL) /*!< DBGRSTAT (Bitfield-Mask: 0x01) */
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#define RSTGEN_STAT_POIRSTAT_Pos (4UL) /*!< POIRSTAT (Bit 4) */
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#define RSTGEN_STAT_POIRSTAT_Msk (0x10UL) /*!< POIRSTAT (Bitfield-Mask: 0x01) */
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#define RSTGEN_STAT_SWRSTAT_Pos (3UL) /*!< SWRSTAT (Bit 3) */
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#define RSTGEN_STAT_SWRSTAT_Msk (0x8UL) /*!< SWRSTAT (Bitfield-Mask: 0x01) */
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#define RSTGEN_STAT_BORSTAT_Pos (2UL) /*!< BORSTAT (Bit 2) */
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#define RSTGEN_STAT_BORSTAT_Msk (0x4UL) /*!< BORSTAT (Bitfield-Mask: 0x01) */
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#define RSTGEN_STAT_PORSTAT_Pos (1UL) /*!< PORSTAT (Bit 1) */
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#define RSTGEN_STAT_PORSTAT_Msk (0x2UL) /*!< PORSTAT (Bitfield-Mask: 0x01) */
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#define RSTGEN_STAT_EXRSTAT_Pos (0UL) /*!< EXRSTAT (Bit 0) */
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#define RSTGEN_STAT_EXRSTAT_Msk (0x1UL) /*!< EXRSTAT (Bitfield-Mask: 0x01) */
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/* ======================================================== CLRSTAT ======================================================== */
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#define RSTGEN_CLRSTAT_CLRSTAT_Pos (0UL) /*!< CLRSTAT (Bit 0) */
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#define RSTGEN_CLRSTAT_CLRSTAT_Msk (0x1UL) /*!< CLRSTAT (Bitfield-Mask: 0x01) */
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/* ========================================================= INTEN ========================================================= */
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#define RSTGEN_INTEN_BODH_Pos (0UL) /*!< BODH (Bit 0) */
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#define RSTGEN_INTEN_BODH_Msk (0x1UL) /*!< BODH (Bitfield-Mask: 0x01) */
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/* ======================================================== INTSTAT ======================================================== */
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#define RSTGEN_INTSTAT_BODH_Pos (0UL) /*!< BODH (Bit 0) */
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#define RSTGEN_INTSTAT_BODH_Msk (0x1UL) /*!< BODH (Bitfield-Mask: 0x01) */
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/* ======================================================== INTCLR ========================================================= */
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#define RSTGEN_INTCLR_BODH_Pos (0UL) /*!< BODH (Bit 0) */
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#define RSTGEN_INTCLR_BODH_Msk (0x1UL) /*!< BODH (Bitfield-Mask: 0x01) */
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/* ======================================================== INTSET ========================================================= */
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#define RSTGEN_INTSET_BODH_Pos (0UL) /*!< BODH (Bit 0) */
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#define RSTGEN_INTSET_BODH_Msk (0x1UL) /*!< BODH (Bitfield-Mask: 0x01) */
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/* =========================================================================================================================== */
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/* ================ RTC ================ */
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/* =========================================================================================================================== */
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/* ======================================================== CTRLOW ========================================================= */
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#define RTC_CTRLOW_CTRHR_Pos (24UL) /*!< CTRHR (Bit 24) */
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#define RTC_CTRLOW_CTRHR_Msk (0x3f000000UL) /*!< CTRHR (Bitfield-Mask: 0x3f) */
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#define RTC_CTRLOW_CTRMIN_Pos (16UL) /*!< CTRMIN (Bit 16) */
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#define RTC_CTRLOW_CTRMIN_Msk (0x7f0000UL) /*!< CTRMIN (Bitfield-Mask: 0x7f) */
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#define RTC_CTRLOW_CTRSEC_Pos (8UL) /*!< CTRSEC (Bit 8) */
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#define RTC_CTRLOW_CTRSEC_Msk (0x7f00UL) /*!< CTRSEC (Bitfield-Mask: 0x7f) */
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#define RTC_CTRLOW_CTR100_Pos (0UL) /*!< CTR100 (Bit 0) */
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#define RTC_CTRLOW_CTR100_Msk (0xffUL) /*!< CTR100 (Bitfield-Mask: 0xff) */
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/* ========================================================= CTRUP ========================================================= */
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#define RTC_CTRUP_CTERR_Pos (31UL) /*!< CTERR (Bit 31) */
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#define RTC_CTRUP_CTERR_Msk (0x80000000UL) /*!< CTERR (Bitfield-Mask: 0x01) */
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#define RTC_CTRUP_CEB_Pos (28UL) /*!< CEB (Bit 28) */
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#define RTC_CTRUP_CEB_Msk (0x10000000UL) /*!< CEB (Bitfield-Mask: 0x01) */
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#define RTC_CTRUP_CB_Pos (27UL) /*!< CB (Bit 27) */
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#define RTC_CTRUP_CB_Msk (0x8000000UL) /*!< CB (Bitfield-Mask: 0x01) */
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#define RTC_CTRUP_CTRWKDY_Pos (24UL) /*!< CTRWKDY (Bit 24) */
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#define RTC_CTRUP_CTRWKDY_Msk (0x7000000UL) /*!< CTRWKDY (Bitfield-Mask: 0x07) */
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#define RTC_CTRUP_CTRYR_Pos (16UL) /*!< CTRYR (Bit 16) */
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#define RTC_CTRUP_CTRYR_Msk (0xff0000UL) /*!< CTRYR (Bitfield-Mask: 0xff) */
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#define RTC_CTRUP_CTRMO_Pos (8UL) /*!< CTRMO (Bit 8) */
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#define RTC_CTRUP_CTRMO_Msk (0x1f00UL) /*!< CTRMO (Bitfield-Mask: 0x1f) */
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#define RTC_CTRUP_CTRDATE_Pos (0UL) /*!< CTRDATE (Bit 0) */
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#define RTC_CTRUP_CTRDATE_Msk (0x3fUL) /*!< CTRDATE (Bitfield-Mask: 0x3f) */
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/* ======================================================== ALMLOW ========================================================= */
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#define RTC_ALMLOW_ALMHR_Pos (24UL) /*!< ALMHR (Bit 24) */
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#define RTC_ALMLOW_ALMHR_Msk (0x3f000000UL) /*!< ALMHR (Bitfield-Mask: 0x3f) */
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#define RTC_ALMLOW_ALMMIN_Pos (16UL) /*!< ALMMIN (Bit 16) */
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#define RTC_ALMLOW_ALMMIN_Msk (0x7f0000UL) /*!< ALMMIN (Bitfield-Mask: 0x7f) */
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#define RTC_ALMLOW_ALMSEC_Pos (8UL) /*!< ALMSEC (Bit 8) */
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#define RTC_ALMLOW_ALMSEC_Msk (0x7f00UL) /*!< ALMSEC (Bitfield-Mask: 0x7f) */
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#define RTC_ALMLOW_ALM100_Pos (0UL) /*!< ALM100 (Bit 0) */
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#define RTC_ALMLOW_ALM100_Msk (0xffUL) /*!< ALM100 (Bitfield-Mask: 0xff) */
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/* ========================================================= ALMUP ========================================================= */
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#define RTC_ALMUP_ALMWKDY_Pos (16UL) /*!< ALMWKDY (Bit 16) */
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#define RTC_ALMUP_ALMWKDY_Msk (0x70000UL) /*!< ALMWKDY (Bitfield-Mask: 0x07) */
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#define RTC_ALMUP_ALMMO_Pos (8UL) /*!< ALMMO (Bit 8) */
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#define RTC_ALMUP_ALMMO_Msk (0x1f00UL) /*!< ALMMO (Bitfield-Mask: 0x1f) */
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#define RTC_ALMUP_ALMDATE_Pos (0UL) /*!< ALMDATE (Bit 0) */
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#define RTC_ALMUP_ALMDATE_Msk (0x3fUL) /*!< ALMDATE (Bitfield-Mask: 0x3f) */
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/* ======================================================== RTCCTL ========================================================= */
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#define RTC_RTCCTL_HR1224_Pos (5UL) /*!< HR1224 (Bit 5) */
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#define RTC_RTCCTL_HR1224_Msk (0x20UL) /*!< HR1224 (Bitfield-Mask: 0x01) */
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#define RTC_RTCCTL_RSTOP_Pos (4UL) /*!< RSTOP (Bit 4) */
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#define RTC_RTCCTL_RSTOP_Msk (0x10UL) /*!< RSTOP (Bitfield-Mask: 0x01) */
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#define RTC_RTCCTL_RPT_Pos (1UL) /*!< RPT (Bit 1) */
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#define RTC_RTCCTL_RPT_Msk (0xeUL) /*!< RPT (Bitfield-Mask: 0x07) */
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#define RTC_RTCCTL_WRTC_Pos (0UL) /*!< WRTC (Bit 0) */
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#define RTC_RTCCTL_WRTC_Msk (0x1UL) /*!< WRTC (Bitfield-Mask: 0x01) */
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/* ========================================================= INTEN ========================================================= */
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#define RTC_INTEN_ALM_Pos (3UL) /*!< ALM (Bit 3) */
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#define RTC_INTEN_ALM_Msk (0x8UL) /*!< ALM (Bitfield-Mask: 0x01) */
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#define RTC_INTEN_OF_Pos (2UL) /*!< OF (Bit 2) */
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#define RTC_INTEN_OF_Msk (0x4UL) /*!< OF (Bitfield-Mask: 0x01) */
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#define RTC_INTEN_ACC_Pos (1UL) /*!< ACC (Bit 1) */
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#define RTC_INTEN_ACC_Msk (0x2UL) /*!< ACC (Bitfield-Mask: 0x01) */
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#define RTC_INTEN_ACF_Pos (0UL) /*!< ACF (Bit 0) */
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#define RTC_INTEN_ACF_Msk (0x1UL) /*!< ACF (Bitfield-Mask: 0x01) */
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/* ======================================================== INTSTAT ======================================================== */
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#define RTC_INTSTAT_ALM_Pos (3UL) /*!< ALM (Bit 3) */
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#define RTC_INTSTAT_ALM_Msk (0x8UL) /*!< ALM (Bitfield-Mask: 0x01) */
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#define RTC_INTSTAT_OF_Pos (2UL) /*!< OF (Bit 2) */
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#define RTC_INTSTAT_OF_Msk (0x4UL) /*!< OF (Bitfield-Mask: 0x01) */
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#define RTC_INTSTAT_ACC_Pos (1UL) /*!< ACC (Bit 1) */
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#define RTC_INTSTAT_ACC_Msk (0x2UL) /*!< ACC (Bitfield-Mask: 0x01) */
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#define RTC_INTSTAT_ACF_Pos (0UL) /*!< ACF (Bit 0) */
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#define RTC_INTSTAT_ACF_Msk (0x1UL) /*!< ACF (Bitfield-Mask: 0x01) */
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/* ======================================================== INTCLR ========================================================= */
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#define RTC_INTCLR_ALM_Pos (3UL) /*!< ALM (Bit 3) */
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#define RTC_INTCLR_ALM_Msk (0x8UL) /*!< ALM (Bitfield-Mask: 0x01) */
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#define RTC_INTCLR_OF_Pos (2UL) /*!< OF (Bit 2) */
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#define RTC_INTCLR_OF_Msk (0x4UL) /*!< OF (Bitfield-Mask: 0x01) */
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#define RTC_INTCLR_ACC_Pos (1UL) /*!< ACC (Bit 1) */
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#define RTC_INTCLR_ACC_Msk (0x2UL) /*!< ACC (Bitfield-Mask: 0x01) */
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#define RTC_INTCLR_ACF_Pos (0UL) /*!< ACF (Bit 0) */
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#define RTC_INTCLR_ACF_Msk (0x1UL) /*!< ACF (Bitfield-Mask: 0x01) */
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/* ======================================================== INTSET ========================================================= */
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#define RTC_INTSET_ALM_Pos (3UL) /*!< ALM (Bit 3) */
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#define RTC_INTSET_ALM_Msk (0x8UL) /*!< ALM (Bitfield-Mask: 0x01) */
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#define RTC_INTSET_OF_Pos (2UL) /*!< OF (Bit 2) */
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#define RTC_INTSET_OF_Msk (0x4UL) /*!< OF (Bitfield-Mask: 0x01) */
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#define RTC_INTSET_ACC_Pos (1UL) /*!< ACC (Bit 1) */
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#define RTC_INTSET_ACC_Msk (0x2UL) /*!< ACC (Bitfield-Mask: 0x01) */
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#define RTC_INTSET_ACF_Pos (0UL) /*!< ACF (Bit 0) */
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#define RTC_INTSET_ACF_Msk (0x1UL) /*!< ACF (Bitfield-Mask: 0x01) */
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/* =========================================================================================================================== */
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/* ================ UART ================ */
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/* =========================================================================================================================== */
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/* ========================================================== DR =========================================================== */
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#define UART_DR_OEDATA_Pos (11UL) /*!< OEDATA (Bit 11) */
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#define UART_DR_OEDATA_Msk (0x800UL) /*!< OEDATA (Bitfield-Mask: 0x01) */
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#define UART_DR_BEDATA_Pos (10UL) /*!< BEDATA (Bit 10) */
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#define UART_DR_BEDATA_Msk (0x400UL) /*!< BEDATA (Bitfield-Mask: 0x01) */
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#define UART_DR_PEDATA_Pos (9UL) /*!< PEDATA (Bit 9) */
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#define UART_DR_PEDATA_Msk (0x200UL) /*!< PEDATA (Bitfield-Mask: 0x01) */
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#define UART_DR_FEDATA_Pos (8UL) /*!< FEDATA (Bit 8) */
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#define UART_DR_FEDATA_Msk (0x100UL) /*!< FEDATA (Bitfield-Mask: 0x01) */
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#define UART_DR_DATA_Pos (0UL) /*!< DATA (Bit 0) */
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#define UART_DR_DATA_Msk (0xffUL) /*!< DATA (Bitfield-Mask: 0xff) */
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/* ========================================================== RSR ========================================================== */
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#define UART_RSR_OESTAT_Pos (3UL) /*!< OESTAT (Bit 3) */
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#define UART_RSR_OESTAT_Msk (0x8UL) /*!< OESTAT (Bitfield-Mask: 0x01) */
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#define UART_RSR_BESTAT_Pos (2UL) /*!< BESTAT (Bit 2) */
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#define UART_RSR_BESTAT_Msk (0x4UL) /*!< BESTAT (Bitfield-Mask: 0x01) */
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#define UART_RSR_PESTAT_Pos (1UL) /*!< PESTAT (Bit 1) */
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#define UART_RSR_PESTAT_Msk (0x2UL) /*!< PESTAT (Bitfield-Mask: 0x01) */
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#define UART_RSR_FESTAT_Pos (0UL) /*!< FESTAT (Bit 0) */
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#define UART_RSR_FESTAT_Msk (0x1UL) /*!< FESTAT (Bitfield-Mask: 0x01) */
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/* ========================================================== FR =========================================================== */
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#define UART_FR_RI_Pos (8UL) /*!< RI (Bit 8) */
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#define UART_FR_RI_Msk (0x100UL) /*!< RI (Bitfield-Mask: 0x01) */
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#define UART_FR_TXFE_Pos (7UL) /*!< TXFE (Bit 7) */
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#define UART_FR_TXFE_Msk (0x80UL) /*!< TXFE (Bitfield-Mask: 0x01) */
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#define UART_FR_RXFF_Pos (6UL) /*!< RXFF (Bit 6) */
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#define UART_FR_RXFF_Msk (0x40UL) /*!< RXFF (Bitfield-Mask: 0x01) */
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#define UART_FR_TXFF_Pos (5UL) /*!< TXFF (Bit 5) */
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#define UART_FR_TXFF_Msk (0x20UL) /*!< TXFF (Bitfield-Mask: 0x01) */
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#define UART_FR_RXFE_Pos (4UL) /*!< RXFE (Bit 4) */
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#define UART_FR_RXFE_Msk (0x10UL) /*!< RXFE (Bitfield-Mask: 0x01) */
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#define UART_FR_BUSY_Pos (3UL) /*!< BUSY (Bit 3) */
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#define UART_FR_BUSY_Msk (0x8UL) /*!< BUSY (Bitfield-Mask: 0x01) */
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#define UART_FR_DCD_Pos (2UL) /*!< DCD (Bit 2) */
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#define UART_FR_DCD_Msk (0x4UL) /*!< DCD (Bitfield-Mask: 0x01) */
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#define UART_FR_DSR_Pos (1UL) /*!< DSR (Bit 1) */
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#define UART_FR_DSR_Msk (0x2UL) /*!< DSR (Bitfield-Mask: 0x01) */
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#define UART_FR_CTS_Pos (0UL) /*!< CTS (Bit 0) */
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#define UART_FR_CTS_Msk (0x1UL) /*!< CTS (Bitfield-Mask: 0x01) */
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/* ========================================================= ILPR ========================================================== */
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#define UART_ILPR_ILPDVSR_Pos (0UL) /*!< ILPDVSR (Bit 0) */
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#define UART_ILPR_ILPDVSR_Msk (0xffUL) /*!< ILPDVSR (Bitfield-Mask: 0xff) */
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/* ========================================================= IBRD ========================================================== */
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#define UART_IBRD_DIVINT_Pos (0UL) /*!< DIVINT (Bit 0) */
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#define UART_IBRD_DIVINT_Msk (0xffffUL) /*!< DIVINT (Bitfield-Mask: 0xffff) */
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/* ========================================================= FBRD ========================================================== */
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#define UART_FBRD_DIVFRAC_Pos (0UL) /*!< DIVFRAC (Bit 0) */
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#define UART_FBRD_DIVFRAC_Msk (0x3fUL) /*!< DIVFRAC (Bitfield-Mask: 0x3f) */
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/* ========================================================= LCRH ========================================================== */
|
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#define UART_LCRH_SPS_Pos (7UL) /*!< SPS (Bit 7) */
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#define UART_LCRH_SPS_Msk (0x80UL) /*!< SPS (Bitfield-Mask: 0x01) */
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#define UART_LCRH_WLEN_Pos (5UL) /*!< WLEN (Bit 5) */
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#define UART_LCRH_WLEN_Msk (0x60UL) /*!< WLEN (Bitfield-Mask: 0x03) */
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#define UART_LCRH_FEN_Pos (4UL) /*!< FEN (Bit 4) */
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#define UART_LCRH_FEN_Msk (0x10UL) /*!< FEN (Bitfield-Mask: 0x01) */
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#define UART_LCRH_STP2_Pos (3UL) /*!< STP2 (Bit 3) */
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#define UART_LCRH_STP2_Msk (0x8UL) /*!< STP2 (Bitfield-Mask: 0x01) */
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#define UART_LCRH_EPS_Pos (2UL) /*!< EPS (Bit 2) */
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|
#define UART_LCRH_EPS_Msk (0x4UL) /*!< EPS (Bitfield-Mask: 0x01) */
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#define UART_LCRH_PEN_Pos (1UL) /*!< PEN (Bit 1) */
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|
#define UART_LCRH_PEN_Msk (0x2UL) /*!< PEN (Bitfield-Mask: 0x01) */
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|
#define UART_LCRH_BRK_Pos (0UL) /*!< BRK (Bit 0) */
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|
#define UART_LCRH_BRK_Msk (0x1UL) /*!< BRK (Bitfield-Mask: 0x01) */
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|
/* ========================================================== CR =========================================================== */
|
|
#define UART_CR_CTSEN_Pos (15UL) /*!< CTSEN (Bit 15) */
|
|
#define UART_CR_CTSEN_Msk (0x8000UL) /*!< CTSEN (Bitfield-Mask: 0x01) */
|
|
#define UART_CR_RTSEN_Pos (14UL) /*!< RTSEN (Bit 14) */
|
|
#define UART_CR_RTSEN_Msk (0x4000UL) /*!< RTSEN (Bitfield-Mask: 0x01) */
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|
#define UART_CR_OUT2_Pos (13UL) /*!< OUT2 (Bit 13) */
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|
#define UART_CR_OUT2_Msk (0x2000UL) /*!< OUT2 (Bitfield-Mask: 0x01) */
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|
#define UART_CR_OUT1_Pos (12UL) /*!< OUT1 (Bit 12) */
|
|
#define UART_CR_OUT1_Msk (0x1000UL) /*!< OUT1 (Bitfield-Mask: 0x01) */
|
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#define UART_CR_RTS_Pos (11UL) /*!< RTS (Bit 11) */
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|
#define UART_CR_RTS_Msk (0x800UL) /*!< RTS (Bitfield-Mask: 0x01) */
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|
#define UART_CR_DTR_Pos (10UL) /*!< DTR (Bit 10) */
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|
#define UART_CR_DTR_Msk (0x400UL) /*!< DTR (Bitfield-Mask: 0x01) */
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|
#define UART_CR_RXE_Pos (9UL) /*!< RXE (Bit 9) */
|
|
#define UART_CR_RXE_Msk (0x200UL) /*!< RXE (Bitfield-Mask: 0x01) */
|
|
#define UART_CR_TXE_Pos (8UL) /*!< TXE (Bit 8) */
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|
#define UART_CR_TXE_Msk (0x100UL) /*!< TXE (Bitfield-Mask: 0x01) */
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|
#define UART_CR_LBE_Pos (7UL) /*!< LBE (Bit 7) */
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|
#define UART_CR_LBE_Msk (0x80UL) /*!< LBE (Bitfield-Mask: 0x01) */
|
|
#define UART_CR_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */
|
|
#define UART_CR_CLKSEL_Msk (0x70UL) /*!< CLKSEL (Bitfield-Mask: 0x07) */
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#define UART_CR_CLKEN_Pos (3UL) /*!< CLKEN (Bit 3) */
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|
#define UART_CR_CLKEN_Msk (0x8UL) /*!< CLKEN (Bitfield-Mask: 0x01) */
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|
#define UART_CR_SIRLP_Pos (2UL) /*!< SIRLP (Bit 2) */
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#define UART_CR_SIRLP_Msk (0x4UL) /*!< SIRLP (Bitfield-Mask: 0x01) */
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|
#define UART_CR_SIREN_Pos (1UL) /*!< SIREN (Bit 1) */
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|
#define UART_CR_SIREN_Msk (0x2UL) /*!< SIREN (Bitfield-Mask: 0x01) */
|
|
#define UART_CR_UARTEN_Pos (0UL) /*!< UARTEN (Bit 0) */
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|
#define UART_CR_UARTEN_Msk (0x1UL) /*!< UARTEN (Bitfield-Mask: 0x01) */
|
|
/* ========================================================= IFLS ========================================================== */
|
|
#define UART_IFLS_RXIFLSEL_Pos (3UL) /*!< RXIFLSEL (Bit 3) */
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|
#define UART_IFLS_RXIFLSEL_Msk (0x38UL) /*!< RXIFLSEL (Bitfield-Mask: 0x07) */
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|
#define UART_IFLS_TXIFLSEL_Pos (0UL) /*!< TXIFLSEL (Bit 0) */
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#define UART_IFLS_TXIFLSEL_Msk (0x7UL) /*!< TXIFLSEL (Bitfield-Mask: 0x07) */
|
|
/* ========================================================== IER ========================================================== */
|
|
#define UART_IER_OEIM_Pos (10UL) /*!< OEIM (Bit 10) */
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|
#define UART_IER_OEIM_Msk (0x400UL) /*!< OEIM (Bitfield-Mask: 0x01) */
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|
#define UART_IER_BEIM_Pos (9UL) /*!< BEIM (Bit 9) */
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|
#define UART_IER_BEIM_Msk (0x200UL) /*!< BEIM (Bitfield-Mask: 0x01) */
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|
#define UART_IER_PEIM_Pos (8UL) /*!< PEIM (Bit 8) */
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#define UART_IER_PEIM_Msk (0x100UL) /*!< PEIM (Bitfield-Mask: 0x01) */
|
|
#define UART_IER_FEIM_Pos (7UL) /*!< FEIM (Bit 7) */
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|
#define UART_IER_FEIM_Msk (0x80UL) /*!< FEIM (Bitfield-Mask: 0x01) */
|
|
#define UART_IER_RTIM_Pos (6UL) /*!< RTIM (Bit 6) */
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#define UART_IER_RTIM_Msk (0x40UL) /*!< RTIM (Bitfield-Mask: 0x01) */
|
|
#define UART_IER_TXIM_Pos (5UL) /*!< TXIM (Bit 5) */
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#define UART_IER_TXIM_Msk (0x20UL) /*!< TXIM (Bitfield-Mask: 0x01) */
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#define UART_IER_RXIM_Pos (4UL) /*!< RXIM (Bit 4) */
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|
#define UART_IER_RXIM_Msk (0x10UL) /*!< RXIM (Bitfield-Mask: 0x01) */
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|
#define UART_IER_DSRMIM_Pos (3UL) /*!< DSRMIM (Bit 3) */
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|
#define UART_IER_DSRMIM_Msk (0x8UL) /*!< DSRMIM (Bitfield-Mask: 0x01) */
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|
#define UART_IER_DCDMIM_Pos (2UL) /*!< DCDMIM (Bit 2) */
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|
#define UART_IER_DCDMIM_Msk (0x4UL) /*!< DCDMIM (Bitfield-Mask: 0x01) */
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|
#define UART_IER_CTSMIM_Pos (1UL) /*!< CTSMIM (Bit 1) */
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#define UART_IER_CTSMIM_Msk (0x2UL) /*!< CTSMIM (Bitfield-Mask: 0x01) */
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|
#define UART_IER_RIMIM_Pos (0UL) /*!< RIMIM (Bit 0) */
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#define UART_IER_RIMIM_Msk (0x1UL) /*!< RIMIM (Bitfield-Mask: 0x01) */
|
|
/* ========================================================== IES ========================================================== */
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|
#define UART_IES_OERIS_Pos (10UL) /*!< OERIS (Bit 10) */
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|
#define UART_IES_OERIS_Msk (0x400UL) /*!< OERIS (Bitfield-Mask: 0x01) */
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|
#define UART_IES_BERIS_Pos (9UL) /*!< BERIS (Bit 9) */
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#define UART_IES_BERIS_Msk (0x200UL) /*!< BERIS (Bitfield-Mask: 0x01) */
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#define UART_IES_PERIS_Pos (8UL) /*!< PERIS (Bit 8) */
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#define UART_IES_PERIS_Msk (0x100UL) /*!< PERIS (Bitfield-Mask: 0x01) */
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#define UART_IES_FERIS_Pos (7UL) /*!< FERIS (Bit 7) */
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|
#define UART_IES_FERIS_Msk (0x80UL) /*!< FERIS (Bitfield-Mask: 0x01) */
|
|
#define UART_IES_RTRIS_Pos (6UL) /*!< RTRIS (Bit 6) */
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|
#define UART_IES_RTRIS_Msk (0x40UL) /*!< RTRIS (Bitfield-Mask: 0x01) */
|
|
#define UART_IES_TXRIS_Pos (5UL) /*!< TXRIS (Bit 5) */
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|
#define UART_IES_TXRIS_Msk (0x20UL) /*!< TXRIS (Bitfield-Mask: 0x01) */
|
|
#define UART_IES_RXRIS_Pos (4UL) /*!< RXRIS (Bit 4) */
|
|
#define UART_IES_RXRIS_Msk (0x10UL) /*!< RXRIS (Bitfield-Mask: 0x01) */
|
|
#define UART_IES_DSRMRIS_Pos (3UL) /*!< DSRMRIS (Bit 3) */
|
|
#define UART_IES_DSRMRIS_Msk (0x8UL) /*!< DSRMRIS (Bitfield-Mask: 0x01) */
|
|
#define UART_IES_DCDMRIS_Pos (2UL) /*!< DCDMRIS (Bit 2) */
|
|
#define UART_IES_DCDMRIS_Msk (0x4UL) /*!< DCDMRIS (Bitfield-Mask: 0x01) */
|
|
#define UART_IES_CTSMRIS_Pos (1UL) /*!< CTSMRIS (Bit 1) */
|
|
#define UART_IES_CTSMRIS_Msk (0x2UL) /*!< CTSMRIS (Bitfield-Mask: 0x01) */
|
|
#define UART_IES_RIMRIS_Pos (0UL) /*!< RIMRIS (Bit 0) */
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|
#define UART_IES_RIMRIS_Msk (0x1UL) /*!< RIMRIS (Bitfield-Mask: 0x01) */
|
|
/* ========================================================== MIS ========================================================== */
|
|
#define UART_MIS_OEMIS_Pos (10UL) /*!< OEMIS (Bit 10) */
|
|
#define UART_MIS_OEMIS_Msk (0x400UL) /*!< OEMIS (Bitfield-Mask: 0x01) */
|
|
#define UART_MIS_BEMIS_Pos (9UL) /*!< BEMIS (Bit 9) */
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|
#define UART_MIS_BEMIS_Msk (0x200UL) /*!< BEMIS (Bitfield-Mask: 0x01) */
|
|
#define UART_MIS_PEMIS_Pos (8UL) /*!< PEMIS (Bit 8) */
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|
#define UART_MIS_PEMIS_Msk (0x100UL) /*!< PEMIS (Bitfield-Mask: 0x01) */
|
|
#define UART_MIS_FEMIS_Pos (7UL) /*!< FEMIS (Bit 7) */
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|
#define UART_MIS_FEMIS_Msk (0x80UL) /*!< FEMIS (Bitfield-Mask: 0x01) */
|
|
#define UART_MIS_RTMIS_Pos (6UL) /*!< RTMIS (Bit 6) */
|
|
#define UART_MIS_RTMIS_Msk (0x40UL) /*!< RTMIS (Bitfield-Mask: 0x01) */
|
|
#define UART_MIS_TXMIS_Pos (5UL) /*!< TXMIS (Bit 5) */
|
|
#define UART_MIS_TXMIS_Msk (0x20UL) /*!< TXMIS (Bitfield-Mask: 0x01) */
|
|
#define UART_MIS_RXMIS_Pos (4UL) /*!< RXMIS (Bit 4) */
|
|
#define UART_MIS_RXMIS_Msk (0x10UL) /*!< RXMIS (Bitfield-Mask: 0x01) */
|
|
#define UART_MIS_DSRMMIS_Pos (3UL) /*!< DSRMMIS (Bit 3) */
|
|
#define UART_MIS_DSRMMIS_Msk (0x8UL) /*!< DSRMMIS (Bitfield-Mask: 0x01) */
|
|
#define UART_MIS_DCDMMIS_Pos (2UL) /*!< DCDMMIS (Bit 2) */
|
|
#define UART_MIS_DCDMMIS_Msk (0x4UL) /*!< DCDMMIS (Bitfield-Mask: 0x01) */
|
|
#define UART_MIS_CTSMMIS_Pos (1UL) /*!< CTSMMIS (Bit 1) */
|
|
#define UART_MIS_CTSMMIS_Msk (0x2UL) /*!< CTSMMIS (Bitfield-Mask: 0x01) */
|
|
#define UART_MIS_RIMMIS_Pos (0UL) /*!< RIMMIS (Bit 0) */
|
|
#define UART_MIS_RIMMIS_Msk (0x1UL) /*!< RIMMIS (Bitfield-Mask: 0x01) */
|
|
/* ========================================================== IEC ========================================================== */
|
|
#define UART_IEC_OEIC_Pos (10UL) /*!< OEIC (Bit 10) */
|
|
#define UART_IEC_OEIC_Msk (0x400UL) /*!< OEIC (Bitfield-Mask: 0x01) */
|
|
#define UART_IEC_BEIC_Pos (9UL) /*!< BEIC (Bit 9) */
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|
#define UART_IEC_BEIC_Msk (0x200UL) /*!< BEIC (Bitfield-Mask: 0x01) */
|
|
#define UART_IEC_PEIC_Pos (8UL) /*!< PEIC (Bit 8) */
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|
#define UART_IEC_PEIC_Msk (0x100UL) /*!< PEIC (Bitfield-Mask: 0x01) */
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|
#define UART_IEC_FEIC_Pos (7UL) /*!< FEIC (Bit 7) */
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|
#define UART_IEC_FEIC_Msk (0x80UL) /*!< FEIC (Bitfield-Mask: 0x01) */
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|
#define UART_IEC_RTIC_Pos (6UL) /*!< RTIC (Bit 6) */
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|
#define UART_IEC_RTIC_Msk (0x40UL) /*!< RTIC (Bitfield-Mask: 0x01) */
|
|
#define UART_IEC_TXIC_Pos (5UL) /*!< TXIC (Bit 5) */
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|
#define UART_IEC_TXIC_Msk (0x20UL) /*!< TXIC (Bitfield-Mask: 0x01) */
|
|
#define UART_IEC_RXIC_Pos (4UL) /*!< RXIC (Bit 4) */
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|
#define UART_IEC_RXIC_Msk (0x10UL) /*!< RXIC (Bitfield-Mask: 0x01) */
|
|
#define UART_IEC_DSRMIC_Pos (3UL) /*!< DSRMIC (Bit 3) */
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|
#define UART_IEC_DSRMIC_Msk (0x8UL) /*!< DSRMIC (Bitfield-Mask: 0x01) */
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#define UART_IEC_DCDMIC_Pos (2UL) /*!< DCDMIC (Bit 2) */
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|
#define UART_IEC_DCDMIC_Msk (0x4UL) /*!< DCDMIC (Bitfield-Mask: 0x01) */
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#define UART_IEC_CTSMIC_Pos (1UL) /*!< CTSMIC (Bit 1) */
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|
#define UART_IEC_CTSMIC_Msk (0x2UL) /*!< CTSMIC (Bitfield-Mask: 0x01) */
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|
#define UART_IEC_RIMIC_Pos (0UL) /*!< RIMIC (Bit 0) */
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|
#define UART_IEC_RIMIC_Msk (0x1UL) /*!< RIMIC (Bitfield-Mask: 0x01) */
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|
|
|
|
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/* =========================================================================================================================== */
|
|
/* ================ VCOMP ================ */
|
|
/* =========================================================================================================================== */
|
|
|
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/* ========================================================== CFG ========================================================== */
|
|
#define VCOMP_CFG_LVLSEL_Pos (16UL) /*!< LVLSEL (Bit 16) */
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#define VCOMP_CFG_LVLSEL_Msk (0xf0000UL) /*!< LVLSEL (Bitfield-Mask: 0x0f) */
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#define VCOMP_CFG_NSEL_Pos (8UL) /*!< NSEL (Bit 8) */
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#define VCOMP_CFG_NSEL_Msk (0x300UL) /*!< NSEL (Bitfield-Mask: 0x03) */
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#define VCOMP_CFG_PSEL_Pos (0UL) /*!< PSEL (Bit 0) */
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#define VCOMP_CFG_PSEL_Msk (0x3UL) /*!< PSEL (Bitfield-Mask: 0x03) */
|
|
/* ========================================================= STAT ========================================================== */
|
|
#define VCOMP_STAT_PWDSTAT_Pos (1UL) /*!< PWDSTAT (Bit 1) */
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|
#define VCOMP_STAT_PWDSTAT_Msk (0x2UL) /*!< PWDSTAT (Bitfield-Mask: 0x01) */
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#define VCOMP_STAT_CMPOUT_Pos (0UL) /*!< CMPOUT (Bit 0) */
|
|
#define VCOMP_STAT_CMPOUT_Msk (0x1UL) /*!< CMPOUT (Bitfield-Mask: 0x01) */
|
|
/* ======================================================== PWDKEY ========================================================= */
|
|
#define VCOMP_PWDKEY_PWDKEY_Pos (0UL) /*!< PWDKEY (Bit 0) */
|
|
#define VCOMP_PWDKEY_PWDKEY_Msk (0xffffffffUL) /*!< PWDKEY (Bitfield-Mask: 0xffffffff) */
|
|
/* ========================================================= INTEN ========================================================= */
|
|
#define VCOMP_INTEN_OUTHI_Pos (1UL) /*!< OUTHI (Bit 1) */
|
|
#define VCOMP_INTEN_OUTHI_Msk (0x2UL) /*!< OUTHI (Bitfield-Mask: 0x01) */
|
|
#define VCOMP_INTEN_OUTLOW_Pos (0UL) /*!< OUTLOW (Bit 0) */
|
|
#define VCOMP_INTEN_OUTLOW_Msk (0x1UL) /*!< OUTLOW (Bitfield-Mask: 0x01) */
|
|
/* ======================================================== INTSTAT ======================================================== */
|
|
#define VCOMP_INTSTAT_OUTHI_Pos (1UL) /*!< OUTHI (Bit 1) */
|
|
#define VCOMP_INTSTAT_OUTHI_Msk (0x2UL) /*!< OUTHI (Bitfield-Mask: 0x01) */
|
|
#define VCOMP_INTSTAT_OUTLOW_Pos (0UL) /*!< OUTLOW (Bit 0) */
|
|
#define VCOMP_INTSTAT_OUTLOW_Msk (0x1UL) /*!< OUTLOW (Bitfield-Mask: 0x01) */
|
|
/* ======================================================== INTCLR ========================================================= */
|
|
#define VCOMP_INTCLR_OUTHI_Pos (1UL) /*!< OUTHI (Bit 1) */
|
|
#define VCOMP_INTCLR_OUTHI_Msk (0x2UL) /*!< OUTHI (Bitfield-Mask: 0x01) */
|
|
#define VCOMP_INTCLR_OUTLOW_Pos (0UL) /*!< OUTLOW (Bit 0) */
|
|
#define VCOMP_INTCLR_OUTLOW_Msk (0x1UL) /*!< OUTLOW (Bitfield-Mask: 0x01) */
|
|
/* ======================================================== INTSET ========================================================= */
|
|
#define VCOMP_INTSET_OUTHI_Pos (1UL) /*!< OUTHI (Bit 1) */
|
|
#define VCOMP_INTSET_OUTHI_Msk (0x2UL) /*!< OUTHI (Bitfield-Mask: 0x01) */
|
|
#define VCOMP_INTSET_OUTLOW_Pos (0UL) /*!< OUTLOW (Bit 0) */
|
|
#define VCOMP_INTSET_OUTLOW_Msk (0x1UL) /*!< OUTLOW (Bitfield-Mask: 0x01) */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ WDT ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
/* ========================================================== CFG ========================================================== */
|
|
#define WDT_CFG_INTVAL_Pos (16UL) /*!< INTVAL (Bit 16) */
|
|
#define WDT_CFG_INTVAL_Msk (0xff0000UL) /*!< INTVAL (Bitfield-Mask: 0xff) */
|
|
#define WDT_CFG_RESVAL_Pos (8UL) /*!< RESVAL (Bit 8) */
|
|
#define WDT_CFG_RESVAL_Msk (0xff00UL) /*!< RESVAL (Bitfield-Mask: 0xff) */
|
|
#define WDT_CFG_RESEN_Pos (2UL) /*!< RESEN (Bit 2) */
|
|
#define WDT_CFG_RESEN_Msk (0x4UL) /*!< RESEN (Bitfield-Mask: 0x01) */
|
|
#define WDT_CFG_INTEN_Pos (1UL) /*!< INTEN (Bit 1) */
|
|
#define WDT_CFG_INTEN_Msk (0x2UL) /*!< INTEN (Bitfield-Mask: 0x01) */
|
|
#define WDT_CFG_WDTEN_Pos (0UL) /*!< WDTEN (Bit 0) */
|
|
#define WDT_CFG_WDTEN_Msk (0x1UL) /*!< WDTEN (Bitfield-Mask: 0x01) */
|
|
/* ========================================================= RSTRT ========================================================= */
|
|
#define WDT_RSTRT_RSTRT_Pos (0UL) /*!< RSTRT (Bit 0) */
|
|
#define WDT_RSTRT_RSTRT_Msk (0xffUL) /*!< RSTRT (Bitfield-Mask: 0xff) */
|
|
/* ========================================================= LOCK ========================================================== */
|
|
#define WDT_LOCK_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */
|
|
#define WDT_LOCK_LOCK_Msk (0xffUL) /*!< LOCK (Bitfield-Mask: 0xff) */
|
|
/* ========================================================= INTEN ========================================================= */
|
|
#define WDT_INTEN_WDTINT_Pos (0UL) /*!< WDTINT (Bit 0) */
|
|
#define WDT_INTEN_WDTINT_Msk (0x1UL) /*!< WDTINT (Bitfield-Mask: 0x01) */
|
|
/* ======================================================== INTSTAT ======================================================== */
|
|
#define WDT_INTSTAT_WDTINT_Pos (0UL) /*!< WDTINT (Bit 0) */
|
|
#define WDT_INTSTAT_WDTINT_Msk (0x1UL) /*!< WDTINT (Bitfield-Mask: 0x01) */
|
|
/* ======================================================== INTCLR ========================================================= */
|
|
#define WDT_INTCLR_WDTINT_Pos (0UL) /*!< WDTINT (Bit 0) */
|
|
#define WDT_INTCLR_WDTINT_Msk (0x1UL) /*!< WDTINT (Bitfield-Mask: 0x01) */
|
|
/* ======================================================== INTSET ========================================================= */
|
|
#define WDT_INTSET_WDTINT_Pos (0UL) /*!< WDTINT (Bit 0) */
|
|
#define WDT_INTSET_WDTINT_Msk (0x1UL) /*!< WDTINT (Bitfield-Mask: 0x01) */
|
|
|
|
/** @} */ /* End of group PosMask_peripherals */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ Enumerated Values Peripheral Section ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/** @addtogroup EnumValue_peripherals
|
|
* @{
|
|
*/
|
|
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ ADC ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
/* ========================================================== CFG ========================================================== */
|
|
/* ================================================ ADC CFG CLKSEL [24..26] ================================================ */
|
|
typedef enum { /*!< ADC_CFG_CLKSEL */
|
|
ADC_CFG_CLKSEL_OFF = 0, /*!< OFF : Low Power Mode. */
|
|
ADC_CFG_CLKSEL_12MHZ = 1, /*!< 12MHZ : 12 MHz ADC clock. */
|
|
ADC_CFG_CLKSEL_6MHZ = 2, /*!< 6MHZ : 6 MHz ADC clock. */
|
|
ADC_CFG_CLKSEL_3MHZ = 3, /*!< 3MHZ : 12 MHz ADC clock. */
|
|
ADC_CFG_CLKSEL_1_5MHZ = 4, /*!< 1_5MHZ : 1.5 MHz ADC clock. */
|
|
} ADC_CFG_CLKSEL_Enum;
|
|
|
|
/* =============================================== ADC CFG TRIGPOL [20..20] ================================================ */
|
|
typedef enum { /*!< ADC_CFG_TRIGPOL */
|
|
ADC_CFG_TRIGPOL_RISING_EDGE = 0, /*!< RISING_EDGE : Trigger on rising edge. */
|
|
ADC_CFG_TRIGPOL_FALLING_EDGE = 1, /*!< FALLING_EDGE : Trigger on falling edge. */
|
|
} ADC_CFG_TRIGPOL_Enum;
|
|
|
|
/* =============================================== ADC CFG TRIGSEL [16..19] ================================================ */
|
|
typedef enum { /*!< ADC_CFG_TRIGSEL */
|
|
ADC_CFG_TRIGSEL_EXT0 = 0, /*!< EXT0 : Off chip External Trigger0 (ADC_ET0) */
|
|
ADC_CFG_TRIGSEL_EXT1 = 1, /*!< EXT1 : Off chip External Trigger1 (ADC_ET1) */
|
|
ADC_CFG_TRIGSEL_EXT2 = 2, /*!< EXT2 : Off chip External Trigger2 (ADC_ET2) */
|
|
ADC_CFG_TRIGSEL_EXT3 = 3, /*!< EXT3 : Off chip External Trigger3 (ADC_ET3) */
|
|
ADC_CFG_TRIGSEL_EXT4 = 4, /*!< EXT4 : Off chip External Trigger4 (ADC_ET4) */
|
|
ADC_CFG_TRIGSEL_EXT5 = 5, /*!< EXT5 : Off chip External Trigger5 (ADC_ET5) */
|
|
ADC_CFG_TRIGSEL_EXT6 = 6, /*!< EXT6 : Off chip External Trigger6 (ADC_ET6) */
|
|
ADC_CFG_TRIGSEL_EXT7 = 7, /*!< EXT7 : Off chip External Trigger7 (ADC_ET7) */
|
|
ADC_CFG_TRIGSEL_SWT = 8, /*!< SWT : Software Trigger */
|
|
} ADC_CFG_TRIGSEL_Enum;
|
|
|
|
/* ================================================= ADC CFG REFSEL [8..9] ================================================= */
|
|
typedef enum { /*!< ADC_CFG_REFSEL */
|
|
ADC_CFG_REFSEL_INTERNAL = 0, /*!< INTERNAL : Internal Bandgap Reference Voltage */
|
|
ADC_CFG_REFSEL_VDD = 1, /*!< VDD : Select VDD as the ADEC reference voltage. */
|
|
ADC_CFG_REFSEL_ADCREF = 2, /*!< ADCREF : Off Chip Reference (ADC_REF) */
|
|
ADC_CFG_REFSEL_UNDEFINED = 3, /*!< UNDEFINED : Reserved */
|
|
} ADC_CFG_REFSEL_Enum;
|
|
|
|
/* ================================================ ADC CFG BATTLOAD [7..7] ================================================ */
|
|
typedef enum { /*!< ADC_CFG_BATTLOAD */
|
|
ADC_CFG_BATTLOAD_DIS = 0, /*!< DIS : Disable battery load. */
|
|
ADC_CFG_BATTLOAD_EN = 1, /*!< EN : Enable battery load. */
|
|
} ADC_CFG_BATTLOAD_Enum;
|
|
|
|
/* ================================================= ADC CFG OPMODE [5..6] ================================================= */
|
|
typedef enum { /*!< ADC_CFG_OPMODE */
|
|
ADC_CFG_OPMODE_SAMPLE_RATE_LE_125KSPS = 0, /*!< SAMPLE_RATE_LE_125KSPS : Sample Rate <= 125K sps */
|
|
ADC_CFG_OPMODE_SAMPLE_RATE_125K_1MSPS = 2, /*!< SAMPLE_RATE_125K_1MSPS : Sample Rate 125K to 1M sps */
|
|
} ADC_CFG_OPMODE_Enum;
|
|
|
|
/* ================================================= ADC CFG LPMODE [3..4] ================================================= */
|
|
typedef enum { /*!< ADC_CFG_LPMODE */
|
|
ADC_CFG_LPMODE_MODE0 = 0, /*!< MODE0 : Low Power Mode 0 (2'b00). Leaves the ADC fully powered
|
|
between scans with no latency between a
|
|
trigger event and sample data collection. */
|
|
ADC_CFG_LPMODE_MODE1 = 1, /*!< MODE1 : Low Power Mode 1 (2'b01). Enables a low power mode for
|
|
the ADC between scans requiring 50us initialization time
|
|
(latency) between a trigger event and the scan (assuming
|
|
the HFRC remains running and the MCU is not in deepsleep
|
|
mode in which case additional startup latency for HFRC
|
|
startup is required). */
|
|
ADC_CFG_LPMODE_MODE2 = 2, /*!< MODE2 : Low Power Mode 2 (2'b10). Disconnects power and clocks
|
|
to the ADC effectively eliminating all active power associated
|
|
with the ADC between scans. This mode requires 150us initialization
|
|
(again, assuming the HFRC remains running and the MCU is
|
|
not in deepsleep mode in which case additional startup
|
|
latency for HFRC startup is required). */
|
|
ADC_CFG_LPMODE_MODE_UNDEFINED = 3, /*!< MODE_UNDEFINED : Undefined Mode (2'b11) */
|
|
} ADC_CFG_LPMODE_Enum;
|
|
|
|
/* ================================================= ADC CFG RPTEN [2..2] ================================================== */
|
|
typedef enum { /*!< ADC_CFG_RPTEN */
|
|
ADC_CFG_RPTEN_SINGLE_SCAN = 0, /*!< SINGLE_SCAN : In Single Scan Mode, the ADC will complete a single
|
|
scan upon each trigger event. */
|
|
ADC_CFG_RPTEN_REPEATING_SCAN = 1, /*!< REPEATING_SCAN : In Repeating Scan Mode, the ADC will complete
|
|
it's first scan upon the initial trigger event and all
|
|
subsequent scans will occur at regular intervals defined
|
|
by the configuration programmed for the CTTMRA3 internal
|
|
timer until the timer is disabled or the ADC is disabled. */
|
|
} ADC_CFG_RPTEN_Enum;
|
|
|
|
/* ================================================ ADC CFG TMPSPWR [1..1] ================================================= */
|
|
typedef enum { /*!< ADC_CFG_TMPSPWR */
|
|
ADC_CFG_TMPSPWR_DIS = 0, /*!< DIS : Power down the temperature sensor. */
|
|
ADC_CFG_TMPSPWR_EN = 1, /*!< EN : Enable the temperature sensor when the ADC is in it's active
|
|
state. */
|
|
} ADC_CFG_TMPSPWR_Enum;
|
|
|
|
/* ================================================= ADC CFG ADCEN [0..0] ================================================== */
|
|
typedef enum { /*!< ADC_CFG_ADCEN */
|
|
ADC_CFG_ADCEN_DIS = 0, /*!< DIS : Disable the ADC module. */
|
|
ADC_CFG_ADCEN_EN = 1, /*!< EN : Enable the ADC module. */
|
|
} ADC_CFG_ADCEN_Enum;
|
|
|
|
/* ========================================================= STAT ========================================================== */
|
|
/* ================================================ ADC STAT PWDSTAT [0..1] ================================================ */
|
|
typedef enum { /*!< ADC_STAT_PWDSTAT */
|
|
ADC_STAT_PWDSTAT_ON = 0, /*!< ON : Powered on. */
|
|
ADC_STAT_PWDSTAT_SWITCH_ON_SAR_OFF = 1, /*!< SWITCH_ON_SAR_OFF : Power switch on, ADC Low Power Mode 1. */
|
|
ADC_STAT_PWDSTAT_POWER_SWITCH_OFF = 2, /*!< POWER_SWITCH_OFF : Power switch off, ADC disabled. */
|
|
} ADC_STAT_PWDSTAT_Enum;
|
|
|
|
/* ========================================================== SWT ========================================================== */
|
|
/* ================================================== ADC SWT SWT [0..7] =================================================== */
|
|
typedef enum { /*!< ADC_SWT_SWT */
|
|
ADC_SWT_SWT_GEN_SW_TRIGGER = 55, /*!< GEN_SW_TRIGGER : Writing this value generates a software trigger. */
|
|
} ADC_SWT_SWT_Enum;
|
|
|
|
/* ======================================================== SL0CFG ========================================================= */
|
|
/* ============================================== ADC SL0CFG ADSEL0 [24..26] =============================================== */
|
|
typedef enum { /*!< ADC_SL0CFG_ADSEL0 */
|
|
ADC_SL0CFG_ADSEL0_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
|
|
module for this slot. */
|
|
ADC_SL0CFG_ADSEL0_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
|
|
module for this slot. */
|
|
ADC_SL0CFG_ADSEL0_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
|
|
module for this slot. */
|
|
ADC_SL0CFG_ADSEL0_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
|
|
module for this slot. */
|
|
ADC_SL0CFG_ADSEL0_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
|
|
divide module for this slot. */
|
|
ADC_SL0CFG_ADSEL0_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
|
|
divide module for this slot. */
|
|
ADC_SL0CFG_ADSEL0_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
|
|
divide module for this slot. */
|
|
ADC_SL0CFG_ADSEL0_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
|
|
divide module for this slot. */
|
|
} ADC_SL0CFG_ADSEL0_Enum;
|
|
|
|
/* ============================================== ADC SL0CFG THSEL0 [16..18] =============================================== */
|
|
typedef enum { /*!< ADC_SL0CFG_THSEL0 */
|
|
ADC_SL0CFG_THSEL0_1_ADC_CLK = 0, /*!< 1_ADC_CLK : 1 ADC clock cycle. */
|
|
ADC_SL0CFG_THSEL0_2_ADC_CLKS = 1, /*!< 2_ADC_CLKS : 2 ADC clock cycles. */
|
|
ADC_SL0CFG_THSEL0_4_ADC_CLKS = 2, /*!< 4_ADC_CLKS : 4 ADC clock cycles. */
|
|
ADC_SL0CFG_THSEL0_8_ADC_CLKS = 3, /*!< 8_ADC_CLKS : 8 ADC clock cycles. */
|
|
ADC_SL0CFG_THSEL0_16_ADC_CLKS = 4, /*!< 16_ADC_CLKS : 16 ADC clock cycles. */
|
|
ADC_SL0CFG_THSEL0_32_ADC_CLKS = 5, /*!< 32_ADC_CLKS : 32 ADC clock cycles. */
|
|
ADC_SL0CFG_THSEL0_64_ADC_CLKS = 6, /*!< 64_ADC_CLKS : 64 ADC clock cycles. */
|
|
ADC_SL0CFG_THSEL0_128_ADC_CLKS = 7, /*!< 128_ADC_CLKS : 128 ADC clock cycles. */
|
|
} ADC_SL0CFG_THSEL0_Enum;
|
|
|
|
/* =============================================== ADC SL0CFG CHSEL0 [8..11] =============================================== */
|
|
typedef enum { /*!< ADC_SL0CFG_CHSEL0 */
|
|
ADC_SL0CFG_CHSEL0_EXT0 = 0, /*!< EXT0 : ADC_EXT0 external GPIO pin connection. */
|
|
ADC_SL0CFG_CHSEL0_EXT1 = 1, /*!< EXT1 : ADC_EXT1 external GPIO pin connection. */
|
|
ADC_SL0CFG_CHSEL0_EXT2 = 2, /*!< EXT2 : ADC_EXT2 external GPIO pin connection. */
|
|
ADC_SL0CFG_CHSEL0_EXT3 = 3, /*!< EXT3 : ADC_EXT3 external GPIO pin connection. */
|
|
ADC_SL0CFG_CHSEL0_EXT4 = 4, /*!< EXT4 : ADC_EXT4 external GPIO pin connection. */
|
|
ADC_SL0CFG_CHSEL0_EXT5 = 5, /*!< EXT5 : ADC_EXT5 external GPIO pin connection. */
|
|
ADC_SL0CFG_CHSEL0_EXT6 = 6, /*!< EXT6 : ADC_EXT6 external GPIO pin connection. */
|
|
ADC_SL0CFG_CHSEL0_EXT7 = 7, /*!< EXT7 : ADC_EXT7 external GPIO pin connection. */
|
|
ADC_SL0CFG_CHSEL0_TEMP = 8, /*!< TEMP : ADC_TEMP internal temperature sensor. */
|
|
ADC_SL0CFG_CHSEL0_VDD = 9, /*!< VDD : ADC_VDD internal power rail connection. */
|
|
ADC_SL0CFG_CHSEL0_VSS = 10, /*!< VSS : ADC_VSS internal ground connection. */
|
|
ADC_SL0CFG_CHSEL0_VBATT = 12, /*!< VBATT : ADC_VBATT internal voltage divide-by-3 connection to
|
|
input power rail. */
|
|
} ADC_SL0CFG_CHSEL0_Enum;
|
|
|
|
/* ================================================ ADC SL0CFG WCEN0 [1..1] ================================================ */
|
|
typedef enum { /*!< ADC_SL0CFG_WCEN0 */
|
|
ADC_SL0CFG_WCEN0_WCEN = 1, /*!< WCEN : Enable the window compare for slot 0. */
|
|
} ADC_SL0CFG_WCEN0_Enum;
|
|
|
|
/* ================================================ ADC SL0CFG SLEN0 [0..0] ================================================ */
|
|
typedef enum { /*!< ADC_SL0CFG_SLEN0 */
|
|
ADC_SL0CFG_SLEN0_SLEN = 1, /*!< SLEN : Enable slot 0 for ADC conversions. */
|
|
} ADC_SL0CFG_SLEN0_Enum;
|
|
|
|
/* ======================================================== SL1CFG ========================================================= */
|
|
/* ============================================== ADC SL1CFG ADSEL1 [24..26] =============================================== */
|
|
typedef enum { /*!< ADC_SL1CFG_ADSEL1 */
|
|
ADC_SL1CFG_ADSEL1_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
|
|
module for this slot. */
|
|
ADC_SL1CFG_ADSEL1_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
|
|
module for this slot. */
|
|
ADC_SL1CFG_ADSEL1_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
|
|
module for this slot. */
|
|
ADC_SL1CFG_ADSEL1_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
|
|
module for this slot. */
|
|
ADC_SL1CFG_ADSEL1_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
|
|
divide module for this slot. */
|
|
ADC_SL1CFG_ADSEL1_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
|
|
divide module for this slot. */
|
|
ADC_SL1CFG_ADSEL1_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
|
|
divide module for this slot. */
|
|
ADC_SL1CFG_ADSEL1_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
|
|
divide module for this slot. */
|
|
} ADC_SL1CFG_ADSEL1_Enum;
|
|
|
|
/* ============================================== ADC SL1CFG THSEL1 [16..18] =============================================== */
|
|
typedef enum { /*!< ADC_SL1CFG_THSEL1 */
|
|
ADC_SL1CFG_THSEL1_1_ADC_CLK = 0, /*!< 1_ADC_CLK : 1 ADC clock cycle. */
|
|
ADC_SL1CFG_THSEL1_2_ADC_CLKS = 1, /*!< 2_ADC_CLKS : 2 ADC clock cycles. */
|
|
ADC_SL1CFG_THSEL1_4_ADC_CLKS = 2, /*!< 4_ADC_CLKS : 4 ADC clock cycles. */
|
|
ADC_SL1CFG_THSEL1_8_ADC_CLKS = 3, /*!< 8_ADC_CLKS : 8 ADC clock cycles. */
|
|
ADC_SL1CFG_THSEL1_16_ADC_CLKS = 4, /*!< 16_ADC_CLKS : 16 ADC clock cycles. */
|
|
ADC_SL1CFG_THSEL1_32_ADC_CLKS = 5, /*!< 32_ADC_CLKS : 32 ADC clock cycles. */
|
|
ADC_SL1CFG_THSEL1_64_ADC_CLKS = 6, /*!< 64_ADC_CLKS : 64 ADC clock cycles. */
|
|
ADC_SL1CFG_THSEL1_128_ADC_CLKS = 7, /*!< 128_ADC_CLKS : 128 ADC clock cycles. */
|
|
} ADC_SL1CFG_THSEL1_Enum;
|
|
|
|
/* =============================================== ADC SL1CFG CHSEL1 [8..11] =============================================== */
|
|
typedef enum { /*!< ADC_SL1CFG_CHSEL1 */
|
|
ADC_SL1CFG_CHSEL1_EXT0 = 0, /*!< EXT0 : ADC_EXT0 external GPIO pin connection. */
|
|
ADC_SL1CFG_CHSEL1_EXT1 = 1, /*!< EXT1 : ADC_EXT1 external GPIO pin connection. */
|
|
ADC_SL1CFG_CHSEL1_EXT2 = 2, /*!< EXT2 : ADC_EXT2 external GPIO pin connection. */
|
|
ADC_SL1CFG_CHSEL1_EXT3 = 3, /*!< EXT3 : ADC_EXT3 external GPIO pin connection. */
|
|
ADC_SL1CFG_CHSEL1_EXT4 = 4, /*!< EXT4 : ADC_EXT4 external GPIO pin connection. */
|
|
ADC_SL1CFG_CHSEL1_EXT5 = 5, /*!< EXT5 : ADC_EXT5 external GPIO pin connection. */
|
|
ADC_SL1CFG_CHSEL1_EXT6 = 6, /*!< EXT6 : ADC_EXT6 external GPIO pin connection. */
|
|
ADC_SL1CFG_CHSEL1_EXT7 = 7, /*!< EXT7 : ADC_EXT7 external GPIO pin connection. */
|
|
ADC_SL1CFG_CHSEL1_TEMP = 8, /*!< TEMP : ADC_TEMP internal temperature sensor. */
|
|
ADC_SL1CFG_CHSEL1_VDD = 9, /*!< VDD : ADC_VDD internal power rail connection. */
|
|
ADC_SL1CFG_CHSEL1_VSS = 10, /*!< VSS : ADC_VSS internal ground connection. */
|
|
ADC_SL1CFG_CHSEL1_VBATT = 12, /*!< VBATT : ADC_VBATT internal voltage divide-by-3 connection to
|
|
input power rail. */
|
|
} ADC_SL1CFG_CHSEL1_Enum;
|
|
|
|
/* ================================================ ADC SL1CFG WCEN1 [1..1] ================================================ */
|
|
typedef enum { /*!< ADC_SL1CFG_WCEN1 */
|
|
ADC_SL1CFG_WCEN1_WCEN = 1, /*!< WCEN : Enable the window compare for slot 1. */
|
|
} ADC_SL1CFG_WCEN1_Enum;
|
|
|
|
/* ================================================ ADC SL1CFG SLEN1 [0..0] ================================================ */
|
|
typedef enum { /*!< ADC_SL1CFG_SLEN1 */
|
|
ADC_SL1CFG_SLEN1_SLEN = 1, /*!< SLEN : Enable slot 1 for ADC conversions. */
|
|
} ADC_SL1CFG_SLEN1_Enum;
|
|
|
|
/* ======================================================== SL2CFG ========================================================= */
|
|
/* ============================================== ADC SL2CFG ADSEL2 [24..26] =============================================== */
|
|
typedef enum { /*!< ADC_SL2CFG_ADSEL2 */
|
|
ADC_SL2CFG_ADSEL2_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
|
|
module for this slot. */
|
|
ADC_SL2CFG_ADSEL2_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
|
|
module for this slot. */
|
|
ADC_SL2CFG_ADSEL2_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
|
|
module for this slot. */
|
|
ADC_SL2CFG_ADSEL2_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
|
|
module for this slot. */
|
|
ADC_SL2CFG_ADSEL2_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
|
|
divide module for this slot. */
|
|
ADC_SL2CFG_ADSEL2_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
|
|
divide module for this slot. */
|
|
ADC_SL2CFG_ADSEL2_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
|
|
divide module for this slot. */
|
|
ADC_SL2CFG_ADSEL2_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
|
|
divide module for this slot. */
|
|
} ADC_SL2CFG_ADSEL2_Enum;
|
|
|
|
/* ============================================== ADC SL2CFG THSEL2 [16..18] =============================================== */
|
|
typedef enum { /*!< ADC_SL2CFG_THSEL2 */
|
|
ADC_SL2CFG_THSEL2_1_ADC_CLK = 0, /*!< 1_ADC_CLK : 1 ADC clock cycle. */
|
|
ADC_SL2CFG_THSEL2_2_ADC_CLKS = 1, /*!< 2_ADC_CLKS : 2 ADC clock cycles. */
|
|
ADC_SL2CFG_THSEL2_4_ADC_CLKS = 2, /*!< 4_ADC_CLKS : 4 ADC clock cycles. */
|
|
ADC_SL2CFG_THSEL2_8_ADC_CLKS = 3, /*!< 8_ADC_CLKS : 8 ADC clock cycles. */
|
|
ADC_SL2CFG_THSEL2_16_ADC_CLKS = 4, /*!< 16_ADC_CLKS : 16 ADC clock cycles. */
|
|
ADC_SL2CFG_THSEL2_32_ADC_CLKS = 5, /*!< 32_ADC_CLKS : 32 ADC clock cycles. */
|
|
ADC_SL2CFG_THSEL2_64_ADC_CLKS = 6, /*!< 64_ADC_CLKS : 64 ADC clock cycles. */
|
|
ADC_SL2CFG_THSEL2_128_ADC_CLKS = 7, /*!< 128_ADC_CLKS : 128 ADC clock cycles. */
|
|
} ADC_SL2CFG_THSEL2_Enum;
|
|
|
|
/* =============================================== ADC SL2CFG CHSEL2 [8..11] =============================================== */
|
|
typedef enum { /*!< ADC_SL2CFG_CHSEL2 */
|
|
ADC_SL2CFG_CHSEL2_EXT0 = 0, /*!< EXT0 : ADC_EXT0 external GPIO pin connection. */
|
|
ADC_SL2CFG_CHSEL2_EXT1 = 1, /*!< EXT1 : ADC_EXT1 external GPIO pin connection. */
|
|
ADC_SL2CFG_CHSEL2_EXT2 = 2, /*!< EXT2 : ADC_EXT2 external GPIO pin connection. */
|
|
ADC_SL2CFG_CHSEL2_EXT3 = 3, /*!< EXT3 : ADC_EXT3 external GPIO pin connection. */
|
|
ADC_SL2CFG_CHSEL2_EXT4 = 4, /*!< EXT4 : ADC_EXT4 external GPIO pin connection. */
|
|
ADC_SL2CFG_CHSEL2_EXT5 = 5, /*!< EXT5 : ADC_EXT5 external GPIO pin connection. */
|
|
ADC_SL2CFG_CHSEL2_EXT6 = 6, /*!< EXT6 : ADC_EXT6 external GPIO pin connection. */
|
|
ADC_SL2CFG_CHSEL2_EXT7 = 7, /*!< EXT7 : ADC_EXT7 external GPIO pin connection. */
|
|
ADC_SL2CFG_CHSEL2_TEMP = 8, /*!< TEMP : ADC_TEMP internal temperature sensor. */
|
|
ADC_SL2CFG_CHSEL2_VDD = 9, /*!< VDD : ADC_VDD internal power rail connection. */
|
|
ADC_SL2CFG_CHSEL2_VSS = 10, /*!< VSS : ADC_VSS internal ground connection. */
|
|
ADC_SL2CFG_CHSEL2_VBATT = 12, /*!< VBATT : ADC_VBATT internal voltage divide-by-3 connection to
|
|
input power rail. */
|
|
} ADC_SL2CFG_CHSEL2_Enum;
|
|
|
|
/* ================================================ ADC SL2CFG WCEN2 [1..1] ================================================ */
|
|
typedef enum { /*!< ADC_SL2CFG_WCEN2 */
|
|
ADC_SL2CFG_WCEN2_WCEN = 1, /*!< WCEN : Enable the window compare for slot 2. */
|
|
} ADC_SL2CFG_WCEN2_Enum;
|
|
|
|
/* ================================================ ADC SL2CFG SLEN2 [0..0] ================================================ */
|
|
typedef enum { /*!< ADC_SL2CFG_SLEN2 */
|
|
ADC_SL2CFG_SLEN2_SLEN = 1, /*!< SLEN : Enable slot 2 for ADC conversions. */
|
|
} ADC_SL2CFG_SLEN2_Enum;
|
|
|
|
/* ======================================================== SL3CFG ========================================================= */
|
|
/* ============================================== ADC SL3CFG ADSEL3 [24..26] =============================================== */
|
|
typedef enum { /*!< ADC_SL3CFG_ADSEL3 */
|
|
ADC_SL3CFG_ADSEL3_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
|
|
module for this slot. */
|
|
ADC_SL3CFG_ADSEL3_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
|
|
module for this slot. */
|
|
ADC_SL3CFG_ADSEL3_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
|
|
module for this slot. */
|
|
ADC_SL3CFG_ADSEL3_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
|
|
module for this slot. */
|
|
ADC_SL3CFG_ADSEL3_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
|
|
divide module for this slot. */
|
|
ADC_SL3CFG_ADSEL3_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
|
|
divide module for this slot. */
|
|
ADC_SL3CFG_ADSEL3_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
|
|
divide module for this slot. */
|
|
ADC_SL3CFG_ADSEL3_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
|
|
divide module for this slot. */
|
|
} ADC_SL3CFG_ADSEL3_Enum;
|
|
|
|
/* ============================================== ADC SL3CFG THSEL3 [16..18] =============================================== */
|
|
typedef enum { /*!< ADC_SL3CFG_THSEL3 */
|
|
ADC_SL3CFG_THSEL3_1_ADC_CLK = 0, /*!< 1_ADC_CLK : 1 ADC clock cycle. */
|
|
ADC_SL3CFG_THSEL3_2_ADC_CLKS = 1, /*!< 2_ADC_CLKS : 2 ADC clock cycles. */
|
|
ADC_SL3CFG_THSEL3_4_ADC_CLKS = 2, /*!< 4_ADC_CLKS : 4 ADC clock cycles. */
|
|
ADC_SL3CFG_THSEL3_8_ADC_CLKS = 3, /*!< 8_ADC_CLKS : 8 ADC clock cycles. */
|
|
ADC_SL3CFG_THSEL3_16_ADC_CLKS = 4, /*!< 16_ADC_CLKS : 16 ADC clock cycles. */
|
|
ADC_SL3CFG_THSEL3_32_ADC_CLKS = 5, /*!< 32_ADC_CLKS : 32 ADC clock cycles. */
|
|
ADC_SL3CFG_THSEL3_64_ADC_CLKS = 6, /*!< 64_ADC_CLKS : 64 ADC clock cycles. */
|
|
ADC_SL3CFG_THSEL3_128_ADC_CLKS = 7, /*!< 128_ADC_CLKS : 128 ADC clock cycles. */
|
|
} ADC_SL3CFG_THSEL3_Enum;
|
|
|
|
/* =============================================== ADC SL3CFG CHSEL3 [8..11] =============================================== */
|
|
typedef enum { /*!< ADC_SL3CFG_CHSEL3 */
|
|
ADC_SL3CFG_CHSEL3_EXT0 = 0, /*!< EXT0 : ADC_EXT0 external GPIO pin connection. */
|
|
ADC_SL3CFG_CHSEL3_EXT1 = 1, /*!< EXT1 : ADC_EXT1 external GPIO pin connection. */
|
|
ADC_SL3CFG_CHSEL3_EXT2 = 2, /*!< EXT2 : ADC_EXT2 external GPIO pin connection. */
|
|
ADC_SL3CFG_CHSEL3_EXT3 = 3, /*!< EXT3 : ADC_EXT3 external GPIO pin connection. */
|
|
ADC_SL3CFG_CHSEL3_EXT4 = 4, /*!< EXT4 : ADC_EXT4 external GPIO pin connection. */
|
|
ADC_SL3CFG_CHSEL3_EXT5 = 5, /*!< EXT5 : ADC_EXT5 external GPIO pin connection. */
|
|
ADC_SL3CFG_CHSEL3_EXT6 = 6, /*!< EXT6 : ADC_EXT6 external GPIO pin connection. */
|
|
ADC_SL3CFG_CHSEL3_EXT7 = 7, /*!< EXT7 : ADC_EXT7 external GPIO pin connection. */
|
|
ADC_SL3CFG_CHSEL3_TEMP = 8, /*!< TEMP : ADC_TEMP internal temperature sensor. */
|
|
ADC_SL3CFG_CHSEL3_VDD = 9, /*!< VDD : ADC_VDD internal power rail connection. */
|
|
ADC_SL3CFG_CHSEL3_VSS = 10, /*!< VSS : ADC_VSS internal ground connection. */
|
|
ADC_SL3CFG_CHSEL3_VBATT = 12, /*!< VBATT : ADC_VBATT internal voltage divide-by-3 connection to
|
|
input power rail. */
|
|
} ADC_SL3CFG_CHSEL3_Enum;
|
|
|
|
/* ================================================ ADC SL3CFG WCEN3 [1..1] ================================================ */
|
|
typedef enum { /*!< ADC_SL3CFG_WCEN3 */
|
|
ADC_SL3CFG_WCEN3_WCEN = 1, /*!< WCEN : Enable the window compare for slot 3. */
|
|
} ADC_SL3CFG_WCEN3_Enum;
|
|
|
|
/* ================================================ ADC SL3CFG SLEN3 [0..0] ================================================ */
|
|
typedef enum { /*!< ADC_SL3CFG_SLEN3 */
|
|
ADC_SL3CFG_SLEN3_SLEN = 1, /*!< SLEN : Enable slot 3 for ADC conversions. */
|
|
} ADC_SL3CFG_SLEN3_Enum;
|
|
|
|
/* ======================================================== SL4CFG ========================================================= */
|
|
/* ============================================== ADC SL4CFG ADSEL4 [24..26] =============================================== */
|
|
typedef enum { /*!< ADC_SL4CFG_ADSEL4 */
|
|
ADC_SL4CFG_ADSEL4_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
|
|
module for this slot. */
|
|
ADC_SL4CFG_ADSEL4_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
|
|
module for this slot. */
|
|
ADC_SL4CFG_ADSEL4_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
|
|
module for this slot. */
|
|
ADC_SL4CFG_ADSEL4_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
|
|
module for this slot. */
|
|
ADC_SL4CFG_ADSEL4_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
|
|
divide module for this slot. */
|
|
ADC_SL4CFG_ADSEL4_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
|
|
divide module for this slot. */
|
|
ADC_SL4CFG_ADSEL4_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
|
|
divide module for this slot. */
|
|
ADC_SL4CFG_ADSEL4_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
|
|
divide module for this slot. */
|
|
} ADC_SL4CFG_ADSEL4_Enum;
|
|
|
|
/* ============================================== ADC SL4CFG THSEL4 [16..18] =============================================== */
|
|
typedef enum { /*!< ADC_SL4CFG_THSEL4 */
|
|
ADC_SL4CFG_THSEL4_1_ADC_CLK = 0, /*!< 1_ADC_CLK : 1 ADC clock cycle. */
|
|
ADC_SL4CFG_THSEL4_2_ADC_CLKS = 1, /*!< 2_ADC_CLKS : 2 ADC clock cycles. */
|
|
ADC_SL4CFG_THSEL4_4_ADC_CLKS = 2, /*!< 4_ADC_CLKS : 4 ADC clock cycles. */
|
|
ADC_SL4CFG_THSEL4_8_ADC_CLKS = 3, /*!< 8_ADC_CLKS : 8 ADC clock cycles. */
|
|
ADC_SL4CFG_THSEL4_16_ADC_CLKS = 4, /*!< 16_ADC_CLKS : 16 ADC clock cycles. */
|
|
ADC_SL4CFG_THSEL4_32_ADC_CLKS = 5, /*!< 32_ADC_CLKS : 32 ADC clock cycles. */
|
|
ADC_SL4CFG_THSEL4_64_ADC_CLKS = 6, /*!< 64_ADC_CLKS : 64 ADC clock cycles. */
|
|
ADC_SL4CFG_THSEL4_128_ADC_CLKS = 7, /*!< 128_ADC_CLKS : 128 ADC clock cycles. */
|
|
} ADC_SL4CFG_THSEL4_Enum;
|
|
|
|
/* =============================================== ADC SL4CFG CHSEL4 [8..11] =============================================== */
|
|
typedef enum { /*!< ADC_SL4CFG_CHSEL4 */
|
|
ADC_SL4CFG_CHSEL4_EXT0 = 0, /*!< EXT0 : ADC_EXT0 external GPIO pin connection. */
|
|
ADC_SL4CFG_CHSEL4_EXT1 = 1, /*!< EXT1 : ADC_EXT1 external GPIO pin connection. */
|
|
ADC_SL4CFG_CHSEL4_EXT2 = 2, /*!< EXT2 : ADC_EXT2 external GPIO pin connection. */
|
|
ADC_SL4CFG_CHSEL4_EXT3 = 3, /*!< EXT3 : ADC_EXT3 external GPIO pin connection. */
|
|
ADC_SL4CFG_CHSEL4_EXT4 = 4, /*!< EXT4 : ADC_EXT4 external GPIO pin connection. */
|
|
ADC_SL4CFG_CHSEL4_EXT5 = 5, /*!< EXT5 : ADC_EXT5 external GPIO pin connection. */
|
|
ADC_SL4CFG_CHSEL4_EXT6 = 6, /*!< EXT6 : ADC_EXT6 external GPIO pin connection. */
|
|
ADC_SL4CFG_CHSEL4_EXT7 = 7, /*!< EXT7 : ADC_EXT7 external GPIO pin connection. */
|
|
ADC_SL4CFG_CHSEL4_TEMP = 8, /*!< TEMP : ADC_TEMP internal temperature sensor. */
|
|
ADC_SL4CFG_CHSEL4_VDD = 9, /*!< VDD : ADC_VDD internal power rail connection. */
|
|
ADC_SL4CFG_CHSEL4_VSS = 10, /*!< VSS : ADC_VSS internal ground connection. */
|
|
ADC_SL4CFG_CHSEL4_VBATT = 12, /*!< VBATT : ADC_VBATT internal voltage divide-by-3 connection to
|
|
input power rail. */
|
|
} ADC_SL4CFG_CHSEL4_Enum;
|
|
|
|
/* ================================================ ADC SL4CFG WCEN4 [1..1] ================================================ */
|
|
typedef enum { /*!< ADC_SL4CFG_WCEN4 */
|
|
ADC_SL4CFG_WCEN4_WCEN = 1, /*!< WCEN : Enable the window compare for slot 4. */
|
|
} ADC_SL4CFG_WCEN4_Enum;
|
|
|
|
/* ================================================ ADC SL4CFG SLEN4 [0..0] ================================================ */
|
|
typedef enum { /*!< ADC_SL4CFG_SLEN4 */
|
|
ADC_SL4CFG_SLEN4_SLEN = 1, /*!< SLEN : Enable slot 4 for ADC conversions. */
|
|
} ADC_SL4CFG_SLEN4_Enum;
|
|
|
|
/* ======================================================== SL5CFG ========================================================= */
|
|
/* ============================================== ADC SL5CFG ADSEL5 [24..26] =============================================== */
|
|
typedef enum { /*!< ADC_SL5CFG_ADSEL5 */
|
|
ADC_SL5CFG_ADSEL5_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
|
|
module for this slot. */
|
|
ADC_SL5CFG_ADSEL5_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
|
|
module for this slot. */
|
|
ADC_SL5CFG_ADSEL5_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
|
|
module for this slot. */
|
|
ADC_SL5CFG_ADSEL5_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
|
|
module for this slot. */
|
|
ADC_SL5CFG_ADSEL5_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
|
|
divide module for this slot. */
|
|
ADC_SL5CFG_ADSEL5_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
|
|
divide module for this slot. */
|
|
ADC_SL5CFG_ADSEL5_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
|
|
divide module for this slot. */
|
|
ADC_SL5CFG_ADSEL5_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
|
|
divide module for this slot. */
|
|
} ADC_SL5CFG_ADSEL5_Enum;
|
|
|
|
/* ============================================== ADC SL5CFG THSEL5 [16..18] =============================================== */
|
|
typedef enum { /*!< ADC_SL5CFG_THSEL5 */
|
|
ADC_SL5CFG_THSEL5_1_ADC_CLK = 0, /*!< 1_ADC_CLK : 1 ADC clock cycle. */
|
|
ADC_SL5CFG_THSEL5_2_ADC_CLKS = 1, /*!< 2_ADC_CLKS : 2 ADC clock cycles. */
|
|
ADC_SL5CFG_THSEL5_4_ADC_CLKS = 2, /*!< 4_ADC_CLKS : 4 ADC clock cycles. */
|
|
ADC_SL5CFG_THSEL5_8_ADC_CLKS = 3, /*!< 8_ADC_CLKS : 8 ADC clock cycles. */
|
|
ADC_SL5CFG_THSEL5_16_ADC_CLKS = 4, /*!< 16_ADC_CLKS : 16 ADC clock cycles. */
|
|
ADC_SL5CFG_THSEL5_32_ADC_CLKS = 5, /*!< 32_ADC_CLKS : 32 ADC clock cycles. */
|
|
ADC_SL5CFG_THSEL5_64_ADC_CLKS = 6, /*!< 64_ADC_CLKS : 64 ADC clock cycles. */
|
|
ADC_SL5CFG_THSEL5_128_ADC_CLKS = 7, /*!< 128_ADC_CLKS : 128 ADC clock cycles. */
|
|
} ADC_SL5CFG_THSEL5_Enum;
|
|
|
|
/* =============================================== ADC SL5CFG CHSEL5 [8..11] =============================================== */
|
|
typedef enum { /*!< ADC_SL5CFG_CHSEL5 */
|
|
ADC_SL5CFG_CHSEL5_EXT0 = 0, /*!< EXT0 : ADC_EXT0 external GPIO pin connection. */
|
|
ADC_SL5CFG_CHSEL5_EXT1 = 1, /*!< EXT1 : ADC_EXT1 external GPIO pin connection. */
|
|
ADC_SL5CFG_CHSEL5_EXT2 = 2, /*!< EXT2 : ADC_EXT2 external GPIO pin connection. */
|
|
ADC_SL5CFG_CHSEL5_EXT3 = 3, /*!< EXT3 : ADC_EXT3 external GPIO pin connection. */
|
|
ADC_SL5CFG_CHSEL5_EXT4 = 4, /*!< EXT4 : ADC_EXT4 external GPIO pin connection. */
|
|
ADC_SL5CFG_CHSEL5_EXT5 = 5, /*!< EXT5 : ADC_EXT5 external GPIO pin connection. */
|
|
ADC_SL5CFG_CHSEL5_EXT6 = 6, /*!< EXT6 : ADC_EXT6 external GPIO pin connection. */
|
|
ADC_SL5CFG_CHSEL5_EXT7 = 7, /*!< EXT7 : ADC_EXT7 external GPIO pin connection. */
|
|
ADC_SL5CFG_CHSEL5_TEMP = 8, /*!< TEMP : ADC_TEMP internal temperature sensor. */
|
|
ADC_SL5CFG_CHSEL5_VDD = 9, /*!< VDD : ADC_VDD internal power rail connection. */
|
|
ADC_SL5CFG_CHSEL5_VSS = 10, /*!< VSS : ADC_VSS internal ground connection. */
|
|
ADC_SL5CFG_CHSEL5_VBATT = 12, /*!< VBATT : ADC_VBATT internal voltage divide-by-3 connection to
|
|
input power rail. */
|
|
} ADC_SL5CFG_CHSEL5_Enum;
|
|
|
|
/* ================================================ ADC SL5CFG WCEN5 [1..1] ================================================ */
|
|
typedef enum { /*!< ADC_SL5CFG_WCEN5 */
|
|
ADC_SL5CFG_WCEN5_WCEN = 1, /*!< WCEN : Enable the window compare for slot 5. */
|
|
} ADC_SL5CFG_WCEN5_Enum;
|
|
|
|
/* ================================================ ADC SL5CFG SLEN5 [0..0] ================================================ */
|
|
typedef enum { /*!< ADC_SL5CFG_SLEN5 */
|
|
ADC_SL5CFG_SLEN5_SLEN = 1, /*!< SLEN : Enable slot 5 for ADC conversions. */
|
|
} ADC_SL5CFG_SLEN5_Enum;
|
|
|
|
/* ======================================================== SL6CFG ========================================================= */
|
|
/* ============================================== ADC SL6CFG ADSEL6 [24..26] =============================================== */
|
|
typedef enum { /*!< ADC_SL6CFG_ADSEL6 */
|
|
ADC_SL6CFG_ADSEL6_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
|
|
module for this slot. */
|
|
ADC_SL6CFG_ADSEL6_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
|
|
module for this slot. */
|
|
ADC_SL6CFG_ADSEL6_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
|
|
module for this slot. */
|
|
ADC_SL6CFG_ADSEL6_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
|
|
module for this slot. */
|
|
ADC_SL6CFG_ADSEL6_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
|
|
divide module for this slot. */
|
|
ADC_SL6CFG_ADSEL6_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
|
|
divide module for this slot. */
|
|
ADC_SL6CFG_ADSEL6_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
|
|
divide module for this slot. */
|
|
ADC_SL6CFG_ADSEL6_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
|
|
divide module for this slot. */
|
|
} ADC_SL6CFG_ADSEL6_Enum;
|
|
|
|
/* ============================================== ADC SL6CFG THSEL6 [16..18] =============================================== */
|
|
typedef enum { /*!< ADC_SL6CFG_THSEL6 */
|
|
ADC_SL6CFG_THSEL6_1_ADC_CLK = 0, /*!< 1_ADC_CLK : 1 ADC clock cycle. */
|
|
ADC_SL6CFG_THSEL6_2_ADC_CLKS = 1, /*!< 2_ADC_CLKS : 2 ADC clock cycles. */
|
|
ADC_SL6CFG_THSEL6_4_ADC_CLKS = 2, /*!< 4_ADC_CLKS : 4 ADC clock cycles. */
|
|
ADC_SL6CFG_THSEL6_8_ADC_CLKS = 3, /*!< 8_ADC_CLKS : 8 ADC clock cycles. */
|
|
ADC_SL6CFG_THSEL6_16_ADC_CLKS = 4, /*!< 16_ADC_CLKS : 16 ADC clock cycles. */
|
|
ADC_SL6CFG_THSEL6_32_ADC_CLKS = 5, /*!< 32_ADC_CLKS : 32 ADC clock cycles. */
|
|
ADC_SL6CFG_THSEL6_64_ADC_CLKS = 6, /*!< 64_ADC_CLKS : 64 ADC clock cycles. */
|
|
ADC_SL6CFG_THSEL6_128_ADC_CLKS = 7, /*!< 128_ADC_CLKS : 128 ADC clock cycles. */
|
|
} ADC_SL6CFG_THSEL6_Enum;
|
|
|
|
/* =============================================== ADC SL6CFG CHSEL6 [8..11] =============================================== */
|
|
typedef enum { /*!< ADC_SL6CFG_CHSEL6 */
|
|
ADC_SL6CFG_CHSEL6_EXT0 = 0, /*!< EXT0 : ADC_EXT0 external GPIO pin connection. */
|
|
ADC_SL6CFG_CHSEL6_EXT1 = 1, /*!< EXT1 : ADC_EXT1 external GPIO pin connection. */
|
|
ADC_SL6CFG_CHSEL6_EXT2 = 2, /*!< EXT2 : ADC_EXT2 external GPIO pin connection. */
|
|
ADC_SL6CFG_CHSEL6_EXT3 = 3, /*!< EXT3 : ADC_EXT3 external GPIO pin connection. */
|
|
ADC_SL6CFG_CHSEL6_EXT4 = 4, /*!< EXT4 : ADC_EXT4 external GPIO pin connection. */
|
|
ADC_SL6CFG_CHSEL6_EXT5 = 5, /*!< EXT5 : ADC_EXT5 external GPIO pin connection. */
|
|
ADC_SL6CFG_CHSEL6_EXT6 = 6, /*!< EXT6 : ADC_EXT6 external GPIO pin connection. */
|
|
ADC_SL6CFG_CHSEL6_EXT7 = 7, /*!< EXT7 : ADC_EXT7 external GPIO pin connection. */
|
|
ADC_SL6CFG_CHSEL6_TEMP = 8, /*!< TEMP : ADC_TEMP internal temperature sensor. */
|
|
ADC_SL6CFG_CHSEL6_VDD = 9, /*!< VDD : ADC_VDD internal power rail connection. */
|
|
ADC_SL6CFG_CHSEL6_VSS = 10, /*!< VSS : ADC_VSS internal ground connection. */
|
|
ADC_SL6CFG_CHSEL6_VBATT = 12, /*!< VBATT : ADC_VBATT internal voltage divide-by-3 connection to
|
|
input power rail. */
|
|
} ADC_SL6CFG_CHSEL6_Enum;
|
|
|
|
/* ================================================ ADC SL6CFG WCEN6 [1..1] ================================================ */
|
|
typedef enum { /*!< ADC_SL6CFG_WCEN6 */
|
|
ADC_SL6CFG_WCEN6_WCEN = 1, /*!< WCEN : Enable the window compare for slot 6. */
|
|
} ADC_SL6CFG_WCEN6_Enum;
|
|
|
|
/* ================================================ ADC SL6CFG SLEN6 [0..0] ================================================ */
|
|
typedef enum { /*!< ADC_SL6CFG_SLEN6 */
|
|
ADC_SL6CFG_SLEN6_SLEN = 1, /*!< SLEN : Enable slot 6 for ADC conversions. */
|
|
} ADC_SL6CFG_SLEN6_Enum;
|
|
|
|
/* ======================================================== SL7CFG ========================================================= */
|
|
/* ============================================== ADC SL7CFG ADSEL7 [24..26] =============================================== */
|
|
typedef enum { /*!< ADC_SL7CFG_ADSEL7 */
|
|
ADC_SL7CFG_ADSEL7_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
|
|
module for this slot. */
|
|
ADC_SL7CFG_ADSEL7_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
|
|
module for this slot. */
|
|
ADC_SL7CFG_ADSEL7_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
|
|
module for this slot. */
|
|
ADC_SL7CFG_ADSEL7_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
|
|
module for this slot. */
|
|
ADC_SL7CFG_ADSEL7_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
|
|
divide module for this slot. */
|
|
ADC_SL7CFG_ADSEL7_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
|
|
divide module for this slot. */
|
|
ADC_SL7CFG_ADSEL7_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
|
|
divide module for this slot. */
|
|
ADC_SL7CFG_ADSEL7_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
|
|
divide module for this slot. */
|
|
} ADC_SL7CFG_ADSEL7_Enum;
|
|
|
|
/* ============================================== ADC SL7CFG THSEL7 [16..18] =============================================== */
|
|
typedef enum { /*!< ADC_SL7CFG_THSEL7 */
|
|
ADC_SL7CFG_THSEL7_1_ADC_CLK = 0, /*!< 1_ADC_CLK : 1 ADC clock cycle. */
|
|
ADC_SL7CFG_THSEL7_2_ADC_CLKS = 1, /*!< 2_ADC_CLKS : 2 ADC clock cycles. */
|
|
ADC_SL7CFG_THSEL7_4_ADC_CLKS = 2, /*!< 4_ADC_CLKS : 4 ADC clock cycles. */
|
|
ADC_SL7CFG_THSEL7_8_ADC_CLKS = 3, /*!< 8_ADC_CLKS : 8 ADC clock cycles. */
|
|
ADC_SL7CFG_THSEL7_16_ADC_CLKS = 4, /*!< 16_ADC_CLKS : 16 ADC clock cycles. */
|
|
ADC_SL7CFG_THSEL7_32_ADC_CLKS = 5, /*!< 32_ADC_CLKS : 32 ADC clock cycles. */
|
|
ADC_SL7CFG_THSEL7_64_ADC_CLKS = 6, /*!< 64_ADC_CLKS : 64 ADC clock cycles. */
|
|
ADC_SL7CFG_THSEL7_128_ADC_CLKS = 7, /*!< 128_ADC_CLKS : 128 ADC clock cycles. */
|
|
} ADC_SL7CFG_THSEL7_Enum;
|
|
|
|
/* =============================================== ADC SL7CFG CHSEL7 [8..11] =============================================== */
|
|
typedef enum { /*!< ADC_SL7CFG_CHSEL7 */
|
|
ADC_SL7CFG_CHSEL7_EXT0 = 0, /*!< EXT0 : ADC_EXT0 external GPIO pin connection. */
|
|
ADC_SL7CFG_CHSEL7_EXT1 = 1, /*!< EXT1 : ADC_EXT1 external GPIO pin connection. */
|
|
ADC_SL7CFG_CHSEL7_EXT2 = 2, /*!< EXT2 : ADC_EXT2 external GPIO pin connection. */
|
|
ADC_SL7CFG_CHSEL7_EXT3 = 3, /*!< EXT3 : ADC_EXT3 external GPIO pin connection. */
|
|
ADC_SL7CFG_CHSEL7_EXT4 = 4, /*!< EXT4 : ADC_EXT4 external GPIO pin connection. */
|
|
ADC_SL7CFG_CHSEL7_EXT5 = 5, /*!< EXT5 : ADC_EXT5 external GPIO pin connection. */
|
|
ADC_SL7CFG_CHSEL7_EXT6 = 6, /*!< EXT6 : ADC_EXT6 external GPIO pin connection. */
|
|
ADC_SL7CFG_CHSEL7_EXT7 = 7, /*!< EXT7 : ADC_EXT7 external GPIO pin connection. */
|
|
ADC_SL7CFG_CHSEL7_TEMP = 8, /*!< TEMP : ADC_TEMP internal temperature sensor. */
|
|
ADC_SL7CFG_CHSEL7_VDD = 9, /*!< VDD : ADC_VDD internal power rail connection. */
|
|
ADC_SL7CFG_CHSEL7_VSS = 10, /*!< VSS : ADC_VSS internal ground connection. */
|
|
ADC_SL7CFG_CHSEL7_VBATT = 12, /*!< VBATT : ADC_VBATT internal voltage divide-by-3 connection to
|
|
input power rail. */
|
|
} ADC_SL7CFG_CHSEL7_Enum;
|
|
|
|
/* ================================================ ADC SL7CFG WCEN7 [1..1] ================================================ */
|
|
typedef enum { /*!< ADC_SL7CFG_WCEN7 */
|
|
ADC_SL7CFG_WCEN7_WCEN = 1, /*!< WCEN : Enable the window compare for slot 7. */
|
|
} ADC_SL7CFG_WCEN7_Enum;
|
|
|
|
/* ================================================ ADC SL7CFG SLEN7 [0..0] ================================================ */
|
|
typedef enum { /*!< ADC_SL7CFG_SLEN7 */
|
|
ADC_SL7CFG_SLEN7_SLEN = 1, /*!< SLEN : Enable slot 7 for ADC conversions. */
|
|
} ADC_SL7CFG_SLEN7_Enum;
|
|
|
|
/* ========================================================= WLIM ========================================================== */
|
|
/* ========================================================= FIFO ========================================================== */
|
|
/* ========================================================= INTEN ========================================================= */
|
|
/* ================================================ ADC INTEN WCINC [5..5] ================================================= */
|
|
typedef enum { /*!< ADC_INTEN_WCINC */
|
|
ADC_INTEN_WCINC_WCINCINT = 1, /*!< WCINCINT : Window comparitor voltage incursion interrupt. */
|
|
} ADC_INTEN_WCINC_Enum;
|
|
|
|
/* ================================================ ADC INTEN WCEXC [4..4] ================================================= */
|
|
typedef enum { /*!< ADC_INTEN_WCEXC */
|
|
ADC_INTEN_WCEXC_WCEXCINT = 1, /*!< WCEXCINT : Window comparitor voltage excursion interrupt. */
|
|
} ADC_INTEN_WCEXC_Enum;
|
|
|
|
/* =============================================== ADC INTEN FIFOOVR2 [3..3] =============================================== */
|
|
typedef enum { /*!< ADC_INTEN_FIFOOVR2 */
|
|
ADC_INTEN_FIFOOVR2_FIFOFULLINT = 1, /*!< FIFOFULLINT : FIFO 100 percent full interrupt. */
|
|
} ADC_INTEN_FIFOOVR2_Enum;
|
|
|
|
/* =============================================== ADC INTEN FIFOOVR1 [2..2] =============================================== */
|
|
typedef enum { /*!< ADC_INTEN_FIFOOVR1 */
|
|
ADC_INTEN_FIFOOVR1_FIFO75INT = 1, /*!< FIFO75INT : FIFO 75 percent full interrupt. */
|
|
} ADC_INTEN_FIFOOVR1_Enum;
|
|
|
|
/* ================================================ ADC INTEN SCNCMP [1..1] ================================================ */
|
|
typedef enum { /*!< ADC_INTEN_SCNCMP */
|
|
ADC_INTEN_SCNCMP_SCNCMPINT = 1, /*!< SCNCMPINT : ADC scan complete interrupt. */
|
|
} ADC_INTEN_SCNCMP_Enum;
|
|
|
|
/* ================================================ ADC INTEN CNVCMP [0..0] ================================================ */
|
|
typedef enum { /*!< ADC_INTEN_CNVCMP */
|
|
ADC_INTEN_CNVCMP_CNVCMPINT = 1, /*!< CNVCMPINT : ADC conversion complete interrupt. */
|
|
} ADC_INTEN_CNVCMP_Enum;
|
|
|
|
/* ======================================================== INTSTAT ======================================================== */
|
|
/* =============================================== ADC INTSTAT WCINC [5..5] ================================================ */
|
|
typedef enum { /*!< ADC_INTSTAT_WCINC */
|
|
ADC_INTSTAT_WCINC_WCINCINT = 1, /*!< WCINCINT : Window comparitor voltage incursion interrupt. */
|
|
} ADC_INTSTAT_WCINC_Enum;
|
|
|
|
/* =============================================== ADC INTSTAT WCEXC [4..4] ================================================ */
|
|
typedef enum { /*!< ADC_INTSTAT_WCEXC */
|
|
ADC_INTSTAT_WCEXC_WCEXCINT = 1, /*!< WCEXCINT : Window comparitor voltage excursion interrupt. */
|
|
} ADC_INTSTAT_WCEXC_Enum;
|
|
|
|
/* ============================================== ADC INTSTAT FIFOOVR2 [3..3] ============================================== */
|
|
typedef enum { /*!< ADC_INTSTAT_FIFOOVR2 */
|
|
ADC_INTSTAT_FIFOOVR2_FIFOFULLINT = 1, /*!< FIFOFULLINT : FIFO 100 percent full interrupt. */
|
|
} ADC_INTSTAT_FIFOOVR2_Enum;
|
|
|
|
/* ============================================== ADC INTSTAT FIFOOVR1 [2..2] ============================================== */
|
|
typedef enum { /*!< ADC_INTSTAT_FIFOOVR1 */
|
|
ADC_INTSTAT_FIFOOVR1_FIFO75INT = 1, /*!< FIFO75INT : FIFO 75 percent full interrupt. */
|
|
} ADC_INTSTAT_FIFOOVR1_Enum;
|
|
|
|
/* =============================================== ADC INTSTAT SCNCMP [1..1] =============================================== */
|
|
typedef enum { /*!< ADC_INTSTAT_SCNCMP */
|
|
ADC_INTSTAT_SCNCMP_SCNCMPINT = 1, /*!< SCNCMPINT : ADC scan complete interrupt. */
|
|
} ADC_INTSTAT_SCNCMP_Enum;
|
|
|
|
/* =============================================== ADC INTSTAT CNVCMP [0..0] =============================================== */
|
|
typedef enum { /*!< ADC_INTSTAT_CNVCMP */
|
|
ADC_INTSTAT_CNVCMP_CNVCMPINT = 1, /*!< CNVCMPINT : ADC conversion complete interrupt. */
|
|
} ADC_INTSTAT_CNVCMP_Enum;
|
|
|
|
/* ======================================================== INTCLR ========================================================= */
|
|
/* ================================================ ADC INTCLR WCINC [5..5] ================================================ */
|
|
typedef enum { /*!< ADC_INTCLR_WCINC */
|
|
ADC_INTCLR_WCINC_WCINCINT = 1, /*!< WCINCINT : Window comparitor voltage incursion interrupt. */
|
|
} ADC_INTCLR_WCINC_Enum;
|
|
|
|
/* ================================================ ADC INTCLR WCEXC [4..4] ================================================ */
|
|
typedef enum { /*!< ADC_INTCLR_WCEXC */
|
|
ADC_INTCLR_WCEXC_WCEXCINT = 1, /*!< WCEXCINT : Window comparitor voltage excursion interrupt. */
|
|
} ADC_INTCLR_WCEXC_Enum;
|
|
|
|
/* ============================================== ADC INTCLR FIFOOVR2 [3..3] =============================================== */
|
|
typedef enum { /*!< ADC_INTCLR_FIFOOVR2 */
|
|
ADC_INTCLR_FIFOOVR2_FIFOFULLINT = 1, /*!< FIFOFULLINT : FIFO 100 percent full interrupt. */
|
|
} ADC_INTCLR_FIFOOVR2_Enum;
|
|
|
|
/* ============================================== ADC INTCLR FIFOOVR1 [2..2] =============================================== */
|
|
typedef enum { /*!< ADC_INTCLR_FIFOOVR1 */
|
|
ADC_INTCLR_FIFOOVR1_FIFO75INT = 1, /*!< FIFO75INT : FIFO 75 percent full interrupt. */
|
|
} ADC_INTCLR_FIFOOVR1_Enum;
|
|
|
|
/* =============================================== ADC INTCLR SCNCMP [1..1] ================================================ */
|
|
typedef enum { /*!< ADC_INTCLR_SCNCMP */
|
|
ADC_INTCLR_SCNCMP_SCNCMPINT = 1, /*!< SCNCMPINT : ADC scan complete interrupt. */
|
|
} ADC_INTCLR_SCNCMP_Enum;
|
|
|
|
/* =============================================== ADC INTCLR CNVCMP [0..0] ================================================ */
|
|
typedef enum { /*!< ADC_INTCLR_CNVCMP */
|
|
ADC_INTCLR_CNVCMP_CNVCMPINT = 1, /*!< CNVCMPINT : ADC conversion complete interrupt. */
|
|
} ADC_INTCLR_CNVCMP_Enum;
|
|
|
|
/* ======================================================== INTSET ========================================================= */
|
|
/* ================================================ ADC INTSET WCINC [5..5] ================================================ */
|
|
typedef enum { /*!< ADC_INTSET_WCINC */
|
|
ADC_INTSET_WCINC_WCINCINT = 1, /*!< WCINCINT : Window comparitor voltage incursion interrupt. */
|
|
} ADC_INTSET_WCINC_Enum;
|
|
|
|
/* ================================================ ADC INTSET WCEXC [4..4] ================================================ */
|
|
typedef enum { /*!< ADC_INTSET_WCEXC */
|
|
ADC_INTSET_WCEXC_WCEXCINT = 1, /*!< WCEXCINT : Window comparitor voltage excursion interrupt. */
|
|
} ADC_INTSET_WCEXC_Enum;
|
|
|
|
/* ============================================== ADC INTSET FIFOOVR2 [3..3] =============================================== */
|
|
typedef enum { /*!< ADC_INTSET_FIFOOVR2 */
|
|
ADC_INTSET_FIFOOVR2_FIFOFULLINT = 1, /*!< FIFOFULLINT : FIFO 100 percent full interrupt. */
|
|
} ADC_INTSET_FIFOOVR2_Enum;
|
|
|
|
/* ============================================== ADC INTSET FIFOOVR1 [2..2] =============================================== */
|
|
typedef enum { /*!< ADC_INTSET_FIFOOVR1 */
|
|
ADC_INTSET_FIFOOVR1_FIFO75INT = 1, /*!< FIFO75INT : FIFO 75 percent full interrupt. */
|
|
} ADC_INTSET_FIFOOVR1_Enum;
|
|
|
|
/* =============================================== ADC INTSET SCNCMP [1..1] ================================================ */
|
|
typedef enum { /*!< ADC_INTSET_SCNCMP */
|
|
ADC_INTSET_SCNCMP_SCNCMPINT = 1, /*!< SCNCMPINT : ADC scan complete interrupt. */
|
|
} ADC_INTSET_SCNCMP_Enum;
|
|
|
|
/* =============================================== ADC INTSET CNVCMP [0..0] ================================================ */
|
|
typedef enum { /*!< ADC_INTSET_CNVCMP */
|
|
ADC_INTSET_CNVCMP_CNVCMPINT = 1, /*!< CNVCMPINT : ADC conversion complete interrupt. */
|
|
} ADC_INTSET_CNVCMP_Enum;
|
|
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ CLKGEN ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
/* ========================================================= CALXT ========================================================= */
|
|
/* ========================================================= CALRC ========================================================= */
|
|
/* ======================================================== ACALCTR ======================================================== */
|
|
/* ========================================================= OCTRL ========================================================= */
|
|
/* =============================================== CLKGEN OCTRL ACAL [8..10] =============================================== */
|
|
typedef enum { /*!< CLKGEN_OCTRL_ACAL */
|
|
CLKGEN_OCTRL_ACAL_DIS = 0, /*!< DIS : Disable Autocalibration */
|
|
CLKGEN_OCTRL_ACAL_1024SEC = 2, /*!< 1024SEC : Autocalibrate every 1024 seconds */
|
|
CLKGEN_OCTRL_ACAL_512SEC = 3, /*!< 512SEC : Autocalibrate every 512 seconds */
|
|
CLKGEN_OCTRL_ACAL_XTFREQ = 6, /*!< XTFREQ : Frequency measurement using XT */
|
|
CLKGEN_OCTRL_ACAL_EXTFREQ = 7, /*!< EXTFREQ : Frequency measurement using external clock */
|
|
} CLKGEN_OCTRL_ACAL_Enum;
|
|
|
|
/* =============================================== CLKGEN OCTRL OSEL [7..7] ================================================ */
|
|
typedef enum { /*!< CLKGEN_OCTRL_OSEL */
|
|
CLKGEN_OCTRL_OSEL_RTC_XT = 0, /*!< RTC_XT : RTC uses the XT */
|
|
CLKGEN_OCTRL_OSEL_RTC_LFRC = 1, /*!< RTC_LFRC : RTC uses the LFRC */
|
|
} CLKGEN_OCTRL_OSEL_Enum;
|
|
|
|
/* ================================================ CLKGEN OCTRL FOS [6..6] ================================================ */
|
|
typedef enum { /*!< CLKGEN_OCTRL_FOS */
|
|
CLKGEN_OCTRL_FOS_DIS = 0, /*!< DIS : Disable the oscillator switch on failure function */
|
|
CLKGEN_OCTRL_FOS_EN = 1, /*!< EN : Enable the oscillator switch on failure function */
|
|
} CLKGEN_OCTRL_FOS_Enum;
|
|
|
|
/* ============================================== CLKGEN OCTRL STOPRC [1..1] =============================================== */
|
|
typedef enum { /*!< CLKGEN_OCTRL_STOPRC */
|
|
CLKGEN_OCTRL_STOPRC_EN = 0, /*!< EN : Enable the LFRC Oscillator to drive the RTC */
|
|
CLKGEN_OCTRL_STOPRC_STOP = 1, /*!< STOP : Stop the LFRC Oscillator when driving the RTC */
|
|
} CLKGEN_OCTRL_STOPRC_Enum;
|
|
|
|
/* ============================================== CLKGEN OCTRL STOPXT [0..0] =============================================== */
|
|
typedef enum { /*!< CLKGEN_OCTRL_STOPXT */
|
|
CLKGEN_OCTRL_STOPXT_EN = 0, /*!< EN : Enable the XT Oscillator to drive the RTC */
|
|
CLKGEN_OCTRL_STOPXT_STOP = 1, /*!< STOP : Stop the XT Oscillator when driving the RTC */
|
|
} CLKGEN_OCTRL_STOPXT_Enum;
|
|
|
|
/* ======================================================== CLKOUT ========================================================= */
|
|
/* =============================================== CLKGEN CLKOUT CKEN [7..7] =============================================== */
|
|
typedef enum { /*!< CLKGEN_CLKOUT_CKEN */
|
|
CLKGEN_CLKOUT_CKEN_DIS = 0, /*!< DIS : Disable CLKOUT */
|
|
CLKGEN_CLKOUT_CKEN_EN = 1, /*!< EN : Enable CLKOUT */
|
|
} CLKGEN_CLKOUT_CKEN_Enum;
|
|
|
|
/* ============================================== CLKGEN CLKOUT CKSEL [0..5] =============================================== */
|
|
typedef enum { /*!< CLKGEN_CLKOUT_CKSEL */
|
|
CLKGEN_CLKOUT_CKSEL_LFRC = 0, /*!< LFRC : LFRC */
|
|
CLKGEN_CLKOUT_CKSEL_XT_DIV2 = 1, /*!< XT_DIV2 : XT / 2 */
|
|
CLKGEN_CLKOUT_CKSEL_XT_DIV4 = 2, /*!< XT_DIV4 : XT / 4 */
|
|
CLKGEN_CLKOUT_CKSEL_XT_DIV8 = 3, /*!< XT_DIV8 : XT / 8 */
|
|
CLKGEN_CLKOUT_CKSEL_XT_DIV16 = 4, /*!< XT_DIV16 : XT / 16 */
|
|
CLKGEN_CLKOUT_CKSEL_XT_DIV32 = 5, /*!< XT_DIV32 : XT / 32 */
|
|
CLKGEN_CLKOUT_CKSEL_RTC_1Hz = 16, /*!< RTC_1Hz : 1 Hz as selected in RTC */
|
|
CLKGEN_CLKOUT_CKSEL_XT_DIV2M = 22, /*!< XT_DIV2M : XT / 2^21 */
|
|
CLKGEN_CLKOUT_CKSEL_XT = 23, /*!< XT : XT */
|
|
CLKGEN_CLKOUT_CKSEL_CG_100Hz = 24, /*!< CG_100Hz : 100 Hz as selected in CLKGEN */
|
|
CLKGEN_CLKOUT_CKSEL_HFRC = 25, /*!< HFRC : HFRC */
|
|
CLKGEN_CLKOUT_CKSEL_HFRC_DIV2 = 26, /*!< HFRC_DIV2 : HFRC / 2 */
|
|
CLKGEN_CLKOUT_CKSEL_HFRC_DIV4 = 27, /*!< HFRC_DIV4 : HFRC / 4 */
|
|
CLKGEN_CLKOUT_CKSEL_HFRC_DIV8 = 28, /*!< HFRC_DIV8 : HFRC / 8 */
|
|
CLKGEN_CLKOUT_CKSEL_HFRC_DIV32 = 29, /*!< HFRC_DIV32 : HFRC / 32 */
|
|
CLKGEN_CLKOUT_CKSEL_HFRC_DIV64 = 30, /*!< HFRC_DIV64 : HFRC / 64 */
|
|
CLKGEN_CLKOUT_CKSEL_HFRC_DIV128 = 31, /*!< HFRC_DIV128 : HFRC / 128 */
|
|
CLKGEN_CLKOUT_CKSEL_HFRC_DIV256 = 32, /*!< HFRC_DIV256 : HFRC / 256 */
|
|
CLKGEN_CLKOUT_CKSEL_FLASH_CLK = 34, /*!< FLASH_CLK : Flash Clock */
|
|
CLKGEN_CLKOUT_CKSEL_LFRC_DIV2 = 35, /*!< LFRC_DIV2 : LFRC / 2 */
|
|
CLKGEN_CLKOUT_CKSEL_LFRC_DIV32 = 36, /*!< LFRC_DIV32 : LFRC / 32 */
|
|
CLKGEN_CLKOUT_CKSEL_LFRC_DIV512 = 37, /*!< LFRC_DIV512 : LFRC / 512 */
|
|
CLKGEN_CLKOUT_CKSEL_LFRC_DIV32K = 38, /*!< LFRC_DIV32K : LFRC / 32768 */
|
|
CLKGEN_CLKOUT_CKSEL_XT_DIV256 = 39, /*!< XT_DIV256 : XT / 256 */
|
|
CLKGEN_CLKOUT_CKSEL_XT_DIV8K = 40, /*!< XT_DIV8K : XT / 8192 */
|
|
CLKGEN_CLKOUT_CKSEL_XT_DIV64K = 41, /*!< XT_DIV64K : XT / 2^16 */
|
|
CLKGEN_CLKOUT_CKSEL_ULFRC_DIV16 = 42, /*!< ULFRC_DIV16 : Uncal LFRC / 16 */
|
|
CLKGEN_CLKOUT_CKSEL_ULFRC_DIV128 = 43, /*!< ULFRC_DIV128 : Uncal LFRC / 128 */
|
|
CLKGEN_CLKOUT_CKSEL_ULFRC_1Hz = 44, /*!< ULFRC_1Hz : Uncal LFRC / 1024 */
|
|
CLKGEN_CLKOUT_CKSEL_ULFRC_DIV4K = 45, /*!< ULFRC_DIV4K : Uncal LFRC / 4096 */
|
|
CLKGEN_CLKOUT_CKSEL_ULFRC_DIV1M = 46, /*!< ULFRC_DIV1M : Uncal LFRC / 2^20 */
|
|
CLKGEN_CLKOUT_CKSEL_HFRC_DIV64K = 47, /*!< HFRC_DIV64K : HFRC / 2^16 */
|
|
CLKGEN_CLKOUT_CKSEL_HFRC_DIV16M = 48, /*!< HFRC_DIV16M : HFRC / 2^24 */
|
|
CLKGEN_CLKOUT_CKSEL_LFRC_DIV2M = 49, /*!< LFRC_DIV2M : LFRC / 2^20 */
|
|
CLKGEN_CLKOUT_CKSEL_HFRCNE = 50, /*!< HFRCNE : HFRC (not autoenabled) */
|
|
CLKGEN_CLKOUT_CKSEL_HFRCNE_DIV8 = 51, /*!< HFRCNE_DIV8 : HFRC / 8 (not autoenabled) */
|
|
CLKGEN_CLKOUT_CKSEL_XTNE = 53, /*!< XTNE : XT (not autoenabled) */
|
|
CLKGEN_CLKOUT_CKSEL_XTNE_DIV16 = 54, /*!< XTNE_DIV16 : XT / 16 (not autoenabled) */
|
|
CLKGEN_CLKOUT_CKSEL_LFRCNE_DIV32 = 55, /*!< LFRCNE_DIV32 : LFRC / 32 (not autoenabled) */
|
|
CLKGEN_CLKOUT_CKSEL_LFRCNE = 57, /*!< LFRCNE : LFRC (not autoenabled) - Default for undefined values */
|
|
} CLKGEN_CLKOUT_CKSEL_Enum;
|
|
|
|
/* ======================================================== CLKKEY ========================================================= */
|
|
/* ============================================= CLKGEN CLKKEY CLKKEY [0..31] ============================================== */
|
|
typedef enum { /*!< CLKGEN_CLKKEY_CLKKEY */
|
|
CLKGEN_CLKKEY_CLKKEY_Key = 71, /*!< Key : Key */
|
|
} CLKGEN_CLKKEY_CLKKEY_Enum;
|
|
|
|
/* ========================================================= CCTRL ========================================================= */
|
|
/* ============================================== CLKGEN CCTRL MEMSEL [3..3] =============================================== */
|
|
typedef enum { /*!< CLKGEN_CCTRL_MEMSEL */
|
|
CLKGEN_CCTRL_MEMSEL_HFRC_DIV25 = 0, /*!< HFRC_DIV25 : Flash Clock is HFRC / 25 */
|
|
CLKGEN_CCTRL_MEMSEL_HFRC_DIV45 = 1, /*!< HFRC_DIV45 : Flash Clock is HFRC / 45 */
|
|
} CLKGEN_CCTRL_MEMSEL_Enum;
|
|
|
|
/* ============================================== CLKGEN CCTRL CORESEL [0..2] ============================================== */
|
|
typedef enum { /*!< CLKGEN_CCTRL_CORESEL */
|
|
CLKGEN_CCTRL_CORESEL_HFRC = 0, /*!< HFRC : Core Clock is HFRC */
|
|
CLKGEN_CCTRL_CORESEL_HFRC_DIV2 = 1, /*!< HFRC_DIV2 : Core Clock is HFRC / 2 */
|
|
CLKGEN_CCTRL_CORESEL_HFRC_DIV3 = 2, /*!< HFRC_DIV3 : Core Clock is HFRC / 3 */
|
|
CLKGEN_CCTRL_CORESEL_HFRC_DIV4 = 3, /*!< HFRC_DIV4 : Core Clock is HFRC / 4 */
|
|
CLKGEN_CCTRL_CORESEL_HFRC_DIV5 = 4, /*!< HFRC_DIV5 : Core Clock is HFRC / 5 */
|
|
CLKGEN_CCTRL_CORESEL_HFRC_DIV6 = 5, /*!< HFRC_DIV6 : Core Clock is HFRC / 6 */
|
|
CLKGEN_CCTRL_CORESEL_HFRC_DIV7 = 6, /*!< HFRC_DIV7 : Core Clock is HFRC / 7 */
|
|
CLKGEN_CCTRL_CORESEL_HFRC_DIV8 = 7, /*!< HFRC_DIV8 : Core Clock is HFRC / 8 */
|
|
} CLKGEN_CCTRL_CORESEL_Enum;
|
|
|
|
/* ======================================================== STATUS ========================================================= */
|
|
/* ========================================================= HFADJ ========================================================= */
|
|
/* ============================================ CLKGEN HFADJ HFWARMUP [19..19] ============================================= */
|
|
typedef enum { /*!< CLKGEN_HFADJ_HFWARMUP */
|
|
CLKGEN_HFADJ_HFWARMUP_1SEC = 0, /*!< 1SEC : Autoadjust XT warmup period = 1-2 seconds */
|
|
CLKGEN_HFADJ_HFWARMUP_2SEC = 1, /*!< 2SEC : Autoadjust XT warmup period = 2-4 seconds */
|
|
} CLKGEN_HFADJ_HFWARMUP_Enum;
|
|
|
|
/* ============================================== CLKGEN HFADJ HFADJCK [1..3] ============================================== */
|
|
typedef enum { /*!< CLKGEN_HFADJ_HFADJCK */
|
|
CLKGEN_HFADJ_HFADJCK_4SEC = 0, /*!< 4SEC : Autoadjust repeat period = 4 seconds */
|
|
CLKGEN_HFADJ_HFADJCK_16SEC = 1, /*!< 16SEC : Autoadjust repeat period = 16 seconds */
|
|
CLKGEN_HFADJ_HFADJCK_32SEC = 2, /*!< 32SEC : Autoadjust repeat period = 32 seconds */
|
|
CLKGEN_HFADJ_HFADJCK_64SEC = 3, /*!< 64SEC : Autoadjust repeat period = 64 seconds */
|
|
CLKGEN_HFADJ_HFADJCK_128SEC = 4, /*!< 128SEC : Autoadjust repeat period = 128 seconds */
|
|
CLKGEN_HFADJ_HFADJCK_256SEC = 5, /*!< 256SEC : Autoadjust repeat period = 256 seconds */
|
|
CLKGEN_HFADJ_HFADJCK_512SEC = 6, /*!< 512SEC : Autoadjust repeat period = 512 seconds */
|
|
CLKGEN_HFADJ_HFADJCK_1024SEC = 7, /*!< 1024SEC : Autoadjust repeat period = 1024 seconds */
|
|
} CLKGEN_HFADJ_HFADJCK_Enum;
|
|
|
|
/* ============================================== CLKGEN HFADJ HFADJEN [0..0] ============================================== */
|
|
typedef enum { /*!< CLKGEN_HFADJ_HFADJEN */
|
|
CLKGEN_HFADJ_HFADJEN_DIS = 0, /*!< DIS : Disable the HFRC adjustment */
|
|
CLKGEN_HFADJ_HFADJEN_EN = 1, /*!< EN : Enable the HFRC adjustment */
|
|
} CLKGEN_HFADJ_HFADJEN_Enum;
|
|
|
|
/* ========================================================= HFVAL ========================================================= */
|
|
/* ======================================================== CLOCKEN ======================================================== */
|
|
/* ======================================================== UARTEN ========================================================= */
|
|
/* ============================================== CLKGEN UARTEN UARTEN [0..0] ============================================== */
|
|
typedef enum { /*!< CLKGEN_UARTEN_UARTEN */
|
|
CLKGEN_UARTEN_UARTEN_DIS = 0, /*!< DIS : Disable the UART system clock */
|
|
CLKGEN_UARTEN_UARTEN_EN = 1, /*!< EN : Enable the UART system clock */
|
|
} CLKGEN_UARTEN_UARTEN_Enum;
|
|
|
|
/* ========================================================= INTEN ========================================================= */
|
|
/* ======================================================== INTSTAT ======================================================== */
|
|
/* ======================================================== INTCLR ========================================================= */
|
|
/* ======================================================== INTSET ========================================================= */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ CTIMER ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
/* ========================================================= TMR0 ========================================================== */
|
|
/* ======================================================== CMPRA0 ========================================================= */
|
|
/* ======================================================== CMPRB0 ========================================================= */
|
|
/* ========================================================= CTRL0 ========================================================= */
|
|
/* ============================================= CTIMER CTRL0 CTLINK0 [31..31] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL0_CTLINK0 */
|
|
CTIMER_CTRL0_CTLINK0_TWO_16BIT_TIMERS = 0, /*!< TWO_16BIT_TIMERS : Use A0/B0 timers as two independent 16-bit
|
|
timers (default). */
|
|
CTIMER_CTRL0_CTLINK0_32BIT_TIMER = 1, /*!< 32BIT_TIMER : Link A0/B0 timers into a single 32-bit timer. */
|
|
} CTIMER_CTRL0_CTLINK0_Enum;
|
|
|
|
/* ============================================ CTIMER CTRL0 TMRB0POL [28..28] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL0_TMRB0POL */
|
|
CTIMER_CTRL0_TMRB0POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINB0 pin is the same as the
|
|
timer output. */
|
|
CTIMER_CTRL0_TMRB0POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINB0 pin is the inverse of
|
|
the timer output. */
|
|
} CTIMER_CTRL0_TMRB0POL_Enum;
|
|
|
|
/* ============================================ CTIMER CTRL0 TMRB0CLR [27..27] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL0_TMRB0CLR */
|
|
CTIMER_CTRL0_TMRB0CLR_RUN = 0, /*!< RUN : Allow counter/timer B0 to run */
|
|
CTIMER_CTRL0_TMRB0CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer B0 at 0x0000. */
|
|
} CTIMER_CTRL0_TMRB0CLR_Enum;
|
|
|
|
/* ============================================= CTIMER CTRL0 TMRB0PE [26..26] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL0_TMRB0PE */
|
|
CTIMER_CTRL0_TMRB0PE_DIS = 0, /*!< DIS : Counter/Timer B holds the TMRPINB signal at the value
|
|
TMRB0POL. */
|
|
CTIMER_CTRL0_TMRB0PE_EN = 1, /*!< EN : Enable counter/timer B0 to generate a signal on TMRPINB. */
|
|
} CTIMER_CTRL0_TMRB0PE_Enum;
|
|
|
|
/* ============================================= CTIMER CTRL0 TMRB0IE [25..25] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL0_TMRB0IE */
|
|
CTIMER_CTRL0_TMRB0IE_DIS = 0, /*!< DIS : Disable counter/timer B0 from generating an interrupt. */
|
|
CTIMER_CTRL0_TMRB0IE_EN = 1, /*!< EN : Enable counter/timer B0 to generate an interrupt. */
|
|
} CTIMER_CTRL0_TMRB0IE_Enum;
|
|
|
|
/* ============================================= CTIMER CTRL0 TMRB0FN [22..24] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL0_TMRB0FN */
|
|
CTIMER_CTRL0_TMRB0FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
|
|
to CMPR0B0, stop. */
|
|
CTIMER_CTRL0_TMRB0FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
|
|
pulses). Count to CMPR0B0, restart. */
|
|
CTIMER_CTRL0_TMRB0FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B0, assert,
|
|
count to CMPR1B, deassert, stop. */
|
|
CTIMER_CTRL0_TMRB0FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0B0, assert, count
|
|
to CMPR1B0, deassert, restart. */
|
|
CTIMER_CTRL0_TMRB0FN_CONTINUOUS = 4, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */
|
|
} CTIMER_CTRL0_TMRB0FN_Enum;
|
|
|
|
/* ============================================ CTIMER CTRL0 TMRB0CLK [17..21] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL0_TMRB0CLK */
|
|
CTIMER_CTRL0_TMRB0CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINB. */
|
|
CTIMER_CTRL0_TMRB0CLK_HFRC = 1, /*!< HFRC : Clock source is the HFRC */
|
|
CTIMER_CTRL0_TMRB0CLK_HFRC_DIV8 = 2, /*!< HFRC_DIV8 : Clock source is HFRC / 8 */
|
|
CTIMER_CTRL0_TMRB0CLK_HFRC_DIV128 = 3, /*!< HFRC_DIV128 : Clock source is HFRC / 128 */
|
|
CTIMER_CTRL0_TMRB0CLK_HFRC_DIV512 = 4, /*!< HFRC_DIV512 : Clock source is HFRC / 512 */
|
|
CTIMER_CTRL0_TMRB0CLK_HFRC_DIV2K = 5, /*!< HFRC_DIV2K : Clock source is HFRC / 2048 */
|
|
CTIMER_CTRL0_TMRB0CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */
|
|
CTIMER_CTRL0_TMRB0CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */
|
|
CTIMER_CTRL0_TMRB0CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */
|
|
CTIMER_CTRL0_TMRB0CLK_XT_DIV256 = 9, /*!< XT_DIV256 : Clock source is XT / 256 */
|
|
CTIMER_CTRL0_TMRB0CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */
|
|
CTIMER_CTRL0_TMRB0CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */
|
|
CTIMER_CTRL0_TMRB0CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */
|
|
CTIMER_CTRL0_TMRB0CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC / 16K */
|
|
CTIMER_CTRL0_TMRB0CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */
|
|
CTIMER_CTRL0_TMRB0CLK_HCLK = 15, /*!< HCLK : Clock source is HCLK. */
|
|
CTIMER_CTRL0_TMRB0CLK_BUCKB = 16, /*!< BUCKB : Clock source is buck converter stream B. */
|
|
} CTIMER_CTRL0_TMRB0CLK_Enum;
|
|
|
|
/* ============================================= CTIMER CTRL0 TMRB0EN [16..16] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL0_TMRB0EN */
|
|
CTIMER_CTRL0_TMRB0EN_DIS = 0, /*!< DIS : Counter/Timer B0 Disable. */
|
|
CTIMER_CTRL0_TMRB0EN_EN = 1, /*!< EN : Counter/Timer B0 Enable. */
|
|
} CTIMER_CTRL0_TMRB0EN_Enum;
|
|
|
|
/* ============================================ CTIMER CTRL0 TMRA0POL [12..12] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL0_TMRA0POL */
|
|
CTIMER_CTRL0_TMRA0POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINA0 pin is the same as the
|
|
timer output. */
|
|
CTIMER_CTRL0_TMRA0POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINA0 pin is the inverse of
|
|
the timer output. */
|
|
} CTIMER_CTRL0_TMRA0POL_Enum;
|
|
|
|
/* ============================================ CTIMER CTRL0 TMRA0CLR [11..11] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL0_TMRA0CLR */
|
|
CTIMER_CTRL0_TMRA0CLR_RUN = 0, /*!< RUN : Allow counter/timer A0 to run */
|
|
CTIMER_CTRL0_TMRA0CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer A0 at 0x0000. */
|
|
} CTIMER_CTRL0_TMRA0CLR_Enum;
|
|
|
|
/* ============================================= CTIMER CTRL0 TMRA0PE [10..10] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL0_TMRA0PE */
|
|
CTIMER_CTRL0_TMRA0PE_DIS = 0, /*!< DIS : Counter/Timer A holds the TMRPINA signal at the value
|
|
TMRA0POL. */
|
|
CTIMER_CTRL0_TMRA0PE_EN = 1, /*!< EN : Enable counter/timer B0 to generate a signal on TMRPINB. */
|
|
} CTIMER_CTRL0_TMRA0PE_Enum;
|
|
|
|
/* ============================================== CTIMER CTRL0 TMRA0IE [9..9] ============================================== */
|
|
typedef enum { /*!< CTIMER_CTRL0_TMRA0IE */
|
|
CTIMER_CTRL0_TMRA0IE_DIS = 0, /*!< DIS : Disable counter/timer A0 from generating an interrupt. */
|
|
CTIMER_CTRL0_TMRA0IE_EN = 1, /*!< EN : Enable counter/timer A0 to generate an interrupt. */
|
|
} CTIMER_CTRL0_TMRA0IE_Enum;
|
|
|
|
/* ============================================== CTIMER CTRL0 TMRA0FN [6..8] ============================================== */
|
|
typedef enum { /*!< CTIMER_CTRL0_TMRA0FN */
|
|
CTIMER_CTRL0_TMRA0FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
|
|
to CMPR0A0, stop. */
|
|
CTIMER_CTRL0_TMRA0FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
|
|
pulses). Count to CMPR0A0, restart. */
|
|
CTIMER_CTRL0_TMRA0FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A0, assert,
|
|
count to CMPR1B, deassert, stop. */
|
|
CTIMER_CTRL0_TMRA0FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0A0, assert, count
|
|
to CMPR1A0, deassert, restart. */
|
|
CTIMER_CTRL0_TMRA0FN_CONTINUOUS = 4, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */
|
|
} CTIMER_CTRL0_TMRA0FN_Enum;
|
|
|
|
/* ============================================= CTIMER CTRL0 TMRA0CLK [1..5] ============================================== */
|
|
typedef enum { /*!< CTIMER_CTRL0_TMRA0CLK */
|
|
CTIMER_CTRL0_TMRA0CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINA. */
|
|
CTIMER_CTRL0_TMRA0CLK_HFRC = 1, /*!< HFRC : Clock source is the HFRC */
|
|
CTIMER_CTRL0_TMRA0CLK_HFRC_DIV8 = 2, /*!< HFRC_DIV8 : Clock source is HFRC / 8 */
|
|
CTIMER_CTRL0_TMRA0CLK_HFRC_DIV128 = 3, /*!< HFRC_DIV128 : Clock source is HFRC / 128 */
|
|
CTIMER_CTRL0_TMRA0CLK_HFRC_DIV512 = 4, /*!< HFRC_DIV512 : Clock source is HFRC / 512 */
|
|
CTIMER_CTRL0_TMRA0CLK_HFRC_DIV2K = 5, /*!< HFRC_DIV2K : Clock source is HFRC / 2048 */
|
|
CTIMER_CTRL0_TMRA0CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */
|
|
CTIMER_CTRL0_TMRA0CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */
|
|
CTIMER_CTRL0_TMRA0CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */
|
|
CTIMER_CTRL0_TMRA0CLK_XT_DIV256 = 9, /*!< XT_DIV256 : Clock source is XT / 256 */
|
|
CTIMER_CTRL0_TMRA0CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */
|
|
CTIMER_CTRL0_TMRA0CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */
|
|
CTIMER_CTRL0_TMRA0CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */
|
|
CTIMER_CTRL0_TMRA0CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC / 16K */
|
|
CTIMER_CTRL0_TMRA0CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */
|
|
CTIMER_CTRL0_TMRA0CLK_HCLK = 15, /*!< HCLK : Clock source is HCLK. */
|
|
CTIMER_CTRL0_TMRA0CLK_BUCKA = 16, /*!< BUCKA : Clock source is buck converter stream A. */
|
|
} CTIMER_CTRL0_TMRA0CLK_Enum;
|
|
|
|
/* ============================================== CTIMER CTRL0 TMRA0EN [0..0] ============================================== */
|
|
typedef enum { /*!< CTIMER_CTRL0_TMRA0EN */
|
|
CTIMER_CTRL0_TMRA0EN_DIS = 0, /*!< DIS : Counter/Timer A0 Disable. */
|
|
CTIMER_CTRL0_TMRA0EN_EN = 1, /*!< EN : Counter/Timer A0 Enable. */
|
|
} CTIMER_CTRL0_TMRA0EN_Enum;
|
|
|
|
/* ========================================================= TMR1 ========================================================== */
|
|
/* ======================================================== CMPRA1 ========================================================= */
|
|
/* ======================================================== CMPRB1 ========================================================= */
|
|
/* ========================================================= CTRL1 ========================================================= */
|
|
/* ============================================= CTIMER CTRL1 CTLINK1 [31..31] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL1_CTLINK1 */
|
|
CTIMER_CTRL1_CTLINK1_TWO_16BIT_TIMERS = 0, /*!< TWO_16BIT_TIMERS : Use A0/B0 timers as two independent 16-bit
|
|
timers (default). */
|
|
CTIMER_CTRL1_CTLINK1_32BIT_TIMER = 1, /*!< 32BIT_TIMER : Link A1/B1 timers into a single 32-bit timer. */
|
|
} CTIMER_CTRL1_CTLINK1_Enum;
|
|
|
|
/* ============================================ CTIMER CTRL1 TMRB1POL [28..28] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL1_TMRB1POL */
|
|
CTIMER_CTRL1_TMRB1POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINB1 pin is the same as the
|
|
timer output. */
|
|
CTIMER_CTRL1_TMRB1POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINB1 pin is the inverse of
|
|
the timer output. */
|
|
} CTIMER_CTRL1_TMRB1POL_Enum;
|
|
|
|
/* ============================================ CTIMER CTRL1 TMRB1CLR [27..27] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL1_TMRB1CLR */
|
|
CTIMER_CTRL1_TMRB1CLR_RUN = 0, /*!< RUN : Allow counter/timer B1 to run */
|
|
CTIMER_CTRL1_TMRB1CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer B1 at 0x0000. */
|
|
} CTIMER_CTRL1_TMRB1CLR_Enum;
|
|
|
|
/* ============================================= CTIMER CTRL1 TMRB1PE [26..26] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL1_TMRB1PE */
|
|
CTIMER_CTRL1_TMRB1PE_DIS = 0, /*!< DIS : Counter/Timer B holds the TMRPINB signal at the value
|
|
TMRB1POL. */
|
|
CTIMER_CTRL1_TMRB1PE_EN = 1, /*!< EN : Enable counter/timer B1 to generate a signal on TMRPINB. */
|
|
} CTIMER_CTRL1_TMRB1PE_Enum;
|
|
|
|
/* ============================================= CTIMER CTRL1 TMRB1IE [25..25] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL1_TMRB1IE */
|
|
CTIMER_CTRL1_TMRB1IE_DIS = 0, /*!< DIS : Disable counter/timer B1 from generating an interrupt. */
|
|
CTIMER_CTRL1_TMRB1IE_EN = 1, /*!< EN : Enable counter/timer B1 to generate an interrupt. */
|
|
} CTIMER_CTRL1_TMRB1IE_Enum;
|
|
|
|
/* ============================================= CTIMER CTRL1 TMRB1FN [22..24] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL1_TMRB1FN */
|
|
CTIMER_CTRL1_TMRB1FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
|
|
to CMPR0B1, stop. */
|
|
CTIMER_CTRL1_TMRB1FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
|
|
pulses). Count to CMPR0B1, restart. */
|
|
CTIMER_CTRL1_TMRB1FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B1, assert,
|
|
count to CMPR1B, deassert, stop. */
|
|
CTIMER_CTRL1_TMRB1FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0B1, assert, count
|
|
to CMPR1B1, deassert, restart. */
|
|
CTIMER_CTRL1_TMRB1FN_CONTINUOUS = 4, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */
|
|
} CTIMER_CTRL1_TMRB1FN_Enum;
|
|
|
|
/* ============================================ CTIMER CTRL1 TMRB1CLK [17..21] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL1_TMRB1CLK */
|
|
CTIMER_CTRL1_TMRB1CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINB. */
|
|
CTIMER_CTRL1_TMRB1CLK_HFRC = 1, /*!< HFRC : Clock source is the HFRC */
|
|
CTIMER_CTRL1_TMRB1CLK_HFRC_DIV8 = 2, /*!< HFRC_DIV8 : Clock source is HFRC / 8 */
|
|
CTIMER_CTRL1_TMRB1CLK_HFRC_DIV128 = 3, /*!< HFRC_DIV128 : Clock source is HFRC / 128 */
|
|
CTIMER_CTRL1_TMRB1CLK_HFRC_DIV512 = 4, /*!< HFRC_DIV512 : Clock source is HFRC / 512 */
|
|
CTIMER_CTRL1_TMRB1CLK_HFRC_DIV2K = 5, /*!< HFRC_DIV2K : Clock source is HFRC / 2048 */
|
|
CTIMER_CTRL1_TMRB1CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */
|
|
CTIMER_CTRL1_TMRB1CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */
|
|
CTIMER_CTRL1_TMRB1CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */
|
|
CTIMER_CTRL1_TMRB1CLK_XT_DIV256 = 9, /*!< XT_DIV256 : Clock source is XT / 256 */
|
|
CTIMER_CTRL1_TMRB1CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */
|
|
CTIMER_CTRL1_TMRB1CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */
|
|
CTIMER_CTRL1_TMRB1CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */
|
|
CTIMER_CTRL1_TMRB1CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC / 16K */
|
|
CTIMER_CTRL1_TMRB1CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */
|
|
CTIMER_CTRL1_TMRB1CLK_HCLK = 15, /*!< HCLK : Clock source is HCLK. */
|
|
CTIMER_CTRL1_TMRB1CLK_BUCKB = 16, /*!< BUCKB : Clock source is buck converter stream B. */
|
|
} CTIMER_CTRL1_TMRB1CLK_Enum;
|
|
|
|
/* ============================================= CTIMER CTRL1 TMRB1EN [16..16] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL1_TMRB1EN */
|
|
CTIMER_CTRL1_TMRB1EN_DIS = 0, /*!< DIS : Counter/Timer B1 Disable. */
|
|
CTIMER_CTRL1_TMRB1EN_EN = 1, /*!< EN : Counter/Timer B1 Enable. */
|
|
} CTIMER_CTRL1_TMRB1EN_Enum;
|
|
|
|
/* ============================================ CTIMER CTRL1 TMRA1POL [12..12] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL1_TMRA1POL */
|
|
CTIMER_CTRL1_TMRA1POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINA1 pin is the same as the
|
|
timer output. */
|
|
CTIMER_CTRL1_TMRA1POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINA1 pin is the inverse of
|
|
the timer output. */
|
|
} CTIMER_CTRL1_TMRA1POL_Enum;
|
|
|
|
/* ============================================ CTIMER CTRL1 TMRA1CLR [11..11] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL1_TMRA1CLR */
|
|
CTIMER_CTRL1_TMRA1CLR_RUN = 0, /*!< RUN : Allow counter/timer A1 to run */
|
|
CTIMER_CTRL1_TMRA1CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer A1 at 0x0000. */
|
|
} CTIMER_CTRL1_TMRA1CLR_Enum;
|
|
|
|
/* ============================================= CTIMER CTRL1 TMRA1PE [10..10] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL1_TMRA1PE */
|
|
CTIMER_CTRL1_TMRA1PE_DIS = 0, /*!< DIS : Counter/Timer A holds the TMRPINA signal at the value
|
|
TMRA1POL. */
|
|
CTIMER_CTRL1_TMRA1PE_EN = 1, /*!< EN : Enable counter/timer A1 to generate a signal on TMRPINA. */
|
|
} CTIMER_CTRL1_TMRA1PE_Enum;
|
|
|
|
/* ============================================== CTIMER CTRL1 TMRA1IE [9..9] ============================================== */
|
|
typedef enum { /*!< CTIMER_CTRL1_TMRA1IE */
|
|
CTIMER_CTRL1_TMRA1IE_DIS = 0, /*!< DIS : Disable counter/timer A1 from generating an interrupt. */
|
|
CTIMER_CTRL1_TMRA1IE_EN = 1, /*!< EN : Enable counter/timer A1 to generate an interrupt. */
|
|
} CTIMER_CTRL1_TMRA1IE_Enum;
|
|
|
|
/* ============================================== CTIMER CTRL1 TMRA1FN [6..8] ============================================== */
|
|
typedef enum { /*!< CTIMER_CTRL1_TMRA1FN */
|
|
CTIMER_CTRL1_TMRA1FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
|
|
to CMPR0A1, stop. */
|
|
CTIMER_CTRL1_TMRA1FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
|
|
pulses). Count to CMPR0A1, restart. */
|
|
CTIMER_CTRL1_TMRA1FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A1, assert,
|
|
count to CMPR1B, deassert, stop. */
|
|
CTIMER_CTRL1_TMRA1FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0A1, assert, count
|
|
to CMPR1A1, deassert, restart. */
|
|
CTIMER_CTRL1_TMRA1FN_CONTINUOUS = 4, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */
|
|
} CTIMER_CTRL1_TMRA1FN_Enum;
|
|
|
|
/* ============================================= CTIMER CTRL1 TMRA1CLK [1..5] ============================================== */
|
|
typedef enum { /*!< CTIMER_CTRL1_TMRA1CLK */
|
|
CTIMER_CTRL1_TMRA1CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINA. */
|
|
CTIMER_CTRL1_TMRA1CLK_HFRC = 1, /*!< HFRC : Clock source is the HFRC */
|
|
CTIMER_CTRL1_TMRA1CLK_HFRC_DIV8 = 2, /*!< HFRC_DIV8 : Clock source is the HFRC / 8 */
|
|
CTIMER_CTRL1_TMRA1CLK_HFRC_DIV128 = 3, /*!< HFRC_DIV128 : Clock source is HFRC / 128 */
|
|
CTIMER_CTRL1_TMRA1CLK_HFRC_DIV512 = 4, /*!< HFRC_DIV512 : Clock source is HFRC / 512 */
|
|
CTIMER_CTRL1_TMRA1CLK_HFRC_DIV2K = 5, /*!< HFRC_DIV2K : Clock source is HFRC / 2048 */
|
|
CTIMER_CTRL1_TMRA1CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */
|
|
CTIMER_CTRL1_TMRA1CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */
|
|
CTIMER_CTRL1_TMRA1CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */
|
|
CTIMER_CTRL1_TMRA1CLK_XT_DIV256 = 9, /*!< XT_DIV256 : Clock source is XT / 256 */
|
|
CTIMER_CTRL1_TMRA1CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */
|
|
CTIMER_CTRL1_TMRA1CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */
|
|
CTIMER_CTRL1_TMRA1CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */
|
|
CTIMER_CTRL1_TMRA1CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC / 16K */
|
|
CTIMER_CTRL1_TMRA1CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */
|
|
CTIMER_CTRL1_TMRA1CLK_HCLK = 15, /*!< HCLK : Clock source is HCLK. */
|
|
CTIMER_CTRL1_TMRA1CLK_BUCKA = 16, /*!< BUCKA : Clock source is buck converter stream A. */
|
|
} CTIMER_CTRL1_TMRA1CLK_Enum;
|
|
|
|
/* ============================================== CTIMER CTRL1 TMRA1EN [0..0] ============================================== */
|
|
typedef enum { /*!< CTIMER_CTRL1_TMRA1EN */
|
|
CTIMER_CTRL1_TMRA1EN_DIS = 0, /*!< DIS : Counter/Timer A1 Disable. */
|
|
CTIMER_CTRL1_TMRA1EN_EN = 1, /*!< EN : Counter/Timer A1 Enable. */
|
|
} CTIMER_CTRL1_TMRA1EN_Enum;
|
|
|
|
/* ========================================================= TMR2 ========================================================== */
|
|
/* ======================================================== CMPRA2 ========================================================= */
|
|
/* ======================================================== CMPRB2 ========================================================= */
|
|
/* ========================================================= CTRL2 ========================================================= */
|
|
/* ============================================= CTIMER CTRL2 CTLINK2 [31..31] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL2_CTLINK2 */
|
|
CTIMER_CTRL2_CTLINK2_TWO_16BIT_TIMERS = 0, /*!< TWO_16BIT_TIMERS : Use A0/B0 timers as two independent 16-bit
|
|
timers (default). */
|
|
CTIMER_CTRL2_CTLINK2_32BIT_TIMER = 1, /*!< 32BIT_TIMER : Link A2/B2 timers into a single 32-bit timer. */
|
|
} CTIMER_CTRL2_CTLINK2_Enum;
|
|
|
|
/* ============================================ CTIMER CTRL2 TMRB2POL [28..28] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL2_TMRB2POL */
|
|
CTIMER_CTRL2_TMRB2POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINB2 pin is the same as the
|
|
timer output. */
|
|
CTIMER_CTRL2_TMRB2POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINB2 pin is the inverse of
|
|
the timer output. */
|
|
} CTIMER_CTRL2_TMRB2POL_Enum;
|
|
|
|
/* ============================================ CTIMER CTRL2 TMRB2CLR [27..27] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL2_TMRB2CLR */
|
|
CTIMER_CTRL2_TMRB2CLR_RUN = 0, /*!< RUN : Allow counter/timer B2 to run */
|
|
CTIMER_CTRL2_TMRB2CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer B2 at 0x0000. */
|
|
} CTIMER_CTRL2_TMRB2CLR_Enum;
|
|
|
|
/* ============================================= CTIMER CTRL2 TMRB2PE [26..26] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL2_TMRB2PE */
|
|
CTIMER_CTRL2_TMRB2PE_DIS = 0, /*!< DIS : Counter/Timer B holds the TMRPINB signal at the value
|
|
TMRB2POL. */
|
|
CTIMER_CTRL2_TMRB2PE_EN = 1, /*!< EN : Enable counter/timer B2 to generate a signal on TMRPINB. */
|
|
} CTIMER_CTRL2_TMRB2PE_Enum;
|
|
|
|
/* ============================================= CTIMER CTRL2 TMRB2IE [25..25] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL2_TMRB2IE */
|
|
CTIMER_CTRL2_TMRB2IE_DIS = 0, /*!< DIS : Disable counter/timer B2 from generating an interrupt. */
|
|
CTIMER_CTRL2_TMRB2IE_EN = 1, /*!< EN : Enable counter/timer B2 to generate an interrupt. */
|
|
} CTIMER_CTRL2_TMRB2IE_Enum;
|
|
|
|
/* ============================================= CTIMER CTRL2 TMRB2FN [22..24] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL2_TMRB2FN */
|
|
CTIMER_CTRL2_TMRB2FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
|
|
to CMPR0B2, stop. */
|
|
CTIMER_CTRL2_TMRB2FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
|
|
pulses). Count to CMPR0B2, restart. */
|
|
CTIMER_CTRL2_TMRB2FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B2, assert,
|
|
count to CMPR1B, deassert, stop. */
|
|
CTIMER_CTRL2_TMRB2FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0B2, assert, count
|
|
to CMPR1B2, deassert, restart. */
|
|
CTIMER_CTRL2_TMRB2FN_CONTINUOUS = 4, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */
|
|
} CTIMER_CTRL2_TMRB2FN_Enum;
|
|
|
|
/* ============================================ CTIMER CTRL2 TMRB2CLK [17..21] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL2_TMRB2CLK */
|
|
CTIMER_CTRL2_TMRB2CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINB. */
|
|
CTIMER_CTRL2_TMRB2CLK_HFRC = 1, /*!< HFRC : Clock source is the HFRC */
|
|
CTIMER_CTRL2_TMRB2CLK_HFRC_DIV8 = 2, /*!< HFRC_DIV8 : Clock source is HFRC / 8 */
|
|
CTIMER_CTRL2_TMRB2CLK_HFRC_DIV128 = 3, /*!< HFRC_DIV128 : Clock source is HFRC / 128 */
|
|
CTIMER_CTRL2_TMRB2CLK_HFRC_DIV512 = 4, /*!< HFRC_DIV512 : Clock source is HFRC / 512 */
|
|
CTIMER_CTRL2_TMRB2CLK_HFRC_DIV2K = 5, /*!< HFRC_DIV2K : Clock source is HFRC / 2048 */
|
|
CTIMER_CTRL2_TMRB2CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */
|
|
CTIMER_CTRL2_TMRB2CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */
|
|
CTIMER_CTRL2_TMRB2CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */
|
|
CTIMER_CTRL2_TMRB2CLK_XT_DIV256 = 9, /*!< XT_DIV256 : Clock source is XT / 256 */
|
|
CTIMER_CTRL2_TMRB2CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */
|
|
CTIMER_CTRL2_TMRB2CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */
|
|
CTIMER_CTRL2_TMRB2CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */
|
|
CTIMER_CTRL2_TMRB2CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC / 16K */
|
|
CTIMER_CTRL2_TMRB2CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */
|
|
CTIMER_CTRL2_TMRB2CLK_HCLK = 15, /*!< HCLK : Clock source is HCLK. */
|
|
CTIMER_CTRL2_TMRB2CLK_BUCKA = 16, /*!< BUCKA : Clock source is buck converter stream A. */
|
|
} CTIMER_CTRL2_TMRB2CLK_Enum;
|
|
|
|
/* ============================================= CTIMER CTRL2 TMRB2EN [16..16] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL2_TMRB2EN */
|
|
CTIMER_CTRL2_TMRB2EN_DIS = 0, /*!< DIS : Counter/Timer B2 Disable. */
|
|
CTIMER_CTRL2_TMRB2EN_EN = 1, /*!< EN : Counter/Timer B2 Enable. */
|
|
} CTIMER_CTRL2_TMRB2EN_Enum;
|
|
|
|
/* ============================================ CTIMER CTRL2 TMRA2POL [12..12] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL2_TMRA2POL */
|
|
CTIMER_CTRL2_TMRA2POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINA2 pin is the same as the
|
|
timer output. */
|
|
CTIMER_CTRL2_TMRA2POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINA2 pin is the inverse of
|
|
the timer output. */
|
|
} CTIMER_CTRL2_TMRA2POL_Enum;
|
|
|
|
/* ============================================ CTIMER CTRL2 TMRA2CLR [11..11] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL2_TMRA2CLR */
|
|
CTIMER_CTRL2_TMRA2CLR_RUN = 0, /*!< RUN : Allow counter/timer A2 to run */
|
|
CTIMER_CTRL2_TMRA2CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer A2 at 0x0000. */
|
|
} CTIMER_CTRL2_TMRA2CLR_Enum;
|
|
|
|
/* ============================================= CTIMER CTRL2 TMRA2PE [10..10] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL2_TMRA2PE */
|
|
CTIMER_CTRL2_TMRA2PE_DIS = 0, /*!< DIS : Counter/Timer A holds the TMRPINA signal at the value
|
|
TMRA2POL. */
|
|
CTIMER_CTRL2_TMRA2PE_EN = 1, /*!< EN : Enable counter/timer A2 to generate a signal on TMRPINA. */
|
|
} CTIMER_CTRL2_TMRA2PE_Enum;
|
|
|
|
/* ============================================== CTIMER CTRL2 TMRA2IE [9..9] ============================================== */
|
|
typedef enum { /*!< CTIMER_CTRL2_TMRA2IE */
|
|
CTIMER_CTRL2_TMRA2IE_DIS = 0, /*!< DIS : Disable counter/timer A2 from generating an interrupt. */
|
|
CTIMER_CTRL2_TMRA2IE_EN = 1, /*!< EN : Enable counter/timer A2 to generate an interrupt. */
|
|
} CTIMER_CTRL2_TMRA2IE_Enum;
|
|
|
|
/* ============================================== CTIMER CTRL2 TMRA2FN [6..8] ============================================== */
|
|
typedef enum { /*!< CTIMER_CTRL2_TMRA2FN */
|
|
CTIMER_CTRL2_TMRA2FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
|
|
to CMPR0A2, stop. */
|
|
CTIMER_CTRL2_TMRA2FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
|
|
pulses). Count to CMPR0A2, restart. */
|
|
CTIMER_CTRL2_TMRA2FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A2, assert,
|
|
count to CMPR1B, deassert, stop. */
|
|
CTIMER_CTRL2_TMRA2FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0A2, assert, count
|
|
to CMPR1A2, deassert, restart. */
|
|
CTIMER_CTRL2_TMRA2FN_CONTINUOUS = 4, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */
|
|
} CTIMER_CTRL2_TMRA2FN_Enum;
|
|
|
|
/* ============================================= CTIMER CTRL2 TMRA2CLK [1..5] ============================================== */
|
|
typedef enum { /*!< CTIMER_CTRL2_TMRA2CLK */
|
|
CTIMER_CTRL2_TMRA2CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINA. */
|
|
CTIMER_CTRL2_TMRA2CLK_HFRC = 1, /*!< HFRC : Clock source is the HFRC */
|
|
CTIMER_CTRL2_TMRA2CLK_HFRC_DIV8 = 2, /*!< HFRC_DIV8 : Clock source is HFRC / 8 */
|
|
CTIMER_CTRL2_TMRA2CLK_HFRC_DIV128 = 3, /*!< HFRC_DIV128 : Clock source is HFRC / 128 */
|
|
CTIMER_CTRL2_TMRA2CLK_HFRC_DIV512 = 4, /*!< HFRC_DIV512 : Clock source is HFRC / 512 */
|
|
CTIMER_CTRL2_TMRA2CLK_HFRC_DIV2K = 5, /*!< HFRC_DIV2K : Clock source is HFRC / 2048 */
|
|
CTIMER_CTRL2_TMRA2CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */
|
|
CTIMER_CTRL2_TMRA2CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */
|
|
CTIMER_CTRL2_TMRA2CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */
|
|
CTIMER_CTRL2_TMRA2CLK_XT_DIV256 = 9, /*!< XT_DIV256 : Clock source is XT / 256 */
|
|
CTIMER_CTRL2_TMRA2CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */
|
|
CTIMER_CTRL2_TMRA2CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */
|
|
CTIMER_CTRL2_TMRA2CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */
|
|
CTIMER_CTRL2_TMRA2CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC / 16K */
|
|
CTIMER_CTRL2_TMRA2CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */
|
|
CTIMER_CTRL2_TMRA2CLK_HCLK = 15, /*!< HCLK : Clock source is HCLK. */
|
|
CTIMER_CTRL2_TMRA2CLK_BUCKB = 16, /*!< BUCKB : Clock source is buck converter stream B. */
|
|
} CTIMER_CTRL2_TMRA2CLK_Enum;
|
|
|
|
/* ============================================== CTIMER CTRL2 TMRA2EN [0..0] ============================================== */
|
|
typedef enum { /*!< CTIMER_CTRL2_TMRA2EN */
|
|
CTIMER_CTRL2_TMRA2EN_DIS = 0, /*!< DIS : Counter/Timer A2 Disable. */
|
|
CTIMER_CTRL2_TMRA2EN_EN = 1, /*!< EN : Counter/Timer A2 Enable. */
|
|
} CTIMER_CTRL2_TMRA2EN_Enum;
|
|
|
|
/* ========================================================= TMR3 ========================================================== */
|
|
/* ======================================================== CMPRA3 ========================================================= */
|
|
/* ======================================================== CMPRB3 ========================================================= */
|
|
/* ========================================================= CTRL3 ========================================================= */
|
|
/* ============================================= CTIMER CTRL3 CTLINK3 [31..31] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL3_CTLINK3 */
|
|
CTIMER_CTRL3_CTLINK3_TWO_16BIT_TIMERS = 0, /*!< TWO_16BIT_TIMERS : Use A0/B0 timers as two independent 16-bit
|
|
timers (default). */
|
|
CTIMER_CTRL3_CTLINK3_32BIT_TIMER = 1, /*!< 32BIT_TIMER : Link A3/B3 timers into a single 32-bit timer. */
|
|
} CTIMER_CTRL3_CTLINK3_Enum;
|
|
|
|
/* ============================================ CTIMER CTRL3 TMRB3POL [28..28] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL3_TMRB3POL */
|
|
CTIMER_CTRL3_TMRB3POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINB3 pin is the same as the
|
|
timer output. */
|
|
CTIMER_CTRL3_TMRB3POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINB3 pin is the inverse of
|
|
the timer output. */
|
|
} CTIMER_CTRL3_TMRB3POL_Enum;
|
|
|
|
/* ============================================ CTIMER CTRL3 TMRB3CLR [27..27] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL3_TMRB3CLR */
|
|
CTIMER_CTRL3_TMRB3CLR_RUN = 0, /*!< RUN : Allow counter/timer B3 to run. */
|
|
CTIMER_CTRL3_TMRB3CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer B3 at 0x0000. */
|
|
} CTIMER_CTRL3_TMRB3CLR_Enum;
|
|
|
|
/* ============================================= CTIMER CTRL3 TMRB3PE [26..26] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL3_TMRB3PE */
|
|
CTIMER_CTRL3_TMRB3PE_DIS = 0, /*!< DIS : Counter/Timer B holds the TMRPINB signal at the value
|
|
TMRB3POL. */
|
|
CTIMER_CTRL3_TMRB3PE_EN = 1, /*!< EN : Enable counter/timer B3 to generate a signal on TMRPINB. */
|
|
} CTIMER_CTRL3_TMRB3PE_Enum;
|
|
|
|
/* ============================================= CTIMER CTRL3 TMRB3IE [25..25] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL3_TMRB3IE */
|
|
CTIMER_CTRL3_TMRB3IE_DIS = 0, /*!< DIS : Disable counter/timer B3 from generating an interrupt. */
|
|
CTIMER_CTRL3_TMRB3IE_EN = 1, /*!< EN : Enable counter/timer B3 to generate an interrupt. */
|
|
} CTIMER_CTRL3_TMRB3IE_Enum;
|
|
|
|
/* ============================================= CTIMER CTRL3 TMRB3FN [22..24] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL3_TMRB3FN */
|
|
CTIMER_CTRL3_TMRB3FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
|
|
to CMPR0B3, stop. */
|
|
CTIMER_CTRL3_TMRB3FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
|
|
pulses). Count to CMPR0B3, restart. */
|
|
CTIMER_CTRL3_TMRB3FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B3, assert,
|
|
count to CMPR1B, deassert, stop. */
|
|
CTIMER_CTRL3_TMRB3FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0B3, assert, count
|
|
to CMPR1B3, deassert, restart. */
|
|
CTIMER_CTRL3_TMRB3FN_CONTINUOUS = 4, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */
|
|
} CTIMER_CTRL3_TMRB3FN_Enum;
|
|
|
|
/* ============================================ CTIMER CTRL3 TMRB3CLK [17..21] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL3_TMRB3CLK */
|
|
CTIMER_CTRL3_TMRB3CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINB. */
|
|
CTIMER_CTRL3_TMRB3CLK_HFRC = 1, /*!< HFRC : Clock source is the HFRC */
|
|
CTIMER_CTRL3_TMRB3CLK_HFRC_DIV8 = 2, /*!< HFRC_DIV8 : Clock source is HFRC / 8 */
|
|
CTIMER_CTRL3_TMRB3CLK_HFRC_DIV128 = 3, /*!< HFRC_DIV128 : Clock source is HFRC / 128 */
|
|
CTIMER_CTRL3_TMRB3CLK_HFRC_DIV512 = 4, /*!< HFRC_DIV512 : Clock source is HFRC / 512 */
|
|
CTIMER_CTRL3_TMRB3CLK_HFRC_DIV2K = 5, /*!< HFRC_DIV2K : Clock source is HFRC / 2048 */
|
|
CTIMER_CTRL3_TMRB3CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */
|
|
CTIMER_CTRL3_TMRB3CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */
|
|
CTIMER_CTRL3_TMRB3CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */
|
|
CTIMER_CTRL3_TMRB3CLK_XT_DIV256 = 9, /*!< XT_DIV256 : Clock source is XT / 256 */
|
|
CTIMER_CTRL3_TMRB3CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */
|
|
CTIMER_CTRL3_TMRB3CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */
|
|
CTIMER_CTRL3_TMRB3CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */
|
|
CTIMER_CTRL3_TMRB3CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC / 16K */
|
|
CTIMER_CTRL3_TMRB3CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */
|
|
CTIMER_CTRL3_TMRB3CLK_HCLK = 15, /*!< HCLK : Clock source is HCLK. */
|
|
CTIMER_CTRL3_TMRB3CLK_BUCKA = 16, /*!< BUCKA : Clock source is buck converter stream A. */
|
|
} CTIMER_CTRL3_TMRB3CLK_Enum;
|
|
|
|
/* ============================================= CTIMER CTRL3 TMRB3EN [16..16] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL3_TMRB3EN */
|
|
CTIMER_CTRL3_TMRB3EN_DIS = 0, /*!< DIS : Counter/Timer B3 Disable. */
|
|
CTIMER_CTRL3_TMRB3EN_EN = 1, /*!< EN : Counter/Timer B3 Enable. */
|
|
} CTIMER_CTRL3_TMRB3EN_Enum;
|
|
|
|
/* ============================================ CTIMER CTRL3 TMRA3POL [12..12] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL3_TMRA3POL */
|
|
CTIMER_CTRL3_TMRA3POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINA3 pin is the same as the
|
|
timer output. */
|
|
CTIMER_CTRL3_TMRA3POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINA3 pin is the inverse of
|
|
the timer output. */
|
|
} CTIMER_CTRL3_TMRA3POL_Enum;
|
|
|
|
/* ============================================ CTIMER CTRL3 TMRA3CLR [11..11] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL3_TMRA3CLR */
|
|
CTIMER_CTRL3_TMRA3CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer A3 at 0x0000. */
|
|
} CTIMER_CTRL3_TMRA3CLR_Enum;
|
|
|
|
/* ============================================= CTIMER CTRL3 TMRA3PE [10..10] ============================================= */
|
|
typedef enum { /*!< CTIMER_CTRL3_TMRA3PE */
|
|
CTIMER_CTRL3_TMRA3PE_DIS = 0, /*!< DIS : Counter/Timer A holds the TMRPINA signal at the value
|
|
TMRA3POL. */
|
|
CTIMER_CTRL3_TMRA3PE_EN = 1, /*!< EN : Enable counter/timer A3 to generate a signal on TMRPINA. */
|
|
} CTIMER_CTRL3_TMRA3PE_Enum;
|
|
|
|
/* ============================================== CTIMER CTRL3 TMRA3IE [9..9] ============================================== */
|
|
typedef enum { /*!< CTIMER_CTRL3_TMRA3IE */
|
|
CTIMER_CTRL3_TMRA3IE_DIS = 0, /*!< DIS : Disable counter/timer A3 from generating an interrupt. */
|
|
CTIMER_CTRL3_TMRA3IE_EN = 1, /*!< EN : Enable counter/timer A3 to generate an interrupt. */
|
|
} CTIMER_CTRL3_TMRA3IE_Enum;
|
|
|
|
/* ============================================== CTIMER CTRL3 TMRA3FN [6..8] ============================================== */
|
|
typedef enum { /*!< CTIMER_CTRL3_TMRA3FN */
|
|
CTIMER_CTRL3_TMRA3FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
|
|
to CMPR0A3, stop. */
|
|
CTIMER_CTRL3_TMRA3FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
|
|
pulses). Count to CMPR0A3, restart. */
|
|
CTIMER_CTRL3_TMRA3FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A3, assert,
|
|
count to CMPR1B, deassert, stop. */
|
|
CTIMER_CTRL3_TMRA3FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0A3, assert, count
|
|
to CMPR1A3, deassert, restart. */
|
|
CTIMER_CTRL3_TMRA3FN_CONTINUOUS = 4, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */
|
|
} CTIMER_CTRL3_TMRA3FN_Enum;
|
|
|
|
/* ============================================= CTIMER CTRL3 TMRA3CLK [1..5] ============================================== */
|
|
typedef enum { /*!< CTIMER_CTRL3_TMRA3CLK */
|
|
CTIMER_CTRL3_TMRA3CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINA. */
|
|
CTIMER_CTRL3_TMRA3CLK_HFRC = 1, /*!< HFRC : Clock source is the HFRC */
|
|
CTIMER_CTRL3_TMRA3CLK_HFRC_DIV8 = 2, /*!< HFRC_DIV8 : Clock source is HFRC / 8 */
|
|
CTIMER_CTRL3_TMRA3CLK_HFRC_DIV128 = 3, /*!< HFRC_DIV128 : Clock source is HFRC / 128 */
|
|
CTIMER_CTRL3_TMRA3CLK_HFRC_DIV512 = 4, /*!< HFRC_DIV512 : Clock source is HFRC / 512 */
|
|
CTIMER_CTRL3_TMRA3CLK_HFRC_DIV2K = 5, /*!< HFRC_DIV2K : Clock source is HFRC / 2048 */
|
|
CTIMER_CTRL3_TMRA3CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */
|
|
CTIMER_CTRL3_TMRA3CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */
|
|
CTIMER_CTRL3_TMRA3CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */
|
|
CTIMER_CTRL3_TMRA3CLK_XT_DIV256 = 9, /*!< XT_DIV256 : Clock source is XT / 256 */
|
|
CTIMER_CTRL3_TMRA3CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */
|
|
CTIMER_CTRL3_TMRA3CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */
|
|
CTIMER_CTRL3_TMRA3CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */
|
|
CTIMER_CTRL3_TMRA3CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC / 16K */
|
|
CTIMER_CTRL3_TMRA3CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */
|
|
CTIMER_CTRL3_TMRA3CLK_HCLK = 15, /*!< HCLK : Clock source is HCLK. */
|
|
CTIMER_CTRL3_TMRA3CLK_BUCKB = 16, /*!< BUCKB : Clock source is buck converter stream B. */
|
|
} CTIMER_CTRL3_TMRA3CLK_Enum;
|
|
|
|
/* ============================================== CTIMER CTRL3 TMRA3EN [0..0] ============================================== */
|
|
typedef enum { /*!< CTIMER_CTRL3_TMRA3EN */
|
|
CTIMER_CTRL3_TMRA3EN_DIS = 0, /*!< DIS : Counter/Timer A3 Disable. */
|
|
CTIMER_CTRL3_TMRA3EN_EN = 1, /*!< EN : Counter/Timer A3 Enable. */
|
|
} CTIMER_CTRL3_TMRA3EN_Enum;
|
|
|
|
/* ========================================================= INTEN ========================================================= */
|
|
/* ======================================================== INTSTAT ======================================================== */
|
|
/* ======================================================== INTCLR ========================================================= */
|
|
/* ======================================================== INTSET ========================================================= */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ GPIO ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
/* ======================================================== PADREGA ======================================================== */
|
|
/* ============================================ GPIO PADREGA PAD3PWRUP [31..31] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGA_PAD3PWRUP */
|
|
GPIO_PADREGA_PAD3PWRUP_DIS = 0, /*!< DIS : Power switch disabled */
|
|
GPIO_PADREGA_PAD3PWRUP_EN = 1, /*!< EN : Power switch enabled */
|
|
} GPIO_PADREGA_PAD3PWRUP_Enum;
|
|
|
|
/* =========================================== GPIO PADREGA PAD3FNCSEL [27..29] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGA_PAD3FNCSEL */
|
|
GPIO_PADREGA_PAD3FNCSEL_TRIG0 = 0, /*!< TRIG0 : Configure as the ADC Trigger 0 signal */
|
|
GPIO_PADREGA_PAD3FNCSEL_SLnCE = 1, /*!< SLnCE : Configure as the IOSLAVE SPI nCE signal */
|
|
GPIO_PADREGA_PAD3FNCSEL_M1nCE4 = 2, /*!< M1nCE4 : Configure as the SPI channel 4 nCE signal from IOMSTR1 */
|
|
GPIO_PADREGA_PAD3FNCSEL_GPIO3 = 3, /*!< GPIO3 : Configure as GPIO3 */
|
|
GPIO_PADREGA_PAD3FNCSEL_M0nCE = 4, /*!< M0nCE : Configure as the IOSLAVE SPI nCE loopback signal from
|
|
IOMSTR0 */
|
|
GPIO_PADREGA_PAD3FNCSEL_M1nCE = 5, /*!< M1nCE : Configure as the IOSLAVE SPI nCE loopback signal from
|
|
IOMSTR1 */
|
|
GPIO_PADREGA_PAD3FNCSEL_DIS = 6, /*!< DIS : Pad disabled */
|
|
} GPIO_PADREGA_PAD3FNCSEL_Enum;
|
|
|
|
/* ============================================ GPIO PADREGA PAD3STRNG [26..26] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGA_PAD3STRNG */
|
|
GPIO_PADREGA_PAD3STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGA_PAD3STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGA_PAD3STRNG_Enum;
|
|
|
|
/* ============================================ GPIO PADREGA PAD3INPEN [25..25] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGA_PAD3INPEN */
|
|
GPIO_PADREGA_PAD3INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGA_PAD3INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGA_PAD3INPEN_Enum;
|
|
|
|
/* ============================================ GPIO PADREGA PAD3PULL [24..24] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGA_PAD3PULL */
|
|
GPIO_PADREGA_PAD3PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGA_PAD3PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGA_PAD3PULL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGA PAD2FNCSEL [19..21] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGA_PAD2FNCSEL */
|
|
GPIO_PADREGA_PAD2FNCSEL_SLWIR3 = 0, /*!< SLWIR3 : Configure as the IOSLAVE SPI 3-wire MOSI/MISO signal */
|
|
GPIO_PADREGA_PAD2FNCSEL_SLMOSI = 1, /*!< SLMOSI : Configure as the IOSLAVE SPI MOSI signal */
|
|
GPIO_PADREGA_PAD2FNCSEL_CLKOUT = 2, /*!< CLKOUT : Configure as the CLKOUT signal */
|
|
GPIO_PADREGA_PAD2FNCSEL_GPIO2 = 3, /*!< GPIO2 : Configure as GPIO2 */
|
|
GPIO_PADREGA_PAD2FNCSEL_M0MOSI = 4, /*!< M0MOSI : Configure as the IOSLAVE SPI MOSI loopback signal from
|
|
IOMSTR0 */
|
|
GPIO_PADREGA_PAD2FNCSEL_M1MOSI = 5, /*!< M1MOSI : Configure as the IOSLAVE SPI MOSI loopback signal from
|
|
IOMSTR1 */
|
|
GPIO_PADREGA_PAD2FNCSEL_M0WIR3 = 6, /*!< M0WIR3 : Configure as the IOSLAVE SPI 3-wire MOSI/MISO loopback
|
|
signal from IOMSTR0 */
|
|
GPIO_PADREGA_PAD2FNCSEL_M1WIR3 = 7, /*!< M1WIR3 : Configure as the IOSLAVE SPI 3-wire MOSI/MISO loopback
|
|
signal from IOMSTR1 */
|
|
} GPIO_PADREGA_PAD2FNCSEL_Enum;
|
|
|
|
/* ============================================ GPIO PADREGA PAD2STRNG [18..18] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGA_PAD2STRNG */
|
|
GPIO_PADREGA_PAD2STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGA_PAD2STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGA_PAD2STRNG_Enum;
|
|
|
|
/* ============================================ GPIO PADREGA PAD2INPEN [17..17] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGA_PAD2INPEN */
|
|
GPIO_PADREGA_PAD2INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGA_PAD2INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGA_PAD2INPEN_Enum;
|
|
|
|
/* ============================================ GPIO PADREGA PAD2PULL [16..16] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGA_PAD2PULL */
|
|
GPIO_PADREGA_PAD2PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGA_PAD2PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGA_PAD2PULL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGA PAD1FNCSEL [11..13] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGA_PAD1FNCSEL */
|
|
GPIO_PADREGA_PAD1FNCSEL_SLSDA = 0, /*!< SLSDA : Configure as the IOSLAVE I2C SDA signal */
|
|
GPIO_PADREGA_PAD1FNCSEL_SLMISO = 1, /*!< SLMISO : Configure as the IOSLAVE SPI MISO signal */
|
|
GPIO_PADREGA_PAD1FNCSEL_UARTRX = 2, /*!< UARTRX : Configure as the UART RX signal */
|
|
GPIO_PADREGA_PAD1FNCSEL_GPIO1 = 3, /*!< GPIO1 : Configure as GPIO1 */
|
|
GPIO_PADREGA_PAD1FNCSEL_M0MISO = 4, /*!< M0MISO : Configure as the IOSLAVE SPI MISO loopback signal from
|
|
IOMSTR0 */
|
|
GPIO_PADREGA_PAD1FNCSEL_M1MISO = 5, /*!< M1MISO : Configure as the IOSLAVE SPI MISO loopback signal from
|
|
IOMSTR1 */
|
|
GPIO_PADREGA_PAD1FNCSEL_M0SDA = 6, /*!< M0SDA : Configure as the IOSLAVE I2C SDA loopback signal from
|
|
IOMSTR0 */
|
|
GPIO_PADREGA_PAD1FNCSEL_M1SDA = 7, /*!< M1SDA : Configure as the IOSLAVE I2C SDA loopback signal from
|
|
IOMSTR1 */
|
|
} GPIO_PADREGA_PAD1FNCSEL_Enum;
|
|
|
|
/* ============================================ GPIO PADREGA PAD1STRNG [10..10] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGA_PAD1STRNG */
|
|
GPIO_PADREGA_PAD1STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGA_PAD1STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGA_PAD1STRNG_Enum;
|
|
|
|
/* ============================================= GPIO PADREGA PAD1INPEN [9..9] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGA_PAD1INPEN */
|
|
GPIO_PADREGA_PAD1INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGA_PAD1INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGA_PAD1INPEN_Enum;
|
|
|
|
/* ============================================= GPIO PADREGA PAD1PULL [8..8] ============================================== */
|
|
typedef enum { /*!< GPIO_PADREGA_PAD1PULL */
|
|
GPIO_PADREGA_PAD1PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGA_PAD1PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGA_PAD1PULL_Enum;
|
|
|
|
/* ============================================ GPIO PADREGA PAD0FNCSEL [3..5] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGA_PAD0FNCSEL */
|
|
GPIO_PADREGA_PAD0FNCSEL_SLSCL = 0, /*!< SLSCL : Configure as the IOSLAVE I2C SCL signal */
|
|
GPIO_PADREGA_PAD0FNCSEL_SLSCK = 1, /*!< SLSCK : Configure as the IOSLAVE SPI SCK signal */
|
|
GPIO_PADREGA_PAD0FNCSEL_UARTTX = 2, /*!< UARTTX : Configure as the UART TX signal */
|
|
GPIO_PADREGA_PAD0FNCSEL_GPIO0 = 3, /*!< GPIO0 : Configure as GPIO0 */
|
|
GPIO_PADREGA_PAD0FNCSEL_M0SCK = 4, /*!< M0SCK : Configure as the IOSLAVE SPI SCK loopback signal from
|
|
IOMSTR0 */
|
|
GPIO_PADREGA_PAD0FNCSEL_M1SCK = 5, /*!< M1SCK : Configure as the IOSLAVE SPI SCK loopback signal from
|
|
IOMSTR1 */
|
|
GPIO_PADREGA_PAD0FNCSEL_M0SCL = 6, /*!< M0SCL : Configure as the IOSLAVE I2C SCL loopback signal from
|
|
IOMSTR0 */
|
|
GPIO_PADREGA_PAD0FNCSEL_M1SCL = 7, /*!< M1SCL : Configure as the IOSLAVE I2C SCL loopback signal from
|
|
IOMSTR1 */
|
|
} GPIO_PADREGA_PAD0FNCSEL_Enum;
|
|
|
|
/* ============================================= GPIO PADREGA PAD0STRNG [2..2] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGA_PAD0STRNG */
|
|
GPIO_PADREGA_PAD0STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGA_PAD0STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGA_PAD0STRNG_Enum;
|
|
|
|
/* ============================================= GPIO PADREGA PAD0INPEN [1..1] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGA_PAD0INPEN */
|
|
GPIO_PADREGA_PAD0INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGA_PAD0INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGA_PAD0INPEN_Enum;
|
|
|
|
/* ============================================= GPIO PADREGA PAD0PULL [0..0] ============================================== */
|
|
typedef enum { /*!< GPIO_PADREGA_PAD0PULL */
|
|
GPIO_PADREGA_PAD0PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGA_PAD0PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGA_PAD0PULL_Enum;
|
|
|
|
/* ======================================================== PADREGB ======================================================== */
|
|
/* =========================================== GPIO PADREGB PAD7FNCSEL [27..29] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGB_PAD7FNCSEL */
|
|
GPIO_PADREGB_PAD7FNCSEL_M0WIR3 = 0, /*!< M0WIR3 : Configure as the IOMSTR0 SPI 3-wire MOSI/MISO signal */
|
|
GPIO_PADREGB_PAD7FNCSEL_M0MOSI = 1, /*!< M0MOSI : Configure as the IOMSTR0 SPI MOSI signal */
|
|
GPIO_PADREGB_PAD7FNCSEL_CLKOUT = 2, /*!< CLKOUT : Configure as the CLKOUT signal */
|
|
GPIO_PADREGB_PAD7FNCSEL_GPIO7 = 3, /*!< GPIO7 : Configure as GPIO7 */
|
|
GPIO_PADREGB_PAD7FNCSEL_SLWIR3 = 6, /*!< SLWIR3 : Configure as the IOMSTR0 SPI 3-wire MOSI/MISO loopback
|
|
signal from IOSLAVE */
|
|
GPIO_PADREGB_PAD7FNCSEL_DIS = 7, /*!< DIS : Pad disabled */
|
|
} GPIO_PADREGB_PAD7FNCSEL_Enum;
|
|
|
|
/* ============================================ GPIO PADREGB PAD7STRNG [26..26] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGB_PAD7STRNG */
|
|
GPIO_PADREGB_PAD7STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGB_PAD7STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGB_PAD7STRNG_Enum;
|
|
|
|
/* ============================================ GPIO PADREGB PAD7INPEN [25..25] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGB_PAD7INPEN */
|
|
GPIO_PADREGB_PAD7INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGB_PAD7INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGB_PAD7INPEN_Enum;
|
|
|
|
/* ============================================ GPIO PADREGB PAD7PULL [24..24] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGB_PAD7PULL */
|
|
GPIO_PADREGB_PAD7PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGB_PAD7PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGB_PAD7PULL_Enum;
|
|
|
|
/* ============================================ GPIO PADREGB PAD6RSEL [22..23] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGB_PAD6RSEL */
|
|
GPIO_PADREGB_PAD6RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */
|
|
GPIO_PADREGB_PAD6RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */
|
|
GPIO_PADREGB_PAD6RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */
|
|
GPIO_PADREGB_PAD6RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */
|
|
} GPIO_PADREGB_PAD6RSEL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGB PAD6FNCSEL [19..21] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGB_PAD6FNCSEL */
|
|
GPIO_PADREGB_PAD6FNCSEL_M0SDA = 0, /*!< M0SDA : Configure as the IOMSTR0 I2C SDA signal */
|
|
GPIO_PADREGB_PAD6FNCSEL_M0MISO = 1, /*!< M0MISO : Configure as the IOMSTR0 SPI MISO signal */
|
|
GPIO_PADREGB_PAD6FNCSEL_UACTS = 2, /*!< UACTS : Configure as the UART CTS signal */
|
|
GPIO_PADREGB_PAD6FNCSEL_GPIO6 = 3, /*!< GPIO6 : Configure as GPIO6 */
|
|
GPIO_PADREGB_PAD6FNCSEL_SLMISO = 4, /*!< SLMISO : Configure as the IOMSTR0 SPI MISO loopback signal from
|
|
IOSLAVE */
|
|
GPIO_PADREGB_PAD6FNCSEL_SLSDA = 6, /*!< SLSDA : Configure as the IOMSTR0 I2C SDA loopback signal from
|
|
IOSLAVE */
|
|
GPIO_PADREGB_PAD6FNCSEL_DIS = 7, /*!< DIS : Pad disabled */
|
|
} GPIO_PADREGB_PAD6FNCSEL_Enum;
|
|
|
|
/* ============================================ GPIO PADREGB PAD6STRNG [18..18] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGB_PAD6STRNG */
|
|
GPIO_PADREGB_PAD6STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGB_PAD6STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGB_PAD6STRNG_Enum;
|
|
|
|
/* ============================================ GPIO PADREGB PAD6INPEN [17..17] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGB_PAD6INPEN */
|
|
GPIO_PADREGB_PAD6INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGB_PAD6INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGB_PAD6INPEN_Enum;
|
|
|
|
/* ============================================ GPIO PADREGB PAD6PULL [16..16] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGB_PAD6PULL */
|
|
GPIO_PADREGB_PAD6PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGB_PAD6PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGB_PAD6PULL_Enum;
|
|
|
|
/* ============================================ GPIO PADREGB PAD5RSEL [14..15] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGB_PAD5RSEL */
|
|
GPIO_PADREGB_PAD5RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */
|
|
GPIO_PADREGB_PAD5RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */
|
|
GPIO_PADREGB_PAD5RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */
|
|
GPIO_PADREGB_PAD5RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */
|
|
} GPIO_PADREGB_PAD5RSEL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGB PAD5FNCSEL [11..13] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGB_PAD5FNCSEL */
|
|
GPIO_PADREGB_PAD5FNCSEL_M0SCL = 0, /*!< M0SCL : Configure as the IOMSTR0 I2C SCL signal */
|
|
GPIO_PADREGB_PAD5FNCSEL_M0SCK = 1, /*!< M0SCK : Configure as the IOMSTR0 SPI SCK signal */
|
|
GPIO_PADREGB_PAD5FNCSEL_UARTS = 2, /*!< UARTS : Configure as the UART RTS signal */
|
|
GPIO_PADREGB_PAD5FNCSEL_GPIO5 = 3, /*!< GPIO5 : Configure as GPIO5 */
|
|
GPIO_PADREGB_PAD5FNCSEL_SLSCK = 4, /*!< SLSCK : Configure as the IOMSTR0 SPI SCK loopback signal from
|
|
IOSLAVE */
|
|
GPIO_PADREGB_PAD5FNCSEL_SLSCL = 6, /*!< SLSCL : Configure as the IOMSTR0 I2C SCL loopback signal from
|
|
IOSLAVE */
|
|
GPIO_PADREGB_PAD5FNCSEL_DIS = 7, /*!< DIS : Pad disabled */
|
|
} GPIO_PADREGB_PAD5FNCSEL_Enum;
|
|
|
|
/* ============================================ GPIO PADREGB PAD5STRNG [10..10] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGB_PAD5STRNG */
|
|
GPIO_PADREGB_PAD5STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGB_PAD5STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGB_PAD5STRNG_Enum;
|
|
|
|
/* ============================================= GPIO PADREGB PAD5INPEN [9..9] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGB_PAD5INPEN */
|
|
GPIO_PADREGB_PAD5INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGB_PAD5INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGB_PAD5INPEN_Enum;
|
|
|
|
/* ============================================= GPIO PADREGB PAD5PULL [8..8] ============================================== */
|
|
typedef enum { /*!< GPIO_PADREGB_PAD5PULL */
|
|
GPIO_PADREGB_PAD5PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGB_PAD5PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGB_PAD5PULL_Enum;
|
|
|
|
/* ============================================= GPIO PADREGB PAD4PWRUP [7..7] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGB_PAD4PWRUP */
|
|
GPIO_PADREGB_PAD4PWRUP_DIS = 0, /*!< DIS : Power switch disabled */
|
|
GPIO_PADREGB_PAD4PWRUP_EN = 1, /*!< EN : Power switch enabled */
|
|
} GPIO_PADREGB_PAD4PWRUP_Enum;
|
|
|
|
/* ============================================ GPIO PADREGB PAD4FNCSEL [3..5] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGB_PAD4FNCSEL */
|
|
GPIO_PADREGB_PAD4FNCSEL_TRIG1 = 0, /*!< TRIG1 : Configure as the ADC Trigger 1 signal */
|
|
GPIO_PADREGB_PAD4FNCSEL_SLINT = 1, /*!< SLINT : Configure as the IOSLAVE interrupt out signal */
|
|
GPIO_PADREGB_PAD4FNCSEL_M0nCE5 = 2, /*!< M0nCE5 : Configure as the SPI channel 5 nCE signal from IOMSTR0 */
|
|
GPIO_PADREGB_PAD4FNCSEL_GPIO4 = 3, /*!< GPIO4 : Configure as GPIO4 */
|
|
GPIO_PADREGB_PAD4FNCSEL_SLINTGP = 4, /*!< SLINTGP : Configure as the IOSLAVE interrupt loopback signal
|
|
to GPIO4 */
|
|
GPIO_PADREGB_PAD4FNCSEL_SWO = 5, /*!< SWO : Configure as the serial wire debug SWO signal */
|
|
GPIO_PADREGB_PAD4FNCSEL_CLKOUT = 6, /*!< CLKOUT : Configure as the CLKOUT signal */
|
|
GPIO_PADREGB_PAD4FNCSEL_DIS = 7, /*!< DIS : Pad disabled */
|
|
} GPIO_PADREGB_PAD4FNCSEL_Enum;
|
|
|
|
/* ============================================= GPIO PADREGB PAD4STRNG [2..2] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGB_PAD4STRNG */
|
|
GPIO_PADREGB_PAD4STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGB_PAD4STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGB_PAD4STRNG_Enum;
|
|
|
|
/* ============================================= GPIO PADREGB PAD4INPEN [1..1] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGB_PAD4INPEN */
|
|
GPIO_PADREGB_PAD4INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGB_PAD4INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGB_PAD4INPEN_Enum;
|
|
|
|
/* ============================================= GPIO PADREGB PAD4PULL [0..0] ============================================== */
|
|
typedef enum { /*!< GPIO_PADREGB_PAD4PULL */
|
|
GPIO_PADREGB_PAD4PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGB_PAD4PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGB_PAD4PULL_Enum;
|
|
|
|
/* ======================================================== PADREGC ======================================================== */
|
|
/* =========================================== GPIO PADREGC PAD11PWRDN [30..30] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGC_PAD11PWRDN */
|
|
GPIO_PADREGC_PAD11PWRDN_DIS = 0, /*!< DIS : Power switch disabled */
|
|
GPIO_PADREGC_PAD11PWRDN_EN = 1, /*!< EN : Power switch enabled */
|
|
} GPIO_PADREGC_PAD11PWRDN_Enum;
|
|
|
|
/* =========================================== GPIO PADREGC PAD11FNCSEL [27..28] =========================================== */
|
|
typedef enum { /*!< GPIO_PADREGC_PAD11FNCSEL */
|
|
GPIO_PADREGC_PAD11FNCSEL_ANATST = 0, /*!< ANATST : Configure as the analog test output signal */
|
|
GPIO_PADREGC_PAD11FNCSEL_M0nCE0 = 1, /*!< M0nCE0 : Configure as the SPI channel 0 nCE signal from IOMSTR0 */
|
|
GPIO_PADREGC_PAD11FNCSEL_CLKOUT = 2, /*!< CLKOUT : Configure as the CLKOUT signal */
|
|
GPIO_PADREGC_PAD11FNCSEL_GPIO11 = 3, /*!< GPIO11 : Configure as GPIO11 */
|
|
} GPIO_PADREGC_PAD11FNCSEL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGC PAD11STRNG [26..26] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGC_PAD11STRNG */
|
|
GPIO_PADREGC_PAD11STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGC_PAD11STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGC_PAD11STRNG_Enum;
|
|
|
|
/* =========================================== GPIO PADREGC PAD11INPEN [25..25] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGC_PAD11INPEN */
|
|
GPIO_PADREGC_PAD11INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGC_PAD11INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGC_PAD11INPEN_Enum;
|
|
|
|
/* ============================================ GPIO PADREGC PAD11PULL [24..24] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGC_PAD11PULL */
|
|
GPIO_PADREGC_PAD11PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGC_PAD11PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGC_PAD11PULL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGC PAD10FNCSEL [19..21] =========================================== */
|
|
typedef enum { /*!< GPIO_PADREGC_PAD10FNCSEL */
|
|
GPIO_PADREGC_PAD10FNCSEL_M1WIR3 = 0, /*!< M1WIR3 : Configure as the IOMSTR1 SPI 3-wire MOSI/MISO signal */
|
|
GPIO_PADREGC_PAD10FNCSEL_M1MOSI = 1, /*!< M1MOSI : Configure as the IOMSTR1 SPI MOSI signal */
|
|
GPIO_PADREGC_PAD10FNCSEL_M0nCE6 = 2, /*!< M0nCE6 : Configure as the SPI channel 6 nCE signal from IOMSTR0 */
|
|
GPIO_PADREGC_PAD10FNCSEL_GPIO10 = 3, /*!< GPIO10 : Configure as GPIO10 */
|
|
GPIO_PADREGC_PAD10FNCSEL_EXTHFA = 5, /*!< EXTHFA : Configure as the external HFRC A clock signal */
|
|
GPIO_PADREGC_PAD10FNCSEL_DIS = 6, /*!< DIS : Pad disabled */
|
|
GPIO_PADREGC_PAD10FNCSEL_SLWIR3 = 7, /*!< SLWIR3 : Configure as the IOMSTR1 SPI 3-wire MOSI/MISO loopback
|
|
signal from IOSLAVE */
|
|
} GPIO_PADREGC_PAD10FNCSEL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGC PAD10STRNG [18..18] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGC_PAD10STRNG */
|
|
GPIO_PADREGC_PAD10STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGC_PAD10STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGC_PAD10STRNG_Enum;
|
|
|
|
/* =========================================== GPIO PADREGC PAD10INPEN [17..17] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGC_PAD10INPEN */
|
|
GPIO_PADREGC_PAD10INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGC_PAD10INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGC_PAD10INPEN_Enum;
|
|
|
|
/* ============================================ GPIO PADREGC PAD10PULL [16..16] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGC_PAD10PULL */
|
|
GPIO_PADREGC_PAD10PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGC_PAD10PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGC_PAD10PULL_Enum;
|
|
|
|
/* ============================================ GPIO PADREGC PAD9RSEL [14..15] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGC_PAD9RSEL */
|
|
GPIO_PADREGC_PAD9RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */
|
|
GPIO_PADREGC_PAD9RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */
|
|
GPIO_PADREGC_PAD9RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */
|
|
GPIO_PADREGC_PAD9RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */
|
|
} GPIO_PADREGC_PAD9RSEL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGC PAD9FNCSEL [11..13] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGC_PAD9FNCSEL */
|
|
GPIO_PADREGC_PAD9FNCSEL_M1SDA = 0, /*!< M1SDA : Configure as the IOMSTR1 I2C SDA signal */
|
|
GPIO_PADREGC_PAD9FNCSEL_M1MISO = 1, /*!< M1MISO : Configure as the IOMSTR1 SPI MISO signal */
|
|
GPIO_PADREGC_PAD9FNCSEL_M0nCE5 = 2, /*!< M0nCE5 : Configure as the SPI channel 5 nCE signal from IOMSTR0 */
|
|
GPIO_PADREGC_PAD9FNCSEL_GPIO9 = 3, /*!< GPIO9 : Configure as GPIO9 */
|
|
GPIO_PADREGC_PAD9FNCSEL_SLMISO = 5, /*!< SLMISO : Configure as the IOMSTR1 SPI MISO loopback signal from
|
|
IOSLAVE */
|
|
GPIO_PADREGC_PAD9FNCSEL_DIS = 6, /*!< DIS : Pad disabled */
|
|
GPIO_PADREGC_PAD9FNCSEL_SLSDA = 7, /*!< SLSDA : Configure as the IOMSTR1 I2C SDA loopback signal from
|
|
IOSLAVE */
|
|
} GPIO_PADREGC_PAD9FNCSEL_Enum;
|
|
|
|
/* ============================================ GPIO PADREGC PAD9STRNG [10..10] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGC_PAD9STRNG */
|
|
GPIO_PADREGC_PAD9STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGC_PAD9STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGC_PAD9STRNG_Enum;
|
|
|
|
/* ============================================= GPIO PADREGC PAD9INPEN [9..9] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGC_PAD9INPEN */
|
|
GPIO_PADREGC_PAD9INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGC_PAD9INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGC_PAD9INPEN_Enum;
|
|
|
|
/* ============================================= GPIO PADREGC PAD9PULL [8..8] ============================================== */
|
|
typedef enum { /*!< GPIO_PADREGC_PAD9PULL */
|
|
GPIO_PADREGC_PAD9PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGC_PAD9PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGC_PAD9PULL_Enum;
|
|
|
|
/* ============================================= GPIO PADREGC PAD8RSEL [6..7] ============================================== */
|
|
typedef enum { /*!< GPIO_PADREGC_PAD8RSEL */
|
|
GPIO_PADREGC_PAD8RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */
|
|
GPIO_PADREGC_PAD8RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */
|
|
GPIO_PADREGC_PAD8RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */
|
|
GPIO_PADREGC_PAD8RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */
|
|
} GPIO_PADREGC_PAD8RSEL_Enum;
|
|
|
|
/* ============================================ GPIO PADREGC PAD8FNCSEL [3..5] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGC_PAD8FNCSEL */
|
|
GPIO_PADREGC_PAD8FNCSEL_M1SCL = 0, /*!< M1SCL : Configure as the IOMSTR1 I2C SCL signal */
|
|
GPIO_PADREGC_PAD8FNCSEL_M1SCK = 1, /*!< M1SCK : Configure as the IOMSTR1 SPI SCK signal */
|
|
GPIO_PADREGC_PAD8FNCSEL_M0nCE4 = 2, /*!< M0nCE4 : Configure as the SPI channel 4 nCE signal from IOMSTR0 */
|
|
GPIO_PADREGC_PAD8FNCSEL_GPIO8 = 3, /*!< GPIO8 : Configure as GPIO8 */
|
|
GPIO_PADREGC_PAD8FNCSEL_SLSCK = 5, /*!< SLSCK : Configure as the IOMSTR1 SPI SCK loopback signal from
|
|
IOSLAVE */
|
|
GPIO_PADREGC_PAD8FNCSEL_DIS = 6, /*!< DIS : Pad disabled */
|
|
GPIO_PADREGC_PAD8FNCSEL_SLSCL = 7, /*!< SLSCL : Configure as the IOMSTR1 I2C SCL loopback signal from
|
|
IOSLAVE */
|
|
} GPIO_PADREGC_PAD8FNCSEL_Enum;
|
|
|
|
/* ============================================= GPIO PADREGC PAD8STRNG [2..2] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGC_PAD8STRNG */
|
|
GPIO_PADREGC_PAD8STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGC_PAD8STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGC_PAD8STRNG_Enum;
|
|
|
|
/* ============================================= GPIO PADREGC PAD8INPEN [1..1] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGC_PAD8INPEN */
|
|
GPIO_PADREGC_PAD8INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGC_PAD8INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGC_PAD8INPEN_Enum;
|
|
|
|
/* ============================================= GPIO PADREGC PAD8PULL [0..0] ============================================== */
|
|
typedef enum { /*!< GPIO_PADREGC_PAD8PULL */
|
|
GPIO_PADREGC_PAD8PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGC_PAD8PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGC_PAD8PULL_Enum;
|
|
|
|
/* ======================================================== PADREGD ======================================================== */
|
|
/* =========================================== GPIO PADREGD PAD15FNCSEL [27..29] =========================================== */
|
|
typedef enum { /*!< GPIO_PADREGD_PAD15FNCSEL */
|
|
GPIO_PADREGD_PAD15FNCSEL_ADC3 = 0, /*!< ADC3 : Configure as the analog ADC input 3 */
|
|
GPIO_PADREGD_PAD15FNCSEL_M1nCE3 = 1, /*!< M1nCE3 : Configure as the SPI channel 3 nCE signal from IOMSTR1 */
|
|
GPIO_PADREGD_PAD15FNCSEL_UARTRX = 2, /*!< UARTRX : Configure as the UART RX signal */
|
|
GPIO_PADREGD_PAD15FNCSEL_GPIO15 = 3, /*!< GPIO15 : Configure as GPIO15 */
|
|
GPIO_PADREGD_PAD15FNCSEL_EXTXT = 5, /*!< EXTXT : Configure as the external XT clock signal */
|
|
GPIO_PADREGD_PAD15FNCSEL_DIS = 7, /*!< DIS : Pad disabled */
|
|
} GPIO_PADREGD_PAD15FNCSEL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGD PAD15STRNG [26..26] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGD_PAD15STRNG */
|
|
GPIO_PADREGD_PAD15STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGD_PAD15STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGD_PAD15STRNG_Enum;
|
|
|
|
/* =========================================== GPIO PADREGD PAD15INPEN [25..25] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGD_PAD15INPEN */
|
|
GPIO_PADREGD_PAD15INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGD_PAD15INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGD_PAD15INPEN_Enum;
|
|
|
|
/* ============================================ GPIO PADREGD PAD15PULL [24..24] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGD_PAD15PULL */
|
|
GPIO_PADREGD_PAD15PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGD_PAD15PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGD_PAD15PULL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGD PAD14FNCSEL [19..21] =========================================== */
|
|
typedef enum { /*!< GPIO_PADREGD_PAD14FNCSEL */
|
|
GPIO_PADREGD_PAD14FNCSEL_ADC2 = 0, /*!< ADC2 : Configure as the analog ADC input 2 */
|
|
GPIO_PADREGD_PAD14FNCSEL_M1nCE2 = 1, /*!< M1nCE2 : Configure as the SPI channel 2 nCE signal from IOMSTR1 */
|
|
GPIO_PADREGD_PAD14FNCSEL_UARTTX = 2, /*!< UARTTX : Configure as the UART TX signal */
|
|
GPIO_PADREGD_PAD14FNCSEL_GPIO14 = 3, /*!< GPIO14 : Configure as GPIO14 */
|
|
GPIO_PADREGD_PAD14FNCSEL_EXTHFS = 5, /*!< EXTHFS : Configure as the external HFRC select signal */
|
|
GPIO_PADREGD_PAD14FNCSEL_DIS = 7, /*!< DIS : Pad disabled */
|
|
} GPIO_PADREGD_PAD14FNCSEL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGD PAD14STRNG [18..18] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGD_PAD14STRNG */
|
|
GPIO_PADREGD_PAD14STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGD_PAD14STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGD_PAD14STRNG_Enum;
|
|
|
|
/* =========================================== GPIO PADREGD PAD14INPEN [17..17] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGD_PAD14INPEN */
|
|
GPIO_PADREGD_PAD14INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGD_PAD14INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGD_PAD14INPEN_Enum;
|
|
|
|
/* ============================================ GPIO PADREGD PAD14PULL [16..16] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGD_PAD14PULL */
|
|
GPIO_PADREGD_PAD14PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGD_PAD14PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGD_PAD14PULL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGD PAD13FNCSEL [11..13] =========================================== */
|
|
typedef enum { /*!< GPIO_PADREGD_PAD13FNCSEL */
|
|
GPIO_PADREGD_PAD13FNCSEL_ADC1 = 0, /*!< ADC1 : Configure as the analog ADC input 1 */
|
|
GPIO_PADREGD_PAD13FNCSEL_M1nCE1 = 1, /*!< M1nCE1 : Configure as the SPI channel 1 nCE signal from IOMSTR1 */
|
|
GPIO_PADREGD_PAD13FNCSEL_TCTB0 = 2, /*!< TCTB0 : Configure as the input/output signal from CTIMER B0 */
|
|
GPIO_PADREGD_PAD13FNCSEL_GPIO13 = 3, /*!< GPIO13 : Configure as GPIO13 */
|
|
GPIO_PADREGD_PAD13FNCSEL_EXTHFA = 5, /*!< EXTHFA : Configure as the external HFRC B clock signal */
|
|
GPIO_PADREGD_PAD13FNCSEL_SWO = 6, /*!< SWO : Configure as the serial wire debug SWO signal */
|
|
GPIO_PADREGD_PAD13FNCSEL_DIS = 7, /*!< DIS : Pad disabled */
|
|
} GPIO_PADREGD_PAD13FNCSEL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGD PAD13STRNG [10..10] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGD_PAD13STRNG */
|
|
GPIO_PADREGD_PAD13STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGD_PAD13STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGD_PAD13STRNG_Enum;
|
|
|
|
/* ============================================ GPIO PADREGD PAD13INPEN [9..9] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGD_PAD13INPEN */
|
|
GPIO_PADREGD_PAD13INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGD_PAD13INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGD_PAD13INPEN_Enum;
|
|
|
|
/* ============================================= GPIO PADREGD PAD13PULL [8..8] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGD_PAD13PULL */
|
|
GPIO_PADREGD_PAD13PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGD_PAD13PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGD_PAD13PULL_Enum;
|
|
|
|
/* ============================================ GPIO PADREGD PAD12FNCSEL [3..4] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGD_PAD12FNCSEL */
|
|
GPIO_PADREGD_PAD12FNCSEL_ADC0 = 0, /*!< ADC0 : Configure as the analog ADC input 0 */
|
|
GPIO_PADREGD_PAD12FNCSEL_M1nCE0 = 1, /*!< M1nCE0 : Configure as the SPI channel 0 nCE signal from IOMSTR1 */
|
|
GPIO_PADREGD_PAD12FNCSEL_TCTA0 = 2, /*!< TCTA0 : Configure as the input/output signal from CTIMER A0 */
|
|
GPIO_PADREGD_PAD12FNCSEL_GPIO12 = 3, /*!< GPIO12 : Configure as GPIO12 */
|
|
} GPIO_PADREGD_PAD12FNCSEL_Enum;
|
|
|
|
/* ============================================ GPIO PADREGD PAD12STRNG [2..2] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGD_PAD12STRNG */
|
|
GPIO_PADREGD_PAD12STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGD_PAD12STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGD_PAD12STRNG_Enum;
|
|
|
|
/* ============================================ GPIO PADREGD PAD12INPEN [1..1] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGD_PAD12INPEN */
|
|
GPIO_PADREGD_PAD12INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGD_PAD12INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGD_PAD12INPEN_Enum;
|
|
|
|
/* ============================================= GPIO PADREGD PAD12PULL [0..0] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGD_PAD12PULL */
|
|
GPIO_PADREGD_PAD12PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGD_PAD12PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGD_PAD12PULL_Enum;
|
|
|
|
/* ======================================================== PADREGE ======================================================== */
|
|
/* =========================================== GPIO PADREGE PAD19FNCSEL [27..28] =========================================== */
|
|
typedef enum { /*!< GPIO_PADREGE_PAD19FNCSEL */
|
|
GPIO_PADREGE_PAD19FNCSEL_CMPRF = 0, /*!< CMPRF : Configure as the analog comparator reference signal */
|
|
GPIO_PADREGE_PAD19FNCSEL_M0nCE3 = 1, /*!< M0nCE3 : Configure as the SPI channel 3 nCE signal from IOMSTR0 */
|
|
GPIO_PADREGE_PAD19FNCSEL_TCTB1 = 2, /*!< TCTB1 : Configure as the input/output signal from CTIMER B1 */
|
|
GPIO_PADREGE_PAD19FNCSEL_GPIO19 = 3, /*!< GPIO19 : Configure as GPIO19 */
|
|
} GPIO_PADREGE_PAD19FNCSEL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGE PAD19STRNG [26..26] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGE_PAD19STRNG */
|
|
GPIO_PADREGE_PAD19STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGE_PAD19STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGE_PAD19STRNG_Enum;
|
|
|
|
/* =========================================== GPIO PADREGE PAD19INPEN [25..25] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGE_PAD19INPEN */
|
|
GPIO_PADREGE_PAD19INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGE_PAD19INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGE_PAD19INPEN_Enum;
|
|
|
|
/* ============================================ GPIO PADREGE PAD19PULL [24..24] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGE_PAD19PULL */
|
|
GPIO_PADREGE_PAD19PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGE_PAD19PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGE_PAD19PULL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGE PAD18FNCSEL [19..20] =========================================== */
|
|
typedef enum { /*!< GPIO_PADREGE_PAD18FNCSEL */
|
|
GPIO_PADREGE_PAD18FNCSEL_CMPIN1 = 0, /*!< CMPIN1 : Configure as the analog comparator input 1 signal */
|
|
GPIO_PADREGE_PAD18FNCSEL_M0nCE2 = 1, /*!< M0nCE2 : Configure as the SPI channel 2 nCE signal from IOMSTR0 */
|
|
GPIO_PADREGE_PAD18FNCSEL_TCTA1 = 2, /*!< TCTA1 : Configure as the input/output signal from CTIMER A1 */
|
|
GPIO_PADREGE_PAD18FNCSEL_GPIO18 = 3, /*!< GPIO18 : Configure as GPIO18 */
|
|
} GPIO_PADREGE_PAD18FNCSEL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGE PAD18STRNG [18..18] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGE_PAD18STRNG */
|
|
GPIO_PADREGE_PAD18STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGE_PAD18STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGE_PAD18STRNG_Enum;
|
|
|
|
/* =========================================== GPIO PADREGE PAD18INPEN [17..17] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGE_PAD18INPEN */
|
|
GPIO_PADREGE_PAD18INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGE_PAD18INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGE_PAD18INPEN_Enum;
|
|
|
|
/* ============================================ GPIO PADREGE PAD18PULL [16..16] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGE_PAD18PULL */
|
|
GPIO_PADREGE_PAD18PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGE_PAD18PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGE_PAD18PULL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGE PAD17FNCSEL [11..13] =========================================== */
|
|
typedef enum { /*!< GPIO_PADREGE_PAD17FNCSEL */
|
|
GPIO_PADREGE_PAD17FNCSEL_CMPIN0 = 0, /*!< CMPIN0 : Configure as the analog comparator input 0 signal */
|
|
GPIO_PADREGE_PAD17FNCSEL_M0nCE1 = 1, /*!< M0nCE1 : Configure as the SPI channel 1 nCE signal from IOMSTR0 */
|
|
GPIO_PADREGE_PAD17FNCSEL_TRIG3 = 2, /*!< TRIG3 : Configure as the ADC Trigger 3 signal */
|
|
GPIO_PADREGE_PAD17FNCSEL_GPIO17 = 3, /*!< GPIO17 : Configure as GPIO17 */
|
|
GPIO_PADREGE_PAD17FNCSEL_EXTLF = 5, /*!< EXTLF : Configure as the external LFRC clock signal */
|
|
GPIO_PADREGE_PAD17FNCSEL_DIS = 7, /*!< DIS : Pad disabled */
|
|
} GPIO_PADREGE_PAD17FNCSEL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGE PAD17STRNG [10..10] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGE_PAD17STRNG */
|
|
GPIO_PADREGE_PAD17STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGE_PAD17STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGE_PAD17STRNG_Enum;
|
|
|
|
/* ============================================ GPIO PADREGE PAD17INPEN [9..9] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGE_PAD17INPEN */
|
|
GPIO_PADREGE_PAD17INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGE_PAD17INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGE_PAD17INPEN_Enum;
|
|
|
|
/* ============================================= GPIO PADREGE PAD17PULL [8..8] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGE_PAD17PULL */
|
|
GPIO_PADREGE_PAD17PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGE_PAD17PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGE_PAD17PULL_Enum;
|
|
|
|
/* ============================================ GPIO PADREGE PAD16FNCSEL [3..4] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGE_PAD16FNCSEL */
|
|
GPIO_PADREGE_PAD16FNCSEL_ADCREF = 0, /*!< ADCREF : Configure as the analog ADC reference input signal */
|
|
GPIO_PADREGE_PAD16FNCSEL_M0nCE4 = 1, /*!< M0nCE4 : Configure as the SPI channel 4 nCE signal from IOMSTR0 */
|
|
GPIO_PADREGE_PAD16FNCSEL_TRIG2 = 2, /*!< TRIG2 : Configure as the ADC Trigger 2 signal */
|
|
GPIO_PADREGE_PAD16FNCSEL_GPIO16 = 3, /*!< GPIO16 : Configure as GPIO16 */
|
|
} GPIO_PADREGE_PAD16FNCSEL_Enum;
|
|
|
|
/* ============================================ GPIO PADREGE PAD16STRNG [2..2] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGE_PAD16STRNG */
|
|
GPIO_PADREGE_PAD16STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGE_PAD16STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGE_PAD16STRNG_Enum;
|
|
|
|
/* ============================================ GPIO PADREGE PAD16INPEN [1..1] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGE_PAD16INPEN */
|
|
GPIO_PADREGE_PAD16INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGE_PAD16INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGE_PAD16INPEN_Enum;
|
|
|
|
/* ============================================= GPIO PADREGE PAD16PULL [0..0] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGE_PAD16PULL */
|
|
GPIO_PADREGE_PAD16PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGE_PAD16PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGE_PAD16PULL_Enum;
|
|
|
|
/* ======================================================== PADREGF ======================================================== */
|
|
/* =========================================== GPIO PADREGF PAD23FNCSEL [27..28] =========================================== */
|
|
typedef enum { /*!< GPIO_PADREGF_PAD23FNCSEL */
|
|
GPIO_PADREGF_PAD23FNCSEL_UARTRX = 0, /*!< UARTRX : Configure as the UART RX signal */
|
|
GPIO_PADREGF_PAD23FNCSEL_M0nCE0 = 1, /*!< M0nCE0 : Configure as the SPI channel 0 nCE signal from IOMSTR0 */
|
|
GPIO_PADREGF_PAD23FNCSEL_TCTB3 = 2, /*!< TCTB3 : Configure as the input/output signal from CTIMER B3 */
|
|
GPIO_PADREGF_PAD23FNCSEL_GPIO23 = 3, /*!< GPIO23 : Configure as GPIO23 */
|
|
} GPIO_PADREGF_PAD23FNCSEL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGF PAD23STRNG [26..26] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGF_PAD23STRNG */
|
|
GPIO_PADREGF_PAD23STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGF_PAD23STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGF_PAD23STRNG_Enum;
|
|
|
|
/* =========================================== GPIO PADREGF PAD23INPEN [25..25] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGF_PAD23INPEN */
|
|
GPIO_PADREGF_PAD23INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGF_PAD23INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGF_PAD23INPEN_Enum;
|
|
|
|
/* ============================================ GPIO PADREGF PAD23PULL [24..24] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGF_PAD23PULL */
|
|
GPIO_PADREGF_PAD23PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGF_PAD23PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGF_PAD23PULL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGF PAD22FNCSEL [19..20] =========================================== */
|
|
typedef enum { /*!< GPIO_PADREGF_PAD22FNCSEL */
|
|
GPIO_PADREGF_PAD22FNCSEL_UARTTX = 0, /*!< UARTTX : Configure as the UART TX signal */
|
|
GPIO_PADREGF_PAD22FNCSEL_M1nCE7 = 1, /*!< M1nCE7 : Configure as the SPI channel 7 nCE signal from IOMSTR1 */
|
|
GPIO_PADREGF_PAD22FNCSEL_TCTA3 = 2, /*!< TCTA3 : Configure as the input/output signal from CTIMER A3 */
|
|
GPIO_PADREGF_PAD22FNCSEL_GPIO22 = 3, /*!< GPIO22 : Configure as GPIO22 */
|
|
} GPIO_PADREGF_PAD22FNCSEL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGF PAD22STRNG [18..18] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGF_PAD22STRNG */
|
|
GPIO_PADREGF_PAD22STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGF_PAD22STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGF_PAD22STRNG_Enum;
|
|
|
|
/* =========================================== GPIO PADREGF PAD22INPEN [17..17] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGF_PAD22INPEN */
|
|
GPIO_PADREGF_PAD22INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGF_PAD22INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGF_PAD22INPEN_Enum;
|
|
|
|
/* ============================================ GPIO PADREGF PAD22PULL [16..16] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGF_PAD22PULL */
|
|
GPIO_PADREGF_PAD22PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGF_PAD22PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGF_PAD22PULL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGF PAD21FNCSEL [11..12] =========================================== */
|
|
typedef enum { /*!< GPIO_PADREGF_PAD21FNCSEL */
|
|
GPIO_PADREGF_PAD21FNCSEL_SWDIO = 0, /*!< SWDIO : Configure as the serial wire debug data signal */
|
|
GPIO_PADREGF_PAD21FNCSEL_M1nCE6 = 1, /*!< M1nCE6 : Configure as the SPI channel 6 nCE signal from IOMSTR1 */
|
|
GPIO_PADREGF_PAD21FNCSEL_TCTB2 = 2, /*!< TCTB2 : Configure as the input/output signal from CTIMER B2 */
|
|
GPIO_PADREGF_PAD21FNCSEL_GPIO21 = 3, /*!< GPIO21 : Configure as GPIO21 */
|
|
} GPIO_PADREGF_PAD21FNCSEL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGF PAD21STRNG [10..10] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGF_PAD21STRNG */
|
|
GPIO_PADREGF_PAD21STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGF_PAD21STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGF_PAD21STRNG_Enum;
|
|
|
|
/* ============================================ GPIO PADREGF PAD21INPEN [9..9] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGF_PAD21INPEN */
|
|
GPIO_PADREGF_PAD21INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGF_PAD21INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGF_PAD21INPEN_Enum;
|
|
|
|
/* ============================================= GPIO PADREGF PAD21PULL [8..8] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGF_PAD21PULL */
|
|
GPIO_PADREGF_PAD21PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGF_PAD21PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGF_PAD21PULL_Enum;
|
|
|
|
/* ============================================ GPIO PADREGF PAD20FNCSEL [3..4] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGF_PAD20FNCSEL */
|
|
GPIO_PADREGF_PAD20FNCSEL_SWDCK = 0, /*!< SWDCK : Configure as the serial wire debug clock signal */
|
|
GPIO_PADREGF_PAD20FNCSEL_M1nCE5 = 1, /*!< M1nCE5 : Configure as the SPI channel 5 nCE signal from IOMSTR1 */
|
|
GPIO_PADREGF_PAD20FNCSEL_TCTA2 = 2, /*!< TCTA2 : Configure as the input/output signal from CTIMER A2 */
|
|
GPIO_PADREGF_PAD20FNCSEL_GPIO20 = 3, /*!< GPIO20 : Configure as GPIO20 */
|
|
} GPIO_PADREGF_PAD20FNCSEL_Enum;
|
|
|
|
/* ============================================ GPIO PADREGF PAD20STRNG [2..2] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGF_PAD20STRNG */
|
|
GPIO_PADREGF_PAD20STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGF_PAD20STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGF_PAD20STRNG_Enum;
|
|
|
|
/* ============================================ GPIO PADREGF PAD20INPEN [1..1] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGF_PAD20INPEN */
|
|
GPIO_PADREGF_PAD20INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGF_PAD20INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGF_PAD20INPEN_Enum;
|
|
|
|
/* ============================================= GPIO PADREGF PAD20PULL [0..0] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGF_PAD20PULL */
|
|
GPIO_PADREGF_PAD20PULL_DIS = 0, /*!< DIS : Pulldown disabled */
|
|
GPIO_PADREGF_PAD20PULL_EN = 1, /*!< EN : Pulldown enabled */
|
|
} GPIO_PADREGF_PAD20PULL_Enum;
|
|
|
|
/* ======================================================== PADREGG ======================================================== */
|
|
/* =========================================== GPIO PADREGG PAD27FNCSEL [27..28] =========================================== */
|
|
typedef enum { /*!< GPIO_PADREGG_PAD27FNCSEL */
|
|
GPIO_PADREGG_PAD27FNCSEL_EXTHF = 0, /*!< EXTHF : Configure as the external HFRC clock signal */
|
|
GPIO_PADREGG_PAD27FNCSEL_M1nCE4 = 1, /*!< M1nCE4 : Configure as the SPI channel 4 nCE signal from IOMSTR1 */
|
|
GPIO_PADREGG_PAD27FNCSEL_TCTA1 = 2, /*!< TCTA1 : Configure as the input/output signal from CTIMER A1 */
|
|
GPIO_PADREGG_PAD27FNCSEL_GPIO27 = 3, /*!< GPIO27 : Configure as GPIO27 */
|
|
} GPIO_PADREGG_PAD27FNCSEL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGG PAD27STRNG [26..26] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGG_PAD27STRNG */
|
|
GPIO_PADREGG_PAD27STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGG_PAD27STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGG_PAD27STRNG_Enum;
|
|
|
|
/* =========================================== GPIO PADREGG PAD27INPEN [25..25] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGG_PAD27INPEN */
|
|
GPIO_PADREGG_PAD27INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGG_PAD27INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGG_PAD27INPEN_Enum;
|
|
|
|
/* ============================================ GPIO PADREGG PAD27PULL [24..24] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGG_PAD27PULL */
|
|
GPIO_PADREGG_PAD27PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGG_PAD27PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGG_PAD27PULL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGG PAD26FNCSEL [19..20] =========================================== */
|
|
typedef enum { /*!< GPIO_PADREGG_PAD26FNCSEL */
|
|
GPIO_PADREGG_PAD26FNCSEL_EXTLF = 0, /*!< EXTLF : Configure as the external LFRC clock signal */
|
|
GPIO_PADREGG_PAD26FNCSEL_M0nCE3 = 1, /*!< M0nCE3 : Configure as the SPI channel 3 nCE signal from IOMSTR0 */
|
|
GPIO_PADREGG_PAD26FNCSEL_TCTB0 = 2, /*!< TCTB0 : Configure as the input/output signal from CTIMER B0 */
|
|
GPIO_PADREGG_PAD26FNCSEL_GPIO26 = 3, /*!< GPIO26 : Configure as GPIO26 */
|
|
} GPIO_PADREGG_PAD26FNCSEL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGG PAD26STRNG [18..18] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGG_PAD26STRNG */
|
|
GPIO_PADREGG_PAD26STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGG_PAD26STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGG_PAD26STRNG_Enum;
|
|
|
|
/* =========================================== GPIO PADREGG PAD26INPEN [17..17] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGG_PAD26INPEN */
|
|
GPIO_PADREGG_PAD26INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGG_PAD26INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGG_PAD26INPEN_Enum;
|
|
|
|
/* ============================================ GPIO PADREGG PAD26PULL [16..16] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGG_PAD26PULL */
|
|
GPIO_PADREGG_PAD26PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGG_PAD26PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGG_PAD26PULL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGG PAD25FNCSEL [11..12] =========================================== */
|
|
typedef enum { /*!< GPIO_PADREGG_PAD25FNCSEL */
|
|
GPIO_PADREGG_PAD25FNCSEL_EXTXT = 0, /*!< EXTXT : Configure as the external XT clock signal */
|
|
GPIO_PADREGG_PAD25FNCSEL_M0nCE2 = 1, /*!< M0nCE2 : Configure as the SPI channel 2 nCE signal from IOMSTR0 */
|
|
GPIO_PADREGG_PAD25FNCSEL_TCTA0 = 2, /*!< TCTA0 : Configure as the input/output signal from CTIMER A0 */
|
|
GPIO_PADREGG_PAD25FNCSEL_GPIO25 = 3, /*!< GPIO25 : Configure as GPIO25 */
|
|
} GPIO_PADREGG_PAD25FNCSEL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGG PAD25STRNG [10..10] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGG_PAD25STRNG */
|
|
GPIO_PADREGG_PAD25STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGG_PAD25STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGG_PAD25STRNG_Enum;
|
|
|
|
/* ============================================ GPIO PADREGG PAD25INPEN [9..9] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGG_PAD25INPEN */
|
|
GPIO_PADREGG_PAD25INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGG_PAD25INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGG_PAD25INPEN_Enum;
|
|
|
|
/* ============================================= GPIO PADREGG PAD25PULL [8..8] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGG_PAD25PULL */
|
|
GPIO_PADREGG_PAD25PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGG_PAD25PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGG_PAD25PULL_Enum;
|
|
|
|
/* ============================================ GPIO PADREGG PAD24FNCSEL [3..4] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGG_PAD24FNCSEL */
|
|
GPIO_PADREGG_PAD24FNCSEL_DIS = 0, /*!< DIS : Pad disabled */
|
|
GPIO_PADREGG_PAD24FNCSEL_M0nCE1 = 1, /*!< M0nCE1 : Configure as the SPI channel 1 nCE signal from IOMSTR0 */
|
|
GPIO_PADREGG_PAD24FNCSEL_CLKOUT = 2, /*!< CLKOUT : Configure as the CLKOUT signal */
|
|
GPIO_PADREGG_PAD24FNCSEL_GPIO24 = 3, /*!< GPIO24 : Configure as GPIO24 */
|
|
} GPIO_PADREGG_PAD24FNCSEL_Enum;
|
|
|
|
/* ============================================ GPIO PADREGG PAD24STRNG [2..2] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGG_PAD24STRNG */
|
|
GPIO_PADREGG_PAD24STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGG_PAD24STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGG_PAD24STRNG_Enum;
|
|
|
|
/* ============================================ GPIO PADREGG PAD24INPEN [1..1] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGG_PAD24INPEN */
|
|
GPIO_PADREGG_PAD24INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGG_PAD24INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGG_PAD24INPEN_Enum;
|
|
|
|
/* ============================================= GPIO PADREGG PAD24PULL [0..0] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGG_PAD24PULL */
|
|
GPIO_PADREGG_PAD24PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGG_PAD24PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGG_PAD24PULL_Enum;
|
|
|
|
/* ======================================================== PADREGH ======================================================== */
|
|
/* =========================================== GPIO PADREGH PAD31FNCSEL [27..28] =========================================== */
|
|
typedef enum { /*!< GPIO_PADREGH_PAD31FNCSEL */
|
|
GPIO_PADREGH_PAD31FNCSEL_ADC6 = 0, /*!< ADC6 : Configure as the analog ADC input 6 signal */
|
|
GPIO_PADREGH_PAD31FNCSEL_M0nCE4 = 1, /*!< M0nCE4 : Configure as the SPI channel 4 nCE signal from IOMSTR0 */
|
|
GPIO_PADREGH_PAD31FNCSEL_TCTA3 = 2, /*!< TCTA3 : Configure as the input/output signal from CTIMER A3 */
|
|
GPIO_PADREGH_PAD31FNCSEL_GPIO31 = 3, /*!< GPIO31 : Configure as GPIO31 */
|
|
} GPIO_PADREGH_PAD31FNCSEL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGH PAD31STRNG [26..26] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGH_PAD31STRNG */
|
|
GPIO_PADREGH_PAD31STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGH_PAD31STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGH_PAD31STRNG_Enum;
|
|
|
|
/* =========================================== GPIO PADREGH PAD31INPEN [25..25] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGH_PAD31INPEN */
|
|
GPIO_PADREGH_PAD31INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGH_PAD31INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGH_PAD31INPEN_Enum;
|
|
|
|
/* ============================================ GPIO PADREGH PAD31PULL [24..24] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGH_PAD31PULL */
|
|
GPIO_PADREGH_PAD31PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGH_PAD31PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGH_PAD31PULL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGH PAD30FNCSEL [19..20] =========================================== */
|
|
typedef enum { /*!< GPIO_PADREGH_PAD30FNCSEL */
|
|
GPIO_PADREGH_PAD30FNCSEL_ADC5 = 0, /*!< ADC5 : Configure as the analog ADC input 5 signal */
|
|
GPIO_PADREGH_PAD30FNCSEL_M1nCE7 = 1, /*!< M1nCE7 : Configure as the SPI channel 7 nCE signal from IOMSTR1 */
|
|
GPIO_PADREGH_PAD30FNCSEL_TCTB2 = 2, /*!< TCTB2 : Configure as the input/output signal from CTIMER B2 */
|
|
GPIO_PADREGH_PAD30FNCSEL_GPIO30 = 3, /*!< GPIO30 : Configure as GPIO30 */
|
|
} GPIO_PADREGH_PAD30FNCSEL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGH PAD30STRNG [18..18] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGH_PAD30STRNG */
|
|
GPIO_PADREGH_PAD30STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGH_PAD30STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGH_PAD30STRNG_Enum;
|
|
|
|
/* =========================================== GPIO PADREGH PAD30INPEN [17..17] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGH_PAD30INPEN */
|
|
GPIO_PADREGH_PAD30INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGH_PAD30INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGH_PAD30INPEN_Enum;
|
|
|
|
/* ============================================ GPIO PADREGH PAD30PULL [16..16] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGH_PAD30PULL */
|
|
GPIO_PADREGH_PAD30PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGH_PAD30PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGH_PAD30PULL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGH PAD29FNCSEL [11..12] =========================================== */
|
|
typedef enum { /*!< GPIO_PADREGH_PAD29FNCSEL */
|
|
GPIO_PADREGH_PAD29FNCSEL_ADC4 = 0, /*!< ADC4 : Configure as the analog ADC input 4 signal */
|
|
GPIO_PADREGH_PAD29FNCSEL_M1nCE6 = 1, /*!< M1nCE6 : Configure as the SPI channel 6 nCE signal from IOMSTR1 */
|
|
GPIO_PADREGH_PAD29FNCSEL_TCTA2 = 2, /*!< TCTA2 : Configure as the input/output signal from CTIMER A2 */
|
|
GPIO_PADREGH_PAD29FNCSEL_GPIO29 = 3, /*!< GPIO29 : Configure as GPIO29 */
|
|
} GPIO_PADREGH_PAD29FNCSEL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGH PAD29STRNG [10..10] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGH_PAD29STRNG */
|
|
GPIO_PADREGH_PAD29STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGH_PAD29STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGH_PAD29STRNG_Enum;
|
|
|
|
/* ============================================ GPIO PADREGH PAD29INPEN [9..9] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGH_PAD29INPEN */
|
|
GPIO_PADREGH_PAD29INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGH_PAD29INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGH_PAD29INPEN_Enum;
|
|
|
|
/* ============================================= GPIO PADREGH PAD29PULL [8..8] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGH_PAD29PULL */
|
|
GPIO_PADREGH_PAD29PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGH_PAD29PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGH_PAD29PULL_Enum;
|
|
|
|
/* ============================================ GPIO PADREGH PAD28FNCSEL [3..4] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGH_PAD28FNCSEL */
|
|
GPIO_PADREGH_PAD28FNCSEL_DIS = 0, /*!< DIS : Pad disabled */
|
|
GPIO_PADREGH_PAD28FNCSEL_M1nCE5 = 1, /*!< M1nCE5 : Configure as the SPI channel 5 nCE signal from IOMSTR1 */
|
|
GPIO_PADREGH_PAD28FNCSEL_TCTB1 = 2, /*!< TCTB1 : Configure as the input/output signal from CTIMER B1 */
|
|
GPIO_PADREGH_PAD28FNCSEL_GPIO28 = 3, /*!< GPIO28 : Configure as GPIO28 */
|
|
} GPIO_PADREGH_PAD28FNCSEL_Enum;
|
|
|
|
/* ============================================ GPIO PADREGH PAD28STRNG [2..2] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGH_PAD28STRNG */
|
|
GPIO_PADREGH_PAD28STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGH_PAD28STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGH_PAD28STRNG_Enum;
|
|
|
|
/* ============================================ GPIO PADREGH PAD28INPEN [1..1] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGH_PAD28INPEN */
|
|
GPIO_PADREGH_PAD28INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGH_PAD28INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGH_PAD28INPEN_Enum;
|
|
|
|
/* ============================================= GPIO PADREGH PAD28PULL [0..0] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGH_PAD28PULL */
|
|
GPIO_PADREGH_PAD28PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGH_PAD28PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGH_PAD28PULL_Enum;
|
|
|
|
/* ======================================================== PADREGI ======================================================== */
|
|
/* =========================================== GPIO PADREGI PAD35FNCSEL [27..28] =========================================== */
|
|
typedef enum { /*!< GPIO_PADREGI_PAD35FNCSEL */
|
|
GPIO_PADREGI_PAD35FNCSEL_DIS = 0, /*!< DIS : Pad disabled */
|
|
GPIO_PADREGI_PAD35FNCSEL_M1nCE0 = 1, /*!< M1nCE0 : Configure as the SPI channel 0 nCE signal from IOMSTR1 */
|
|
GPIO_PADREGI_PAD35FNCSEL_UARTTX = 2, /*!< UARTTX : Configure as the UART TX signal */
|
|
GPIO_PADREGI_PAD35FNCSEL_GPIO35 = 3, /*!< GPIO35 : Configure as GPIO35 */
|
|
} GPIO_PADREGI_PAD35FNCSEL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGI PAD35STRNG [26..26] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGI_PAD35STRNG */
|
|
GPIO_PADREGI_PAD35STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGI_PAD35STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGI_PAD35STRNG_Enum;
|
|
|
|
/* =========================================== GPIO PADREGI PAD35INPEN [25..25] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGI_PAD35INPEN */
|
|
GPIO_PADREGI_PAD35INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGI_PAD35INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGI_PAD35INPEN_Enum;
|
|
|
|
/* ============================================ GPIO PADREGI PAD35PULL [24..24] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGI_PAD35PULL */
|
|
GPIO_PADREGI_PAD35PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGI_PAD35PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGI_PAD35PULL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGI PAD34FNCSEL [19..20] =========================================== */
|
|
typedef enum { /*!< GPIO_PADREGI_PAD34FNCSEL */
|
|
GPIO_PADREGI_PAD34FNCSEL_CMPRF2 = 0, /*!< CMPRF2 : Configure as the analog comparator reference 2 signal */
|
|
GPIO_PADREGI_PAD34FNCSEL_M0nCE7 = 1, /*!< M0nCE7 : Configure as the SPI channel 7 nCE signal from IOMSTR0 */
|
|
GPIO_PADREGI_PAD34FNCSEL_DIS = 2, /*!< DIS : Pad disabled */
|
|
GPIO_PADREGI_PAD34FNCSEL_GPIO34 = 3, /*!< GPIO34 : Configure as GPIO34 */
|
|
} GPIO_PADREGI_PAD34FNCSEL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGI PAD34STRNG [18..18] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGI_PAD34STRNG */
|
|
GPIO_PADREGI_PAD34STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGI_PAD34STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGI_PAD34STRNG_Enum;
|
|
|
|
/* =========================================== GPIO PADREGI PAD34INPEN [17..17] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGI_PAD34INPEN */
|
|
GPIO_PADREGI_PAD34INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGI_PAD34INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGI_PAD34INPEN_Enum;
|
|
|
|
/* ============================================ GPIO PADREGI PAD34PULL [16..16] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGI_PAD34PULL */
|
|
GPIO_PADREGI_PAD34PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGI_PAD34PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGI_PAD34PULL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGI PAD33FNCSEL [11..12] =========================================== */
|
|
typedef enum { /*!< GPIO_PADREGI_PAD33FNCSEL */
|
|
GPIO_PADREGI_PAD33FNCSEL_CMPRF1 = 0, /*!< CMPRF1 : Configure as the analog comparator reference 1 signal */
|
|
GPIO_PADREGI_PAD33FNCSEL_M0nCE6 = 1, /*!< M0nCE6 : Configure as the SPI channel 6 nCE signal from IOMSTR0 */
|
|
GPIO_PADREGI_PAD33FNCSEL_DIS = 2, /*!< DIS : Pad disabled */
|
|
GPIO_PADREGI_PAD33FNCSEL_GPIO33 = 3, /*!< GPIO33 : Configure as GPIO33 */
|
|
} GPIO_PADREGI_PAD33FNCSEL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGI PAD33STRNG [10..10] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGI_PAD33STRNG */
|
|
GPIO_PADREGI_PAD33STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGI_PAD33STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGI_PAD33STRNG_Enum;
|
|
|
|
/* ============================================ GPIO PADREGI PAD33INPEN [9..9] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGI_PAD33INPEN */
|
|
GPIO_PADREGI_PAD33INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGI_PAD33INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGI_PAD33INPEN_Enum;
|
|
|
|
/* ============================================= GPIO PADREGI PAD33PULL [8..8] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGI_PAD33PULL */
|
|
GPIO_PADREGI_PAD33PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGI_PAD33PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGI_PAD33PULL_Enum;
|
|
|
|
/* ============================================ GPIO PADREGI PAD32FNCSEL [3..4] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGI_PAD32FNCSEL */
|
|
GPIO_PADREGI_PAD32FNCSEL_ADC7 = 0, /*!< ADC7 : Configure as the analog ADC input 7 signal */
|
|
GPIO_PADREGI_PAD32FNCSEL_M0nCE5 = 1, /*!< M0nCE5 : Configure as the SPI channel 5 nCE signal from IOMSTR0 */
|
|
GPIO_PADREGI_PAD32FNCSEL_TCTB3 = 2, /*!< TCTB3 : Configure as the input/output signal from CTIMER B3 */
|
|
GPIO_PADREGI_PAD32FNCSEL_GPIO32 = 3, /*!< GPIO32 : Configure as GPIO32 */
|
|
} GPIO_PADREGI_PAD32FNCSEL_Enum;
|
|
|
|
/* ============================================ GPIO PADREGI PAD32STRNG [2..2] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGI_PAD32STRNG */
|
|
GPIO_PADREGI_PAD32STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGI_PAD32STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGI_PAD32STRNG_Enum;
|
|
|
|
/* ============================================ GPIO PADREGI PAD32INPEN [1..1] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGI_PAD32INPEN */
|
|
GPIO_PADREGI_PAD32INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGI_PAD32INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGI_PAD32INPEN_Enum;
|
|
|
|
/* ============================================= GPIO PADREGI PAD32PULL [0..0] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGI_PAD32PULL */
|
|
GPIO_PADREGI_PAD32PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGI_PAD32PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGI_PAD32PULL_Enum;
|
|
|
|
/* ======================================================== PADREGJ ======================================================== */
|
|
/* =========================================== GPIO PADREGJ PAD39FNCSEL [27..28] =========================================== */
|
|
typedef enum { /*!< GPIO_PADREGJ_PAD39FNCSEL */
|
|
GPIO_PADREGJ_PAD39FNCSEL_TRIG2 = 0, /*!< TRIG2 : Configure as the ADC Trigger 2 signal */
|
|
GPIO_PADREGJ_PAD39FNCSEL_UARTTX = 1, /*!< UARTTX : Configure as the UART TX signal */
|
|
GPIO_PADREGJ_PAD39FNCSEL_CLKOUT = 2, /*!< CLKOUT : Configure as the CLKOUT signal */
|
|
GPIO_PADREGJ_PAD39FNCSEL_GPIO39 = 3, /*!< GPIO39 : Configure as GPIO39 */
|
|
} GPIO_PADREGJ_PAD39FNCSEL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGJ PAD39STRNG [26..26] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGJ_PAD39STRNG */
|
|
GPIO_PADREGJ_PAD39STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGJ_PAD39STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGJ_PAD39STRNG_Enum;
|
|
|
|
/* =========================================== GPIO PADREGJ PAD39INPEN [25..25] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGJ_PAD39INPEN */
|
|
GPIO_PADREGJ_PAD39INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGJ_PAD39INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGJ_PAD39INPEN_Enum;
|
|
|
|
/* ============================================ GPIO PADREGJ PAD39PULL [24..24] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGJ_PAD39PULL */
|
|
GPIO_PADREGJ_PAD39PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGJ_PAD39PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGJ_PAD39PULL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGJ PAD38FNCSEL [19..20] =========================================== */
|
|
typedef enum { /*!< GPIO_PADREGJ_PAD38FNCSEL */
|
|
GPIO_PADREGJ_PAD38FNCSEL_TRIG1 = 0, /*!< TRIG1 : Configure as the ADC Trigger 1 signal */
|
|
GPIO_PADREGJ_PAD38FNCSEL_M1nCE3 = 1, /*!< M1nCE3 : Configure as the SPI channel 3 nCE signal from IOMSTR1 */
|
|
GPIO_PADREGJ_PAD38FNCSEL_UACTS = 2, /*!< UACTS : Configure as the UART CTS signal */
|
|
GPIO_PADREGJ_PAD38FNCSEL_GPIO38 = 3, /*!< GPIO38 : Configure as GPIO38 */
|
|
} GPIO_PADREGJ_PAD38FNCSEL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGJ PAD38STRNG [18..18] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGJ_PAD38STRNG */
|
|
GPIO_PADREGJ_PAD38STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGJ_PAD38STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGJ_PAD38STRNG_Enum;
|
|
|
|
/* =========================================== GPIO PADREGJ PAD38INPEN [17..17] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGJ_PAD38INPEN */
|
|
GPIO_PADREGJ_PAD38INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGJ_PAD38INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGJ_PAD38INPEN_Enum;
|
|
|
|
/* ============================================ GPIO PADREGJ PAD38PULL [16..16] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGJ_PAD38PULL */
|
|
GPIO_PADREGJ_PAD38PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGJ_PAD38PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGJ_PAD38PULL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGJ PAD37FNCSEL [11..12] =========================================== */
|
|
typedef enum { /*!< GPIO_PADREGJ_PAD37FNCSEL */
|
|
GPIO_PADREGJ_PAD37FNCSEL_TRIG0 = 0, /*!< TRIG0 : Configure as the ADC Trigger 0 signal */
|
|
GPIO_PADREGJ_PAD37FNCSEL_M1nCE2 = 1, /*!< M1nCE2 : Configure as the SPI channel 2 nCE signal from IOMSTR1 */
|
|
GPIO_PADREGJ_PAD37FNCSEL_UARTS = 2, /*!< UARTS : Configure as the UART RTS signal */
|
|
GPIO_PADREGJ_PAD37FNCSEL_GPIO37 = 3, /*!< GPIO37 : Configure as GPIO37 */
|
|
} GPIO_PADREGJ_PAD37FNCSEL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGJ PAD37STRNG [10..10] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGJ_PAD37STRNG */
|
|
GPIO_PADREGJ_PAD37STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGJ_PAD37STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGJ_PAD37STRNG_Enum;
|
|
|
|
/* ============================================ GPIO PADREGJ PAD37INPEN [9..9] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGJ_PAD37INPEN */
|
|
GPIO_PADREGJ_PAD37INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGJ_PAD37INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGJ_PAD37INPEN_Enum;
|
|
|
|
/* ============================================= GPIO PADREGJ PAD37PULL [8..8] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGJ_PAD37PULL */
|
|
GPIO_PADREGJ_PAD37PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGJ_PAD37PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGJ_PAD37PULL_Enum;
|
|
|
|
/* ============================================ GPIO PADREGJ PAD36FNCSEL [3..4] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGJ_PAD36FNCSEL */
|
|
GPIO_PADREGJ_PAD36FNCSEL_DIS = 0, /*!< DIS : Pad disabled */
|
|
GPIO_PADREGJ_PAD36FNCSEL_M1nCE1 = 1, /*!< M1nCE1 : Configure as the SPI channel 1 nCE signal from IOMSTR1 */
|
|
GPIO_PADREGJ_PAD36FNCSEL_UARTRX = 2, /*!< UARTRX : Configure as the UART RX signal */
|
|
GPIO_PADREGJ_PAD36FNCSEL_GPIO36 = 3, /*!< GPIO36 : Configure as GPIO36 */
|
|
} GPIO_PADREGJ_PAD36FNCSEL_Enum;
|
|
|
|
/* ============================================ GPIO PADREGJ PAD36STRNG [2..2] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGJ_PAD36STRNG */
|
|
GPIO_PADREGJ_PAD36STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGJ_PAD36STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGJ_PAD36STRNG_Enum;
|
|
|
|
/* ============================================ GPIO PADREGJ PAD36INPEN [1..1] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGJ_PAD36INPEN */
|
|
GPIO_PADREGJ_PAD36INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGJ_PAD36INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGJ_PAD36INPEN_Enum;
|
|
|
|
/* ============================================= GPIO PADREGJ PAD36PULL [0..0] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGJ_PAD36PULL */
|
|
GPIO_PADREGJ_PAD36PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGJ_PAD36PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGJ_PAD36PULL_Enum;
|
|
|
|
/* ======================================================== PADREGK ======================================================== */
|
|
/* =========================================== GPIO PADREGK PAD43FNCSEL [27..28] =========================================== */
|
|
typedef enum { /*!< GPIO_PADREGK_PAD43FNCSEL */
|
|
GPIO_PADREGK_PAD43FNCSEL_TRIG6 = 0, /*!< TRIG6 : Configure as the ADC Trigger 6 signal */
|
|
GPIO_PADREGK_PAD43FNCSEL_M0nCE1 = 1, /*!< M0nCE1 : Configure as the SPI channel 1 nCE signal from IOMSTR0 */
|
|
GPIO_PADREGK_PAD43FNCSEL_TCTB0 = 2, /*!< TCTB0 : Configure as the input/output signal from CTIMER B0 */
|
|
GPIO_PADREGK_PAD43FNCSEL_GPIO43 = 3, /*!< GPIO43 : Configure as GPIO43 */
|
|
} GPIO_PADREGK_PAD43FNCSEL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGK PAD43STRNG [26..26] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGK_PAD43STRNG */
|
|
GPIO_PADREGK_PAD43STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGK_PAD43STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGK_PAD43STRNG_Enum;
|
|
|
|
/* =========================================== GPIO PADREGK PAD43INPEN [25..25] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGK_PAD43INPEN */
|
|
GPIO_PADREGK_PAD43INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGK_PAD43INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGK_PAD43INPEN_Enum;
|
|
|
|
/* ============================================ GPIO PADREGK PAD43PULL [24..24] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGK_PAD43PULL */
|
|
GPIO_PADREGK_PAD43PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGK_PAD43PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGK_PAD43PULL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGK PAD42FNCSEL [19..20] =========================================== */
|
|
typedef enum { /*!< GPIO_PADREGK_PAD42FNCSEL */
|
|
GPIO_PADREGK_PAD42FNCSEL_TRIG5 = 0, /*!< TRIG5 : Configure as the ADC Trigger 5 signal */
|
|
GPIO_PADREGK_PAD42FNCSEL_M0nCE0 = 1, /*!< M0nCE0 : Configure as the SPI channel 0 nCE signal from IOMSTR0 */
|
|
GPIO_PADREGK_PAD42FNCSEL_TCTA0 = 2, /*!< TCTA0 : Configure as the input/output signal from CTIMER A0 */
|
|
GPIO_PADREGK_PAD42FNCSEL_GPIO42 = 3, /*!< GPIO42 : Configure as GPIO42 */
|
|
} GPIO_PADREGK_PAD42FNCSEL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGK PAD42STRNG [18..18] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGK_PAD42STRNG */
|
|
GPIO_PADREGK_PAD42STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGK_PAD42STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGK_PAD42STRNG_Enum;
|
|
|
|
/* =========================================== GPIO PADREGK PAD42INPEN [17..17] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGK_PAD42INPEN */
|
|
GPIO_PADREGK_PAD42INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGK_PAD42INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGK_PAD42INPEN_Enum;
|
|
|
|
/* ============================================ GPIO PADREGK PAD42PULL [16..16] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGK_PAD42PULL */
|
|
GPIO_PADREGK_PAD42PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGK_PAD42PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGK_PAD42PULL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGK PAD41FNCSEL [11..12] =========================================== */
|
|
typedef enum { /*!< GPIO_PADREGK_PAD41FNCSEL */
|
|
GPIO_PADREGK_PAD41FNCSEL_TRIG4 = 0, /*!< TRIG4 : Configure as the ADC Trigger 4 signal */
|
|
GPIO_PADREGK_PAD41FNCSEL_DIS = 1, /*!< DIS : Pad disabled */
|
|
GPIO_PADREGK_PAD41FNCSEL_SWO = 2, /*!< SWO : Configure as the serial wire debug SWO signal */
|
|
GPIO_PADREGK_PAD41FNCSEL_GPIO41 = 3, /*!< GPIO41 : Configure as GPIO41 */
|
|
} GPIO_PADREGK_PAD41FNCSEL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGK PAD41STRNG [10..10] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGK_PAD41STRNG */
|
|
GPIO_PADREGK_PAD41STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGK_PAD41STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGK_PAD41STRNG_Enum;
|
|
|
|
/* ============================================ GPIO PADREGK PAD41INPEN [9..9] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGK_PAD41INPEN */
|
|
GPIO_PADREGK_PAD41INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGK_PAD41INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGK_PAD41INPEN_Enum;
|
|
|
|
/* ============================================= GPIO PADREGK PAD41PULL [8..8] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGK_PAD41PULL */
|
|
GPIO_PADREGK_PAD41PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGK_PAD41PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGK_PAD41PULL_Enum;
|
|
|
|
/* ============================================ GPIO PADREGK PAD40FNCSEL [3..4] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGK_PAD40FNCSEL */
|
|
GPIO_PADREGK_PAD40FNCSEL_TRIG3 = 0, /*!< TRIG3 : Configure as the ADC Trigger 3 signal */
|
|
GPIO_PADREGK_PAD40FNCSEL_UARTRX = 1, /*!< UARTRX : Configure as the UART RX signal */
|
|
GPIO_PADREGK_PAD40FNCSEL_DIS = 2, /*!< DIS : Pad disabled */
|
|
GPIO_PADREGK_PAD40FNCSEL_GPIO40 = 3, /*!< GPIO40 : Configure as GPIO40 */
|
|
} GPIO_PADREGK_PAD40FNCSEL_Enum;
|
|
|
|
/* ============================================ GPIO PADREGK PAD40STRNG [2..2] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGK_PAD40STRNG */
|
|
GPIO_PADREGK_PAD40STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGK_PAD40STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGK_PAD40STRNG_Enum;
|
|
|
|
/* ============================================ GPIO PADREGK PAD40INPEN [1..1] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGK_PAD40INPEN */
|
|
GPIO_PADREGK_PAD40INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGK_PAD40INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGK_PAD40INPEN_Enum;
|
|
|
|
/* ============================================= GPIO PADREGK PAD40PULL [0..0] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGK_PAD40PULL */
|
|
GPIO_PADREGK_PAD40PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGK_PAD40PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGK_PAD40PULL_Enum;
|
|
|
|
/* ======================================================== PADREGL ======================================================== */
|
|
/* =========================================== GPIO PADREGL PAD47FNCSEL [27..28] =========================================== */
|
|
typedef enum { /*!< GPIO_PADREGL_PAD47FNCSEL */
|
|
GPIO_PADREGL_PAD47FNCSEL_DIS = 0, /*!< DIS : Pad disabled */
|
|
GPIO_PADREGL_PAD47FNCSEL_M0nCE5 = 1, /*!< M0nCE5 : Configure as the SPI channel 5 nCE signal from IOMSTR0 */
|
|
GPIO_PADREGL_PAD47FNCSEL_TCTB2 = 2, /*!< TCTB2 : Configure as the input/output signal from CTIMER B2 */
|
|
GPIO_PADREGL_PAD47FNCSEL_GPIO47 = 3, /*!< GPIO47 : Configure as GPIO47 */
|
|
} GPIO_PADREGL_PAD47FNCSEL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGL PAD47STRNG [26..26] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGL_PAD47STRNG */
|
|
GPIO_PADREGL_PAD47STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGL_PAD47STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGL_PAD47STRNG_Enum;
|
|
|
|
/* =========================================== GPIO PADREGL PAD47INPEN [25..25] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGL_PAD47INPEN */
|
|
GPIO_PADREGL_PAD47INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGL_PAD47INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGL_PAD47INPEN_Enum;
|
|
|
|
/* ============================================ GPIO PADREGL PAD47PULL [24..24] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGL_PAD47PULL */
|
|
GPIO_PADREGL_PAD47PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGL_PAD47PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGL_PAD47PULL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGL PAD46FNCSEL [19..20] =========================================== */
|
|
typedef enum { /*!< GPIO_PADREGL_PAD46FNCSEL */
|
|
GPIO_PADREGL_PAD46FNCSEL_DIS = 0, /*!< DIS : Pad disabled */
|
|
GPIO_PADREGL_PAD46FNCSEL_M0nCE4 = 1, /*!< M0nCE4 : Configure as the SPI channel 4 nCE signal from IOMSTR0 */
|
|
GPIO_PADREGL_PAD46FNCSEL_TCTA2 = 2, /*!< TCTA2 : Configure as the input/output signal from CTIMER A2 */
|
|
GPIO_PADREGL_PAD46FNCSEL_GPIO46 = 3, /*!< GPIO46 : Configure as GPIO46 */
|
|
} GPIO_PADREGL_PAD46FNCSEL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGL PAD46STRNG [18..18] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGL_PAD46STRNG */
|
|
GPIO_PADREGL_PAD46STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGL_PAD46STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGL_PAD46STRNG_Enum;
|
|
|
|
/* =========================================== GPIO PADREGL PAD46INPEN [17..17] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGL_PAD46INPEN */
|
|
GPIO_PADREGL_PAD46INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGL_PAD46INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGL_PAD46INPEN_Enum;
|
|
|
|
/* ============================================ GPIO PADREGL PAD46PULL [16..16] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGL_PAD46PULL */
|
|
GPIO_PADREGL_PAD46PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGL_PAD46PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGL_PAD46PULL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGL PAD45FNCSEL [11..12] =========================================== */
|
|
typedef enum { /*!< GPIO_PADREGL_PAD45FNCSEL */
|
|
GPIO_PADREGL_PAD45FNCSEL_DIS = 0, /*!< DIS : Pad disabled */
|
|
GPIO_PADREGL_PAD45FNCSEL_M0nCE3 = 1, /*!< M0nCE3 : Configure as the SPI channel 3 nCE signal from IOMSTR0 */
|
|
GPIO_PADREGL_PAD45FNCSEL_TCTB1 = 2, /*!< TCTB1 : Configure as the input/output signal from CTIMER B1 */
|
|
GPIO_PADREGL_PAD45FNCSEL_GPIO45 = 3, /*!< GPIO45 : Configure as GPIO45 */
|
|
} GPIO_PADREGL_PAD45FNCSEL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGL PAD45STRNG [10..10] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGL_PAD45STRNG */
|
|
GPIO_PADREGL_PAD45STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGL_PAD45STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGL_PAD45STRNG_Enum;
|
|
|
|
/* ============================================ GPIO PADREGL PAD45INPEN [9..9] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGL_PAD45INPEN */
|
|
GPIO_PADREGL_PAD45INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGL_PAD45INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGL_PAD45INPEN_Enum;
|
|
|
|
/* ============================================= GPIO PADREGL PAD45PULL [8..8] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGL_PAD45PULL */
|
|
GPIO_PADREGL_PAD45PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGL_PAD45PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGL_PAD45PULL_Enum;
|
|
|
|
/* ============================================ GPIO PADREGL PAD44FNCSEL [3..4] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGL_PAD44FNCSEL */
|
|
GPIO_PADREGL_PAD44FNCSEL_TRIG7 = 0, /*!< TRIG7 : Configure as the ADC Trigger 7 signal */
|
|
GPIO_PADREGL_PAD44FNCSEL_M0nCE2 = 1, /*!< M0nCE2 : Configure as the SPI channel 2 nCE signal from IOMSTR0 */
|
|
GPIO_PADREGL_PAD44FNCSEL_TCTA1 = 2, /*!< TCTA1 : Configure as the input/output signal from CTIMER A1 */
|
|
GPIO_PADREGL_PAD44FNCSEL_GPIO44 = 3, /*!< GPIO44 : Configure as GPIO44 */
|
|
} GPIO_PADREGL_PAD44FNCSEL_Enum;
|
|
|
|
/* ============================================ GPIO PADREGL PAD44STRNG [2..2] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGL_PAD44STRNG */
|
|
GPIO_PADREGL_PAD44STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGL_PAD44STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGL_PAD44STRNG_Enum;
|
|
|
|
/* ============================================ GPIO PADREGL PAD44INPEN [1..1] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGL_PAD44INPEN */
|
|
GPIO_PADREGL_PAD44INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGL_PAD44INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGL_PAD44INPEN_Enum;
|
|
|
|
/* ============================================= GPIO PADREGL PAD44PULL [0..0] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGL_PAD44PULL */
|
|
GPIO_PADREGL_PAD44PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGL_PAD44PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGL_PAD44PULL_Enum;
|
|
|
|
/* ======================================================== PADREGM ======================================================== */
|
|
/* =========================================== GPIO PADREGM PAD49FNCSEL [11..12] =========================================== */
|
|
typedef enum { /*!< GPIO_PADREGM_PAD49FNCSEL */
|
|
GPIO_PADREGM_PAD49FNCSEL_DIS = 0, /*!< DIS : Pad disabled */
|
|
GPIO_PADREGM_PAD49FNCSEL_M0nCE7 = 1, /*!< M0nCE7 : Configure as the SPI channel 7 nCE signal from IOMSTR0 */
|
|
GPIO_PADREGM_PAD49FNCSEL_TCTB3 = 2, /*!< TCTB3 : Configure as the input/output signal from CTIMER B3 */
|
|
GPIO_PADREGM_PAD49FNCSEL_GPIO49 = 3, /*!< GPIO49 : Configure as GPIO49 */
|
|
} GPIO_PADREGM_PAD49FNCSEL_Enum;
|
|
|
|
/* =========================================== GPIO PADREGM PAD49STRNG [10..10] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGM_PAD49STRNG */
|
|
GPIO_PADREGM_PAD49STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGM_PAD49STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGM_PAD49STRNG_Enum;
|
|
|
|
/* ============================================ GPIO PADREGM PAD49INPEN [9..9] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGM_PAD49INPEN */
|
|
GPIO_PADREGM_PAD49INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGM_PAD49INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGM_PAD49INPEN_Enum;
|
|
|
|
/* ============================================= GPIO PADREGM PAD49PULL [8..8] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGM_PAD49PULL */
|
|
GPIO_PADREGM_PAD49PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGM_PAD49PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGM_PAD49PULL_Enum;
|
|
|
|
/* ============================================ GPIO PADREGM PAD48FNCSEL [3..4] ============================================ */
|
|
typedef enum { /*!< GPIO_PADREGM_PAD48FNCSEL */
|
|
GPIO_PADREGM_PAD48FNCSEL_DIS = 0, /*!< DIS : Pad disabled */
|
|
GPIO_PADREGM_PAD48FNCSEL_M0nCE6 = 1, /*!< M0nCE6 : Configure as the SPI channel 6 nCE signal from IOMSTR0 */
|
|
GPIO_PADREGM_PAD48FNCSEL_TCTA3 = 2, /*!< TCTA3 : Configure as the input/output signal from CTIMER A3 */
|
|
GPIO_PADREGM_PAD48FNCSEL_GPIO48 = 3, /*!< GPIO48 : Configure as GPIO48 */
|
|
} GPIO_PADREGM_PAD48FNCSEL_Enum;
|
|
|
|
/* ============================================ GPIO PADREGM PAD48STRNG [2..2] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGM_PAD48STRNG */
|
|
GPIO_PADREGM_PAD48STRNG_LOW = 0, /*!< LOW : Low drive strength */
|
|
GPIO_PADREGM_PAD48STRNG_HIGH = 1, /*!< HIGH : High drive strength */
|
|
} GPIO_PADREGM_PAD48STRNG_Enum;
|
|
|
|
/* ============================================ GPIO PADREGM PAD48INPEN [1..1] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGM_PAD48INPEN */
|
|
GPIO_PADREGM_PAD48INPEN_DIS = 0, /*!< DIS : Pad input disabled */
|
|
GPIO_PADREGM_PAD48INPEN_EN = 1, /*!< EN : Pad input enabled */
|
|
} GPIO_PADREGM_PAD48INPEN_Enum;
|
|
|
|
/* ============================================= GPIO PADREGM PAD48PULL [0..0] ============================================= */
|
|
typedef enum { /*!< GPIO_PADREGM_PAD48PULL */
|
|
GPIO_PADREGM_PAD48PULL_DIS = 0, /*!< DIS : Pullup disabled */
|
|
GPIO_PADREGM_PAD48PULL_EN = 1, /*!< EN : Pullup enabled */
|
|
} GPIO_PADREGM_PAD48PULL_Enum;
|
|
|
|
/* ========================================================= CFGA ========================================================== */
|
|
/* ============================================= GPIO CFGA GPIO7INTD [31..31] ============================================== */
|
|
typedef enum { /*!< GPIO_CFGA_GPIO7INTD */
|
|
GPIO_CFGA_GPIO7INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGA_GPIO7INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGA_GPIO7INTD_Enum;
|
|
|
|
/* ============================================ GPIO CFGA GPIO7OUTCFG [29..30] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGA_GPIO7OUTCFG */
|
|
GPIO_CFGA_GPIO7OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGA_GPIO7OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGA_GPIO7OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGA_GPIO7OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGA_GPIO7OUTCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGA GPIO7INCFG [28..28] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGA_GPIO7INCFG */
|
|
GPIO_CFGA_GPIO7INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGA_GPIO7INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGA_GPIO7INCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGA GPIO6INTD [27..27] ============================================== */
|
|
typedef enum { /*!< GPIO_CFGA_GPIO6INTD */
|
|
GPIO_CFGA_GPIO6INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGA_GPIO6INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGA_GPIO6INTD_Enum;
|
|
|
|
/* ============================================ GPIO CFGA GPIO6OUTCFG [25..26] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGA_GPIO6OUTCFG */
|
|
GPIO_CFGA_GPIO6OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGA_GPIO6OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGA_GPIO6OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGA_GPIO6OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGA_GPIO6OUTCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGA GPIO6INCFG [24..24] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGA_GPIO6INCFG */
|
|
GPIO_CFGA_GPIO6INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGA_GPIO6INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGA_GPIO6INCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGA GPIO5INTD [23..23] ============================================== */
|
|
typedef enum { /*!< GPIO_CFGA_GPIO5INTD */
|
|
GPIO_CFGA_GPIO5INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGA_GPIO5INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGA_GPIO5INTD_Enum;
|
|
|
|
/* ============================================ GPIO CFGA GPIO5OUTCFG [21..22] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGA_GPIO5OUTCFG */
|
|
GPIO_CFGA_GPIO5OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGA_GPIO5OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGA_GPIO5OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGA_GPIO5OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGA_GPIO5OUTCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGA GPIO5INCFG [20..20] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGA_GPIO5INCFG */
|
|
GPIO_CFGA_GPIO5INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGA_GPIO5INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGA_GPIO5INCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGA GPIO4INTD [19..19] ============================================== */
|
|
typedef enum { /*!< GPIO_CFGA_GPIO4INTD */
|
|
GPIO_CFGA_GPIO4INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGA_GPIO4INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGA_GPIO4INTD_Enum;
|
|
|
|
/* ============================================ GPIO CFGA GPIO4OUTCFG [17..18] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGA_GPIO4OUTCFG */
|
|
GPIO_CFGA_GPIO4OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGA_GPIO4OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGA_GPIO4OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGA_GPIO4OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGA_GPIO4OUTCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGA GPIO4INCFG [16..16] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGA_GPIO4INCFG */
|
|
GPIO_CFGA_GPIO4INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGA_GPIO4INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGA_GPIO4INCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGA GPIO3INTD [15..15] ============================================== */
|
|
typedef enum { /*!< GPIO_CFGA_GPIO3INTD */
|
|
GPIO_CFGA_GPIO3INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGA_GPIO3INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGA_GPIO3INTD_Enum;
|
|
|
|
/* ============================================ GPIO CFGA GPIO3OUTCFG [13..14] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGA_GPIO3OUTCFG */
|
|
GPIO_CFGA_GPIO3OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGA_GPIO3OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGA_GPIO3OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGA_GPIO3OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGA_GPIO3OUTCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGA GPIO3INCFG [12..12] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGA_GPIO3INCFG */
|
|
GPIO_CFGA_GPIO3INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGA_GPIO3INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGA_GPIO3INCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGA GPIO2INTD [11..11] ============================================== */
|
|
typedef enum { /*!< GPIO_CFGA_GPIO2INTD */
|
|
GPIO_CFGA_GPIO2INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGA_GPIO2INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGA_GPIO2INTD_Enum;
|
|
|
|
/* ============================================= GPIO CFGA GPIO2OUTCFG [9..10] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGA_GPIO2OUTCFG */
|
|
GPIO_CFGA_GPIO2OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGA_GPIO2OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGA_GPIO2OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGA_GPIO2OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGA_GPIO2OUTCFG_Enum;
|
|
|
|
/* ============================================== GPIO CFGA GPIO2INCFG [8..8] ============================================== */
|
|
typedef enum { /*!< GPIO_CFGA_GPIO2INCFG */
|
|
GPIO_CFGA_GPIO2INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGA_GPIO2INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGA_GPIO2INCFG_Enum;
|
|
|
|
/* ============================================== GPIO CFGA GPIO1INTD [7..7] =============================================== */
|
|
typedef enum { /*!< GPIO_CFGA_GPIO1INTD */
|
|
GPIO_CFGA_GPIO1INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGA_GPIO1INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGA_GPIO1INTD_Enum;
|
|
|
|
/* ============================================= GPIO CFGA GPIO1OUTCFG [5..6] ============================================== */
|
|
typedef enum { /*!< GPIO_CFGA_GPIO1OUTCFG */
|
|
GPIO_CFGA_GPIO1OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGA_GPIO1OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGA_GPIO1OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGA_GPIO1OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGA_GPIO1OUTCFG_Enum;
|
|
|
|
/* ============================================== GPIO CFGA GPIO1INCFG [4..4] ============================================== */
|
|
typedef enum { /*!< GPIO_CFGA_GPIO1INCFG */
|
|
GPIO_CFGA_GPIO1INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGA_GPIO1INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGA_GPIO1INCFG_Enum;
|
|
|
|
/* ============================================== GPIO CFGA GPIO0INTD [3..3] =============================================== */
|
|
typedef enum { /*!< GPIO_CFGA_GPIO0INTD */
|
|
GPIO_CFGA_GPIO0INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGA_GPIO0INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGA_GPIO0INTD_Enum;
|
|
|
|
/* ============================================= GPIO CFGA GPIO0OUTCFG [1..2] ============================================== */
|
|
typedef enum { /*!< GPIO_CFGA_GPIO0OUTCFG */
|
|
GPIO_CFGA_GPIO0OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGA_GPIO0OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGA_GPIO0OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGA_GPIO0OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGA_GPIO0OUTCFG_Enum;
|
|
|
|
/* ============================================== GPIO CFGA GPIO0INCFG [0..0] ============================================== */
|
|
typedef enum { /*!< GPIO_CFGA_GPIO0INCFG */
|
|
GPIO_CFGA_GPIO0INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGA_GPIO0INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGA_GPIO0INCFG_Enum;
|
|
|
|
/* ========================================================= CFGB ========================================================== */
|
|
/* ============================================= GPIO CFGB GPIO15INTD [31..31] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGB_GPIO15INTD */
|
|
GPIO_CFGB_GPIO15INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGB_GPIO15INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGB_GPIO15INTD_Enum;
|
|
|
|
/* ============================================ GPIO CFGB GPIO15OUTCFG [29..30] ============================================ */
|
|
typedef enum { /*!< GPIO_CFGB_GPIO15OUTCFG */
|
|
GPIO_CFGB_GPIO15OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGB_GPIO15OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGB_GPIO15OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGB_GPIO15OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGB_GPIO15OUTCFG_Enum;
|
|
|
|
/* ============================================ GPIO CFGB GPIO15INCFG [28..28] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGB_GPIO15INCFG */
|
|
GPIO_CFGB_GPIO15INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGB_GPIO15INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGB_GPIO15INCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGB GPIO14INTD [27..27] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGB_GPIO14INTD */
|
|
GPIO_CFGB_GPIO14INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGB_GPIO14INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGB_GPIO14INTD_Enum;
|
|
|
|
/* ============================================ GPIO CFGB GPIO14OUTCFG [25..26] ============================================ */
|
|
typedef enum { /*!< GPIO_CFGB_GPIO14OUTCFG */
|
|
GPIO_CFGB_GPIO14OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGB_GPIO14OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGB_GPIO14OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGB_GPIO14OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGB_GPIO14OUTCFG_Enum;
|
|
|
|
/* ============================================ GPIO CFGB GPIO14INCFG [24..24] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGB_GPIO14INCFG */
|
|
GPIO_CFGB_GPIO14INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGB_GPIO14INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGB_GPIO14INCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGB GPIO13INTD [23..23] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGB_GPIO13INTD */
|
|
GPIO_CFGB_GPIO13INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGB_GPIO13INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGB_GPIO13INTD_Enum;
|
|
|
|
/* ============================================ GPIO CFGB GPIO13OUTCFG [21..22] ============================================ */
|
|
typedef enum { /*!< GPIO_CFGB_GPIO13OUTCFG */
|
|
GPIO_CFGB_GPIO13OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGB_GPIO13OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGB_GPIO13OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGB_GPIO13OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGB_GPIO13OUTCFG_Enum;
|
|
|
|
/* ============================================ GPIO CFGB GPIO13INCFG [20..20] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGB_GPIO13INCFG */
|
|
GPIO_CFGB_GPIO13INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGB_GPIO13INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGB_GPIO13INCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGB GPIO12INTD [19..19] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGB_GPIO12INTD */
|
|
GPIO_CFGB_GPIO12INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGB_GPIO12INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGB_GPIO12INTD_Enum;
|
|
|
|
/* ============================================ GPIO CFGB GPIO12OUTCFG [17..18] ============================================ */
|
|
typedef enum { /*!< GPIO_CFGB_GPIO12OUTCFG */
|
|
GPIO_CFGB_GPIO12OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGB_GPIO12OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGB_GPIO12OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGB_GPIO12OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGB_GPIO12OUTCFG_Enum;
|
|
|
|
/* ============================================ GPIO CFGB GPIO12INCFG [16..16] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGB_GPIO12INCFG */
|
|
GPIO_CFGB_GPIO12INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGB_GPIO12INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGB_GPIO12INCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGB GPIO11INTD [15..15] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGB_GPIO11INTD */
|
|
GPIO_CFGB_GPIO11INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGB_GPIO11INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGB_GPIO11INTD_Enum;
|
|
|
|
/* ============================================ GPIO CFGB GPIO11OUTCFG [13..14] ============================================ */
|
|
typedef enum { /*!< GPIO_CFGB_GPIO11OUTCFG */
|
|
GPIO_CFGB_GPIO11OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGB_GPIO11OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGB_GPIO11OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGB_GPIO11OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGB_GPIO11OUTCFG_Enum;
|
|
|
|
/* ============================================ GPIO CFGB GPIO11INCFG [12..12] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGB_GPIO11INCFG */
|
|
GPIO_CFGB_GPIO11INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGB_GPIO11INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGB_GPIO11INCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGB GPIO10INTD [11..11] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGB_GPIO10INTD */
|
|
GPIO_CFGB_GPIO10INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGB_GPIO10INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGB_GPIO10INTD_Enum;
|
|
|
|
/* ============================================ GPIO CFGB GPIO10OUTCFG [9..10] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGB_GPIO10OUTCFG */
|
|
GPIO_CFGB_GPIO10OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGB_GPIO10OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGB_GPIO10OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGB_GPIO10OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGB_GPIO10OUTCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGB GPIO10INCFG [8..8] ============================================== */
|
|
typedef enum { /*!< GPIO_CFGB_GPIO10INCFG */
|
|
GPIO_CFGB_GPIO10INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGB_GPIO10INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGB_GPIO10INCFG_Enum;
|
|
|
|
/* ============================================== GPIO CFGB GPIO9INTD [7..7] =============================================== */
|
|
typedef enum { /*!< GPIO_CFGB_GPIO9INTD */
|
|
GPIO_CFGB_GPIO9INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGB_GPIO9INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGB_GPIO9INTD_Enum;
|
|
|
|
/* ============================================= GPIO CFGB GPIO9OUTCFG [5..6] ============================================== */
|
|
typedef enum { /*!< GPIO_CFGB_GPIO9OUTCFG */
|
|
GPIO_CFGB_GPIO9OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGB_GPIO9OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGB_GPIO9OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGB_GPIO9OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGB_GPIO9OUTCFG_Enum;
|
|
|
|
/* ============================================== GPIO CFGB GPIO9INCFG [4..4] ============================================== */
|
|
typedef enum { /*!< GPIO_CFGB_GPIO9INCFG */
|
|
GPIO_CFGB_GPIO9INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGB_GPIO9INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGB_GPIO9INCFG_Enum;
|
|
|
|
/* ============================================== GPIO CFGB GPIO8INTD [3..3] =============================================== */
|
|
typedef enum { /*!< GPIO_CFGB_GPIO8INTD */
|
|
GPIO_CFGB_GPIO8INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGB_GPIO8INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGB_GPIO8INTD_Enum;
|
|
|
|
/* ============================================= GPIO CFGB GPIO8OUTCFG [1..2] ============================================== */
|
|
typedef enum { /*!< GPIO_CFGB_GPIO8OUTCFG */
|
|
GPIO_CFGB_GPIO8OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGB_GPIO8OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGB_GPIO8OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGB_GPIO8OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGB_GPIO8OUTCFG_Enum;
|
|
|
|
/* ============================================== GPIO CFGB GPIO8INCFG [0..0] ============================================== */
|
|
typedef enum { /*!< GPIO_CFGB_GPIO8INCFG */
|
|
GPIO_CFGB_GPIO8INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGB_GPIO8INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGB_GPIO8INCFG_Enum;
|
|
|
|
/* ========================================================= CFGC ========================================================== */
|
|
/* ============================================= GPIO CFGC GPIO23INTD [31..31] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGC_GPIO23INTD */
|
|
GPIO_CFGC_GPIO23INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGC_GPIO23INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGC_GPIO23INTD_Enum;
|
|
|
|
/* ============================================ GPIO CFGC GPIO23OUTCFG [29..30] ============================================ */
|
|
typedef enum { /*!< GPIO_CFGC_GPIO23OUTCFG */
|
|
GPIO_CFGC_GPIO23OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGC_GPIO23OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGC_GPIO23OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGC_GPIO23OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGC_GPIO23OUTCFG_Enum;
|
|
|
|
/* ============================================ GPIO CFGC GPIO23INCFG [28..28] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGC_GPIO23INCFG */
|
|
GPIO_CFGC_GPIO23INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGC_GPIO23INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGC_GPIO23INCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGC GPIO22INTD [27..27] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGC_GPIO22INTD */
|
|
GPIO_CFGC_GPIO22INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGC_GPIO22INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGC_GPIO22INTD_Enum;
|
|
|
|
/* ============================================ GPIO CFGC GPIO22OUTCFG [25..26] ============================================ */
|
|
typedef enum { /*!< GPIO_CFGC_GPIO22OUTCFG */
|
|
GPIO_CFGC_GPIO22OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGC_GPIO22OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGC_GPIO22OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGC_GPIO22OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGC_GPIO22OUTCFG_Enum;
|
|
|
|
/* ============================================ GPIO CFGC GPIO22INCFG [24..24] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGC_GPIO22INCFG */
|
|
GPIO_CFGC_GPIO22INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGC_GPIO22INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGC_GPIO22INCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGC GPIO21INTD [23..23] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGC_GPIO21INTD */
|
|
GPIO_CFGC_GPIO21INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGC_GPIO21INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGC_GPIO21INTD_Enum;
|
|
|
|
/* ============================================ GPIO CFGC GPIO21OUTCFG [21..22] ============================================ */
|
|
typedef enum { /*!< GPIO_CFGC_GPIO21OUTCFG */
|
|
GPIO_CFGC_GPIO21OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGC_GPIO21OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGC_GPIO21OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGC_GPIO21OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGC_GPIO21OUTCFG_Enum;
|
|
|
|
/* ============================================ GPIO CFGC GPIO21INCFG [20..20] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGC_GPIO21INCFG */
|
|
GPIO_CFGC_GPIO21INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGC_GPIO21INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGC_GPIO21INCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGC GPIO20INTD [19..19] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGC_GPIO20INTD */
|
|
GPIO_CFGC_GPIO20INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGC_GPIO20INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGC_GPIO20INTD_Enum;
|
|
|
|
/* ============================================ GPIO CFGC GPIO20OUTCFG [17..18] ============================================ */
|
|
typedef enum { /*!< GPIO_CFGC_GPIO20OUTCFG */
|
|
GPIO_CFGC_GPIO20OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGC_GPIO20OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGC_GPIO20OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGC_GPIO20OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGC_GPIO20OUTCFG_Enum;
|
|
|
|
/* ============================================ GPIO CFGC GPIO20INCFG [16..16] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGC_GPIO20INCFG */
|
|
GPIO_CFGC_GPIO20INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGC_GPIO20INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGC_GPIO20INCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGC GPIO19INTD [15..15] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGC_GPIO19INTD */
|
|
GPIO_CFGC_GPIO19INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGC_GPIO19INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGC_GPIO19INTD_Enum;
|
|
|
|
/* ============================================ GPIO CFGC GPIO19OUTCFG [13..14] ============================================ */
|
|
typedef enum { /*!< GPIO_CFGC_GPIO19OUTCFG */
|
|
GPIO_CFGC_GPIO19OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGC_GPIO19OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGC_GPIO19OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGC_GPIO19OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGC_GPIO19OUTCFG_Enum;
|
|
|
|
/* ============================================ GPIO CFGC GPIO19INCFG [12..12] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGC_GPIO19INCFG */
|
|
GPIO_CFGC_GPIO19INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGC_GPIO19INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGC_GPIO19INCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGC GPIO18INTD [11..11] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGC_GPIO18INTD */
|
|
GPIO_CFGC_GPIO18INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGC_GPIO18INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGC_GPIO18INTD_Enum;
|
|
|
|
/* ============================================ GPIO CFGC GPIO18OUTCFG [9..10] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGC_GPIO18OUTCFG */
|
|
GPIO_CFGC_GPIO18OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGC_GPIO18OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGC_GPIO18OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGC_GPIO18OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGC_GPIO18OUTCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGC GPIO18INCFG [8..8] ============================================== */
|
|
typedef enum { /*!< GPIO_CFGC_GPIO18INCFG */
|
|
GPIO_CFGC_GPIO18INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGC_GPIO18INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGC_GPIO18INCFG_Enum;
|
|
|
|
/* ============================================== GPIO CFGC GPIO17INTD [7..7] ============================================== */
|
|
typedef enum { /*!< GPIO_CFGC_GPIO17INTD */
|
|
GPIO_CFGC_GPIO17INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGC_GPIO17INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGC_GPIO17INTD_Enum;
|
|
|
|
/* ============================================= GPIO CFGC GPIO17OUTCFG [5..6] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGC_GPIO17OUTCFG */
|
|
GPIO_CFGC_GPIO17OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGC_GPIO17OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGC_GPIO17OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGC_GPIO17OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGC_GPIO17OUTCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGC GPIO17INCFG [4..4] ============================================== */
|
|
typedef enum { /*!< GPIO_CFGC_GPIO17INCFG */
|
|
GPIO_CFGC_GPIO17INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGC_GPIO17INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGC_GPIO17INCFG_Enum;
|
|
|
|
/* ============================================== GPIO CFGC GPIO16INTD [3..3] ============================================== */
|
|
typedef enum { /*!< GPIO_CFGC_GPIO16INTD */
|
|
GPIO_CFGC_GPIO16INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGC_GPIO16INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGC_GPIO16INTD_Enum;
|
|
|
|
/* ============================================= GPIO CFGC GPIO16OUTCFG [1..2] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGC_GPIO16OUTCFG */
|
|
GPIO_CFGC_GPIO16OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGC_GPIO16OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGC_GPIO16OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGC_GPIO16OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGC_GPIO16OUTCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGC GPIO16INCFG [0..0] ============================================== */
|
|
typedef enum { /*!< GPIO_CFGC_GPIO16INCFG */
|
|
GPIO_CFGC_GPIO16INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGC_GPIO16INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGC_GPIO16INCFG_Enum;
|
|
|
|
/* ========================================================= CFGD ========================================================== */
|
|
/* ============================================= GPIO CFGD GPIO31INTD [31..31] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGD_GPIO31INTD */
|
|
GPIO_CFGD_GPIO31INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGD_GPIO31INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGD_GPIO31INTD_Enum;
|
|
|
|
/* ============================================ GPIO CFGD GPIO31OUTCFG [29..30] ============================================ */
|
|
typedef enum { /*!< GPIO_CFGD_GPIO31OUTCFG */
|
|
GPIO_CFGD_GPIO31OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGD_GPIO31OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGD_GPIO31OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGD_GPIO31OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGD_GPIO31OUTCFG_Enum;
|
|
|
|
/* ============================================ GPIO CFGD GPIO31INCFG [28..28] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGD_GPIO31INCFG */
|
|
GPIO_CFGD_GPIO31INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGD_GPIO31INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGD_GPIO31INCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGD GPIO30INTD [27..27] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGD_GPIO30INTD */
|
|
GPIO_CFGD_GPIO30INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGD_GPIO30INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGD_GPIO30INTD_Enum;
|
|
|
|
/* ============================================ GPIO CFGD GPIO30OUTCFG [25..26] ============================================ */
|
|
typedef enum { /*!< GPIO_CFGD_GPIO30OUTCFG */
|
|
GPIO_CFGD_GPIO30OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGD_GPIO30OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGD_GPIO30OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGD_GPIO30OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGD_GPIO30OUTCFG_Enum;
|
|
|
|
/* ============================================ GPIO CFGD GPIO30INCFG [24..24] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGD_GPIO30INCFG */
|
|
GPIO_CFGD_GPIO30INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGD_GPIO30INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGD_GPIO30INCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGD GPIO29INTD [23..23] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGD_GPIO29INTD */
|
|
GPIO_CFGD_GPIO29INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGD_GPIO29INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGD_GPIO29INTD_Enum;
|
|
|
|
/* ============================================ GPIO CFGD GPIO29OUTCFG [21..22] ============================================ */
|
|
typedef enum { /*!< GPIO_CFGD_GPIO29OUTCFG */
|
|
GPIO_CFGD_GPIO29OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGD_GPIO29OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGD_GPIO29OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGD_GPIO29OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGD_GPIO29OUTCFG_Enum;
|
|
|
|
/* ============================================ GPIO CFGD GPIO29INCFG [20..20] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGD_GPIO29INCFG */
|
|
GPIO_CFGD_GPIO29INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGD_GPIO29INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGD_GPIO29INCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGD GPIO28INTD [19..19] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGD_GPIO28INTD */
|
|
GPIO_CFGD_GPIO28INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGD_GPIO28INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGD_GPIO28INTD_Enum;
|
|
|
|
/* ============================================ GPIO CFGD GPIO28OUTCFG [17..18] ============================================ */
|
|
typedef enum { /*!< GPIO_CFGD_GPIO28OUTCFG */
|
|
GPIO_CFGD_GPIO28OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGD_GPIO28OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGD_GPIO28OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGD_GPIO28OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGD_GPIO28OUTCFG_Enum;
|
|
|
|
/* ============================================ GPIO CFGD GPIO28INCFG [16..16] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGD_GPIO28INCFG */
|
|
GPIO_CFGD_GPIO28INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGD_GPIO28INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGD_GPIO28INCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGD GPIO27INTD [15..15] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGD_GPIO27INTD */
|
|
GPIO_CFGD_GPIO27INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGD_GPIO27INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGD_GPIO27INTD_Enum;
|
|
|
|
/* ============================================ GPIO CFGD GPIO27OUTCFG [13..14] ============================================ */
|
|
typedef enum { /*!< GPIO_CFGD_GPIO27OUTCFG */
|
|
GPIO_CFGD_GPIO27OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGD_GPIO27OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGD_GPIO27OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGD_GPIO27OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGD_GPIO27OUTCFG_Enum;
|
|
|
|
/* ============================================ GPIO CFGD GPIO27INCFG [12..12] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGD_GPIO27INCFG */
|
|
GPIO_CFGD_GPIO27INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGD_GPIO27INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGD_GPIO27INCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGD GPIO26INTD [11..11] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGD_GPIO26INTD */
|
|
GPIO_CFGD_GPIO26INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGD_GPIO26INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGD_GPIO26INTD_Enum;
|
|
|
|
/* ============================================ GPIO CFGD GPIO26OUTCFG [9..10] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGD_GPIO26OUTCFG */
|
|
GPIO_CFGD_GPIO26OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGD_GPIO26OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGD_GPIO26OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGD_GPIO26OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGD_GPIO26OUTCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGD GPIO26INCFG [8..8] ============================================== */
|
|
typedef enum { /*!< GPIO_CFGD_GPIO26INCFG */
|
|
GPIO_CFGD_GPIO26INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGD_GPIO26INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGD_GPIO26INCFG_Enum;
|
|
|
|
/* ============================================== GPIO CFGD GPIO25INTD [7..7] ============================================== */
|
|
typedef enum { /*!< GPIO_CFGD_GPIO25INTD */
|
|
GPIO_CFGD_GPIO25INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGD_GPIO25INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGD_GPIO25INTD_Enum;
|
|
|
|
/* ============================================= GPIO CFGD GPIO25OUTCFG [5..6] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGD_GPIO25OUTCFG */
|
|
GPIO_CFGD_GPIO25OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGD_GPIO25OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGD_GPIO25OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGD_GPIO25OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGD_GPIO25OUTCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGD GPIO25INCFG [4..4] ============================================== */
|
|
typedef enum { /*!< GPIO_CFGD_GPIO25INCFG */
|
|
GPIO_CFGD_GPIO25INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGD_GPIO25INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGD_GPIO25INCFG_Enum;
|
|
|
|
/* ============================================== GPIO CFGD GPIO24INTD [3..3] ============================================== */
|
|
typedef enum { /*!< GPIO_CFGD_GPIO24INTD */
|
|
GPIO_CFGD_GPIO24INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGD_GPIO24INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGD_GPIO24INTD_Enum;
|
|
|
|
/* ============================================= GPIO CFGD GPIO24OUTCFG [1..2] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGD_GPIO24OUTCFG */
|
|
GPIO_CFGD_GPIO24OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGD_GPIO24OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGD_GPIO24OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGD_GPIO24OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGD_GPIO24OUTCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGD GPIO24INCFG [0..0] ============================================== */
|
|
typedef enum { /*!< GPIO_CFGD_GPIO24INCFG */
|
|
GPIO_CFGD_GPIO24INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGD_GPIO24INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGD_GPIO24INCFG_Enum;
|
|
|
|
/* ========================================================= CFGE ========================================================== */
|
|
/* ============================================= GPIO CFGE GPIO39INTD [31..31] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGE_GPIO39INTD */
|
|
GPIO_CFGE_GPIO39INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGE_GPIO39INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGE_GPIO39INTD_Enum;
|
|
|
|
/* ============================================ GPIO CFGE GPIO39OUTCFG [29..30] ============================================ */
|
|
typedef enum { /*!< GPIO_CFGE_GPIO39OUTCFG */
|
|
GPIO_CFGE_GPIO39OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGE_GPIO39OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGE_GPIO39OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGE_GPIO39OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGE_GPIO39OUTCFG_Enum;
|
|
|
|
/* ============================================ GPIO CFGE GPIO39INCFG [28..28] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGE_GPIO39INCFG */
|
|
GPIO_CFGE_GPIO39INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGE_GPIO39INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGE_GPIO39INCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGE GPIO38INTD [27..27] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGE_GPIO38INTD */
|
|
GPIO_CFGE_GPIO38INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGE_GPIO38INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGE_GPIO38INTD_Enum;
|
|
|
|
/* ============================================ GPIO CFGE GPIO38OUTCFG [25..26] ============================================ */
|
|
typedef enum { /*!< GPIO_CFGE_GPIO38OUTCFG */
|
|
GPIO_CFGE_GPIO38OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGE_GPIO38OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGE_GPIO38OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGE_GPIO38OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGE_GPIO38OUTCFG_Enum;
|
|
|
|
/* ============================================ GPIO CFGE GPIO38INCFG [24..24] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGE_GPIO38INCFG */
|
|
GPIO_CFGE_GPIO38INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGE_GPIO38INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGE_GPIO38INCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGE GPIO37INTD [23..23] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGE_GPIO37INTD */
|
|
GPIO_CFGE_GPIO37INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGE_GPIO37INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGE_GPIO37INTD_Enum;
|
|
|
|
/* ============================================ GPIO CFGE GPIO37OUTCFG [21..22] ============================================ */
|
|
typedef enum { /*!< GPIO_CFGE_GPIO37OUTCFG */
|
|
GPIO_CFGE_GPIO37OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGE_GPIO37OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGE_GPIO37OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGE_GPIO37OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGE_GPIO37OUTCFG_Enum;
|
|
|
|
/* ============================================ GPIO CFGE GPIO37INCFG [20..20] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGE_GPIO37INCFG */
|
|
GPIO_CFGE_GPIO37INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGE_GPIO37INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGE_GPIO37INCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGE GPIO36INTD [19..19] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGE_GPIO36INTD */
|
|
GPIO_CFGE_GPIO36INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGE_GPIO36INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGE_GPIO36INTD_Enum;
|
|
|
|
/* ============================================ GPIO CFGE GPIO36OUTCFG [17..18] ============================================ */
|
|
typedef enum { /*!< GPIO_CFGE_GPIO36OUTCFG */
|
|
GPIO_CFGE_GPIO36OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGE_GPIO36OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGE_GPIO36OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGE_GPIO36OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGE_GPIO36OUTCFG_Enum;
|
|
|
|
/* ============================================ GPIO CFGE GPIO36INCFG [16..16] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGE_GPIO36INCFG */
|
|
GPIO_CFGE_GPIO36INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGE_GPIO36INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGE_GPIO36INCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGE GPIO35INTD [15..15] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGE_GPIO35INTD */
|
|
GPIO_CFGE_GPIO35INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGE_GPIO35INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGE_GPIO35INTD_Enum;
|
|
|
|
/* ============================================ GPIO CFGE GPIO35OUTCFG [13..14] ============================================ */
|
|
typedef enum { /*!< GPIO_CFGE_GPIO35OUTCFG */
|
|
GPIO_CFGE_GPIO35OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGE_GPIO35OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGE_GPIO35OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGE_GPIO35OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGE_GPIO35OUTCFG_Enum;
|
|
|
|
/* ============================================ GPIO CFGE GPIO35INCFG [12..12] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGE_GPIO35INCFG */
|
|
GPIO_CFGE_GPIO35INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGE_GPIO35INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGE_GPIO35INCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGE GPIO34INTD [11..11] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGE_GPIO34INTD */
|
|
GPIO_CFGE_GPIO34INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGE_GPIO34INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGE_GPIO34INTD_Enum;
|
|
|
|
/* ============================================ GPIO CFGE GPIO34OUTCFG [9..10] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGE_GPIO34OUTCFG */
|
|
GPIO_CFGE_GPIO34OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGE_GPIO34OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGE_GPIO34OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGE_GPIO34OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGE_GPIO34OUTCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGE GPIO34INCFG [8..8] ============================================== */
|
|
typedef enum { /*!< GPIO_CFGE_GPIO34INCFG */
|
|
GPIO_CFGE_GPIO34INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGE_GPIO34INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGE_GPIO34INCFG_Enum;
|
|
|
|
/* ============================================== GPIO CFGE GPIO33INTD [7..7] ============================================== */
|
|
typedef enum { /*!< GPIO_CFGE_GPIO33INTD */
|
|
GPIO_CFGE_GPIO33INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGE_GPIO33INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGE_GPIO33INTD_Enum;
|
|
|
|
/* ============================================= GPIO CFGE GPIO33OUTCFG [5..6] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGE_GPIO33OUTCFG */
|
|
GPIO_CFGE_GPIO33OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGE_GPIO33OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGE_GPIO33OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGE_GPIO33OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGE_GPIO33OUTCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGE GPIO33INCFG [4..4] ============================================== */
|
|
typedef enum { /*!< GPIO_CFGE_GPIO33INCFG */
|
|
GPIO_CFGE_GPIO33INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGE_GPIO33INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGE_GPIO33INCFG_Enum;
|
|
|
|
/* ============================================== GPIO CFGE GPIO32INTD [3..3] ============================================== */
|
|
typedef enum { /*!< GPIO_CFGE_GPIO32INTD */
|
|
GPIO_CFGE_GPIO32INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGE_GPIO32INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGE_GPIO32INTD_Enum;
|
|
|
|
/* ============================================= GPIO CFGE GPIO32OUTCFG [1..2] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGE_GPIO32OUTCFG */
|
|
GPIO_CFGE_GPIO32OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGE_GPIO32OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGE_GPIO32OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGE_GPIO32OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGE_GPIO32OUTCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGE GPIO32INCFG [0..0] ============================================== */
|
|
typedef enum { /*!< GPIO_CFGE_GPIO32INCFG */
|
|
GPIO_CFGE_GPIO32INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGE_GPIO32INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGE_GPIO32INCFG_Enum;
|
|
|
|
/* ========================================================= CFGF ========================================================== */
|
|
/* ============================================= GPIO CFGF GPIO47INTD [31..31] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGF_GPIO47INTD */
|
|
GPIO_CFGF_GPIO47INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGF_GPIO47INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGF_GPIO47INTD_Enum;
|
|
|
|
/* ============================================ GPIO CFGF GPIO47OUTCFG [29..30] ============================================ */
|
|
typedef enum { /*!< GPIO_CFGF_GPIO47OUTCFG */
|
|
GPIO_CFGF_GPIO47OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGF_GPIO47OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGF_GPIO47OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGF_GPIO47OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGF_GPIO47OUTCFG_Enum;
|
|
|
|
/* ============================================ GPIO CFGF GPIO47INCFG [28..28] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGF_GPIO47INCFG */
|
|
GPIO_CFGF_GPIO47INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGF_GPIO47INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGF_GPIO47INCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGF GPIO46INTD [27..27] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGF_GPIO46INTD */
|
|
GPIO_CFGF_GPIO46INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGF_GPIO46INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGF_GPIO46INTD_Enum;
|
|
|
|
/* ============================================ GPIO CFGF GPIO46OUTCFG [25..26] ============================================ */
|
|
typedef enum { /*!< GPIO_CFGF_GPIO46OUTCFG */
|
|
GPIO_CFGF_GPIO46OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGF_GPIO46OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGF_GPIO46OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGF_GPIO46OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGF_GPIO46OUTCFG_Enum;
|
|
|
|
/* ============================================ GPIO CFGF GPIO46INCFG [24..24] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGF_GPIO46INCFG */
|
|
GPIO_CFGF_GPIO46INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGF_GPIO46INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGF_GPIO46INCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGF GPIO45INTD [23..23] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGF_GPIO45INTD */
|
|
GPIO_CFGF_GPIO45INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGF_GPIO45INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGF_GPIO45INTD_Enum;
|
|
|
|
/* ============================================ GPIO CFGF GPIO45OUTCFG [21..22] ============================================ */
|
|
typedef enum { /*!< GPIO_CFGF_GPIO45OUTCFG */
|
|
GPIO_CFGF_GPIO45OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGF_GPIO45OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGF_GPIO45OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGF_GPIO45OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGF_GPIO45OUTCFG_Enum;
|
|
|
|
/* ============================================ GPIO CFGF GPIO45INCFG [20..20] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGF_GPIO45INCFG */
|
|
GPIO_CFGF_GPIO45INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGF_GPIO45INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGF_GPIO45INCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGF GPIO44INTD [19..19] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGF_GPIO44INTD */
|
|
GPIO_CFGF_GPIO44INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGF_GPIO44INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGF_GPIO44INTD_Enum;
|
|
|
|
/* ============================================ GPIO CFGF GPIO44OUTCFG [17..18] ============================================ */
|
|
typedef enum { /*!< GPIO_CFGF_GPIO44OUTCFG */
|
|
GPIO_CFGF_GPIO44OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGF_GPIO44OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGF_GPIO44OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGF_GPIO44OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGF_GPIO44OUTCFG_Enum;
|
|
|
|
/* ============================================ GPIO CFGF GPIO44INCFG [16..16] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGF_GPIO44INCFG */
|
|
GPIO_CFGF_GPIO44INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGF_GPIO44INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGF_GPIO44INCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGF GPIO43INTD [15..15] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGF_GPIO43INTD */
|
|
GPIO_CFGF_GPIO43INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGF_GPIO43INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGF_GPIO43INTD_Enum;
|
|
|
|
/* ============================================ GPIO CFGF GPIO43OUTCFG [13..14] ============================================ */
|
|
typedef enum { /*!< GPIO_CFGF_GPIO43OUTCFG */
|
|
GPIO_CFGF_GPIO43OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGF_GPIO43OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGF_GPIO43OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGF_GPIO43OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGF_GPIO43OUTCFG_Enum;
|
|
|
|
/* ============================================ GPIO CFGF GPIO43INCFG [12..12] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGF_GPIO43INCFG */
|
|
GPIO_CFGF_GPIO43INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGF_GPIO43INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGF_GPIO43INCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGF GPIO42INTD [11..11] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGF_GPIO42INTD */
|
|
GPIO_CFGF_GPIO42INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGF_GPIO42INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGF_GPIO42INTD_Enum;
|
|
|
|
/* ============================================ GPIO CFGF GPIO42OUTCFG [9..10] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGF_GPIO42OUTCFG */
|
|
GPIO_CFGF_GPIO42OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGF_GPIO42OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGF_GPIO42OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGF_GPIO42OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGF_GPIO42OUTCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGF GPIO42INCFG [8..8] ============================================== */
|
|
typedef enum { /*!< GPIO_CFGF_GPIO42INCFG */
|
|
GPIO_CFGF_GPIO42INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGF_GPIO42INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGF_GPIO42INCFG_Enum;
|
|
|
|
/* ============================================== GPIO CFGF GPIO41INTD [7..7] ============================================== */
|
|
typedef enum { /*!< GPIO_CFGF_GPIO41INTD */
|
|
GPIO_CFGF_GPIO41INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGF_GPIO41INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGF_GPIO41INTD_Enum;
|
|
|
|
/* ============================================= GPIO CFGF GPIO41OUTCFG [5..6] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGF_GPIO41OUTCFG */
|
|
GPIO_CFGF_GPIO41OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGF_GPIO41OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGF_GPIO41OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGF_GPIO41OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGF_GPIO41OUTCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGF GPIO41INCFG [4..4] ============================================== */
|
|
typedef enum { /*!< GPIO_CFGF_GPIO41INCFG */
|
|
GPIO_CFGF_GPIO41INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGF_GPIO41INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGF_GPIO41INCFG_Enum;
|
|
|
|
/* ============================================== GPIO CFGF GPIO40INTD [3..3] ============================================== */
|
|
typedef enum { /*!< GPIO_CFGF_GPIO40INTD */
|
|
GPIO_CFGF_GPIO40INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGF_GPIO40INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGF_GPIO40INTD_Enum;
|
|
|
|
/* ============================================= GPIO CFGF GPIO40OUTCFG [1..2] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGF_GPIO40OUTCFG */
|
|
GPIO_CFGF_GPIO40OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGF_GPIO40OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGF_GPIO40OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGF_GPIO40OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGF_GPIO40OUTCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGF GPIO40INCFG [0..0] ============================================== */
|
|
typedef enum { /*!< GPIO_CFGF_GPIO40INCFG */
|
|
GPIO_CFGF_GPIO40INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGF_GPIO40INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGF_GPIO40INCFG_Enum;
|
|
|
|
/* ========================================================= CFGG ========================================================== */
|
|
/* ============================================== GPIO CFGG GPIO49INTD [7..7] ============================================== */
|
|
typedef enum { /*!< GPIO_CFGG_GPIO49INTD */
|
|
GPIO_CFGG_GPIO49INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGG_GPIO49INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGG_GPIO49INTD_Enum;
|
|
|
|
/* ============================================= GPIO CFGG GPIO49OUTCFG [5..6] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGG_GPIO49OUTCFG */
|
|
GPIO_CFGG_GPIO49OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGG_GPIO49OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGG_GPIO49OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGG_GPIO49OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGG_GPIO49OUTCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGG GPIO49INCFG [4..4] ============================================== */
|
|
typedef enum { /*!< GPIO_CFGG_GPIO49INCFG */
|
|
GPIO_CFGG_GPIO49INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGG_GPIO49INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGG_GPIO49INCFG_Enum;
|
|
|
|
/* ============================================== GPIO CFGG GPIO48INTD [3..3] ============================================== */
|
|
typedef enum { /*!< GPIO_CFGG_GPIO48INTD */
|
|
GPIO_CFGG_GPIO48INTD_INTLH = 0, /*!< INTLH : Interrupt on low to high GPIO transition */
|
|
GPIO_CFGG_GPIO48INTD_INTHL = 1, /*!< INTHL : Interrupt on high to low GPIO transition */
|
|
} GPIO_CFGG_GPIO48INTD_Enum;
|
|
|
|
/* ============================================= GPIO CFGG GPIO48OUTCFG [1..2] ============================================= */
|
|
typedef enum { /*!< GPIO_CFGG_GPIO48OUTCFG */
|
|
GPIO_CFGG_GPIO48OUTCFG_DIS = 0, /*!< DIS : Output disabled */
|
|
GPIO_CFGG_GPIO48OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Output is push-pull */
|
|
GPIO_CFGG_GPIO48OUTCFG_OD = 2, /*!< OD : Output is open drain */
|
|
GPIO_CFGG_GPIO48OUTCFG_TS = 3, /*!< TS : Output is tri-state */
|
|
} GPIO_CFGG_GPIO48OUTCFG_Enum;
|
|
|
|
/* ============================================= GPIO CFGG GPIO48INCFG [0..0] ============================================== */
|
|
typedef enum { /*!< GPIO_CFGG_GPIO48INCFG */
|
|
GPIO_CFGG_GPIO48INCFG_READ = 0, /*!< READ : Read the GPIO pin data */
|
|
GPIO_CFGG_GPIO48INCFG_RDZERO = 1, /*!< RDZERO : Readback will always be zero */
|
|
} GPIO_CFGG_GPIO48INCFG_Enum;
|
|
|
|
/* ======================================================== PADKEY ========================================================= */
|
|
/* ============================================== GPIO PADKEY PADKEY [0..31] =============================================== */
|
|
typedef enum { /*!< GPIO_PADKEY_PADKEY */
|
|
GPIO_PADKEY_PADKEY_Key = 115, /*!< Key : Key */
|
|
} GPIO_PADKEY_PADKEY_Enum;
|
|
|
|
/* ========================================================== RDA ========================================================== */
|
|
/* ========================================================== RDB ========================================================== */
|
|
/* ========================================================== WTA ========================================================== */
|
|
/* ========================================================== WTB ========================================================== */
|
|
/* ========================================================= WTSA ========================================================== */
|
|
/* ========================================================= WTSB ========================================================== */
|
|
/* ========================================================= WTCA ========================================================== */
|
|
/* ========================================================= WTCB ========================================================== */
|
|
/* ========================================================== ENA ========================================================== */
|
|
/* ========================================================== ENB ========================================================== */
|
|
/* ========================================================= ENSA ========================================================== */
|
|
/* ========================================================= ENSB ========================================================== */
|
|
/* ========================================================= ENCA ========================================================== */
|
|
/* ========================================================= ENCB ========================================================== */
|
|
/* ======================================================== INT0EN ========================================================= */
|
|
/* ======================================================= INT0STAT ======================================================== */
|
|
/* ======================================================== INT0CLR ======================================================== */
|
|
/* ======================================================== INT0SET ======================================================== */
|
|
/* ======================================================== INT1EN ========================================================= */
|
|
/* ======================================================= INT1STAT ======================================================== */
|
|
/* ======================================================== INT1CLR ======================================================== */
|
|
/* ======================================================== INT1SET ======================================================== */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ IOMSTR0 ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
/* ========================================================= FIFO ========================================================== */
|
|
/* ======================================================== FIFOPTR ======================================================== */
|
|
/* ======================================================== TLNGTH ========================================================= */
|
|
/* ======================================================== FIFOTHR ======================================================== */
|
|
/* ======================================================== CLKCFG ========================================================= */
|
|
/* ============================================= IOMSTR0 CLKCFG DIVEN [12..12] ============================================= */
|
|
typedef enum { /*!< IOMSTR0_CLKCFG_DIVEN */
|
|
IOMSTR0_CLKCFG_DIVEN_DIS = 0, /*!< DIS : Disable TOTPER division. */
|
|
IOMSTR0_CLKCFG_DIVEN_EN = 1, /*!< EN : Enable TOTPER division. */
|
|
} IOMSTR0_CLKCFG_DIVEN_Enum;
|
|
|
|
/* ============================================= IOMSTR0 CLKCFG DIV3 [11..11] ============================================== */
|
|
typedef enum { /*!< IOMSTR0_CLKCFG_DIV3 */
|
|
IOMSTR0_CLKCFG_DIV3_DIS = 0, /*!< DIS : Select divide by 1. */
|
|
IOMSTR0_CLKCFG_DIV3_EN = 1, /*!< EN : Select divide by 3. */
|
|
} IOMSTR0_CLKCFG_DIV3_Enum;
|
|
|
|
/* ============================================== IOMSTR0 CLKCFG FSEL [8..10] ============================================== */
|
|
typedef enum { /*!< IOMSTR0_CLKCFG_FSEL */
|
|
IOMSTR0_CLKCFG_FSEL_HFRC_DIV64 = 0, /*!< HFRC_DIV64 : Selects the HFRC / 64 as the input clock. */
|
|
IOMSTR0_CLKCFG_FSEL_HFRC = 1, /*!< HFRC : Selects the HFRC as the input clock. */
|
|
IOMSTR0_CLKCFG_FSEL_HFRC_DIV2 = 2, /*!< HFRC_DIV2 : Selects the HFRC / 2 as the input clock. */
|
|
IOMSTR0_CLKCFG_FSEL_HFRC_DIV4 = 3, /*!< HFRC_DIV4 : Selects the HFRC / 4 as the input clock. */
|
|
IOMSTR0_CLKCFG_FSEL_HFRC_DIV8 = 4, /*!< HFRC_DIV8 : Selects the HFRC / 8 as the input clock. */
|
|
IOMSTR0_CLKCFG_FSEL_HFRC_DIV16 = 5, /*!< HFRC_DIV16 : Selects the HFRC / 16 as the input clock. */
|
|
IOMSTR0_CLKCFG_FSEL_HFRC_DIV32 = 6, /*!< HFRC_DIV32 : Selects the HFRC / 32 as the input clock. */
|
|
} IOMSTR0_CLKCFG_FSEL_Enum;
|
|
|
|
/* ========================================================== CMD ========================================================== */
|
|
/* ================================================ IOMSTR0 CMD CMD [0..31] ================================================ */
|
|
typedef enum { /*!< IOMSTR0_CMD_CMD */
|
|
IOMSTR0_CMD_CMD_POS_LENGTH = 0, /*!< POS_LENGTH : LSB bit position of the CMD LENGTH field. */
|
|
IOMSTR0_CMD_CMD_POS_OFFSET = 8, /*!< POS_OFFSET : LSB bit position of the CMD OFFSET field. */
|
|
IOMSTR0_CMD_CMD_POS_ADDRESS = 16, /*!< POS_ADDRESS : LSB bit position of the I2C CMD ADDRESS field. */
|
|
IOMSTR0_CMD_CMD_POS_UPLNGTH = 23, /*!< POS_UPLNGTH : LSB bit position of the SPI CMD UPLNGTH field. */
|
|
IOMSTR0_CMD_CMD_POS_10BIT = 26, /*!< POS_10BIT : LSB bit position of the I2C CMD 10-bit field. */
|
|
IOMSTR0_CMD_CMD_POS_LSB = 27, /*!< POS_LSB : LSB bit position of the CMD LSB-first field. */
|
|
IOMSTR0_CMD_CMD_POS_CONT = 28, /*!< POS_CONT : LSB bit position of the CMD CONTinue field. */
|
|
IOMSTR0_CMD_CMD_POS_OPER = 29, /*!< POS_OPER : LSB bit position of the CMD OPERation field. */
|
|
IOMSTR0_CMD_CMD_MSK_LENGTH = 255, /*!< MSK_LENGTH : LSB bit mask of the CMD LENGTH field. */
|
|
IOMSTR0_CMD_CMD_MSK_OFFSET = 65280, /*!< MSK_OFFSET : LSB bit mask of the CMD OFFSET field. */
|
|
IOMSTR0_CMD_CMD_MSK_ADDRESS = 16711680,/*!< MSK_ADDRESS : LSB bit mask of the I2C CMD ADDRESS field. */
|
|
IOMSTR0_CMD_CMD_MSK_CHNL = 458752,/*!< MSK_CHNL : LSB bit mask of the SPI CMD CHANNEL field. */
|
|
IOMSTR0_CMD_CMD_MSK_UPLNGTH = 125829120,/*!< MSK_UPLNGTH : LSB bit mask of the SPI CMD UPLNGTH field. */
|
|
IOMSTR0_CMD_CMD_MSK_10BIT = 67108864,/*!< MSK_10BIT : LSB bit mask of the I2C CMD 10-bit field. */
|
|
IOMSTR0_CMD_CMD_MSK_LSB = 134217728,/*!< MSK_LSB : LSB bit mask of the CMD LSB-first field. */
|
|
IOMSTR0_CMD_CMD_MSK_CONT = 268435456,/*!< MSK_CONT : LSB bit mask of the CMD CONTinue field. */
|
|
IOMSTR0_CMD_CMD_MSK_OPER = -536870912,/*!< MSK_OPER : LSB bit mask of the CMD OPERation field. */
|
|
} IOMSTR0_CMD_CMD_Enum;
|
|
|
|
/* ======================================================== CMDRPT ========================================================= */
|
|
/* ======================================================== STATUS ========================================================= */
|
|
/* ============================================= IOMSTR0 STATUS IDLEST [2..2] ============================================== */
|
|
typedef enum { /*!< IOMSTR0_STATUS_IDLEST */
|
|
IOMSTR0_STATUS_IDLEST_IDLE = 1, /*!< IDLE : The I/O state machine is in the idle state. */
|
|
} IOMSTR0_STATUS_IDLEST_Enum;
|
|
|
|
/* ============================================= IOMSTR0 STATUS CMDACT [1..1] ============================================== */
|
|
typedef enum { /*!< IOMSTR0_STATUS_CMDACT */
|
|
IOMSTR0_STATUS_CMDACT_ACTIVE = 1, /*!< ACTIVE : An I/O command is active. */
|
|
} IOMSTR0_STATUS_CMDACT_Enum;
|
|
|
|
/* =============================================== IOMSTR0 STATUS ERR [0..0] =============================================== */
|
|
typedef enum { /*!< IOMSTR0_STATUS_ERR */
|
|
IOMSTR0_STATUS_ERR_ERROR = 1, /*!< ERROR : An error has been indicated by the IOM. */
|
|
} IOMSTR0_STATUS_ERR_Enum;
|
|
|
|
/* ========================================================== CFG ========================================================== */
|
|
/* ============================================== IOMSTR0 CFG IFCEN [31..31] =============================================== */
|
|
typedef enum { /*!< IOMSTR0_CFG_IFCEN */
|
|
IOMSTR0_CFG_IFCEN_DIS = 0, /*!< DIS : Disable the IO Master. */
|
|
IOMSTR0_CFG_IFCEN_EN = 1, /*!< EN : Enable the IO Master. */
|
|
} IOMSTR0_CFG_IFCEN_Enum;
|
|
|
|
/* ================================================ IOMSTR0 CFG SPHA [2..2] ================================================ */
|
|
typedef enum { /*!< IOMSTR0_CFG_SPHA */
|
|
IOMSTR0_CFG_SPHA_SAMPLE_LEADING_EDGE = 0, /*!< SAMPLE_LEADING_EDGE : Sample on the leading (first) clock edge. */
|
|
IOMSTR0_CFG_SPHA_SAMPLE_TRAILING_EDGE = 1, /*!< SAMPLE_TRAILING_EDGE : Sample on the trailing (second) clock
|
|
edge. */
|
|
} IOMSTR0_CFG_SPHA_Enum;
|
|
|
|
/* ================================================ IOMSTR0 CFG SPOL [1..1] ================================================ */
|
|
typedef enum { /*!< IOMSTR0_CFG_SPOL */
|
|
IOMSTR0_CFG_SPOL_CLK_BASE_0 = 0, /*!< CLK_BASE_0 : The base value of the clock is 0. */
|
|
IOMSTR0_CFG_SPOL_CLK_BASE_1 = 1, /*!< CLK_BASE_1 : The base value of the clock is 1. */
|
|
} IOMSTR0_CFG_SPOL_Enum;
|
|
|
|
/* =============================================== IOMSTR0 CFG IFCSEL [0..0] =============================================== */
|
|
typedef enum { /*!< IOMSTR0_CFG_IFCSEL */
|
|
IOMSTR0_CFG_IFCSEL_I2C = 0, /*!< I2C : Selects I2C interface for the I/O Master. */
|
|
IOMSTR0_CFG_IFCSEL_SPI = 1, /*!< SPI : Selects SPI interface for the I/O Master. */
|
|
} IOMSTR0_CFG_IFCSEL_Enum;
|
|
|
|
/* ========================================================= INTEN ========================================================= */
|
|
/* ======================================================== INTSTAT ======================================================== */
|
|
/* ======================================================== INTCLR ========================================================= */
|
|
/* ======================================================== INTSET ========================================================= */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ IOSLAVE ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
/* ======================================================== FIFOPTR ======================================================== */
|
|
/* ======================================================== FIFOCFG ======================================================== */
|
|
/* ======================================================== FIFOTHR ======================================================== */
|
|
/* ========================================================= FUPD ========================================================== */
|
|
/* ======================================================== FIFOCTR ======================================================== */
|
|
/* ======================================================== FIFOINC ======================================================== */
|
|
/* ========================================================== CFG ========================================================== */
|
|
/* ============================================== IOSLAVE CFG IFCEN [31..31] =============================================== */
|
|
typedef enum { /*!< IOSLAVE_CFG_IFCEN */
|
|
IOSLAVE_CFG_IFCEN_DIS = 0, /*!< DIS : Disable the IOSLAVE */
|
|
IOSLAVE_CFG_IFCEN_EN = 1, /*!< EN : Enable the IOSLAVE */
|
|
} IOSLAVE_CFG_IFCEN_Enum;
|
|
|
|
/* ============================================== IOSLAVE CFG STARTRD [4..4] =============================================== */
|
|
typedef enum { /*!< IOSLAVE_CFG_STARTRD */
|
|
IOSLAVE_CFG_STARTRD_LATE = 0, /*!< LATE : Initiate I/O RAM read late in each transferred byte. */
|
|
IOSLAVE_CFG_STARTRD_EARLY = 1, /*!< EARLY : Initiate I/O RAM read early in each transferred byte. */
|
|
} IOSLAVE_CFG_STARTRD_Enum;
|
|
|
|
/* ================================================ IOSLAVE CFG LSB [2..2] ================================================= */
|
|
typedef enum { /*!< IOSLAVE_CFG_LSB */
|
|
IOSLAVE_CFG_LSB_MSB_FIRST = 0, /*!< MSB_FIRST : Data is assumed to be sent and received with MSB
|
|
first. */
|
|
IOSLAVE_CFG_LSB_LSB_FIRST = 1, /*!< LSB_FIRST : Data is assumed to be sent and received with LSB
|
|
first. */
|
|
} IOSLAVE_CFG_LSB_Enum;
|
|
|
|
/* ================================================ IOSLAVE CFG SPOL [1..1] ================================================ */
|
|
typedef enum { /*!< IOSLAVE_CFG_SPOL */
|
|
IOSLAVE_CFG_SPOL_SPI_MODES_0_3 = 0, /*!< SPI_MODES_0_3 : Polarity 0, handles SPI modes 0 and 3. */
|
|
IOSLAVE_CFG_SPOL_SPI_MODES_1_2 = 1, /*!< SPI_MODES_1_2 : Polarity 1, handles SPI modes 1 and 2. */
|
|
} IOSLAVE_CFG_SPOL_Enum;
|
|
|
|
/* =============================================== IOSLAVE CFG IFCSEL [0..0] =============================================== */
|
|
typedef enum { /*!< IOSLAVE_CFG_IFCSEL */
|
|
IOSLAVE_CFG_IFCSEL_I2C = 0, /*!< I2C : Selects I2C interface for the IO Slave. */
|
|
IOSLAVE_CFG_IFCSEL_SPI = 1, /*!< SPI : Selects SPI interface for the IO Slave. */
|
|
} IOSLAVE_CFG_IFCSEL_Enum;
|
|
|
|
/* ========================================================= PRENC ========================================================= */
|
|
/* ======================================================= IOINTCTL ======================================================== */
|
|
/* ======================================================== GENADD ========================================================= */
|
|
/* ========================================================= INTEN ========================================================= */
|
|
/* ======================================================== INTSTAT ======================================================== */
|
|
/* ======================================================== INTCLR ========================================================= */
|
|
/* ======================================================== INTSET ========================================================= */
|
|
/* ====================================================== REGACCINTEN ====================================================== */
|
|
/* ===================================================== REGACCINTSTAT ===================================================== */
|
|
/* ===================================================== REGACCINTCLR ====================================================== */
|
|
/* ===================================================== REGACCINTSET ====================================================== */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ MCUCTRL ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
/* ======================================================= CHIP_INFO ======================================================= */
|
|
/* =========================================== MCUCTRL CHIP_INFO CLASS [24..31] ============================================ */
|
|
typedef enum { /*!< MCUCTRL_CHIP_INFO_CLASS */
|
|
MCUCTRL_CHIP_INFO_CLASS_APOLLO = 1, /*!< APOLLO : APOLLO */
|
|
} MCUCTRL_CHIP_INFO_CLASS_Enum;
|
|
|
|
/* =========================================== MCUCTRL CHIP_INFO FLASH [20..23] ============================================ */
|
|
typedef enum { /*!< MCUCTRL_CHIP_INFO_FLASH */
|
|
MCUCTRL_CHIP_INFO_FLASH_256K = 3, /*!< 256K : 256K of available flash. */
|
|
MCUCTRL_CHIP_INFO_FLASH_512K = 4, /*!< 512K : 512K of available flash. */
|
|
} MCUCTRL_CHIP_INFO_FLASH_Enum;
|
|
|
|
/* ============================================ MCUCTRL CHIP_INFO RAM [16..19] ============================================= */
|
|
typedef enum { /*!< MCUCTRL_CHIP_INFO_RAM */
|
|
MCUCTRL_CHIP_INFO_RAM_32K = 0, /*!< 32K : 32K of available SRAM. */
|
|
MCUCTRL_CHIP_INFO_RAM_64K = 1, /*!< 64K : 64K of available SRAM. */
|
|
} MCUCTRL_CHIP_INFO_RAM_Enum;
|
|
|
|
/* ============================================= MCUCTRL CHIP_INFO PKG [6..7] ============================================== */
|
|
typedef enum { /*!< MCUCTRL_CHIP_INFO_PKG */
|
|
MCUCTRL_CHIP_INFO_PKG_BGA = 2, /*!< BGA : Ball grid array. */
|
|
MCUCTRL_CHIP_INFO_PKG_CSP = 3, /*!< CSP : Chip-scale package. */
|
|
} MCUCTRL_CHIP_INFO_PKG_Enum;
|
|
|
|
/* ============================================= MCUCTRL CHIP_INFO PINS [3..5] ============================================= */
|
|
typedef enum { /*!< MCUCTRL_CHIP_INFO_PINS */
|
|
MCUCTRL_CHIP_INFO_PINS_41PINS = 1, /*!< 41PINS : 41 package pins total. */
|
|
} MCUCTRL_CHIP_INFO_PINS_Enum;
|
|
|
|
/* ============================================= MCUCTRL CHIP_INFO TEMP [1..2] ============================================= */
|
|
typedef enum { /*!< MCUCTRL_CHIP_INFO_TEMP */
|
|
MCUCTRL_CHIP_INFO_TEMP_COMMERCIAL = 0, /*!< COMMERCIAL : Commercial temperature range. */
|
|
} MCUCTRL_CHIP_INFO_TEMP_Enum;
|
|
|
|
/* ============================================= MCUCTRL CHIP_INFO QUAL [0..0] ============================================= */
|
|
typedef enum { /*!< MCUCTRL_CHIP_INFO_QUAL */
|
|
MCUCTRL_CHIP_INFO_QUAL_PROTOTYPE = 0, /*!< PROTOTYPE : Prototype device. */
|
|
MCUCTRL_CHIP_INFO_QUAL_QUALIFIED = 1, /*!< QUALIFIED : Fully qualified device. */
|
|
} MCUCTRL_CHIP_INFO_QUAL_Enum;
|
|
|
|
/* ======================================================== CHIPID0 ======================================================== */
|
|
/* ============================================= MCUCTRL CHIPID0 VALUE [0..31] ============================================= */
|
|
typedef enum { /*!< MCUCTRL_CHIPID0_VALUE */
|
|
MCUCTRL_CHIPID0_VALUE_APOLLO = 0, /*!< APOLLO : Apollo CHIPID0. */
|
|
} MCUCTRL_CHIPID0_VALUE_Enum;
|
|
|
|
/* ======================================================== CHIPID1 ======================================================== */
|
|
/* ============================================= MCUCTRL CHIPID1 VALUE [0..31] ============================================= */
|
|
typedef enum { /*!< MCUCTRL_CHIPID1_VALUE */
|
|
MCUCTRL_CHIPID1_VALUE_APOLLO = 0, /*!< APOLLO : Apollo CHIPID1. */
|
|
} MCUCTRL_CHIPID1_VALUE_Enum;
|
|
|
|
/* ======================================================== CHIPREV ======================================================== */
|
|
/* ============================================ MCUCTRL CHIPREV REVISION [0..7] ============================================ */
|
|
typedef enum { /*!< MCUCTRL_CHIPREV_REVISION */
|
|
MCUCTRL_CHIPREV_REVISION_APOLLO = 0, /*!< APOLLO : Apollo CHIPREV. */
|
|
} MCUCTRL_CHIPREV_REVISION_Enum;
|
|
|
|
/* ======================================================= SUPPLYSRC ======================================================= */
|
|
/* ========================================== MCUCTRL SUPPLYSRC COREBUCKEN [1..1] ========================================== */
|
|
typedef enum { /*!< MCUCTRL_SUPPLYSRC_COREBUCKEN */
|
|
MCUCTRL_SUPPLYSRC_COREBUCKEN_EN = 1, /*!< EN : Enable the Core Buck for the low-voltage power domain. */
|
|
} MCUCTRL_SUPPLYSRC_COREBUCKEN_Enum;
|
|
|
|
/* ========================================== MCUCTRL SUPPLYSRC MEMBUCKEN [0..0] =========================================== */
|
|
typedef enum { /*!< MCUCTRL_SUPPLYSRC_MEMBUCKEN */
|
|
MCUCTRL_SUPPLYSRC_MEMBUCKEN_EN = 1, /*!< EN : Enable the Memory Buck as the supply for flash and SRAM. */
|
|
} MCUCTRL_SUPPLYSRC_MEMBUCKEN_Enum;
|
|
|
|
/* ===================================================== SUPPLYSTATUS ====================================================== */
|
|
/* ======================================== MCUCTRL SUPPLYSTATUS COREBUCKON [1..1] ========================================= */
|
|
typedef enum { /*!< MCUCTRL_SUPPLYSTATUS_COREBUCKON */
|
|
MCUCTRL_SUPPLYSTATUS_COREBUCKON_LDO = 0, /*!< LDO : Indicates the the LDO is supplying the Core low-voltage. */
|
|
MCUCTRL_SUPPLYSTATUS_COREBUCKON_BUCK = 1, /*!< BUCK : Indicates the the Buck is supplying the Core low-voltage. */
|
|
} MCUCTRL_SUPPLYSTATUS_COREBUCKON_Enum;
|
|
|
|
/* ========================================= MCUCTRL SUPPLYSTATUS MEMBUCKON [0..0] ========================================= */
|
|
typedef enum { /*!< MCUCTRL_SUPPLYSTATUS_MEMBUCKON */
|
|
MCUCTRL_SUPPLYSTATUS_MEMBUCKON_LDO = 0, /*!< LDO : Indicates the LDO is supplying the memory power domain. */
|
|
MCUCTRL_SUPPLYSTATUS_MEMBUCKON_BUCK = 1, /*!< BUCK : Indicates the Buck is supplying the memory power domain. */
|
|
} MCUCTRL_SUPPLYSTATUS_MEMBUCKON_Enum;
|
|
|
|
/* ======================================================= BANDGAPEN ======================================================= */
|
|
/* ============================================ MCUCTRL BANDGAPEN BGPEN [0..0] ============================================= */
|
|
typedef enum { /*!< MCUCTRL_BANDGAPEN_BGPEN */
|
|
MCUCTRL_BANDGAPEN_BGPEN_DIS = 0, /*!< DIS : Bandgap disable. */
|
|
MCUCTRL_BANDGAPEN_BGPEN_EN = 1, /*!< EN : Bandgap enable. */
|
|
} MCUCTRL_BANDGAPEN_BGPEN_Enum;
|
|
|
|
/* ==================================================== SRAMPWDINSLEEP ===================================================== */
|
|
/* ========================================== MCUCTRL SRAMPWDINSLEEP BANK7 [7..7] ========================================== */
|
|
typedef enum { /*!< MCUCTRL_SRAMPWDINSLEEP_BANK7 */
|
|
MCUCTRL_SRAMPWDINSLEEP_BANK7_NORMAL = 0, /*!< NORMAL : SRAM Bank 7 normal operation. */
|
|
MCUCTRL_SRAMPWDINSLEEP_BANK7_PWRDN_IN_DEEPSLEEP = 1,/*!< PWRDN_IN_DEEPSLEEP : SRAM Bank 7 deep sleep. */
|
|
} MCUCTRL_SRAMPWDINSLEEP_BANK7_Enum;
|
|
|
|
/* ========================================== MCUCTRL SRAMPWDINSLEEP BANK6 [6..6] ========================================== */
|
|
typedef enum { /*!< MCUCTRL_SRAMPWDINSLEEP_BANK6 */
|
|
MCUCTRL_SRAMPWDINSLEEP_BANK6_NORMAL = 0, /*!< NORMAL : SRAM Bank 6 normal operation. */
|
|
MCUCTRL_SRAMPWDINSLEEP_BANK6_PWRDN_IN_DEEPSLEEP = 1,/*!< PWRDN_IN_DEEPSLEEP : SRAM Bank 6 deep sleep. */
|
|
} MCUCTRL_SRAMPWDINSLEEP_BANK6_Enum;
|
|
|
|
/* ========================================== MCUCTRL SRAMPWDINSLEEP BANK5 [5..5] ========================================== */
|
|
typedef enum { /*!< MCUCTRL_SRAMPWDINSLEEP_BANK5 */
|
|
MCUCTRL_SRAMPWDINSLEEP_BANK5_NORMAL = 0, /*!< NORMAL : SRAM Bank 5 normal operation. */
|
|
MCUCTRL_SRAMPWDINSLEEP_BANK5_PWRDN_IN_DEEPSLEEP = 1,/*!< PWRDN_IN_DEEPSLEEP : SRAM Bank 5 deep sleep. */
|
|
} MCUCTRL_SRAMPWDINSLEEP_BANK5_Enum;
|
|
|
|
/* ========================================== MCUCTRL SRAMPWDINSLEEP BANK4 [4..4] ========================================== */
|
|
typedef enum { /*!< MCUCTRL_SRAMPWDINSLEEP_BANK4 */
|
|
MCUCTRL_SRAMPWDINSLEEP_BANK4_NORMAL = 0, /*!< NORMAL : SRAM Bank 4 normal operation. */
|
|
MCUCTRL_SRAMPWDINSLEEP_BANK4_PWRDN_IN_DEEPSLEEP = 1,/*!< PWRDN_IN_DEEPSLEEP : SRAM Bank 4 deep sleep. */
|
|
} MCUCTRL_SRAMPWDINSLEEP_BANK4_Enum;
|
|
|
|
/* ========================================== MCUCTRL SRAMPWDINSLEEP BANK3 [3..3] ========================================== */
|
|
typedef enum { /*!< MCUCTRL_SRAMPWDINSLEEP_BANK3 */
|
|
MCUCTRL_SRAMPWDINSLEEP_BANK3_NORMAL = 0, /*!< NORMAL : SRAM Bank 3 normal operation. */
|
|
MCUCTRL_SRAMPWDINSLEEP_BANK3_PWRDN_IN_DEEPSLEEP = 1,/*!< PWRDN_IN_DEEPSLEEP : SRAM Bank 3 deep sleep. */
|
|
} MCUCTRL_SRAMPWDINSLEEP_BANK3_Enum;
|
|
|
|
/* ========================================== MCUCTRL SRAMPWDINSLEEP BANK2 [2..2] ========================================== */
|
|
typedef enum { /*!< MCUCTRL_SRAMPWDINSLEEP_BANK2 */
|
|
MCUCTRL_SRAMPWDINSLEEP_BANK2_NORMAL = 0, /*!< NORMAL : SRAM Bank 2 normal operation. */
|
|
MCUCTRL_SRAMPWDINSLEEP_BANK2_PWRDN_IN_DEEPSLEEP = 1,/*!< PWRDN_IN_DEEPSLEEP : SRAM Bank 2 deep sleep. */
|
|
} MCUCTRL_SRAMPWDINSLEEP_BANK2_Enum;
|
|
|
|
/* ========================================== MCUCTRL SRAMPWDINSLEEP BANK1 [1..1] ========================================== */
|
|
typedef enum { /*!< MCUCTRL_SRAMPWDINSLEEP_BANK1 */
|
|
MCUCTRL_SRAMPWDINSLEEP_BANK1_NORMAL = 0, /*!< NORMAL : SRAM Bank 1 normal operation. */
|
|
MCUCTRL_SRAMPWDINSLEEP_BANK1_PWRDN_IN_DEEPSLEEP = 1,/*!< PWRDN_IN_DEEPSLEEP : SRAM Bank 1 deep sleep. */
|
|
} MCUCTRL_SRAMPWDINSLEEP_BANK1_Enum;
|
|
|
|
/* ========================================== MCUCTRL SRAMPWDINSLEEP BANK0 [0..0] ========================================== */
|
|
typedef enum { /*!< MCUCTRL_SRAMPWDINSLEEP_BANK0 */
|
|
MCUCTRL_SRAMPWDINSLEEP_BANK0_NORMAL = 0, /*!< NORMAL : SRAM Bank 0 normal operation. */
|
|
MCUCTRL_SRAMPWDINSLEEP_BANK0_PWRDN_IN_DEEPSLEEP = 1,/*!< PWRDN_IN_DEEPSLEEP : SRAM Bank 0 deep sleep. */
|
|
} MCUCTRL_SRAMPWDINSLEEP_BANK0_Enum;
|
|
|
|
/* ====================================================== SRAMPWRDIS ======================================================= */
|
|
/* ============================================ MCUCTRL SRAMPWRDIS BANK7 [7..7] ============================================ */
|
|
typedef enum { /*!< MCUCTRL_SRAMPWRDIS_BANK7 */
|
|
MCUCTRL_SRAMPWRDIS_BANK7_DIS = 1, /*!< DIS : Disable SRAM Bank 7. */
|
|
} MCUCTRL_SRAMPWRDIS_BANK7_Enum;
|
|
|
|
/* ============================================ MCUCTRL SRAMPWRDIS BANK6 [6..6] ============================================ */
|
|
typedef enum { /*!< MCUCTRL_SRAMPWRDIS_BANK6 */
|
|
MCUCTRL_SRAMPWRDIS_BANK6_DIS = 1, /*!< DIS : Disable SRAM Bank 6. */
|
|
} MCUCTRL_SRAMPWRDIS_BANK6_Enum;
|
|
|
|
/* ============================================ MCUCTRL SRAMPWRDIS BANK5 [5..5] ============================================ */
|
|
typedef enum { /*!< MCUCTRL_SRAMPWRDIS_BANK5 */
|
|
MCUCTRL_SRAMPWRDIS_BANK5_DIS = 1, /*!< DIS : Disable SRAM Bank 5. */
|
|
} MCUCTRL_SRAMPWRDIS_BANK5_Enum;
|
|
|
|
/* ============================================ MCUCTRL SRAMPWRDIS BANK4 [4..4] ============================================ */
|
|
typedef enum { /*!< MCUCTRL_SRAMPWRDIS_BANK4 */
|
|
MCUCTRL_SRAMPWRDIS_BANK4_DIS = 1, /*!< DIS : Disable SRAM Bank 4. */
|
|
} MCUCTRL_SRAMPWRDIS_BANK4_Enum;
|
|
|
|
/* ============================================ MCUCTRL SRAMPWRDIS BANK3 [3..3] ============================================ */
|
|
typedef enum { /*!< MCUCTRL_SRAMPWRDIS_BANK3 */
|
|
MCUCTRL_SRAMPWRDIS_BANK3_DIS = 1, /*!< DIS : Disable SRAM Bank 3. */
|
|
} MCUCTRL_SRAMPWRDIS_BANK3_Enum;
|
|
|
|
/* ============================================ MCUCTRL SRAMPWRDIS BANK2 [2..2] ============================================ */
|
|
typedef enum { /*!< MCUCTRL_SRAMPWRDIS_BANK2 */
|
|
MCUCTRL_SRAMPWRDIS_BANK2_DIS = 1, /*!< DIS : Disable SRAM Bank 2. */
|
|
} MCUCTRL_SRAMPWRDIS_BANK2_Enum;
|
|
|
|
/* ============================================ MCUCTRL SRAMPWRDIS BANK1 [1..1] ============================================ */
|
|
typedef enum { /*!< MCUCTRL_SRAMPWRDIS_BANK1 */
|
|
MCUCTRL_SRAMPWRDIS_BANK1_DIS = 1, /*!< DIS : Disable SRAM Bank 1. */
|
|
} MCUCTRL_SRAMPWRDIS_BANK1_Enum;
|
|
|
|
/* ============================================ MCUCTRL SRAMPWRDIS BANK0 [0..0] ============================================ */
|
|
typedef enum { /*!< MCUCTRL_SRAMPWRDIS_BANK0 */
|
|
MCUCTRL_SRAMPWRDIS_BANK0_DIS = 1, /*!< DIS : Disable SRAM Bank 0. */
|
|
} MCUCTRL_SRAMPWRDIS_BANK0_Enum;
|
|
|
|
/* ====================================================== FLASHPWRDIS ====================================================== */
|
|
/* =========================================== MCUCTRL FLASHPWRDIS BANK1 [1..1] ============================================ */
|
|
typedef enum { /*!< MCUCTRL_FLASHPWRDIS_BANK1 */
|
|
MCUCTRL_FLASHPWRDIS_BANK1_DIS = 1, /*!< DIS : Disable Flash instance 1. */
|
|
} MCUCTRL_FLASHPWRDIS_BANK1_Enum;
|
|
|
|
/* =========================================== MCUCTRL FLASHPWRDIS BANK0 [0..0] ============================================ */
|
|
typedef enum { /*!< MCUCTRL_FLASHPWRDIS_BANK0 */
|
|
MCUCTRL_FLASHPWRDIS_BANK0_DIS = 1, /*!< DIS : Disable Flash instance 0. */
|
|
} MCUCTRL_FLASHPWRDIS_BANK0_Enum;
|
|
|
|
/* ==================================================== ICODEFAULTADDR ===================================================== */
|
|
/* ==================================================== DCODEFAULTADDR ===================================================== */
|
|
/* ===================================================== SYSFAULTADDR ====================================================== */
|
|
/* ====================================================== FAULTSTATUS ====================================================== */
|
|
/* ============================================ MCUCTRL FAULTSTATUS SYS [2..2] ============================================= */
|
|
typedef enum { /*!< MCUCTRL_FAULTSTATUS_SYS */
|
|
MCUCTRL_FAULTSTATUS_SYS_NOFAULT = 0, /*!< NOFAULT : No bus fault has been detected. */
|
|
MCUCTRL_FAULTSTATUS_SYS_FAULT = 1, /*!< FAULT : Bus fault detected. */
|
|
} MCUCTRL_FAULTSTATUS_SYS_Enum;
|
|
|
|
/* =========================================== MCUCTRL FAULTSTATUS DCODE [1..1] ============================================ */
|
|
typedef enum { /*!< MCUCTRL_FAULTSTATUS_DCODE */
|
|
MCUCTRL_FAULTSTATUS_DCODE_NOFAULT = 0, /*!< NOFAULT : No DCODE fault has been detected. */
|
|
MCUCTRL_FAULTSTATUS_DCODE_FAULT = 1, /*!< FAULT : DCODE fault detected. */
|
|
} MCUCTRL_FAULTSTATUS_DCODE_Enum;
|
|
|
|
/* =========================================== MCUCTRL FAULTSTATUS ICODE [0..0] ============================================ */
|
|
typedef enum { /*!< MCUCTRL_FAULTSTATUS_ICODE */
|
|
MCUCTRL_FAULTSTATUS_ICODE_NOFAULT = 0, /*!< NOFAULT : No ICODE fault has been detected. */
|
|
MCUCTRL_FAULTSTATUS_ICODE_FAULT = 1, /*!< FAULT : ICODE fault detected. */
|
|
} MCUCTRL_FAULTSTATUS_ICODE_Enum;
|
|
|
|
/* ==================================================== FAULTCAPTUREEN ===================================================== */
|
|
/* ========================================= MCUCTRL FAULTCAPTUREEN ENABLE [0..0] ========================================== */
|
|
typedef enum { /*!< MCUCTRL_FAULTCAPTUREEN_ENABLE */
|
|
MCUCTRL_FAULTCAPTUREEN_ENABLE_DIS = 0, /*!< DIS : Disable fault capture. */
|
|
MCUCTRL_FAULTCAPTUREEN_ENABLE_EN = 1, /*!< EN : Enable fault capture. */
|
|
} MCUCTRL_FAULTCAPTUREEN_ENABLE_Enum;
|
|
|
|
/* ======================================================= TPIUCTRL ======================================================== */
|
|
/* ============================================ MCUCTRL TPIUCTRL CLKSEL [8..9] ============================================= */
|
|
typedef enum { /*!< MCUCTRL_TPIUCTRL_CLKSEL */
|
|
MCUCTRL_TPIUCTRL_CLKSEL_LOW_PWR = 0, /*!< LOW_PWR : Low power state. */
|
|
MCUCTRL_TPIUCTRL_CLKSEL_6MHZ = 1, /*!< 6MHZ : Selects 6MHz frequency. */
|
|
MCUCTRL_TPIUCTRL_CLKSEL_3MHZ = 2, /*!< 3MHZ : Selects 3MHz frequency. */
|
|
MCUCTRL_TPIUCTRL_CLKSEL_1_5MHZ = 3, /*!< 1_5MHZ : Selects 1.5 MHz frequency. */
|
|
} MCUCTRL_TPIUCTRL_CLKSEL_Enum;
|
|
|
|
/* ============================================ MCUCTRL TPIUCTRL ENABLE [0..0] ============================================= */
|
|
typedef enum { /*!< MCUCTRL_TPIUCTRL_ENABLE */
|
|
MCUCTRL_TPIUCTRL_ENABLE_DIS = 0, /*!< DIS : Disable the TPIU. */
|
|
MCUCTRL_TPIUCTRL_ENABLE_EN = 1, /*!< EN : Enable the TPIU. */
|
|
} MCUCTRL_TPIUCTRL_ENABLE_Enum;
|
|
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ RSTGEN ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
/* ========================================================== CFG ========================================================== */
|
|
/* ========================================================= SWPOI ========================================================= */
|
|
/* ============================================= RSTGEN SWPOI SWPOIKEY [0..7] ============================================== */
|
|
typedef enum { /*!< RSTGEN_SWPOI_SWPOIKEY */
|
|
RSTGEN_SWPOI_SWPOIKEY_KEYVALUE = 27, /*!< KEYVALUE : Writing 0x1B key value generates a software POI reset. */
|
|
} RSTGEN_SWPOI_SWPOIKEY_Enum;
|
|
|
|
/* ========================================================= SWPOR ========================================================= */
|
|
/* ============================================= RSTGEN SWPOR SWPORKEY [0..7] ============================================== */
|
|
typedef enum { /*!< RSTGEN_SWPOR_SWPORKEY */
|
|
RSTGEN_SWPOR_SWPORKEY_KEYVALUE = 212, /*!< KEYVALUE : Writing 0xD4 key value generates a software POR reset. */
|
|
} RSTGEN_SWPOR_SWPORKEY_Enum;
|
|
|
|
/* ========================================================= STAT ========================================================== */
|
|
/* ======================================================== CLRSTAT ======================================================== */
|
|
/* ========================================================= INTEN ========================================================= */
|
|
/* ======================================================== INTSTAT ======================================================== */
|
|
/* ======================================================== INTCLR ========================================================= */
|
|
/* ======================================================== INTSET ========================================================= */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ RTC ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
/* ======================================================== CTRLOW ========================================================= */
|
|
/* ========================================================= CTRUP ========================================================= */
|
|
/* =============================================== RTC CTRUP CTERR [31..31] ================================================ */
|
|
typedef enum { /*!< RTC_CTRUP_CTERR */
|
|
RTC_CTRUP_CTERR_NOERR = 0, /*!< NOERR : No read error occurred */
|
|
RTC_CTRUP_CTERR_RDERR = 1, /*!< RDERR : Read error occurred */
|
|
} RTC_CTRUP_CTERR_Enum;
|
|
|
|
/* ================================================ RTC CTRUP CEB [28..28] ================================================= */
|
|
typedef enum { /*!< RTC_CTRUP_CEB */
|
|
RTC_CTRUP_CEB_DIS = 0, /*!< DIS : Disable the Century bit from changing */
|
|
RTC_CTRUP_CEB_EN = 1, /*!< EN : Enable the Century bit to change */
|
|
} RTC_CTRUP_CEB_Enum;
|
|
|
|
/* ================================================= RTC CTRUP CB [27..27] ================================================= */
|
|
typedef enum { /*!< RTC_CTRUP_CB */
|
|
RTC_CTRUP_CB_2000 = 0, /*!< 2000 : Century is 2000s */
|
|
RTC_CTRUP_CB_1900_2100 = 1, /*!< 1900_2100 : Century is 1900s/2100s */
|
|
} RTC_CTRUP_CB_Enum;
|
|
|
|
/* ======================================================== ALMLOW ========================================================= */
|
|
/* ========================================================= ALMUP ========================================================= */
|
|
/* ======================================================== RTCCTL ========================================================= */
|
|
/* =============================================== RTC RTCCTL HR1224 [5..5] ================================================ */
|
|
typedef enum { /*!< RTC_RTCCTL_HR1224 */
|
|
RTC_RTCCTL_HR1224_24HR = 0, /*!< 24HR : Hours in 24 hour mode */
|
|
RTC_RTCCTL_HR1224_12HR = 1, /*!< 12HR : Hours in 12 hour mode */
|
|
} RTC_RTCCTL_HR1224_Enum;
|
|
|
|
/* ================================================ RTC RTCCTL RSTOP [4..4] ================================================ */
|
|
typedef enum { /*!< RTC_RTCCTL_RSTOP */
|
|
RTC_RTCCTL_RSTOP_RUN = 0, /*!< RUN : Allow the RTC input clock to run */
|
|
RTC_RTCCTL_RSTOP_STOP = 1, /*!< STOP : Stop the RTC input clock */
|
|
} RTC_RTCCTL_RSTOP_Enum;
|
|
|
|
/* ================================================= RTC RTCCTL RPT [1..3] ================================================= */
|
|
typedef enum { /*!< RTC_RTCCTL_RPT */
|
|
RTC_RTCCTL_RPT_DIS = 0, /*!< DIS : Alarm interrupt disabled */
|
|
RTC_RTCCTL_RPT_YEAR = 1, /*!< YEAR : Interrupt every year */
|
|
RTC_RTCCTL_RPT_MONTH = 2, /*!< MONTH : Interrupt every month */
|
|
RTC_RTCCTL_RPT_WEEK = 3, /*!< WEEK : Interrupt every week */
|
|
RTC_RTCCTL_RPT_DAY = 4, /*!< DAY : Interrupt every day */
|
|
RTC_RTCCTL_RPT_HR = 5, /*!< HR : Interrupt every hour */
|
|
RTC_RTCCTL_RPT_MIN = 6, /*!< MIN : Interrupt every minute */
|
|
RTC_RTCCTL_RPT_SEC = 7, /*!< SEC : Interrupt every second/10th/100th */
|
|
} RTC_RTCCTL_RPT_Enum;
|
|
|
|
/* ================================================ RTC RTCCTL WRTC [0..0] ================================================= */
|
|
typedef enum { /*!< RTC_RTCCTL_WRTC */
|
|
RTC_RTCCTL_WRTC_DIS = 0, /*!< DIS : Counter writes are disabled */
|
|
RTC_RTCCTL_WRTC_EN = 1, /*!< EN : Counter writes are enabled */
|
|
} RTC_RTCCTL_WRTC_Enum;
|
|
|
|
/* ========================================================= INTEN ========================================================= */
|
|
/* ======================================================== INTSTAT ======================================================== */
|
|
/* ======================================================== INTCLR ========================================================= */
|
|
/* ======================================================== INTSET ========================================================= */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ UART ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
/* ========================================================== DR =========================================================== */
|
|
/* ================================================ UART DR OEDATA [11..11] ================================================ */
|
|
typedef enum { /*!< UART_DR_OEDATA */
|
|
UART_DR_OEDATA_NOERR = 0, /*!< NOERR : No error on UART OEDATA, overrun error indicator. */
|
|
UART_DR_OEDATA_ERR = 1, /*!< ERR : Error on UART OEDATA, overrun error indicator. */
|
|
} UART_DR_OEDATA_Enum;
|
|
|
|
/* ================================================ UART DR BEDATA [10..10] ================================================ */
|
|
typedef enum { /*!< UART_DR_BEDATA */
|
|
UART_DR_BEDATA_NOERR = 0, /*!< NOERR : No error on UART BEDATA, break error indicator. */
|
|
UART_DR_BEDATA_ERR = 1, /*!< ERR : Error on UART BEDATA, break error indicator. */
|
|
} UART_DR_BEDATA_Enum;
|
|
|
|
/* ================================================= UART DR PEDATA [9..9] ================================================= */
|
|
typedef enum { /*!< UART_DR_PEDATA */
|
|
UART_DR_PEDATA_NOERR = 0, /*!< NOERR : No error on UART PEDATA, parity error indicator. */
|
|
UART_DR_PEDATA_ERR = 1, /*!< ERR : Error on UART PEDATA, parity error indicator. */
|
|
} UART_DR_PEDATA_Enum;
|
|
|
|
/* ================================================= UART DR FEDATA [8..8] ================================================= */
|
|
typedef enum { /*!< UART_DR_FEDATA */
|
|
UART_DR_FEDATA_NOERR = 0, /*!< NOERR : No error on UART FEDATA, framing error indicator. */
|
|
UART_DR_FEDATA_ERR = 1, /*!< ERR : Error on UART FEDATA, framing error indicator. */
|
|
} UART_DR_FEDATA_Enum;
|
|
|
|
/* ========================================================== RSR ========================================================== */
|
|
/* ================================================ UART RSR OESTAT [3..3] ================================================= */
|
|
typedef enum { /*!< UART_RSR_OESTAT */
|
|
UART_RSR_OESTAT_NOERR = 0, /*!< NOERR : No error on UART OESTAT, overrun error indicator. */
|
|
UART_RSR_OESTAT_ERR = 1, /*!< ERR : Error on UART OESTAT, overrun error indicator. */
|
|
} UART_RSR_OESTAT_Enum;
|
|
|
|
/* ================================================ UART RSR BESTAT [2..2] ================================================= */
|
|
typedef enum { /*!< UART_RSR_BESTAT */
|
|
UART_RSR_BESTAT_NOERR = 0, /*!< NOERR : No error on UART BESTAT, break error indicator. */
|
|
UART_RSR_BESTAT_ERR = 1, /*!< ERR : Error on UART BESTAT, break error indicator. */
|
|
} UART_RSR_BESTAT_Enum;
|
|
|
|
/* ================================================ UART RSR PESTAT [1..1] ================================================= */
|
|
typedef enum { /*!< UART_RSR_PESTAT */
|
|
UART_RSR_PESTAT_NOERR = 0, /*!< NOERR : No error on UART PESTAT, parity error indicator. */
|
|
UART_RSR_PESTAT_ERR = 1, /*!< ERR : Error on UART PESTAT, parity error indicator. */
|
|
} UART_RSR_PESTAT_Enum;
|
|
|
|
/* ================================================ UART RSR FESTAT [0..0] ================================================= */
|
|
typedef enum { /*!< UART_RSR_FESTAT */
|
|
UART_RSR_FESTAT_NOERR = 0, /*!< NOERR : No error on UART FESTAT, framing error indicator. */
|
|
UART_RSR_FESTAT_ERR = 1, /*!< ERR : Error on UART FESTAT, framing error indicator. */
|
|
} UART_RSR_FESTAT_Enum;
|
|
|
|
/* ========================================================== FR =========================================================== */
|
|
/* ================================================== UART FR TXFE [7..7] ================================================== */
|
|
typedef enum { /*!< UART_FR_TXFE */
|
|
UART_FR_TXFE_XMTFIFO_EMPTY = 1, /*!< XMTFIFO_EMPTY : Transmit fifo is empty. */
|
|
} UART_FR_TXFE_Enum;
|
|
|
|
/* ================================================== UART FR RXFF [6..6] ================================================== */
|
|
typedef enum { /*!< UART_FR_RXFF */
|
|
UART_FR_RXFF_RCVFIFO_FULL = 1, /*!< RCVFIFO_FULL : Receive fifo is full. */
|
|
} UART_FR_RXFF_Enum;
|
|
|
|
/* ================================================== UART FR TXFF [5..5] ================================================== */
|
|
typedef enum { /*!< UART_FR_TXFF */
|
|
UART_FR_TXFF_XMTFIFO_FULL = 1, /*!< XMTFIFO_FULL : Transmit fifo is full. */
|
|
} UART_FR_TXFF_Enum;
|
|
|
|
/* ================================================== UART FR RXFE [4..4] ================================================== */
|
|
typedef enum { /*!< UART_FR_RXFE */
|
|
UART_FR_RXFE_RCVFIFO_EMPTY = 1, /*!< RCVFIFO_EMPTY : Receive fifo is empty. */
|
|
} UART_FR_RXFE_Enum;
|
|
|
|
/* ================================================== UART FR BUSY [3..3] ================================================== */
|
|
typedef enum { /*!< UART_FR_BUSY */
|
|
UART_FR_BUSY_BUSY = 1, /*!< BUSY : UART busy indicator. */
|
|
} UART_FR_BUSY_Enum;
|
|
|
|
/* ================================================== UART FR DCD [2..2] =================================================== */
|
|
typedef enum { /*!< UART_FR_DCD */
|
|
UART_FR_DCD_DETECTED = 1, /*!< DETECTED : Data carrier detect detected. */
|
|
} UART_FR_DCD_Enum;
|
|
|
|
/* ================================================== UART FR DSR [1..1] =================================================== */
|
|
typedef enum { /*!< UART_FR_DSR */
|
|
UART_FR_DSR_READY = 1, /*!< READY : Data set ready. */
|
|
} UART_FR_DSR_Enum;
|
|
|
|
/* ================================================== UART FR CTS [0..0] =================================================== */
|
|
typedef enum { /*!< UART_FR_CTS */
|
|
UART_FR_CTS_CLEARTOSEND = 1, /*!< CLEARTOSEND : Clear to send is indicated. */
|
|
} UART_FR_CTS_Enum;
|
|
|
|
/* ========================================================= ILPR ========================================================== */
|
|
/* ========================================================= IBRD ========================================================== */
|
|
/* ========================================================= FBRD ========================================================== */
|
|
/* ========================================================= LCRH ========================================================== */
|
|
/* ========================================================== CR =========================================================== */
|
|
/* ================================================= UART CR CLKSEL [4..6] ================================================= */
|
|
typedef enum { /*!< UART_CR_CLKSEL */
|
|
UART_CR_CLKSEL_NOCLK = 0, /*!< NOCLK : No UART clock. This is the low power default. */
|
|
UART_CR_CLKSEL_24MHZ = 1, /*!< 24MHZ : 24 MHz clock. Must be used if CLKGEN CORESEL=0. */
|
|
UART_CR_CLKSEL_12MHZ = 2, /*!< 12MHZ : 12 MHz clock. Must be used if CLKGEN CORESEL=1. Note
|
|
that CORESEL=1 is unsupported by the IO Master. */
|
|
UART_CR_CLKSEL_6MHZ = 3, /*!< 6MHZ : 6 MHz clock. Must be used if CLKGEN CORESEL=2, 3, or
|
|
4. Note that CORESEL=2 is unsupported. */
|
|
UART_CR_CLKSEL_3MHZ = 4, /*!< 3MHZ : 3 MHz clock. Must be used if CLKGEN CORESEL=5, 6, or
|
|
7. */
|
|
} UART_CR_CLKSEL_Enum;
|
|
|
|
/* ========================================================= IFLS ========================================================== */
|
|
/* ========================================================== IER ========================================================== */
|
|
/* ========================================================== IES ========================================================== */
|
|
/* ========================================================== MIS ========================================================== */
|
|
/* ========================================================== IEC ========================================================== */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ VCOMP ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
/* ========================================================== CFG ========================================================== */
|
|
/* =============================================== VCOMP CFG LVLSEL [16..19] =============================================== */
|
|
typedef enum { /*!< VCOMP_CFG_LVLSEL */
|
|
VCOMP_CFG_LVLSEL_0P58V = 0, /*!< 0P58V : Set Reference input to 0.58 Volts. */
|
|
VCOMP_CFG_LVLSEL_0P77V = 1, /*!< 0P77V : Set Reference input to 0.77 Volts. */
|
|
VCOMP_CFG_LVLSEL_0P97V = 2, /*!< 0P97V : Set Reference input to 0.97 Volts. */
|
|
VCOMP_CFG_LVLSEL_1P16V = 3, /*!< 1P16V : Set Reference input to 1.16 Volts. */
|
|
VCOMP_CFG_LVLSEL_1P35V = 4, /*!< 1P35V : Set Reference input to 1.35 Volts. */
|
|
VCOMP_CFG_LVLSEL_1P55V = 5, /*!< 1P55V : Set Reference input to 1.55 Volts. */
|
|
VCOMP_CFG_LVLSEL_1P74V = 6, /*!< 1P74V : Set Reference input to 1.74 Volts. */
|
|
VCOMP_CFG_LVLSEL_1P93V = 7, /*!< 1P93V : Set Reference input to 1.93 Volts. */
|
|
VCOMP_CFG_LVLSEL_2P13V = 8, /*!< 2P13V : Set Reference input to 2.13 Volts. */
|
|
VCOMP_CFG_LVLSEL_2P32V = 9, /*!< 2P32V : Set Reference input to 2.32 Volts. */
|
|
VCOMP_CFG_LVLSEL_2P51V = 10, /*!< 2P51V : Set Reference input to 2.51 Volts. */
|
|
VCOMP_CFG_LVLSEL_2P71V = 11, /*!< 2P71V : Set Reference input to 2.71 Volts. */
|
|
VCOMP_CFG_LVLSEL_2P90V = 12, /*!< 2P90V : Set Reference input to 2.90 Volts. */
|
|
VCOMP_CFG_LVLSEL_3P09V = 13, /*!< 3P09V : Set Reference input to 3.09 Volts. */
|
|
VCOMP_CFG_LVLSEL_3P29V = 14, /*!< 3P29V : Set Reference input to 3.29 Volts. */
|
|
VCOMP_CFG_LVLSEL_3P48V = 15, /*!< 3P48V : Set Reference input to 3.48 Volts. */
|
|
} VCOMP_CFG_LVLSEL_Enum;
|
|
|
|
/* ================================================= VCOMP CFG NSEL [8..9] ================================================= */
|
|
typedef enum { /*!< VCOMP_CFG_NSEL */
|
|
VCOMP_CFG_NSEL_VREFEXT1 = 0, /*!< VREFEXT1 : Use external reference 1 for reference input. */
|
|
VCOMP_CFG_NSEL_VREFEXT2 = 1, /*!< VREFEXT2 : Use external reference 2 for reference input. */
|
|
VCOMP_CFG_NSEL_VREFEXT3 = 3, /*!< VREFEXT3 : Use external reference 3 for reference input. */
|
|
} VCOMP_CFG_NSEL_Enum;
|
|
|
|
/* ================================================= VCOMP CFG PSEL [0..1] ================================================= */
|
|
typedef enum { /*!< VCOMP_CFG_PSEL */
|
|
VCOMP_CFG_PSEL_VDDADJ = 0, /*!< VDDADJ : Use VDDADJ for the positive input. */
|
|
VCOMP_CFG_PSEL_VTEMP = 1, /*!< VTEMP : Use the temperature sensor output for the positive input. */
|
|
VCOMP_CFG_PSEL_VEXT1 = 2, /*!< VEXT1 : Use external voltage 1 for positive input. */
|
|
VCOMP_CFG_PSEL_VEXT2 = 3, /*!< VEXT2 : Use external voltage 1 for positive input. */
|
|
} VCOMP_CFG_PSEL_Enum;
|
|
|
|
/* ========================================================= STAT ========================================================== */
|
|
/* =============================================== VCOMP STAT PWDSTAT [1..1] =============================================== */
|
|
typedef enum { /*!< VCOMP_STAT_PWDSTAT */
|
|
VCOMP_STAT_PWDSTAT_POWERED_DOWN = 1, /*!< POWERED_DOWN : The voltage comparator is powered down. */
|
|
} VCOMP_STAT_PWDSTAT_Enum;
|
|
|
|
/* =============================================== VCOMP STAT CMPOUT [0..0] ================================================ */
|
|
typedef enum { /*!< VCOMP_STAT_CMPOUT */
|
|
VCOMP_STAT_CMPOUT_VOUT_LOW = 0, /*!< VOUT_LOW : The negative input of the comparator is greater than
|
|
the positive input. */
|
|
VCOMP_STAT_CMPOUT_VOUT_HIGH = 1, /*!< VOUT_HIGH : The positive input of the comparator is greater
|
|
than the negative input. */
|
|
} VCOMP_STAT_CMPOUT_Enum;
|
|
|
|
/* ======================================================== PWDKEY ========================================================= */
|
|
/* ============================================== VCOMP PWDKEY PWDKEY [0..31] ============================================== */
|
|
typedef enum { /*!< VCOMP_PWDKEY_PWDKEY */
|
|
VCOMP_PWDKEY_PWDKEY_Key = 55, /*!< Key : Key */
|
|
} VCOMP_PWDKEY_PWDKEY_Enum;
|
|
|
|
/* ========================================================= INTEN ========================================================= */
|
|
/* ======================================================== INTSTAT ======================================================== */
|
|
/* ======================================================== INTCLR ========================================================= */
|
|
/* ======================================================== INTSET ========================================================= */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ WDT ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
/* ========================================================== CFG ========================================================== */
|
|
/* ========================================================= RSTRT ========================================================= */
|
|
/* ================================================ WDT RSTRT RSTRT [0..7] ================================================= */
|
|
typedef enum { /*!< WDT_RSTRT_RSTRT */
|
|
WDT_RSTRT_RSTRT_KEYVALUE = 178, /*!< KEYVALUE : This is the key value to write to WDTRSTRT to restart
|
|
the WDT. */
|
|
} WDT_RSTRT_RSTRT_Enum;
|
|
|
|
/* ========================================================= LOCK ========================================================== */
|
|
/* ================================================= WDT LOCK LOCK [0..7] ================================================== */
|
|
typedef enum { /*!< WDT_LOCK_LOCK */
|
|
WDT_LOCK_LOCK_KEYVALUE = 58, /*!< KEYVALUE : This is the key value to write to WDTLOCK to lock
|
|
the WDT. */
|
|
} WDT_LOCK_LOCK_Enum;
|
|
|
|
/* ========================================================= INTEN ========================================================= */
|
|
/* ======================================================== INTSTAT ======================================================== */
|
|
/* ======================================================== INTCLR ========================================================= */
|
|
/* ======================================================== INTSET ========================================================= */
|
|
|
|
/** @} */ /* End of group EnumValue_peripherals */
|
|
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* APOLLO1_H */
|
|
|
|
|
|
/** @} */ /* End of group apollo1 */
|
|
|
|
/** @} */ /* End of group Ambiq Micro */
|
|
|