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278 lines
10 KiB
278 lines
10 KiB
5 months ago
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-02-02 lizhirui first version
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* 2021-02-11 lizhirui fixed gp save/store bug
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* 2021-11-18 JasonHu add fpu registers save/restore
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*/
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#ifndef __STACKFRAME_H__
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#define __STACKFRAME_H__
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#define BYTES(idx) ((idx) * REGBYTES)
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#define FRAME_OFF_SSTATUS BYTES(2)
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#define FRAME_OFF_SP BYTES(32)
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#include "cpuport.h"
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#include "encoding.h"
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#ifdef ENABLE_FPU
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#define FPU_CTX_F0_OFF 0 /* offsetof(fpu_context_t, fpustatus.f[0]) - offsetof(fpu_context_t, fpustatus.f[0]) */
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#define FPU_CTX_F1_OFF 8 /* offsetof(fpu_context_t, fpustatus.f[1]) - offsetof(fpu_context_t, fpustatus.f[0]) */
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#define FPU_CTX_F2_OFF 16 /* offsetof(fpu_context_t, fpustatus.f[2]) - offsetof(fpu_context_t, fpustatus.f[0]) */
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#define FPU_CTX_F3_OFF 24 /* offsetof(fpu_context_t, fpustatus.f[3]) - offsetof(fpu_context_t, fpustatus.f[0]) */
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#define FPU_CTX_F4_OFF 32 /* offsetof(fpu_context_t, fpustatus.f[4]) - offsetof(fpu_context_t, fpustatus.f[0]) */
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#define FPU_CTX_F5_OFF 40 /* offsetof(fpu_context_t, fpustatus.f[5]) - offsetof(fpu_context_t, fpustatus.f[0]) */
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#define FPU_CTX_F6_OFF 48 /* offsetof(fpu_context_t, fpustatus.f[6]) - offsetof(fpu_context_t, fpustatus.f[0]) */
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#define FPU_CTX_F7_OFF 56 /* offsetof(fpu_context_t, fpustatus.f[7]) - offsetof(fpu_context_t, fpustatus.f[0]) */
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#define FPU_CTX_F8_OFF 64 /* offsetof(fpu_context_t, fpustatus.f[8]) - offsetof(fpu_context_t, fpustatus.f[0]) */
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#define FPU_CTX_F9_OFF 72 /* offsetof(fpu_context_t, fpustatus.f[9]) - offsetof(fpu_context_t, fpustatus.f[0]) */
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#define FPU_CTX_F10_OFF 80 /* offsetof(fpu_context_t, fpustatus.f[10]) - offsetof(fpu_context_t, fpustatus.f[0]) */
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#define FPU_CTX_F11_OFF 88 /* offsetof(fpu_context_t, fpustatus.f[11]) - offsetof(fpu_context_t, fpustatus.f[0]) */
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#define FPU_CTX_F12_OFF 96 /* offsetof(fpu_context_t, fpustatus.f[12]) - offsetof(fpu_context_t, fpustatus.f[0]) */
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#define FPU_CTX_F13_OFF 104 /* offsetof(fpu_context_t, fpustatus.f[13]) - offsetof(fpu_context_t, fpustatus.f[0]) */
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#define FPU_CTX_F14_OFF 112 /* offsetof(fpu_context_t, fpustatus.f[14]) - offsetof(fpu_context_t, fpustatus.f[0]) */
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#define FPU_CTX_F15_OFF 120 /* offsetof(fpu_context_t, fpustatus.f[15]) - offsetof(fpu_context_t, fpustatus.f[0]) */
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#define FPU_CTX_F16_OFF 128 /* offsetof(fpu_context_t, fpustatus.f[16]) - offsetof(fpu_context_t, fpustatus.f[0]) */
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#define FPU_CTX_F17_OFF 136 /* offsetof(fpu_context_t, fpustatus.f[17]) - offsetof(fpu_context_t, fpustatus.f[0]) */
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#define FPU_CTX_F18_OFF 144 /* offsetof(fpu_context_t, fpustatus.f[18]) - offsetof(fpu_context_t, fpustatus.f[0]) */
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#define FPU_CTX_F19_OFF 152 /* offsetof(fpu_context_t, fpustatus.f[19]) - offsetof(fpu_context_t, fpustatus.f[0]) */
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#define FPU_CTX_F20_OFF 160 /* offsetof(fpu_context_t, fpustatus.f[20]) - offsetof(fpu_context_t, fpustatus.f[0]) */
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#define FPU_CTX_F21_OFF 168 /* offsetof(fpu_context_t, fpustatus.f[21]) - offsetof(fpu_context_t, fpustatus.f[0]) */
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#define FPU_CTX_F22_OFF 176 /* offsetof(fpu_context_t, fpustatus.f[22]) - offsetof(fpu_context_t, fpustatus.f[0]) */
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#define FPU_CTX_F23_OFF 184 /* offsetof(fpu_context_t, fpustatus.f[23]) - offsetof(fpu_context_t, fpustatus.f[0]) */
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#define FPU_CTX_F24_OFF 192 /* offsetof(fpu_context_t, fpustatus.f[24]) - offsetof(fpu_context_t, fpustatus.f[0]) */
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#define FPU_CTX_F25_OFF 200 /* offsetof(fpu_context_t, fpustatus.f[25]) - offsetof(fpu_context_t, fpustatus.f[0]) */
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#define FPU_CTX_F26_OFF 208 /* offsetof(fpu_context_t, fpustatus.f[26]) - offsetof(fpu_context_t, fpustatus.f[0]) */
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#define FPU_CTX_F27_OFF 216 /* offsetof(fpu_context_t, fpustatus.f[27]) - offsetof(fpu_context_t, fpustatus.f[0]) */
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#define FPU_CTX_F28_OFF 224 /* offsetof(fpu_context_t, fpustatus.f[28]) - offsetof(fpu_context_t, fpustatus.f[0]) */
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#define FPU_CTX_F29_OFF 232 /* offsetof(fpu_context_t, fpustatus.f[29]) - offsetof(fpu_context_t, fpustatus.f[0]) */
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#define FPU_CTX_F30_OFF 240 /* offsetof(fpu_context_t, fpustatus.f[30]) - offsetof(fpu_context_t, fpustatus.f[0]) */
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#define FPU_CTX_F31_OFF 248 /* offsetof(fpu_context_t, fpustatus.f[31]) - offsetof(fpu_context_t, fpustatus.f[0]) */
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#endif /* ENABLE_FPU */
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/**
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* The register `tp` always save/restore when context switch,
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* we call `lwp_user_setting_save` when syscall enter,
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* call `lwp_user_setting_restore` when syscall exit
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* and modify context stack after `lwp_user_setting_restore` called
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* so that the `tp` can be the correct thread area value.
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*/
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.macro SAVE_ALL
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#ifdef ENABLE_FPU
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/* reserve float registers */
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addi sp, sp, -CTX_FPU_REG_NR * REGBYTES
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#endif /* ENABLE_FPU */
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/* save general registers */
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addi sp, sp, -CTX_GENERAL_REG_NR * REGBYTES
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STORE x1, 1 * REGBYTES(sp)
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csrr x1, sstatus
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STORE x1, 2 * REGBYTES(sp)
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csrr x1, sepc
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STORE x1, 0 * REGBYTES(sp)
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STORE x3, 3 * REGBYTES(sp)
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STORE x4, 4 * REGBYTES(sp) /* save tp */
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STORE x5, 5 * REGBYTES(sp)
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STORE x6, 6 * REGBYTES(sp)
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STORE x7, 7 * REGBYTES(sp)
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STORE x8, 8 * REGBYTES(sp)
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STORE x9, 9 * REGBYTES(sp)
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STORE x10, 10 * REGBYTES(sp)
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STORE x11, 11 * REGBYTES(sp)
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STORE x12, 12 * REGBYTES(sp)
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STORE x13, 13 * REGBYTES(sp)
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STORE x14, 14 * REGBYTES(sp)
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STORE x15, 15 * REGBYTES(sp)
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STORE x16, 16 * REGBYTES(sp)
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STORE x17, 17 * REGBYTES(sp)
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STORE x18, 18 * REGBYTES(sp)
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STORE x19, 19 * REGBYTES(sp)
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STORE x20, 20 * REGBYTES(sp)
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STORE x21, 21 * REGBYTES(sp)
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STORE x22, 22 * REGBYTES(sp)
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STORE x23, 23 * REGBYTES(sp)
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STORE x24, 24 * REGBYTES(sp)
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STORE x25, 25 * REGBYTES(sp)
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STORE x26, 26 * REGBYTES(sp)
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STORE x27, 27 * REGBYTES(sp)
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STORE x28, 28 * REGBYTES(sp)
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STORE x29, 29 * REGBYTES(sp)
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STORE x30, 30 * REGBYTES(sp)
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STORE x31, 31 * REGBYTES(sp)
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csrr t0, sscratch
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STORE t0, 32 * REGBYTES(sp)
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#ifdef ENABLE_FPU
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/* backup sp and adjust sp to save float registers */
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mv t1, sp
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addi t1, t1, CTX_GENERAL_REG_NR * REGBYTES
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li t0, SSTATUS_FS
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csrs sstatus, t0
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fsd f0, FPU_CTX_F0_OFF(t1)
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fsd f1, FPU_CTX_F1_OFF(t1)
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fsd f2, FPU_CTX_F2_OFF(t1)
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fsd f3, FPU_CTX_F3_OFF(t1)
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fsd f4, FPU_CTX_F4_OFF(t1)
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fsd f5, FPU_CTX_F5_OFF(t1)
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fsd f6, FPU_CTX_F6_OFF(t1)
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fsd f7, FPU_CTX_F7_OFF(t1)
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fsd f8, FPU_CTX_F8_OFF(t1)
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fsd f9, FPU_CTX_F9_OFF(t1)
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fsd f10, FPU_CTX_F10_OFF(t1)
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fsd f11, FPU_CTX_F11_OFF(t1)
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fsd f12, FPU_CTX_F12_OFF(t1)
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fsd f13, FPU_CTX_F13_OFF(t1)
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fsd f14, FPU_CTX_F14_OFF(t1)
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fsd f15, FPU_CTX_F15_OFF(t1)
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fsd f16, FPU_CTX_F16_OFF(t1)
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fsd f17, FPU_CTX_F17_OFF(t1)
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fsd f18, FPU_CTX_F18_OFF(t1)
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fsd f19, FPU_CTX_F19_OFF(t1)
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fsd f20, FPU_CTX_F20_OFF(t1)
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fsd f21, FPU_CTX_F21_OFF(t1)
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fsd f22, FPU_CTX_F22_OFF(t1)
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fsd f23, FPU_CTX_F23_OFF(t1)
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fsd f24, FPU_CTX_F24_OFF(t1)
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fsd f25, FPU_CTX_F25_OFF(t1)
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fsd f26, FPU_CTX_F26_OFF(t1)
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fsd f27, FPU_CTX_F27_OFF(t1)
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fsd f28, FPU_CTX_F28_OFF(t1)
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fsd f29, FPU_CTX_F29_OFF(t1)
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fsd f30, FPU_CTX_F30_OFF(t1)
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fsd f31, FPU_CTX_F31_OFF(t1)
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/* clr FS domain */
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csrc sstatus, t0
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/* clean status would clr sr_sd; */
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li t0, SSTATUS_FS_CLEAN
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csrs sstatus, t0
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#endif /* ENABLE_FPU */
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.endm
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.macro RESTORE_ALL
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#ifdef ENABLE_FPU
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/* restore float register */
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mv t2, sp
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addi t2, t2, CTX_GENERAL_REG_NR * REGBYTES /* skip all normal reg */
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li t0, SSTATUS_FS
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csrs sstatus, t0
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fld f0, FPU_CTX_F0_OFF(t2)
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fld f1, FPU_CTX_F1_OFF(t2)
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fld f2, FPU_CTX_F2_OFF(t2)
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fld f3, FPU_CTX_F3_OFF(t2)
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fld f4, FPU_CTX_F4_OFF(t2)
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fld f5, FPU_CTX_F5_OFF(t2)
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fld f6, FPU_CTX_F6_OFF(t2)
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fld f7, FPU_CTX_F7_OFF(t2)
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fld f8, FPU_CTX_F8_OFF(t2)
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fld f9, FPU_CTX_F9_OFF(t2)
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fld f10, FPU_CTX_F10_OFF(t2)
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fld f11, FPU_CTX_F11_OFF(t2)
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fld f12, FPU_CTX_F12_OFF(t2)
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fld f13, FPU_CTX_F13_OFF(t2)
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fld f14, FPU_CTX_F14_OFF(t2)
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fld f15, FPU_CTX_F15_OFF(t2)
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fld f16, FPU_CTX_F16_OFF(t2)
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fld f17, FPU_CTX_F17_OFF(t2)
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fld f18, FPU_CTX_F18_OFF(t2)
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fld f19, FPU_CTX_F19_OFF(t2)
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fld f20, FPU_CTX_F20_OFF(t2)
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fld f21, FPU_CTX_F21_OFF(t2)
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fld f22, FPU_CTX_F22_OFF(t2)
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fld f23, FPU_CTX_F23_OFF(t2)
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fld f24, FPU_CTX_F24_OFF(t2)
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fld f25, FPU_CTX_F25_OFF(t2)
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fld f26, FPU_CTX_F26_OFF(t2)
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fld f27, FPU_CTX_F27_OFF(t2)
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fld f28, FPU_CTX_F28_OFF(t2)
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fld f29, FPU_CTX_F29_OFF(t2)
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fld f30, FPU_CTX_F30_OFF(t2)
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fld f31, FPU_CTX_F31_OFF(t2)
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/* clr FS domain */
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csrc sstatus, t0
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/* clean status would clr sr_sd; */
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li t0, SSTATUS_FS_CLEAN
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csrs sstatus, t0
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#endif /* ENABLE_FPU */
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/* restore general register */
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/* resw ra to sepc */
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LOAD x1, 0 * REGBYTES(sp)
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csrw sepc, x1
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LOAD x1, 2 * REGBYTES(sp)
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csrw sstatus, x1
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LOAD x1, 1 * REGBYTES(sp)
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LOAD x3, 3 * REGBYTES(sp)
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LOAD x4, 4 * REGBYTES(sp) /* restore tp */
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LOAD x5, 5 * REGBYTES(sp)
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LOAD x6, 6 * REGBYTES(sp)
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LOAD x7, 7 * REGBYTES(sp)
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LOAD x8, 8 * REGBYTES(sp)
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LOAD x9, 9 * REGBYTES(sp)
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LOAD x10, 10 * REGBYTES(sp)
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LOAD x11, 11 * REGBYTES(sp)
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LOAD x12, 12 * REGBYTES(sp)
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LOAD x13, 13 * REGBYTES(sp)
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LOAD x14, 14 * REGBYTES(sp)
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LOAD x15, 15 * REGBYTES(sp)
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LOAD x16, 16 * REGBYTES(sp)
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LOAD x17, 17 * REGBYTES(sp)
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LOAD x18, 18 * REGBYTES(sp)
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LOAD x19, 19 * REGBYTES(sp)
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LOAD x20, 20 * REGBYTES(sp)
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LOAD x21, 21 * REGBYTES(sp)
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LOAD x22, 22 * REGBYTES(sp)
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LOAD x23, 23 * REGBYTES(sp)
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LOAD x24, 24 * REGBYTES(sp)
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LOAD x25, 25 * REGBYTES(sp)
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LOAD x26, 26 * REGBYTES(sp)
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LOAD x27, 27 * REGBYTES(sp)
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LOAD x28, 28 * REGBYTES(sp)
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LOAD x29, 29 * REGBYTES(sp)
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LOAD x30, 30 * REGBYTES(sp)
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LOAD x31, 31 * REGBYTES(sp)
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/* restore user sp */
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LOAD sp, 32 * REGBYTES(sp)
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.endm
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.macro RESTORE_SYS_GP
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.option push
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.option norelax
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la gp, __global_pointer$
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.option pop
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.endm
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.macro OPEN_INTERRUPT
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csrsi sstatus, 2
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.endm
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.macro CLOSE_INTERRUPT
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csrci sstatus, 2
|
||
|
|
.endm
|
||
|
|
|
||
|
|
#endif
|