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229 lines
16 KiB
229 lines
16 KiB
5 months ago
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#ifndef __UART_H__
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#define __UART_H__
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/* Accepted Error baud rate value (in percent unit) */
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#define UART_ACCEPTED_BAUDRATE_ERROR (3) /*!< Acceptable UART baudrate error */
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/* --------------------- BIT DEFINITIONS -------------------------------------- */
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/*********************************************************************//**
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* Macro defines for Macro defines for UARTn Receiver Buffer Register
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**********************************************************************/
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#define UART_RBR_MASKBIT ((uint8_t)0xFF) /*!< UART Received Buffer mask bit (8 bits) */
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/*********************************************************************//**
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* Macro defines for Macro defines for UARTn Transmit Holding Register
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**********************************************************************/
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#define UART_THR_MASKBIT ((uint8_t)0xFF) /*!< UART Transmit Holding mask bit (8 bits) */
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/*********************************************************************//**
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* Macro defines for Macro defines for UARTn Divisor Latch LSB register
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**********************************************************************/
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#define UART_LOAD_DLL(div) ((div) & 0xFF) /**< Macro for loading least significant halfs of divisors */
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#define UART_DLL_MASKBIT ((uint8_t)0xFF) /*!< Divisor latch LSB bit mask */
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/*********************************************************************//**
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* Macro defines for Macro defines for UARTn Divisor Latch MSB register
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**********************************************************************/
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#define UART_DLM_MASKBIT ((uint8_t)0xFF) /*!< Divisor latch MSB bit mask */
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#define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF) /**< Macro for loading most significant halfs of divisors */
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/*********************************************************************//**
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* Macro defines for Macro defines for UART interrupt enable register
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**********************************************************************/
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#define UART_IER_RBRINT_EN ((uint32_t)(1<<0)) /*!< RBR Interrupt enable*/
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#define UART_IER_THREINT_EN ((uint32_t)(1<<1)) /*!< THR Interrupt enable*/
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#define UART_IER_RLSINT_EN ((uint32_t)(1<<2)) /*!< RX line status interrupt enable*/
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#define UART1_IER_MSINT_EN ((uint32_t)(1<<3)) /*!< Modem status interrupt enable */
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#define UART1_IER_CTSINT_EN ((uint32_t)(1<<7)) /*!< CTS1 signal transition interrupt enable */
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#define UART_IER_ABEOINT_EN ((uint32_t)(1<<8)) /*!< Enables the end of auto-baud interrupt */
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#define UART_IER_ABTOINT_EN ((uint32_t)(1<<9)) /*!< Enables the auto-baud time-out interrupt */
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#define UART_IER_BITMASK ((uint32_t)(0x307)) /*!< UART interrupt enable register bit mask */
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#define UART1_IER_BITMASK ((uint32_t)(0x38F)) /*!< UART1 interrupt enable register bit mask */
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/*********************************************************************//**
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* Macro defines for Macro defines for UART interrupt identification register
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**********************************************************************/
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#define UART_IIR_INTSTAT_PEND ((uint32_t)(1<<0)) /*!<Interrupt Status - Active low */
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#define UART_IIR_INTID_RLS ((uint32_t)(3<<1)) /*!<Interrupt identification: Receive line status*/
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#define UART_IIR_INTID_RDA ((uint32_t)(2<<1)) /*!<Interrupt identification: Receive data available*/
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#define UART_IIR_INTID_CTI ((uint32_t)(6<<1)) /*!<Interrupt identification: Character time-out indicator*/
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#define UART_IIR_INTID_THRE ((uint32_t)(1<<1)) /*!<Interrupt identification: THRE interrupt*/
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#define UART1_IIR_INTID_MODEM ((uint32_t)(0<<1)) /*!<Interrupt identification: Modem interrupt*/
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#define UART_IIR_INTID_MASK ((uint32_t)(7<<1)) /*!<Interrupt identification: Interrupt ID mask */
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#define UART_IIR_FIFO_EN ((uint32_t)(3<<6)) /*!<These bits are equivalent to UnFCR[0] */
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#define UART_IIR_ABEO_INT ((uint32_t)(1<<8)) /*!< End of auto-baud interrupt */
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#define UART_IIR_ABTO_INT ((uint32_t)(1<<9)) /*!< Auto-baud time-out interrupt */
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#define UART_IIR_BITMASK ((uint32_t)(0x3CF)) /*!< UART interrupt identification register bit mask */
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/*********************************************************************//**
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* Macro defines for Macro defines for UART FIFO control register
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**********************************************************************/
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#define UART_FCR_FIFO_EN ((uint8_t)(1<<0)) /*!< UART FIFO enable */
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#define UART_FCR_RX_RS ((uint8_t)(1<<1)) /*!< UART FIFO RX reset */
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#define UART_FCR_TX_RS ((uint8_t)(1<<2)) /*!< UART FIFO TX reset */
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#define UART_FCR_DMAMODE_SEL ((uint8_t)(1<<3)) /*!< UART DMA mode selection */
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#define UART_FCR_TRG_LEV0 ((uint8_t)(0)) /*!< UART FIFO trigger level 0: 1 character */
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#define UART_FCR_TRG_LEV1 ((uint8_t)(1<<6)) /*!< UART FIFO trigger level 1: 4 character */
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#define UART_FCR_TRG_LEV2 ((uint8_t)(2<<6)) /*!< UART FIFO trigger level 2: 8 character */
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#define UART_FCR_TRG_LEV3 ((uint8_t)(3<<6)) /*!< UART FIFO trigger level 3: 14 character */
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#define UART_FCR_BITMASK ((uint8_t)(0xCF)) /*!< UART FIFO control bit mask */
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#define UART_TX_FIFO_SIZE (16)
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/*********************************************************************//**
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* Macro defines for Macro defines for UART line control register
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**********************************************************************/
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#define UART_LCR_WLEN5 ((uint8_t)(0)) /*!< UART 5 bit data mode */
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#define UART_LCR_WLEN6 ((uint8_t)(1<<0)) /*!< UART 6 bit data mode */
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#define UART_LCR_WLEN7 ((uint8_t)(2<<0)) /*!< UART 7 bit data mode */
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#define UART_LCR_WLEN8 ((uint8_t)(3<<0)) /*!< UART 8 bit data mode */
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#define UART_LCR_STOPBIT_SEL ((uint8_t)(1<<2)) /*!< UART Two Stop Bits Select */
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#define UART_LCR_PARITY_EN ((uint8_t)(1<<3)) /*!< UART Parity Enable */
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#define UART_LCR_PARITY_ODD ((uint8_t)(0)) /*!< UART Odd Parity Select */
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#define UART_LCR_PARITY_EVEN ((uint8_t)(1<<4)) /*!< UART Even Parity Select */
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#define UART_LCR_PARITY_F_1 ((uint8_t)(2<<4)) /*!< UART force 1 stick parity */
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#define UART_LCR_PARITY_F_0 ((uint8_t)(3<<4)) /*!< UART force 0 stick parity */
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#define UART_LCR_BREAK_EN ((uint8_t)(1<<6)) /*!< UART Transmission Break enable */
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#define UART_LCR_DLAB_EN ((uint8_t)(1<<7)) /*!< UART Divisor Latches Access bit enable */
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#define UART_LCR_BITMASK ((uint8_t)(0xFF)) /*!< UART line control bit mask */
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/*********************************************************************//**
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* Macro defines for Macro defines for UART1 Modem Control Register
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**********************************************************************/
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#define UART1_MCR_DTR_CTRL ((uint8_t)(1<<0)) /*!< Source for modem output pin DTR */
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#define UART1_MCR_RTS_CTRL ((uint8_t)(1<<1)) /*!< Source for modem output pin RTS */
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#define UART1_MCR_LOOPB_EN ((uint8_t)(1<<4)) /*!< Loop back mode select */
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#define UART1_MCR_AUTO_RTS_EN ((uint8_t)(1<<6)) /*!< Enable Auto RTS flow-control */
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#define UART1_MCR_AUTO_CTS_EN ((uint8_t)(1<<7)) /*!< Enable Auto CTS flow-control */
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#define UART1_MCR_BITMASK ((uint8_t)(0x0F3)) /*!< UART1 bit mask value */
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/*********************************************************************//**
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* Macro defines for Macro defines for UART line status register
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**********************************************************************/
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#define UART_LSR_RDR ((uint8_t)(1<<0)) /*!<Line status register: Receive data ready*/
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#define UART_LSR_OE ((uint8_t)(1<<1)) /*!<Line status register: Overrun error*/
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#define UART_LSR_PE ((uint8_t)(1<<2)) /*!<Line status register: Parity error*/
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#define UART_LSR_FE ((uint8_t)(1<<3)) /*!<Line status register: Framing error*/
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#define UART_LSR_BI ((uint8_t)(1<<4)) /*!<Line status register: Break interrupt*/
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#define UART_LSR_THRE ((uint8_t)(1<<5)) /*!<Line status register: Transmit holding register empty*/
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#define UART_LSR_TEMT ((uint8_t)(1<<6)) /*!<Line status register: Transmitter empty*/
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#define UART_LSR_RXFE ((uint8_t)(1<<7)) /*!<Error in RX FIFO*/
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#define UART_LSR_BITMASK ((uint8_t)(0xFF)) /*!<UART Line status bit mask */
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/*********************************************************************//**
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* Macro defines for Macro defines for UART Modem (UART1 only) status register
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**********************************************************************/
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#define UART1_MSR_DELTA_CTS ((uint8_t)(1<<0)) /*!< Set upon state change of input CTS */
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#define UART1_MSR_DELTA_DSR ((uint8_t)(1<<1)) /*!< Set upon state change of input DSR */
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#define UART1_MSR_LO2HI_RI ((uint8_t)(1<<2)) /*!< Set upon low to high transition of input RI */
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#define UART1_MSR_DELTA_DCD ((uint8_t)(1<<3)) /*!< Set upon state change of input DCD */
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#define UART1_MSR_CTS ((uint8_t)(1<<4)) /*!< Clear To Send State */
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#define UART1_MSR_DSR ((uint8_t)(1<<5)) /*!< Data Set Ready State */
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#define UART1_MSR_RI ((uint8_t)(1<<6)) /*!< Ring Indicator State */
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#define UART1_MSR_DCD ((uint8_t)(1<<7)) /*!< Data Carrier Detect State */
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#define UART1_MSR_BITMASK ((uint8_t)(0xFF)) /*!< MSR register bit-mask value */
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/*********************************************************************//**
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* Macro defines for Macro defines for UART Scratch Pad Register
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**********************************************************************/
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#define UART_SCR_BIMASK ((uint8_t)(0xFF)) /*!< UART Scratch Pad bit mask */
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/*********************************************************************//**
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* Macro defines for Macro defines for UART Auto baudrate control register
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**********************************************************************/
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#define UART_ACR_START ((uint32_t)(1<<0)) /**< UART Auto-baud start */
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#define UART_ACR_MODE ((uint32_t)(1<<1)) /**< UART Auto baudrate Mode 1 */
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#define UART_ACR_AUTO_RESTART ((uint32_t)(1<<2)) /**< UART Auto baudrate restart */
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#define UART_ACR_ABEOINT_CLR ((uint32_t)(1<<8)) /**< UART End of auto-baud interrupt clear */
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#define UART_ACR_ABTOINT_CLR ((uint32_t)(1<<9)) /**< UART Auto-baud time-out interrupt clear */
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#define UART_ACR_BITMASK ((uint32_t)(0x307)) /**< UART Auto Baudrate register bit mask */
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/*********************************************************************//**
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* Macro defines for Macro defines for UART IrDA control register
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**********************************************************************/
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#define UART_ICR_IRDAEN ((uint32_t)(1<<0)) /**< IrDA mode enable */
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#define UART_ICR_IRDAINV ((uint32_t)(1<<1)) /**< IrDA serial input inverted */
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#define UART_ICR_FIXPULSE_EN ((uint32_t)(1<<2)) /**< IrDA fixed pulse width mode */
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#define UART_ICR_PULSEDIV(n) ((uint32_t)((n&0x07)<<3)) /**< PulseDiv - Configures the pulse when FixPulseEn = 1 */
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#define UART_ICR_BITMASK ((uint32_t)(0x3F)) /*!< UART IRDA bit mask */
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/*********************************************************************//**
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* Macro defines for Macro defines for UART half duplex register
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**********************************************************************/
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#define UART_HDEN_HDEN ((uint32_t)(1<<0)) /**< enable half-duplex mode*/
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/*********************************************************************//**
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* Macro defines for Macro defines for UART smart card interface control register
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**********************************************************************/
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#define UART_SCICTRL_SCIEN ((uint32_t)(1<<0)) /**< enable asynchronous half-duplex smart card interface*/
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#define UART_SCICTRL_NACKDIS ((uint32_t)(1<<1)) /**< NACK response is inhibited*/
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#define UART_SCICTRL_PROTSEL_T1 ((uint32_t)(1<<2)) /**< ISO7816-3 protocol T1 is selected*/
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#define UART_SCICTRL_TXRETRY(n) ((uint32_t)((n&0x07)<<5)) /**< number of retransmission*/
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#define UART_SCICTRL_GUARDTIME(n) ((uint32_t)((n&0xFF)<<8)) /**< Extra guard time*/
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/*********************************************************************//**
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* Macro defines for Macro defines for UART synchronous control register
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**********************************************************************/
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#define UART_SYNCCTRL_SYNC ((uint32_t)(1<<0)) /**< enable synchronous mode*/
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#define UART_SYNCCTRL_CSRC_MASTER ((uint32_t)(1<<1)) /**< synchronous master mode*/
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#define UART_SYNCCTRL_FES ((uint32_t)(1<<2)) /**< sample on falling edge*/
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#define UART_SYNCCTRL_TSBYPASS ((uint32_t)(1<<3)) /**< to be defined*/
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#define UART_SYNCCTRL_CSCEN ((uint32_t)(1<<4)) /**< continuous running clock enable (master mode only)*/
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#define UART_SYNCCTRL_STARTSTOPDISABLE ((uint32_t)(1<<5)) /**< do not send start/stop bit*/
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#define UART_SYNCCTRL_CCCLR ((uint32_t)(1<<6)) /**< stop continuous clock*/
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/*********************************************************************//**
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* Macro defines for Macro defines for UART Fractional divider register
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**********************************************************************/
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#define UART_FDR_DIVADDVAL(n) ((uint32_t)(n&0x0F)) /**< Baud-rate generation pre-scaler divisor */
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#define UART_FDR_MULVAL(n) ((uint32_t)((n<<4)&0xF0)) /**< Baud-rate pre-scaler multiplier value */
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#define UART_FDR_BITMASK ((uint32_t)(0xFF)) /**< UART Fractional Divider register bit mask */
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/*********************************************************************//**
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* Macro defines for Macro defines for UART Tx Enable register
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**********************************************************************/
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#define UART1_TER_TXEN ((uint8_t)(1<<7)) /*!< Transmit enable bit */
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#define UART1_TER_BITMASK ((uint8_t)(0x80)) /**< UART Transmit Enable Register bit mask */
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#define UART0_2_3_TER_TXEN ((uint8_t)(1<<0)) /*!< Transmit enable bit */
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#define UART0_2_3_TER_BITMASK ((uint8_t)(0x01)) /**< UART Transmit Enable Register bit mask */
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/*********************************************************************//**
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* Macro defines for Macro defines for UART1 RS485 Control register
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**********************************************************************/
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#define UART_RS485CTRL_NMM_EN ((uint32_t)(1<<0)) /*!< RS-485/EIA-485 Normal Multi-drop Mode (NMM)
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is disabled */
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#define UART_RS485CTRL_RX_DIS ((uint32_t)(1<<1)) /*!< The receiver is disabled */
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#define UART_RS485CTRL_AADEN ((uint32_t)(1<<2)) /*!< Auto Address Detect (AAD) is enabled */
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#define UART_RS485CTRL_SEL_DTR ((uint32_t)(1<<3)) /*!< If direction control is enabled
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(bit DCTRL = 1), pin DTR is used for direction control */
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#define UART_RS485CTRL_DCTRL_EN ((uint32_t)(1<<4)) /*!< Enable Auto Direction Control */
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#define UART_RS485CTRL_OINV_1 ((uint32_t)(1<<5)) /*!< This bit reverses the polarity of the direction
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control signal on the RTS (or DTR) pin. The direction control pin
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will be driven to logic "1" when the transmitter has data to be sent */
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#define UART_RS485CTRL_BITMASK ((uint32_t)(0x3F)) /**< RS485 control bit-mask value */
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/*********************************************************************//**
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* Macro defines for Macro defines for UART1 RS-485 Address Match register
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**********************************************************************/
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#define UART_RS485ADRMATCH_BITMASK ((uint8_t)(0xFF)) /**< Bit mask value */
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/*********************************************************************//**
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* Macro defines for Macro defines for UART1 RS-485 Delay value register
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**********************************************************************/
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/* Macro defines for UART1 RS-485 Delay value register */
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#define UART_RS485DLY_BITMASK ((uint8_t)(0xFF)) /** Bit mask value */
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/*********************************************************************//**
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* Macro defines for Macro defines for UART FIFO Level register
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**********************************************************************/
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#define UART_FIFOLVL_RXFIFOLVL(n) ((uint32_t)(n&0x0F)) /**< Reflects the current level of the UART receiver FIFO */
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#define UART_FIFOLVL_TXFIFOLVL(n) ((uint32_t)((n>>8)&0x0F)) /**< Reflects the current level of the UART transmitter FIFO */
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#define UART_FIFOLVL_BITMASK ((uint32_t)(0x0F0F)) /**< UART FIFO Level Register bit mask */
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void rt_hw_uart_init(void);
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#endif
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