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305 lines
9.8 KiB
305 lines
9.8 KiB
5 months ago
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/*
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* Copyright (c) 2021-2023 HPMicro
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#include "hpm_common.h"
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#include "hpm_soc.h"
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#include <rtthread.h>
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#include "rt_hw_stack_frame.h"
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#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) //!< Instruction Address misaligned
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#define MCAUSE_INSTR_ACCESS_FAULT (1U) //!< Instruction access fault
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#define MCAUSE_ILLEGAL_INSTR (2U) //!< Illegal instruction
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#define MCAUSE_BREAKPOINT (3U) //!< Breakpoint
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#define MCAUSE_LOAD_ADDR_MISALIGNED (4U) //!< Load address misaligned
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#define MCAUSE_LOAD_ACCESS_FAULT (5U) //!< Load access fault
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#define MCAUSE_STORE_AMO_ADDR_MISALIGNED (6U) //!< Store/AMO address misaligned
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#define MCAUSE_STORE_AMO_ACCESS_FAULT (7U) //!< Store/AMO access fault
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#define MCAUSE_ECALL_FROM_USER_MODE (8U) //!< Environment call from User mode
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#define MCAUSE_ECALL_FROM_SUPERVISOR_MODE (9U) //!< Environment call from Supervisor mode
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#define MCAUSE_ECALL_FROM_MACHINE_MODE (11U) //!< Environment call from machine mode
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#define MCAUSE_INSTR_PAGE_FAULT (12U) //!< Instruction page fault
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#define MCAUSE_LOAD_PAGE_FAULT (13) //!< Load page fault
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#define MCAUSE_STORE_AMO_PAGE_FAULT (15U) //!< Store/AMO page fault
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#define IRQ_S_SOFT 1
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#define IRQ_H_SOFT 2
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#define IRQ_M_SOFT 3
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#define IRQ_S_TIMER 5
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#define IRQ_H_TIMER 6
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#define IRQ_M_TIMER 7
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#define IRQ_S_EXT 9
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#define IRQ_H_EXT 10
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#define IRQ_M_EXT 11
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#define IRQ_COP 12
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#define IRQ_HOST 13
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#ifdef DEBUG
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#define RT_EXCEPTION_TRACE rt_kprintf
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#else
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#define RT_EXCEPTION_TRACE(...)
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#endif
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typedef void (*isr_func_t)(void);
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static volatile rt_hw_stack_frame_t *s_stack_frame;
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__attribute((weak)) void mchtmr_isr(void)
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{
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}
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__attribute__((weak)) void mswi_isr(void)
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{
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}
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__attribute__((weak)) void syscall_handler(uint32_t n, uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3)
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{
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}
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void rt_show_stack_frame(void)
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{
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RT_EXCEPTION_TRACE("Stack frame:\r\n----------------------------------------\r\n");
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RT_EXCEPTION_TRACE("ra : 0x%08x\r\n", s_stack_frame->ra);
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RT_EXCEPTION_TRACE("mstatus : 0x%08x\r\n", read_csr(0x300));//mstatus
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RT_EXCEPTION_TRACE("t0 : 0x%08x\r\n", s_stack_frame->t0);
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RT_EXCEPTION_TRACE("t1 : 0x%08x\r\n", s_stack_frame->t1);
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RT_EXCEPTION_TRACE("t2 : 0x%08x\r\n", s_stack_frame->t2);
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RT_EXCEPTION_TRACE("a0 : 0x%08x\r\n", s_stack_frame->a0);
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RT_EXCEPTION_TRACE("a1 : 0x%08x\r\n", s_stack_frame->a1);
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RT_EXCEPTION_TRACE("a2 : 0x%08x\r\n", s_stack_frame->a2);
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RT_EXCEPTION_TRACE("a3 : 0x%08x\r\n", s_stack_frame->a3);
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RT_EXCEPTION_TRACE("a4 : 0x%08x\r\n", s_stack_frame->a4);
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RT_EXCEPTION_TRACE("a5 : 0x%08x\r\n", s_stack_frame->a5);
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#ifndef __riscv_32e
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RT_EXCEPTION_TRACE("a6 : 0x%08x\r\n", s_stack_frame->a6);
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RT_EXCEPTION_TRACE("a7 : 0x%08x\r\n", s_stack_frame->a7);
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RT_EXCEPTION_TRACE("t3 : 0x%08x\r\n", s_stack_frame->t3);
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RT_EXCEPTION_TRACE("t4 : 0x%08x\r\n", s_stack_frame->t4);
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RT_EXCEPTION_TRACE("t5 : 0x%08x\r\n", s_stack_frame->t5);
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RT_EXCEPTION_TRACE("t6 : 0x%08x\r\n", s_stack_frame->t6);
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#endif
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}
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uint32_t exception_handler(uint32_t cause, uint32_t epc)
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{
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/* Unhandled Trap */
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uint32_t mdcause = read_csr(CSR_MDCAUSE);
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uint32_t mtval = read_csr(CSR_MTVAL);
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rt_uint32_t mscratch = read_csr(0x340);
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s_stack_frame = (rt_hw_stack_frame_t *)mscratch;
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rt_show_stack_frame();
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switch (cause)
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{
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case MCAUSE_INSTR_ADDR_MISALIGNED:
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RT_EXCEPTION_TRACE("exception: instruction address was mis-aligned, mtval=0x%08x\n", mtval);
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break;
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case MCAUSE_INSTR_ACCESS_FAULT:
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RT_EXCEPTION_TRACE("exception: instruction access fault happened, mtval=0x%08x, epc=0x%08x\n", mtval, epc);
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switch (mdcause & 0x07)
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{
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case 1:
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RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n");
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break;
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case 2:
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RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n");
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break;
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case 3:
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RT_EXCEPTION_TRACE("mdcause: BUS error\r\n");
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break;
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case 4:
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RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n");
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break;
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default:
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RT_EXCEPTION_TRACE("mdcause: reserved \r\n");
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break;
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}
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break;
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case MCAUSE_ILLEGAL_INSTR:
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RT_EXCEPTION_TRACE("exception: illegal instruction was met, mtval=0x%08x\n", mtval);
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switch (mdcause & 0x07)
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{
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case 0:
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RT_EXCEPTION_TRACE("mdcause: the actual faulting instruction is stored in the mtval CSR\r\n");
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break;
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case 1:
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RT_EXCEPTION_TRACE("mdcause: FP disabled exception \r\n");
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break;
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case 2:
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RT_EXCEPTION_TRACE("mdcause: ACE disabled exception \r\n");
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break;
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default:
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RT_EXCEPTION_TRACE("mdcause: reserved \r\n");
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break;
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}
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break;
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case MCAUSE_BREAKPOINT:
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RT_EXCEPTION_TRACE("exception: breakpoint was hit, mtval=0x%08x\n", mtval);
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break;
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case MCAUSE_LOAD_ADDR_MISALIGNED:
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RT_EXCEPTION_TRACE("exception: load address was mis-aligned, mtval=0x%08x\n", mtval);
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break;
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case MCAUSE_LOAD_ACCESS_FAULT:
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RT_EXCEPTION_TRACE("exception: load access fault happened, epc=%08x, mdcause=0x%x\n", epc, mdcause);
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switch (mdcause & 0x07)
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{
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case 1:
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RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n");
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break;
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case 2:
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RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n");
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break;
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case 3:
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RT_EXCEPTION_TRACE("mdcause: BUS error\r\n");
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break;
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case 4:
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RT_EXCEPTION_TRACE("mdcause: Misaligned access \r\n");
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break;
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case 5:
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RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n");
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break;
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case 6:
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RT_EXCEPTION_TRACE("mdcause: PMA attribute inconsistency\r\n");
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break;
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default:
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RT_EXCEPTION_TRACE("mdcause: reserved \r\n");
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break;
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}
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break;
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case MCAUSE_STORE_AMO_ADDR_MISALIGNED:
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RT_EXCEPTION_TRACE("exception: store amo address was misaligned, epc=%08x\n", epc);
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break;
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case MCAUSE_STORE_AMO_ACCESS_FAULT:
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RT_EXCEPTION_TRACE("exception: store amo access fault happened, epc=%08x\n", epc);
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switch (mdcause & 0x07)
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{
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case 1:
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RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n");
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break;
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case 2:
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RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n");
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break;
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case 3:
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RT_EXCEPTION_TRACE("mdcause: BUS error\r\n");
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break;
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case 4:
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RT_EXCEPTION_TRACE("mdcause: Misaligned access \r\n");
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break;
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case 5:
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RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n");
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break;
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case 6:
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RT_EXCEPTION_TRACE("mdcause: PMA attribute inconsistency\r\n");
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break;
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case 7:
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RT_EXCEPTION_TRACE("mdcause: PMA NAMO exception \r\n");
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default:
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RT_EXCEPTION_TRACE("mdcause: reserved \r\n");
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break;
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}
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break;
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default:
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RT_EXCEPTION_TRACE("Unknown exception happened, cause=%d\n", cause);
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break;
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}
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rt_kprintf("cause=0x%08x, epc=0x%08x, ra=0x%08x\n", cause, epc, s_stack_frame->ra);
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while(1) {
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}
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}
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void trap_entry(void);
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void trap_entry(void)
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{
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uint32_t mcause = read_csr(CSR_MCAUSE);
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uint32_t mepc = read_csr(CSR_MEPC);
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uint32_t mstatus = read_csr(CSR_MSTATUS);
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#if SUPPORT_PFT_ARCH
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uint32_t mxstatus = read_csr(CSR_MXSTATUS);
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#endif
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#ifdef __riscv_dsp
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int ucode = read_csr(CSR_UCODE);
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#endif
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#ifdef __riscv_flen
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int fcsr = read_fcsr();
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#endif
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/* clobbers list for ecall */
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#ifdef __riscv_32e
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__asm volatile("" : : :"t0", "a0", "a1", "a2", "a3");
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#else
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__asm volatile("" : : :"a7", "a0", "a1", "a2", "a3");
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#endif
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/* Do your trap handling */
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uint32_t cause_type = mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK;
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uint32_t irq_index;
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if (mcause & CSR_MCAUSE_INTERRUPT_MASK)
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{
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switch (cause_type)
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{
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/* Machine timer interrupt */
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case IRQ_M_TIMER:
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mchtmr_isr();
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break;
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/* Machine EXT interrupt */
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case IRQ_M_EXT:
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/* Claim interrupt */
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irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE);
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/* Execute EXT interrupt handler */
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if (irq_index > 0)
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{
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((isr_func_t) __vector_table[irq_index])();
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/* Complete interrupt */
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__plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq_index);
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}
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break;
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/* Machine SWI interrupt */
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case IRQ_M_SOFT:
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mswi_isr();
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intc_m_complete_swi();
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break;
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}
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}
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else if (cause_type == MCAUSE_ECALL_FROM_MACHINE_MODE)
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{
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/* Machine Syscal call */
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__asm volatile(
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"mv a4, a3\n"
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"mv a3, a2\n"
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"mv a2, a1\n"
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"mv a1, a0\n"
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#ifdef __riscv_32e
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"mv a0, t0\n"
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#else
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"mv a0, a7\n"
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#endif
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"call syscall_handler\n"
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: : : "a4"
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);
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mepc += 4;
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}
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else
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{
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mepc = exception_handler(mcause, mepc);
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}
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/* Restore CSR */
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write_csr(CSR_MSTATUS, mstatus);
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write_csr(CSR_MEPC, mepc);
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#if SUPPORT_PFT_ARCH
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write_csr(CSR_MXSTATUS, mxstatus);
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#endif
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#ifdef __riscv_dsp
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write_csr(CSR_UCODE, ucode);
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#endif
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#ifdef __riscv_flen
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write_fcsr(fcsr);
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#endif
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}
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