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132 lines
4.4 KiB
132 lines
4.4 KiB
3 months ago
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2011-01-13 weety first version
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*/
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#ifndef __DAVINCI_MMC_H__
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#define __DAVINCI_MMC_H__
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/* DAVINCI_MMCCTL definitions */
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#define MMCCTL_DATRST (1 << 0)
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#define MMCCTL_CMDRST (1 << 1)
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#define MMCCTL_WIDTH_8_BIT (1 << 8)
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#define MMCCTL_WIDTH_4_BIT (1 << 2)
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#define MMCCTL_DATEG_DISABLED (0 << 6)
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#define MMCCTL_DATEG_RISING (1 << 6)
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#define MMCCTL_DATEG_FALLING (2 << 6)
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#define MMCCTL_DATEG_BOTH (3 << 6)
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#define MMCCTL_PERMDR_LE (0 << 9)
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#define MMCCTL_PERMDR_BE (1 << 9)
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#define MMCCTL_PERMDX_LE (0 << 10)
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#define MMCCTL_PERMDX_BE (1 << 10)
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/* DAVINCI_MMCCLK definitions */
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#define MMCCLK_CLKEN (1 << 8)
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#define MMCCLK_CLKRT_MASK (0xFF << 0)
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/* IRQ bit definitions, for DAVINCI_MMCST0 and DAVINCI_MMCIM */
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#define MMCST0_DATDNE (1 << 0) /* data done */
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#define MMCST0_BSYDNE (1 << 1) /* busy done */
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#define MMCST0_RSPDNE (1 << 2) /* command done */
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#define MMCST0_TOUTRD (1 << 3) /* data read timeout */
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#define MMCST0_TOUTRS (1 << 4) /* command response timeout */
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#define MMCST0_CRCWR (1 << 5) /* data write CRC error */
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#define MMCST0_CRCRD (1 << 6) /* data read CRC error */
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#define MMCST0_CRCRS (1 << 7) /* command response CRC error */
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#define MMCST0_DXRDY (1 << 9) /* data transmit ready (fifo empty) */
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#define MMCST0_DRRDY (1 << 10) /* data receive ready (data in fifo)*/
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#define MMCST0_DATED (1 << 11) /* DAT3 edge detect */
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#define MMCST0_TRNDNE (1 << 12) /* transfer done */
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/* DAVINCI_MMCST1 definitions */
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#define MMCST1_BUSY (1 << 0)
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/* DAVINCI_MMCCMD definitions */
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#define MMCCMD_CMD_MASK (0x3F << 0)
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#define MMCCMD_PPLEN (1 << 7)
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#define MMCCMD_BSYEXP (1 << 8)
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#define MMCCMD_RSPFMT_MASK (3 << 9)
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#define MMCCMD_RSPFMT_NONE (0 << 9)
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#define MMCCMD_RSPFMT_R1456 (1 << 9)
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#define MMCCMD_RSPFMT_R2 (2 << 9)
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#define MMCCMD_RSPFMT_R3 (3 << 9)
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#define MMCCMD_DTRW (1 << 11)
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#define MMCCMD_STRMTP (1 << 12)
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#define MMCCMD_WDATX (1 << 13)
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#define MMCCMD_INITCK (1 << 14)
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#define MMCCMD_DCLR (1 << 15)
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#define MMCCMD_DMATRIG (1 << 16)
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/* DAVINCI_MMCFIFOCTL definitions */
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#define MMCFIFOCTL_FIFORST (1 << 0)
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#define MMCFIFOCTL_FIFODIR_WR (1 << 1)
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#define MMCFIFOCTL_FIFODIR_RD (0 << 1)
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#define MMCFIFOCTL_FIFOLEV (1 << 2) /* 0 = 128 bits, 1 = 256 bits */
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#define MMCFIFOCTL_ACCWD_4 (0 << 3) /* access width of 4 bytes */
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#define MMCFIFOCTL_ACCWD_3 (1 << 3) /* access width of 3 bytes */
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#define MMCFIFOCTL_ACCWD_2 (2 << 3) /* access width of 2 bytes */
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#define MMCFIFOCTL_ACCWD_1 (3 << 3) /* access width of 1 byte */
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/* DAVINCI_SDIOST0 definitions */
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#define SDIOST0_DAT1_HI (1 << 0)
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#define SDIOST0_INTPRD (1 << 1)
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#define SDIOST0_RDWTST (1 << 2)
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/* DAVINCI_SDIOIEN definitions */
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#define SDIOIEN_IOINTEN (1 << 0)
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#define SDIOIEN_RWSEN (1 << 1)
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/* DAVINCI_SDIOIST definitions */
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#define SDIOIST_IOINT (1 << 0)
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#define SDIOIST_RWS (1 << 1)
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/* MMCSD Init clock in Hz in opendrain mode */
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#define MMCSD_INIT_CLOCK 200000
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#define MAX_CCNT ((1 << 16) - 1)
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#define MAX_NR_SG 16
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#define MMC_DATA_WRITE (1 << 8)
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#define MMC_DATA_READ (1 << 9)
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#define MMC_DATA_STREAM (1 << 10)
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typedef struct {
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volatile rt_uint32_t MMCCTL;
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volatile rt_uint32_t MMCCLK;
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volatile rt_uint32_t MMCST0;
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volatile rt_uint32_t MMCST1;
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volatile rt_uint32_t MMCIM;
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volatile rt_uint32_t MMCTOR;
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volatile rt_uint32_t MMCTOD;
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volatile rt_uint32_t MMCBLEN;
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volatile rt_uint32_t MMCNBLK;
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volatile rt_uint32_t MMCNBLC;
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volatile rt_uint32_t MMCDRR;
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volatile rt_uint32_t MMCDXR;
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volatile rt_uint32_t MMCCMD;
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volatile rt_uint32_t MMCARGHL;
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volatile rt_uint32_t MMCRSP01;
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volatile rt_uint32_t MMCRSP23;
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volatile rt_uint32_t MMCRSP45;
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volatile rt_uint32_t MMCRSP67;
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volatile rt_uint32_t MMCDRSP;
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volatile rt_uint32_t reserved0;
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volatile rt_uint32_t MMCCIDX;
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volatile rt_uint32_t reserved1[4];
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volatile rt_uint32_t SDIOCTL;
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volatile rt_uint32_t SDIOST0;
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volatile rt_uint32_t SDIOIEN;
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volatile rt_uint32_t SDIOIST;
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volatile rt_uint32_t MMCFIFOCTL;
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}mmcsd_regs_t;
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extern int rt_hw_mmcsd_init(void);
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#endif
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