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234 lines
8.7 KiB
234 lines
8.7 KiB
5 months ago
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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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*2024-02-14 ShichengChu first version
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*/
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#ifndef __DRV_HW_I2C_H__
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#define __DRV_HW_I2C_H__
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#include <rtthread.h>
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#include "rtdevice.h"
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#include <rthw.h>
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#include "pinctrl.h"
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#include "mmio.h"
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#define I2C0 0x0
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#define I2C1 0x1
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#define I2C2 0x2
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#define I2C3 0x3
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#define I2C4 0x4
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#define I2C0_BASE 0x4000000
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#define I2C1_BASE 0x4010000
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#define I2C2_BASE 0x4020000
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#define I2C3_BASE 0x4030000
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#define I2C4_BASE 0x4040000
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#define BIT_I2C_CMD_DATA_READ_BIT (0x01 << 8)
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#define BIT_I2C_CMD_DATA_STOP_BIT (0x01 << 9)
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/* bit definition */
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#define BIT_I2C_CON_MASTER_MODE (0x01 << 0)
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#define BIT_I2C_CON_STANDARD_SPEED (0x01 << 1)
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#define BIT_I2C_CON_FULL_SPEED (0x02 << 1)
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#define BIT_I2C_CON_HIGH_SPEED (0x03 << 1)
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#define BIT_I2C_CON_10B_ADDR_SLAVE (0x01 << 3)
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#define BIT_I2C_CON_10B_ADDR_MASTER (0x01 << 4)
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#define BIT_I2C_CON_RESTART_EN (0x01 << 5)
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#define BIT_I2C_CON_SLAVE_DIS (0x01 << 6)
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#define BIT_I2C_TAR_10B_ADDR_MASTER (0x01 << 12)
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#define BIT_I2C_INT_RX_UNDER (0x01 << 0)
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#define BIT_I2C_INT_RX_OVER (0x01 << 1)
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#define BIT_I2C_INT_RX_FULL (0x01 << 2)
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#define BIT_I2C_INT_TX_OVER (0x01 << 3)
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#define BIT_I2C_INT_TX_EMPTY (0x01 << 4)
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#define BIT_I2C_INT_RD_REQ (0x01 << 5)
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#define BIT_I2C_INT_TX_ABRT (0x01 << 6)
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#define BIT_I2C_INT_RX_DONE (0x01 << 7)
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#define BIT_I2C_INT_ACTIVITY (0x01 << 8)
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#define BIT_I2C_INT_STOP_DET (0x01 << 9)
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#define BIT_I2C_INT_START_DET (0x01 << 10)
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#define BIT_I2C_INT_GEN_ALL (0x01 << 11)
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#define I2C_INTR_MASTER_MASK (BIT_I2C_INT_TX_ABRT | \
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BIT_I2C_INT_STOP_DET | \
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BIT_I2C_INT_RX_FULL | \
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BIT_I2C_INT_TX_EMPTY)
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#define BIT_I2C_INT_RX_UNDER_MASK (0x01 << 0)
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#define BIT_I2C_INT_RX_OVER_MASK (0x01 << 1)
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#define BIT_I2C_INT_RX_FULL_MASK (0x01 << 2)
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#define BIT_I2C_INT_TX_OVER_MASK (0x01 << 3)
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#define BIT_I2C_INT_TX_EMPTY_MASK (0x01 << 4)
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#define BIT_I2C_INT_RD_REQ_MASK (0x01 << 5)
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#define BIT_I2C_INT_TX_ABRT_MASK (0x01 << 6)
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#define BIT_I2C_INT_RX_DONE_MASK (0x01 << 7)
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#define BIT_I2C_INT_ACTIVITY_MASK (0x01 << 8)
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#define BIT_I2C_INT_STOP_DET_MASK (0x01 << 9)
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#define BIT_I2C_INT_START_DET_MASK (0x01 << 10)
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#define BIT_I2C_INT_GEN_ALL_MASK (0x01 << 11)
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#define BIT_I2C_INT_RX_UNDER_RAW (0x01 << 0)
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#define BIT_I2C_INT_RX_OVER_RAW (0x01 << 1)
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#define BIT_I2C_INT_RX_FULL_RAW (0x01 << 2)
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#define BIT_I2C_INT_TX_OVER_RAW (0x01 << 3)
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#define BIT_I2C_INT_TX_EMPTY_RAW (0x01 << 4)
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#define BIT_I2C_INT_RD_REQ_RAW (0x01 << 5)
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#define BIT_I2C_INT_TX_ABRT_RAW (0x01 << 6)
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#define BIT_I2C_INT_RX_DONE_RAW (0x01 << 7)
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#define BIT_I2C_INT_ACTIVITY_RAW (0x01 << 8)
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#define BIT_I2C_INT_STOP_DET_RAW (0x01 << 9)
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#define BIT_I2C_INT_START_DET_RAW (0x01 << 10)
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#define BIT_I2C_INT_GEN_ALL_RAW (0x01 << 11)
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#define BIT_I2C_DMA_CR_TDMAE (0x01 << 1)
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#define BIT_I2C_DMA_CR_RDMAE (0x01 << 0)
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struct i2c_regs {
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volatile uint32_t ic_con; /* 0x00 */
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volatile uint32_t ic_tar; /* 0x04 */
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volatile uint32_t ic_sar; /* 0x08 */
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volatile uint32_t ic_hs_maddr; /* 0x0c */
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volatile uint32_t ic_cmd_data; /* 0x10 */
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volatile uint32_t ic_ss_scl_hcnt; /* 0x14 */
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volatile uint32_t ic_ss_scl_lcnt; /* 0x18 */
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volatile uint32_t ic_fs_scl_hcnt; /* 0x1c */
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volatile uint32_t ic_fs_scl_lcnt; /* 0x20 */
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volatile uint32_t ic_hs_scl_hcnt; /* 0x24 */
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volatile uint32_t ic_hs_scl_lcnt; /* 0x28 */
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volatile uint32_t ic_intr_stat; /* 0x2c */
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volatile uint32_t ic_intr_mask; /* 0x30 */
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volatile uint32_t ic_raw_intr_stat; /* 0x34 */
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volatile uint32_t ic_rx_tl; /* 0x38 */
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volatile uint32_t ic_tx_tl; /* 0x3c */
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volatile uint32_t ic_clr_intr; /* 0x40 */
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volatile uint32_t ic_clr_rx_under; /* 0x44 */
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volatile uint32_t ic_clr_rx_over; /* 0x48 */
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volatile uint32_t ic_clr_tx_over; /* 0x4c */
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volatile uint32_t ic_clr_rd_req; /* 0x50 */
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volatile uint32_t ic_clr_tx_abrt; /* 0x54 */
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volatile uint32_t ic_clr_rx_done; /* 0x58 */
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volatile uint32_t ic_clr_activity; /* 0x5c */
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volatile uint32_t ic_clr_stop_det; /* 0x60 */
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volatile uint32_t ic_clr_start_det; /* 0x64 */
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volatile uint32_t ic_clr_gen_call; /* 0x68 */
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volatile uint32_t ic_enable; /* 0x6c */
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volatile uint32_t ic_status; /* 0x70 */
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volatile uint32_t ic_txflr; /* 0x74 */
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volatile uint32_t ic_rxflr; /* 0x78 */
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volatile uint32_t ic_sda_hold; /* 0x7c */
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volatile uint32_t ic_tx_abrt_source; /* 0x80 */
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volatile uint32_t ic_slv_dat_nack_only; /* 0x84 */
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volatile uint32_t ic_dma_cr; /* 0x88 */
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volatile uint32_t ic_dma_tdlr; /* 0x8c */
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volatile uint32_t ic_dma_rdlr; /* 0x90 */
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volatile uint32_t ic_sda_setup; /* 0x94 */
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volatile uint32_t ic_ack_general_call; /* 0x98 */
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volatile uint32_t ic_enable_status; /* 0x9c */
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volatile uint32_t ic_fs_spklen; /* 0xa0 */
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volatile uint32_t ic_hs_spklen; /* 0xa4 */
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};
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#if !defined(IC_CLK)
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#define IC_CLK 100
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#endif
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#define NANO_TO_MICRO 1000
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/* High and low times in different speed modes (in ns) */
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#define MIN_SS_SCL_HIGHTIME 4000
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#define MIN_SS_SCL_LOWTIME 4700
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#define MIN_FS_SCL_HIGHTIME 600
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#define MIN_FS_SCL_LOWTIME 1300
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#define MIN_HS100pF_SCL_HIGHTIME 60
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#define MIN_HS100pF_SCL_LOWTIME 120
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#define MIN_HS400pF_SCL_HIGHTIME 160
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#define MIN_HS400pF_SCL_LOWTIME 320
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
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/* Worst case timeout for 1 byte is kept as 2ms */
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#define I2C_BYTE_TO (CONFIG_SYS_HZ/500)
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#define I2C_STOPDET_TO (CONFIG_SYS_HZ/500)
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#define I2C_BYTE_TO_BB (I2C_BYTE_TO * 16)
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/* i2c control register definitions */
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#define IC_CON_SD 0x0040
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#define IC_CON_RE 0x0020
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#define IC_CON_10BITADDRMASTER 0x0010
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#define IC_CON_10BITADDR_SLAVE 0x0008
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#define IC_CON_SPD_MSK 0x0006
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#define IC_CON_SPD_SS 0x0002
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#define IC_CON_SPD_FS 0x0004
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#define IC_CON_SPD_HS 0x0006
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#define IC_CON_MM 0x0001
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/* i2c data buffer and command register definitions */
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#define IC_CMD 0x0100
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#define IC_STOP 0x0200
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/* i2c interrupt status register definitions */
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#define IC_GEN_CALL 0x0800
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#define IC_START_DET 0x0400
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#define IC_STOP_DET 0x0200
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#define IC_ACTIVITY 0x0100
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#define IC_RX_DONE 0x0080
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#define IC_TX_ABRT 0x0040
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#define IC_RD_REQ 0x0020
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#define IC_TX_EMPTY 0x0010
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#define IC_TX_OVER 0x0008
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#define IC_RX_FULL 0x0004
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#define IC_RX_OVER 0x0002
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#define IC_RX_UNDER 0x0001
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/* fifo threshold register definitions */
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#define IC_TL0 0x00
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#define IC_TL1 0x01
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#define IC_TL2 0x02
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#define IC_TL3 0x03
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#define IC_TL4 0x04
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#define IC_TL5 0x05
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#define IC_TL6 0x06
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#define IC_TL7 0x07
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#define IC_RX_TL IC_TL0
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#define IC_TX_TL IC_TL0
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/* i2c enable register definitions */
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#define IC_ENABLE 0x0001
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/* i2c status register definitions */
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#define IC_STATUS_SA 0x0040
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#define IC_STATUS_MA 0x0020
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#define IC_STATUS_RFF 0x0010
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#define IC_STATUS_RFNE 0x0008
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#define IC_STATUS_TFE 0x0004
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#define IC_STATUS_TFNF 0x0002
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#define IC_STATUS_ACT 0x0001
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/* Speed Selection */
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#define IC_SPEED_MODE_STANDARD 1
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#define IC_SPEED_MODE_FAST 2
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#define IC_SPEED_MODE_MAX 3
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#define I2C_MAX_SPEED 3400000
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#define I2C_FAST_SPEED 400000
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#define I2C_STANDARD_SPEED 100000
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#define I2C_SPEED I2C_FAST_SPEED
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#define I2C0_IRQ (I2C_IRQ_BASE + 0)
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#define I2C1_IRQ (I2C_IRQ_BASE + 1)
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#define I2C2_IRQ (I2C_IRQ_BASE + 2)
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#define I2C3_IRQ (I2C_IRQ_BASE + 3)
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#define I2C4_IRQ (I2C_IRQ_BASE + 4)
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int rt_hw_i2c_init(void);
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#endif /* __DRV_HW_I2C_H__ */
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