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84 lines
3.3 KiB
84 lines
3.3 KiB
5 months ago
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/*
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* Copyright (c) 2006-2024, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2024/02/22 flyingcys first version
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*/
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#ifndef __DRV_ADC_H__
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#define __DRV_ADC_H__
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#include "pinctrl.h"
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#include "mmio.h"
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#define SARADC_BASE 0x030F0000
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#define SARADC_CH_MAX 3
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#define SARADC_CTRL_OFFSET 0x04
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#define SARADC_CTRL_START (1 << 0)
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#define SARADC_CTRL_SEL_POS 0x04
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#define SARADC_STATUS_OFFSET 0x08
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#define SARADC_STATUS_BUSY (1 << 0)
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#define SARADC_CYC_SET_OFFSET 0x0C
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#define SARADC_CYC_CLKDIV_DIV_POS (12U)
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#define SARADC_CYC_CLKDIV_DIV_MASK (0xF << SARADC_CYC_CLKDIV_DIV_POS)
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#define SARADC_CYC_CLKDIV_DIV_1 (0U<< SARADC_CYC_CLKDIV_DIV_POS)
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#define SARADC_CYC_CLKDIV_DIV_2 (1U<< SARADC_CYC_CLKDIV_DIV_POS)
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#define SARADC_CYC_CLKDIV_DIV_3 (2U<< SARADC_CYC_CLKDIV_DIV_POS)
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#define SARADC_CYC_CLKDIV_DIV_4 (3U<< SARADC_CYC_CLKDIV_DIV_POS)
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#define SARADC_CYC_CLKDIV_DIV_5 (4U<< SARADC_CYC_CLKDIV_DIV_POS)
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#define SARADC_CYC_CLKDIV_DIV_6 (5U<< SARADC_CYC_CLKDIV_DIV_POS)
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#define SARADC_CYC_CLKDIV_DIV_7 (6U<< SARADC_CYC_CLKDIV_DIV_POS)
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#define SARADC_CYC_CLKDIV_DIV_8 (7U<< SARADC_CYC_CLKDIV_DIV_POS)
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#define SARADC_CYC_CLKDIV_DIV_9 (8U<< SARADC_CYC_CLKDIV_DIV_POS)
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#define SARADC_CYC_CLKDIV_DIV_10 (9U<< SARADC_CYC_CLKDIV_DIV_POS)
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#define SARADC_CYC_CLKDIV_DIV_11 (10U<< SARADC_CYC_CLKDIV_DIV_POS)
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#define SARADC_CYC_CLKDIV_DIV_12 (11U<< SARADC_CYC_CLKDIV_DIV_POS)
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#define SARADC_CYC_CLKDIV_DIV_13 (12U<< SARADC_CYC_CLKDIV_DIV_POS)
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#define SARADC_CYC_CLKDIV_DIV_14 (13U<< SARADC_CYC_CLKDIV_DIV_POS)
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#define SARADC_CYC_CLKDIV_DIV_15 (14U<< SARADC_CYC_CLKDIV_DIV_POS)
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#define SARADC_CYC_CLKDIV_DIV_16 (15U<< SARADC_CYC_CLKDIV_DIV_POS)
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#define SARADC_RESULT_OFFSET 0x014
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#define SARADC_RESULT(n) (SARADC_RESULT_OFFSET + (n) * 4)
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#define SARADC_RESULT_MASK 0x0FFF
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#define SARADC_RESULT_VALID (1 << 15)
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rt_inline void cvi_set_saradc_ctrl(unsigned long reg_base, rt_uint32_t value)
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{
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value |= mmio_read_32(reg_base + SARADC_CTRL_OFFSET);
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mmio_write_32(reg_base + SARADC_CTRL_OFFSET, value);
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}
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rt_inline void cvi_reset_saradc_ctrl(unsigned long reg_base, rt_uint32_t value)
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{
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value = mmio_read_32(reg_base + SARADC_CTRL_OFFSET) & ~value;
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mmio_write_32(reg_base + SARADC_CTRL_OFFSET, value);
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}
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rt_inline rt_uint32_t cvi_get_saradc_status(unsigned long reg_base)
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{
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return((rt_uint32_t)mmio_read_32(reg_base + SARADC_STATUS_OFFSET));
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}
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rt_inline void cvi_set_cyc(unsigned long reg_base)
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{
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rt_uint32_t value;
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value = mmio_read_32(reg_base + SARADC_CYC_SET_OFFSET);
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value &= ~SARADC_CYC_CLKDIV_DIV_16;
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mmio_write_32(reg_base + SARADC_CYC_SET_OFFSET, value);
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value |= SARADC_CYC_CLKDIV_DIV_16; //set saradc clock cycle=840ns
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mmio_write_32(reg_base + SARADC_CYC_SET_OFFSET, value);
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}
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int rt_hw_adc_init(void);
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#endif /* __DRV_ADC_H__ */
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