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99 lines
2.6 KiB
99 lines
2.6 KiB
5 months ago
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2015-04-14 ArdaFu first version
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*/
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#include "asm9260t.h"
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#include "rtthread.h"
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#include "uart.h"
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void Hw_UartDisable(HW_USART_TypeDef* uartBase)
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{
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uartBase->INTR[R_CLR] = ASM_UART_INTR_RXIEN | ASM_UART_INTR_TXIEN | ASM_UART_INTR_RTIS;
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uartBase->CTRL2[R_CLR] = ASM_UART_CTRL2_TXE | ASM_UART_CTRL2_RXE;
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}
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void Hw_UartEnable(HW_USART_TypeDef* uartBase)
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{
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uartBase->CTRL2[R_CLR] = 0x0000C000UL; //clear CTSEN and RTSEN
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uartBase->CTRL2[R_SET] = ASM_UART_CTRL2_TXE | ASM_UART_CTRL2_RXE | ASM_UART_CTRL2_USARTEN;
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uartBase->INTR[R_SET] = ASM_UART_INTR_RXIEN | ASM_UART_INTR_RTIEN;
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}
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void Hw_UartReset(HW_USART_TypeDef* uartBase)
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{
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uartBase->CTRL0[R_CLR] = ASM_UART_CTRL0_SFTRST | ASM_UART_CTRL0_CLKGATE | ASM_UART_CTRL0_RXTO_ENABLE;
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uartBase->CTRL0[R_SET] = ASM_UART_CTRL0_SFTRST | ASM_UART_CTRL0_CLKGATE | ASM_UART_CTRL0_RXTO_ENABLE;
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}
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void Hw_UartConfig(HW_USART_TypeDef* uartBase,int baudRate, int dataBits, int stopBits,int parity)
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{
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rt_uint32_t mode = ASM_UART_LINECTRL_FEN;
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switch (dataBits)
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{
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case 8:
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mode |= ASM_UART_LINECTRL_WLEN8;
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break;
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case 7:
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mode |= ASM_UART_LINECTRL_WLEN7;
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break;
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case 6:
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mode |= ASM_UART_LINECTRL_WLEN6;
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break;
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case 5:
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mode |= ASM_UART_LINECTRL_WLEN5;
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break;
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default:
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mode |= ASM_UART_LINECTRL_WLEN8;
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break;
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}
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switch (stopBits)
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{
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case 2:
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mode |= ASM_UART_LINECTRL_STP2;
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break;
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case 1:
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default:
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break;
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}
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switch (parity)
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{
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case 1:
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mode |= ASM_UART_LINECTRL_PEN;
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break;
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case 2:
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mode |= ASM_UART_LINECTRL_PEN | ASM_UART_LINECTRL_EPS;
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break;
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case 0:
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default:
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break;
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}
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//16bit nBaudDivint
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mode |= (((12000000 <<2 ) / baudRate) & UART_BAUD_DIVINT_MASK) << 10;
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//6bit nNaudDivfrac
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mode |= (((12000000 <<2 ) / baudRate) & UART_BAUD_DIVFRAC_MASK) << 8;
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uartBase->LINECTRL[R_VAL] = mode;
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}
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void Hw_UartInit(int index)
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{
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// uart0 = bit11, uart9 = bit20
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int ctrl_bit = index + 11;
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outl(1UL<<ctrl_bit,REG_SET(HW_AHBCLKCTRL0)); //UART4 ENABLE bit15
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outl(0x1, HW_UART0CLKDIV + index*4); //UART4 div 2
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outl(1UL<<ctrl_bit,REG_CLR(HW_AHBCLKCTRL0)); //UART4 clk gate
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outl(1UL<<ctrl_bit,REG_SET(HW_AHBCLKCTRL0)); //UART4 clk gate
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outl(1UL<<ctrl_bit,REG_CLR(HW_PRESETCTRL0)); //UART4 reset
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outl(1UL<<ctrl_bit,REG_SET(HW_PRESETCTRL0)); //UART4 reset
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}
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