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111 lines
2.8 KiB
111 lines
2.8 KiB
5 months ago
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;/******************************************************************************
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;/* @file start
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;/* @brief arm9 start code for armcc
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;/* @date 2022-02-22
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;/* @author kerndev@foxmail.com
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;/*****************************************************************************/
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Stack_Size EQU 0x00000400
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Heap_Size EQU 0x00000000
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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IRQ_StackMem SPACE Stack_Size
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IRQ_StackAddr
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SVC_StackMem SPACE Stack_Size
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SVC_StackAddr
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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;/*****************************************************************************/
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; Vector_Table
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PRESERVE8
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AREA RESET, CODE, READONLY
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Vector_Table
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LDR PC, Reset_Addr
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LDR PC, Undefined_Addr
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LDR PC, SWI_Addr
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LDR PC, Prefetch_Addr
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LDR PC, Abort_Addr
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LDR PC, Reserved_Addr
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LDR PC, IRQ_Addr
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LDR PC, FIQ_Addr
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Reset_Addr DCD Reset_Handler
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Undefined_Addr DCD Reset_Handler
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SWI_Addr DCD Reset_Handler
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Prefetch_Addr DCD Reset_Handler
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Abort_Addr DCD Reset_Handler
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Reserved_Addr DCD Reset_Handler
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IRQ_Addr DCD IRQ_Handler
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FIQ_Addr DCD FIQ_Handler
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;/*****************************************************************************/
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; Mode bits and interrupt flag (I&F) defines
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USR_MODE EQU 0x10
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FIQ_MODE EQU 0x11
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IRQ_MODE EQU 0x12
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SVC_MODE EQU 0x13
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ABT_MODE EQU 0x17
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UDF_MODE EQU 0x1B
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SYS_MODE EQU 0x1F
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I_BIT EQU 0x80
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F_BIT EQU 0x40
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;/*****************************************************************************/
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AREA |.text|, CODE, READONLY
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IRQ_Handler PROC
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EXPORT IRQ_Handler [WEAK]
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B .
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ENDP
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FIQ_Handler PROC
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EXPORT FIQ_Handler [WEAK]
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B .
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ENDP
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;/*****************************************************************************/
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; Reset Handler
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Reset_Handler PROC
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IMPORT __main
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MSR CPSR_c, #IRQ_MODE :OR: I_BIT :OR: F_BIT
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LDR SP, =IRQ_StackAddr
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MSR CPSR_c, #SVC_MODE :OR: I_BIT :OR: F_BIT
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LDR SP, =SVC_StackAddr
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LDR R0, =Vector_Table
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MRC p15, 0, R2, c1, c0, 0 ;Read CP15 to R2
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ANDS R2, R2, #(1 << 13)
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LDREQ R1, =0X00000000
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LDRNE R1, =0XFFFF0000
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LDMIA R0!, {R2-R9}
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STMIA R1!, {R2-R9}
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LDMIA R0!, {R2-R9}
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STMIA R1!, {R2-R9}
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LDR R0, =__main
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BX R0
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ENDP
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;/*****************************************************************************/
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; User Initial Stack & Heap
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IF :DEF:__MICROLIB
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EXPORT __initial_sp
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EXPORT __heap_base
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EXPORT __heap_limit
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ELSE
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IMPORT __use_two_region_memory
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EXPORT __user_initial_stackheap
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__user_initial_stackheap PROC
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LDR R0, = Heap_Mem
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LDR R1, = (SVC_StackMem + Stack_Size)
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LDR R2, = (Heap_Mem + Heap_Size)
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LDR R3, = SVC_StackMem
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BX LR
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ENDP
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ALIGN
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ENDIF
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END
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