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61 lines
1.7 KiB
61 lines
1.7 KiB
5 months ago
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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-10-19 JasonHu first version
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* 2023-04-22 flyingcys add C906_PLIC_PHY_ADDR macro judge
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*/
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#ifndef __RISCV64_PLIC_H__
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#define __RISCV64_PLIC_H__
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#include <rt_interrupt.h>
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#ifndef C906_PLIC_PHY_ADDR
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#define C906_PLIC_PHY_ADDR (0x10000000)
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#endif
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#define C906_PLIC_NR_EXT_IRQS (IRQ_MAX_NR)
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#define C906_NR_CPUS (NR_CPUS)
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/* M and S mode context. */
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#define C906_NR_CONTEXT (2)
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#define MAX_DEVICES 1024
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#define MAX_CONTEXTS 15872
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/*
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* Each interrupt source has a priority register associated with it.
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* We always hardwire it to one in Linux.
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*/
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#define PRIORITY_BASE 0
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#define PRIORITY_PER_ID 4
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/*
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* Each hart context has a vector of interrupt enable bits associated with it.
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* There's one bit for each interrupt source.
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*/
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#define ENABLE_BASE 0x2000
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#define ENABLE_PER_HART 0x80
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/*
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* Each hart context has a set of control registers associated with it. Right
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* now there's only two: a source priority threshold over which the hart will
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* take an interrupt, and a register to claim interrupts.
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*/
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#define CONTEXT_BASE 0x200000
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#define CONTEXT_PER_HART 0x1000
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#define CONTEXT_THRESHOLD 0x00
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#define CONTEXT_CLAIM 0x04
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void plic_init(void);
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void plic_enable_irq(int irqno);
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void plic_disable_irq(int irqno);
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// tell PLIC that we've served this IRQ
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void plic_complete(int irq);
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void plic_handle_irq(void);
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#endif
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