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59 lines
1.8 KiB
59 lines
1.8 KiB
3 months ago
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Email: opensource_embedded@phytium.com.cn
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*
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* Change Logs:
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* Date Author Notes
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* 2022-10-26 huanghe first commit
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* 2022-04-13 zhugengyu support RT-Smart
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* 2023-07-27 liqiaozhong add gpio pin definition
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*
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*/
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#ifndef __BOARD_H__
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#define __BOARD_H__
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#include "fparameters.h"
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#include "phytium_cpu.h"
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#include "mmu.h"
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#ifdef RT_USING_SMART
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#include "ioremap.h"
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#endif
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#if defined(__CC_ARM)
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extern int Image$$RW_IRAM1$$ZI$$Limit;
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#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
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#elif defined(__GNUC__)
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extern int __bss_end;
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#define HEAP_BEGIN ((void *)&__bss_end)
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#endif
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#ifdef RT_USING_SMART
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#define HEAP_END (rt_size_t)((rt_size_t)KERNEL_VADDR_START + 64 * 1024 * 1024)
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#define PAGE_START HEAP_END + 1 * 1024 * 1024
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#define PAGE_END (rt_size_t)((rt_size_t)KERNEL_VADDR_START + 128 * 1024 * 1024)
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#else
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#define HEAP_END (rt_size_t)(HEAP_BEGIN + 64*1024*1024)
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#define PAGE_POOL_SIZE (8ul << 20)
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#define PAGE_START (rt_size_t)(HEAP_END)
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#define PAGE_END (PAGE_START +PAGE_POOL_SIZE)
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#endif
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#ifdef RT_USING_PIN
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/* gpio pin_index handle */
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#define FGPIO_OPS_PIN_INDEX(ctrl, port, pin) SET_REG32_BITS(ctrl, 19, 12) | \
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SET_REG32_BITS(port, 11, 8) | \
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SET_REG32_BITS(pin, 7, 0)
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#define FGPIO_OPS_PIN_CTRL_ID(pin_idx) GET_REG32_BITS(pin_idx, 19, 12)
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#define FGPIO_OPS_PIN_PORT_ID(pin_idx) GET_REG32_BITS(pin_idx, 11, 8)
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#define FGPIO_OPS_PIN_ID(pin_idx) GET_REG32_BITS(pin_idx, 7, 0)
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#endif
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void rt_hw_board_init(void);
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#endif
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